September 2018 - U-Boot

[U-Boot] [PATCH V2] test/py: ignore console read exceptions after test failure
by Stephen Warren 07 Oct '18

07 Oct '18

From: Stephen Warren <swarren(a)nvidia.com> After a test has failed, test/py drains the U-Boot console log to ensure that any relevant output is captured. At this point, we don't care about detecting any additional errors, since the test is already known to have failed, and U-Boot will be restarted. To ensure that the test cleanup code is not interrupted, and can correctly terminate the log sections for the failed test, ignore any exception that occurs while reading the U-Boot console output during this limited period of time. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- v2: * Combine the two except cases into one, since one was a superset of the other. * Fix TAB-vs-spaces issue in identation. --- test/py/u_boot_console_base.py | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py index a14bad6e8c50..326b2ac51fbf 100644 --- a/test/py/u_boot_console_base.py +++ b/test/py/u_boot_console_base.py @@ -304,7 +304,17 @@ class ConsoleBase(object): # Wait for something U-Boot will likely never send. This will # cause the console output to be read and logged. self.p.expect(['This should never match U-Boot output']) - except u_boot_spawn.Timeout: + except: + # We expect a timeout, since U-Boot won't print what we waited + # for. Squash it when it happens. + # + # Squash any other exception too. This function is only used to + # drain (and log) the U-Boot console output after a failed test. + # The U-Boot process will be restarted, or target board reset, once + # this function returns. So, we don't care about detecting any + # additional errors, so they're squashed so that the rest of the + # post-test-failure cleanup code can continue operation, and + # correctly terminate any log sections, etc. pass finally: self.p.timeout = orig_timeout -- 2.18.0

3 4

[U-Boot] [PATCH v5 1/2] spl: add support to booting with OP-TEE
by Kever Yang 04 Oct '18

04 Oct '18

OP-TEE is an open source trusted OS, in armv7, its loading and running are like this: loading: - SPL load both OP-TEE and U-Boot running: - SPL run into OP-TEE in secure mode; - OP-TEE run into U-Boot in non-secure mode; To make code simple, it would be fine to use IH_OS_TEE for the os tyle in TPL(just like IH_OS_LINUX is using both in SPL and U-Boot). Here is the diagram for SPL loading OP-TEE, IH_OS_TEE:(make u-boot.itb for SPL) Non-Secure Secure BootROM | v SPL | v --------- OP-TEE | v U-Boot | V Linux For other two king of OP-TEE loading/booting, see commit message: 45b55712d4 image: Add IH_OS_TEE for TEE chain-load boot More detail: https://github.com/OP-TEE/optee_os and search for 'boot arguments' for detail entry parameter in: core/arch/arm/kernel/generic_entry_a32.S Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> Cc: Bryan O'Donoghue <bryan.odonoghue(a)linaro.org> --- Changes in v5: - Split the patch out from rk3229 seris - Use IH_OS_TEE instead of IH_OS_OP-TEE Changes in v4: - use NULL instead of '0' - add fdt_addr as arg2 of entry Changes in v2: - Using new image type for op-tee common/spl/Kconfig | 7 +++++++ common/spl/Makefile | 1 + common/spl/spl.c | 7 +++++++ common/spl/spl_optee.S | 12 ++++++++++++ include/spl.h | 13 +++++++++++++ 5 files changed, 40 insertions(+) create mode 100644 common/spl/spl_optee.S diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 99c9053ab8..db1915fe5c 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -799,6 +799,13 @@ config SPL_AM33XX_ENABLE_RTC32K_OSC Enable access to the AM33xx RTC and select the external 32kHz clock source. +config SPL_OPTEE + bool "Support OP-TEE Trusted OS" + depends on ARM + help + OP-TEE is an open source Trusted OS which is loaded by SPL. + More detail at: https://github.com/OP-TEE/optee_os + config TPL bool depends on SUPPORT_TPL diff --git a/common/spl/Makefile b/common/spl/Makefile index 814081feda..a130a5be4b 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_$(SPL_TPL_)UBI) += spl_ubi.o obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o obj-$(CONFIG_$(SPL_TPL_)ATF) += spl_atf.o +obj-$(CONFIG_$(SPL_TPL_)OPTEE) += spl_optee.o obj-$(CONFIG_$(SPL_TPL_)USB_SUPPORT) += spl_usb.o obj-$(CONFIG_$(SPL_TPL_)FAT_SUPPORT) += spl_fat.o obj-$(CONFIG_$(SPL_TPL_)EXT_SUPPORT) += spl_ext.o diff --git a/common/spl/spl.c b/common/spl/spl.c index a1e7b9fa91..482f6e53ef 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -529,6 +529,13 @@ void board_init_r(gd_t *dummy1, ulong dummy2) spl_invoke_atf(&spl_image); break; #endif +#if CONFIG_IS_ENABLED(OPTEE) + case IH_OS_TEE: + debug("Jumping to U-Boot via OP-TEE\n"); + spl_optee_entry(NULL, NULL, spl_image.fdt_addr, + (void *)spl_image.entry_point); + break; +#endif #ifdef CONFIG_SPL_OS_BOOT case IH_OS_LINUX: debug("Jumping to Linux\n"); diff --git a/common/spl/spl_optee.S b/common/spl/spl_optee.S new file mode 100644 index 0000000000..86fc398546 --- /dev/null +++ b/common/spl/spl_optee.S @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Rockchip Electronic Co.,Ltd + */ + +#include <linux/linkage.h> +#include <asm/assembler.h> + +ENTRY(spl_optee_entry) + ldr lr, =CONFIG_SYS_TEXT_BASE + mov pc, r3 +ENDPROC(spl_optee_entry) diff --git a/include/spl.h b/include/spl.h index 86287874e1..d9145ad6dc 100644 --- a/include/spl.h +++ b/include/spl.h @@ -288,6 +288,19 @@ int spl_mmc_load_image(struct spl_image_info *spl_image, */ void spl_invoke_atf(struct spl_image_info *spl_image); +/** + * spl_optee_entry - entry function for optee + * + * args defind in op-tee project + * https://github.com/OP-TEE/optee_os/ + * core/arch/arm/kernel/generic_entry_a32.S + * @arg0: pagestore + * @arg1: (ARMv7 standard bootarg #1) + * @arg2: device tree address, (ARMv7 standard bootarg #2) + * @arg3: non-secure entry address (ARMv7 bootarg #0) + */ +void spl_optee_entry(void *arg0, void *arg1, void *arg2, void *arg3); + /** * board_return_to_bootrom - allow for boards to continue with the boot ROM * -- 2.18.0

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[U-Boot] [PATCH] rockchip: make_fit_atf.py depends on u-boot
by Andreas Färber 04 Oct '18

04 Oct '18

u-boot.itb depends on u-boot-nodtb.bin, which in turn depends on u-boot. u-boot.its from Rockchip make_fit_atf.py (used by {evb,firefly}-rk3399) wants to read u-boot but is lacking this dependency, so that u-boot.itb cannot be built in one go. Detect its use and add the missing dependency. Reported-by: Yousaf Kaukab <yousaf.kaukab(a)suse.com> Signed-off-by: Andreas Färber <afaerber(a)suse.de> --- Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index f31ee60e4c..3723346c4f 100644 --- a/Makefile +++ b/Makefile @@ -1051,7 +1051,10 @@ U_BOOT_ITS = $(subst ",,$(CONFIG_SPL_FIT_SOURCE)) else ifneq ($(CONFIG_SPL_FIT_GENERATOR),"") U_BOOT_ITS := u-boot.its -$(U_BOOT_ITS): FORCE +ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-rockchip/make_fit_atf.py") +U_BOOT_ITS_DEPS += u-boot +endif +$(U_BOOT_ITS): $(U_BOOT_ITS_DEPS) FORCE $(srctree)/$(CONFIG_SPL_FIT_GENERATOR) \ $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) > $@ endif -- 2.16.3

2 2

[U-Boot] [PATCH RESEND 1/2] rockchip: make_fit_atf: use elf entry point
by Mian Yousaf Kaukab 04 Oct '18

04 Oct '18

make_fit_atf.py uses physical address of first segment as the entry point to bl31. It is incorrect and causes following abort when bl31_entry() is called: U-Boot SPL board initTrying to boot from MMC1 "Synchronous Abort" handler, esr 0x02000000 elr: 0000000000000000 lr : 00000000ff8c7e8c x 0: 00000000ff8e0000 x 1: 0000000000000000 x 2: 0000000000000000 x 3: 00000000ff8e0180 x 4: 0000000000000000 x 5: 0000000000000000 x 6: 0000000000000030 x 7: 00000000ff8e0188 x 8: 00000000000001e0 x 9: 0000000000000000 x10: 000000000007fcdc x11: 00000000002881b8 x12: 00000000000001a2 x13: 0000000000000198 x14: 000000000007fdcc x15: 00000000002881b8 x16: 00000000003c0724 x17: 00000000003c0718 x18: 000000000007fe80 x19: 00000000ff8e0000 x20: 0000000000200000 x21: 00000000ff8e0000 x22: 0000000000000000 x23: 000000000007fe30 x24: 00000000ff8d1c3c x25: 00000000ff8d5000 x26: 00000000deadbeef x27: 00000000000004a0 x28: 000000000000009c x29: 000000000007fd90 Fix it by using the entry point from the elf header. Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab(a)suse.com> --- arch/arm/mach-rockchip/make_fit_atf.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py index 6b3d9201c9..b88a5e1f16 100755 --- a/arch/arm/mach-rockchip/make_fit_atf.py +++ b/arch/arm/mach-rockchip/make_fit_atf.py @@ -53,7 +53,7 @@ DT_END=""" }; """ -def append_atf_node(file, atf_index, phy_addr): +def append_atf_node(file, atf_index, phy_addr, elf_entry): """ Append ATF DT node to input FIT dts file. """ @@ -67,7 +67,7 @@ def append_atf_node(file, atf_index, phy_addr): print >> file, '\t\t\tcompression = "none";' print >> file, '\t\t\tload = <0x%08x>;' % phy_addr if atf_index == 1: - print >> file, '\t\t\tentry = <0x%08x>;' % phy_addr + print >> file, '\t\t\tentry = <0x%08x>;' % elf_entry print >> file, '\t\t};' print >> file, '' @@ -141,12 +141,13 @@ def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_fi with open(bl31_file_name) as bl31_file: bl31 = ELFFile(bl31_file) + elf_entry = bl31.header['e_entry'] for i in range(bl31.num_segments()): seg = bl31.get_segment(i) if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)): paddr = seg.__getitem__(ELF_SEG_P_PADDR) p= seg.__getitem__(ELF_SEG_P_PADDR) - append_atf_node(fit_file, i+1, paddr) + append_atf_node(fit_file, i+1, paddr, elf_entry) atf_cnt = i+1 append_fdt_node(fit_file, dtbs_file_name) print >> fit_file, '%s' % DT_IMAGES_NODE_END -- 2.11.0

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[U-Boot] [PATCH v4 0/7] Add ethernet support for phyCORE-RK3288
by Janine Hagemann 04 Oct '18

04 Oct '18

- Change a used function Janine Hagemann (7): arch: arm: mach-rockchip: rk3288: Enable regulators in board_init config: phycore-rk3288_defconfig: add PHY_TI drivers: net: designware: Add reading of DT phy-handle node ARM: dts: rockchip: ADD dp83867 CLK_OUT muxing rockchip: rk3288-phycore: set flash1 iodomain to 1.8V net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii net: gmac_rockchip: Add handeling for RGMII_ID/RXID/TXID arch/arm/dts/rk3288-phycore-som.dtsi | 1 + arch/arm/mach-rockchip/rk3288-board.c | 12 ++--- board/phytec/phycore_rk3288/phycore-rk3288.c | 16 ++++++ configs/phycore-rk3288_defconfig | 1 + drivers/net/designware.c | 11 +++- drivers/net/designware.h | 1 + drivers/net/gmac_rockchip.c | 80 ++++++++++++++++++++++------ 7 files changed, 98 insertions(+), 24 deletions(-) -- 2.7.4

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[U-Boot] [RESENT PATCH] rockchip: make_fit_atf: fix warning unit_address_vs_reg
by Kever Yang 04 Oct '18

04 Oct '18

Patch fix warning: /builddir/BUILD/u-boot-2018.05-rc2/"arch/arm/mach-rockchip/make_fit_atf.py" \ arch/arm/dts/rk3399-firefly.dtb > u-boot.its ./tools/mkimage -f u-boot.its -E u-boot.itb >/dev/null && cat /dev/null u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/uboot@1 has a unit name, but no reg property u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@1 has a unit name, but no reg property u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@2 has a unit name, but no reg property u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@3 has a unit name, but no reg property u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/fdt@1 has a unit name, but no reg property u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /configurations/config@1 has a unit name, but no reg property make[1]: Leaving directory '/builddir/BUILD/u-boot-2018.05-rc2/builds/firefly-rk3399' Reported-by: Peter Robinson <pbrobinson(a)gmail.com> Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- arch/arm/mach-rockchip/make_fit_atf.py | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py index 6b3d9201c9..62b9caee34 100755 --- a/arch/arm/mach-rockchip/make_fit_atf.py +++ b/arch/arm/mach-rockchip/make_fit_atf.py @@ -34,7 +34,7 @@ DT_HEADER="""// SPDX-License-Identifier: GPL-2.0+ OR X11 #address-cells = <1>; images { - uboot@1 { + uboot { description = "U-Boot (64-bit)"; data = /incbin/("u-boot-nodtb.bin"); type = "standalone"; @@ -58,7 +58,7 @@ def append_atf_node(file, atf_index, phy_addr): Append ATF DT node to input FIT dts file. """ data = 'bl31_0x%08x.bin' % phy_addr - print >> file, '\t\tatf@%d {' % atf_index + print >> file, '\t\tatf_%d {' % atf_index print >> file, '\t\t\tdescription = \"ARM Trusted Firmware\";' print >> file, '\t\t\tdata = /incbin/("%s");' % data print >> file, '\t\t\ttype = "firmware";' @@ -78,7 +78,7 @@ def append_fdt_node(file, dtbs): cnt = 1 for dtb in dtbs: dtname = os.path.basename(dtb) - print >> file, '\t\tfdt@%d {' % cnt + print >> file, '\t\tfdt_%d {' % cnt print >> file, '\t\t\tdescription = "%s";' % dtname print >> file, '\t\t\tdata = /incbin/("%s");' % dtb print >> file, '\t\t\ttype = "flat_dt";' @@ -88,17 +88,17 @@ def append_fdt_node(file, dtbs): cnt = cnt + 1 def append_conf_section(file, cnt, dtname, atf_cnt): - print >> file, '\t\tconfig@%d {' % cnt + print >> file, '\t\tconfig_%d {' % cnt print >> file, '\t\t\tdescription = "%s";' % dtname - print >> file, '\t\t\tfirmware = "atf@1";' - print >> file, '\t\t\tloadables = "uboot@1",', + print >> file, '\t\t\tfirmware = "atf_1";' + print >> file, '\t\t\tloadables = "uboot",', for i in range(1, atf_cnt): - print >> file, '"atf@%d"' % (i+1), + print >> file, '"atf_%d"' % (i+1), if i != (atf_cnt - 1): print >> file, ',', else: print >> file, ';' - print >> file, '\t\t\tfdt = "fdt@1";' + print >> file, '\t\t\tfdt = "fdt_1";' print >> file, '\t\t};' print >> file, '' @@ -108,7 +108,7 @@ def append_conf_node(file, dtbs, atf_cnt): """ cnt = 1 print >> file, '\tconfigurations {' - print >> file, '\t\tdefault = "config@1";' + print >> file, '\t\tdefault = "config_1";' for dtb in dtbs: dtname = os.path.basename(dtb) append_conf_section(file, cnt, dtname, atf_cnt) -- 2.18.0

3 5

[U-Boot] [PATCH v5] spi: Add SPI driver for MT76xx SoCs
by Stefan Roese 04 Oct '18

04 Oct '18

This patch adds the SPI driver for the MediaTek MT7688 SoC (and derivates). Its been tested on the LinkIt Smart 7688 and the Gardena Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart Gateway additionally with an SPI NAND on CS1. Note that the SPI controller only supports a max transfer size of 32 bytes. This driver implementes a workaround to enable bigger xfer sizes to speed up the transfer especially for the SPI NAND support. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Jagan Teki <jagan(a)openedev.com> Cc: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> Cc: Piotr Dymacz <pepe2k(a)gmail.com> Reviewed-by: Jagan Teki <jagan(a)openedev.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> --- v5: - Move file name and function / macro names to mt7621 instead of the generic mt76xx name as the MT7620 has a different SPI controller integrated (as explained by Piotr) - Added an more extensive text about the supported SoC versions to the Kconfig help text v4: - Rename functions and macros from mt7621 to mt76xx to better reflect the SoC usage and match the driver name v3: - Drop IO wrappers completely as suggested by Daniel - Read "clock-frequency" DT property instead of using CONFIG_SYS_MIPS_TIMER_FREQ v2: - Add some macros instead of hardcoded numbers - Move compatible DT struct down in the file drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/mt7621_spi.c | 312 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 321 insertions(+) create mode 100644 drivers/spi/mt7621_spi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 9fbd26740d..2197d9fc3f 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -116,6 +116,14 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config MT7621_SPI + bool "MediaTek MT7621 SPI driver" + depends on ARCH_MT7620 + help + Enable the MT7621 SPI driver. This driver can be used to access + the SPI NOR flash on platforms embedding this Ralink / MediaTek + SPI core, like MT7621/7628/7688. + config MVEBU_A3700_SPI bool "Marvell Armada 3700 SPI driver" select CLK_ARMADA_3720 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index bdb5b5a02f..67957175ff 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o +obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o diff --git a/drivers/spi/mt7621_spi.c b/drivers/spi/mt7621_spi.c new file mode 100644 index 0000000000..107e58f657 --- /dev/null +++ b/drivers/spi/mt7621_spi.c @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Stefan Roese <sr(a)denx.de> + * + * Derived from the Linux driver version drivers/spi/spi-mt7621.c + * Copyright (C) 2011 Sergiy <piratfm(a)gmail.com> + * Copyright (C) 2011-2013 Gabor Juhos <juhosg(a)openwrt.org> + * Copyright (C) 2014-2015 Felix Fietkau <nbd(a)nbd.name> + */ + +#include <common.h> +#include <dm.h> +#include <spi.h> +#include <wait_bit.h> +#include <linux/io.h> + +#define SPI_MSG_SIZE_MAX 32 /* SPI message chunk size */ +/* Enough for SPI NAND page read / write with page size 2048 bytes */ +#define SPI_MSG_SIZE_OVERALL (2048 + 16) + +#define MT7621_SPI_TRANS 0x00 +#define MT7621_SPI_TRANS_START BIT(8) +#define MT7621_SPI_TRANS_BUSY BIT(16) + +#define MT7621_SPI_OPCODE 0x04 +#define MT7621_SPI_DATA0 0x08 +#define MT7621_SPI_DATA4 0x18 +#define MT7621_SPI_MASTER 0x28 +#define MT7621_SPI_MOREBUF 0x2c +#define MT7621_SPI_POLAR 0x38 + +#define MT7621_LSB_FIRST BIT(3) +#define MT7621_CPOL BIT(4) +#define MT7621_CPHA BIT(5) + +#define MASTER_MORE_BUFMODE BIT(2) +#define MASTER_RS_CLK_SEL GENMASK(27, 16) +#define MASTER_RS_CLK_SEL_SHIFT 16 +#define MASTER_RS_SLAVE_SEL GENMASK(31, 29) + +struct mt7621_spi { + void __iomem *base; + unsigned int sys_freq; + u32 data[(SPI_MSG_SIZE_OVERALL / 4) + 1]; + int tx_len; +}; + +static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex) +{ + setbits_le32(rs->base + MT7621_SPI_MASTER, + MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE); +} + +static void mt7621_spi_set_cs(struct mt7621_spi *rs, int cs, int enable) +{ + u32 val = 0; + + debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" : "disable"); + if (enable) + val = BIT(cs); + iowrite32(val, rs->base + MT7621_SPI_POLAR); +} + +static int mt7621_spi_set_mode(struct udevice *bus, uint mode) +{ + struct mt7621_spi *rs = dev_get_priv(bus); + u32 reg; + + debug("%s: mode=0x%08x\n", __func__, mode); + reg = ioread32(rs->base + MT7621_SPI_MASTER); + + reg &= ~MT7621_LSB_FIRST; + if (mode & SPI_LSB_FIRST) + reg |= MT7621_LSB_FIRST; + + reg &= ~(MT7621_CPHA | MT7621_CPOL); + switch (mode & (SPI_CPOL | SPI_CPHA)) { + case SPI_MODE_0: + break; + case SPI_MODE_1: + reg |= MT7621_CPHA; + break; + case SPI_MODE_2: + reg |= MT7621_CPOL; + break; + case SPI_MODE_3: + reg |= MT7621_CPOL | MT7621_CPHA; + break; + } + iowrite32(reg, rs->base + MT7621_SPI_MASTER); + + return 0; +} + +static int mt7621_spi_set_speed(struct udevice *bus, uint speed) +{ + struct mt7621_spi *rs = dev_get_priv(bus); + u32 rate; + u32 reg; + + debug("%s: speed=%d\n", __func__, speed); + rate = DIV_ROUND_UP(rs->sys_freq, speed); + debug("rate:%u\n", rate); + + if (rate > 4097) + return -EINVAL; + + if (rate < 2) + rate = 2; + + reg = ioread32(rs->base + MT7621_SPI_MASTER); + reg &= ~MASTER_RS_CLK_SEL; + reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT; + iowrite32(reg, rs->base + MT7621_SPI_MASTER); + + return 0; +} + +static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs) +{ + int ret; + + ret = wait_for_bit_le32(rs->base + MT7621_SPI_TRANS, + MT7621_SPI_TRANS_BUSY, 0, 10, 0); + if (ret) + pr_err("Timeout in %s!\n", __func__); + + return ret; +} + +static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct mt7621_spi *rs = dev_get_priv(bus); + const u8 *tx_buf = dout; + u8 *ptr = (u8 *)dout; + u8 *rx_buf = din; + int total_size = bitlen >> 3; + int chunk_size; + int rx_len = 0; + u32 data[(SPI_MSG_SIZE_MAX / 4) + 1] = { 0 }; + u32 val; + int i; + + debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din, + total_size, flags); + + /* + * This driver only supports half-duplex, so complain and bail out + * upon full-duplex messages + */ + if (dout && din) { + printf("Only half-duplex SPI transfer supported\n"); + return -EIO; + } + + if (dout) { + debug("TX-DATA: "); + for (i = 0; i < total_size; i++) + debug("%02x ", *ptr++); + debug("\n"); + } + + mt7621_spi_wait_till_ready(rs); + + /* + * Set CS active upon start of SPI message. This message can + * be split upon multiple calls to this xfer function + */ + if (flags & SPI_XFER_BEGIN) + mt7621_spi_set_cs(rs, spi_chip_select(dev), 1); + + while (total_size > 0) { + /* Don't exceed the max xfer size */ + chunk_size = min_t(int, total_size, SPI_MSG_SIZE_MAX); + + /* + * We might have some TX data buffered from the last xfer + * message. Make sure, that this does not exceed the max + * xfer size + */ + if (rs->tx_len > 4) + chunk_size -= rs->tx_len; + if (din) + rx_len = chunk_size; + + if (tx_buf) { + /* Check if this message does not exceed the buffer */ + if ((chunk_size + rs->tx_len) > SPI_MSG_SIZE_OVERALL) { + printf("TX message size too big (%d)\n", + chunk_size + rs->tx_len); + return -EMSGSIZE; + } + + /* + * Write all TX data into internal buffer to collect + * all TX messages into one buffer (might be split into + * multiple calls to this function) + */ + for (i = 0; i < chunk_size; i++, rs->tx_len++) { + rs->data[rs->tx_len / 4] |= + tx_buf[i] << (8 * (rs->tx_len & 3)); + } + } + + if (flags & SPI_XFER_END) { + /* Write TX data into controller */ + if (rs->tx_len) { + rs->data[0] = swab32(rs->data[0]); + if (rs->tx_len < 4) + rs->data[0] >>= (4 - rs->tx_len) * 8; + + for (i = 0; i < rs->tx_len; i += 4) { + iowrite32(rs->data[i / 4], rs->base + + MT7621_SPI_OPCODE + i); + } + } + + /* Write length into controller */ + val = (min_t(int, rs->tx_len, 4) * 8) << 24; + if (rs->tx_len > 4) + val |= (rs->tx_len - 4) * 8; + val |= (rx_len * 8) << 12; + iowrite32(val, rs->base + MT7621_SPI_MOREBUF); + + /* Start the xfer */ + setbits_le32(rs->base + MT7621_SPI_TRANS, + MT7621_SPI_TRANS_START); + + /* Wait until xfer is finished on bus */ + mt7621_spi_wait_till_ready(rs); + + /* Reset TX length and TX buffer for next xfer */ + rs->tx_len = 0; + memset(rs->data, 0, sizeof(rs->data)); + } + + for (i = 0; i < rx_len; i += 4) + data[i / 4] = ioread32(rs->base + MT7621_SPI_DATA0 + i); + + if (rx_len) { + debug("RX-DATA: "); + for (i = 0; i < rx_len; i++) { + rx_buf[i] = data[i / 4] >> (8 * (i & 3)); + debug("%02x ", rx_buf[i]); + } + debug("\n"); + } + + if (tx_buf) + tx_buf += chunk_size; + if (rx_buf) + rx_buf += chunk_size; + total_size -= chunk_size; + } + + /* Wait until xfer is finished on bus and de-assert CS */ + mt7621_spi_wait_till_ready(rs); + if (flags & SPI_XFER_END) + mt7621_spi_set_cs(rs, spi_chip_select(dev), 0); + + return 0; +} + +static int mt7621_spi_probe(struct udevice *dev) +{ + struct mt7621_spi *rs = dev_get_priv(dev); + + rs->base = dev_remap_addr(dev); + if (!rs->base) + return -EINVAL; + + /* + * Read input clock via DT for now. At some point this should be + * replaced by implementing a clock driver for this SoC and getting + * the SPI frequency via this clock driver. + */ + rs->sys_freq = dev_read_u32_default(dev, "clock-frequency", 0); + if (!rs->sys_freq) { + printf("Please provide clock-frequency!\n"); + return -EINVAL; + } + + mt7621_spi_reset(rs, 0); + + return 0; +} + +static const struct dm_spi_ops mt7621_spi_ops = { + .set_mode = mt7621_spi_set_mode, + .set_speed = mt7621_spi_set_speed, + .xfer = mt7621_spi_xfer, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + +static const struct udevice_id mt7621_spi_ids[] = { + { .compatible = "ralink,mt7621-spi" }, + { } +}; + +U_BOOT_DRIVER(mt7621_spi) = { + .name = "mt7621_spi", + .id = UCLASS_SPI, + .of_match = mt7621_spi_ids, + .ops = &mt7621_spi_ops, + .priv_auto_alloc_size = sizeof(struct mt7621_spi), + .probe = mt7621_spi_probe, +}; -- 2.18.0

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[U-Boot] [PATCH] mtd: nand: spi: Add Gigadevice SPI NAND support
by Stefan Roese 04 Oct '18

04 Oct '18

This patch adds support for Gigadevices SPI NAND device to the new SPI NAND infrastructure in U-Boot. Currently only the 128MiB GD5F1GQ4UC device is supported. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Miquel Raynal <miquel.raynal(a)bootlin.com> Cc: Boris Brezillon <boris.brezillon(a)bootlin.com> Cc: Jagan Teki <jagan(a)openedev.com> --- Miquel, I somehow always forgot to send this Gigadevice support patch in my last series versions. This is the chip I'm currently testing with. Either please fold it into your series, if you re-send it at a later time. Or we should add it on top. Of course only if nobody has any objections or change requests. Thanks, Stefan drivers/mtd/nand/spi/Makefile | 2 +- drivers/mtd/nand/spi/core.c | 1 + drivers/mtd/nand/spi/gigadevice.c | 135 ++++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 1 + 4 files changed, 138 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/nand/spi/gigadevice.c diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile index a66edd9199..dd6bacae34 100644 --- a/drivers/mtd/nand/spi/Makefile +++ b/drivers/mtd/nand/spi/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -spinand-objs := core.o macronix.o micron.o winbond.o +spinand-objs := core.o gigadevice.o macronix.o micron.o winbond.o obj-$(CONFIG_MTD_SPI_NAND) += spinand.o diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 362d104846..cb8ffa3fa9 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -830,6 +830,7 @@ static const struct nand_ops spinand_ops = { }; static const struct spinand_manufacturer *spinand_manufacturers[] = { + &gigadevice_spinand_manufacturer, &macronix_spinand_manufacturer, &micron_spinand_manufacturer, &winbond_spinand_manufacturer, diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c new file mode 100644 index 0000000000..0bade20808 --- /dev/null +++ b/drivers/mtd/nand/spi/gigadevice.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Stefan Roese <sr(a)denx.de> + * + * Derived from drivers/mtd/nand/spi/micron.c + * Copyright (c) 2016-2017 Micron Technology, Inc. + */ + +#ifndef __UBOOT__ +#include <linux/device.h> +#include <linux/kernel.h> +#endif +#include <linux/mtd/spinand.h> + +#define SPINAND_MFR_GIGADEVICE 0xc8 + +#define GIGADEVICE_STATUS_ECC_MASK GENMASK(5, 4) +#define GIGADEVICE_STATUS_ECC_NO_BITFLIPS (0 << 4) +#define GIGADEVICE_STATUS_ECC_1TO7_BITFLIPS (1 << 4) +#define GIGADEVICE_STATUS_ECC_8_BITFLIPS (3 << 4) + +static SPINAND_OP_VARIANTS(read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); + +static SPINAND_OP_VARIANTS(write_cache_variants, + SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), + SPINAND_PROG_LOAD(true, 0, NULL, 0)); + +static SPINAND_OP_VARIANTS(update_cache_variants, + SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), + SPINAND_PROG_LOAD(false, 0, NULL, 0)); + +static int gd5f1gq4u_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + region->offset = 64; + region->length = 64; + + return 0; +} + +static int gd5f1gq4u_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) +{ + if (section) + return -ERANGE; + + /* Reserve 2 bytes for the BBM. */ + region->offset = 2; + region->length = 62; + + return 0; +} + +static const struct mtd_ooblayout_ops gd5f1gq4u_ooblayout = { + .ecc = gd5f1gq4u_ooblayout_ecc, + .free = gd5f1gq4u_ooblayout_free, +}; + +static int gd5f1gq4u_ecc_get_status(struct spinand_device *spinand, + u8 status) +{ + if (status) + debug("%s (%d): status=%02x\n", __func__, __LINE__, status); + + switch (status & GIGADEVICE_STATUS_ECC_MASK) { + case STATUS_ECC_NO_BITFLIPS: + return 0; + + case GIGADEVICE_STATUS_ECC_1TO7_BITFLIPS: + return 7; + + case GIGADEVICE_STATUS_ECC_8_BITFLIPS: + return 8; + + case STATUS_ECC_UNCOR_ERROR: + return -EBADMSG; + + default: + break; + } + + return -EINVAL; +} + +static const struct spinand_info gigadevice_spinand_table[] = { + SPINAND_INFO("GD5F1GQ4UC", 0xd1, + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), + NAND_ECCREQ(8, 2048), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), + 0, + SPINAND_ECCINFO(&gd5f1gq4u_ooblayout, + gd5f1gq4u_ecc_get_status)), +}; + +static int gigadevice_spinand_detect(struct spinand_device *spinand) +{ + u8 *id = spinand->id.data; + int ret; + + /* + * Gigadevice SPI NAND read ID need a dummy byte, + * so the first byte in raw_id is dummy. + */ + if (id[1] != SPINAND_MFR_GIGADEVICE) + return 0; + + ret = spinand_match_and_init(spinand, gigadevice_spinand_table, + ARRAY_SIZE(gigadevice_spinand_table), + id[2]); + if (ret) + return ret; + + return 1; +} + +static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { + .detect = gigadevice_spinand_detect, +}; + +const struct spinand_manufacturer gigadevice_spinand_manufacturer = { + .id = SPINAND_MFR_GIGADEVICE, + .name = "GigaDevice", + .ops = &gigadevice_spinand_manuf_ops, +}; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 8c9c756179..be01e1e82e 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -201,6 +201,7 @@ struct spinand_manufacturer { }; /* SPI NAND manufacturers */ +extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; extern const struct spinand_manufacturer macronix_spinand_manufacturer; extern const struct spinand_manufacturer micron_spinand_manufacturer; extern const struct spinand_manufacturer winbond_spinand_manufacturer; -- 2.18.0

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[U-Boot] [PATCH] sf: Add XMC xm25qh64a and xm25qh128a entries
by Stefan Roese 04 Oct '18

04 Oct '18

This patch adds support for 2 new XMC (Wuhan Xinxin Semiconductor Manufacturing Corp) SPI NOR chips. This support can be enabled by selecting the SPI_FLASH_XMC Kconfig option. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Jagan Teki <jagan(a)openedev.com> --- drivers/mtd/spi/Kconfig | 6 ++++++ drivers/mtd/spi/spi_flash_ids.c | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 5738cd66e8..a76154232a 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -100,6 +100,12 @@ config SPI_FLASH_WINBOND help Add support for various Winbond SPI flash chips (W25xxx) +config SPI_FLASH_XMC + bool "XMC SPI flash support" + help + Add support for various XMC (Wuhan Xinxin Semiconductor + Manufacturing Corp.) SPI flash chips (XM25xxx) + endif config SPI_FLASH_USE_4K_SECTORS diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index e662e4b42e..ad0a0c8150 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -188,6 +188,10 @@ const struct spi_flash_info spi_flash_ids[] = { {"w25q128jv", INFO(0xef7018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, {"w25q256fw", INFO(0xef6019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, {"w25q256jw", INFO(0xef7019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, +#endif +#ifdef CONFIG_SPI_FLASH_XMC /* Wuhan Xinxin Semiconductor Manufacturing Corp */ + { "xm25qh64a", INFO(0x207017, 0x0, 64 * 1024, 128, SECT_4K | RD_DUAL | RD_QUAD) }, + { "xm25qh128a", INFO(0x207018, 0x0, 64 * 1024, 256, SECT_4K | RD_DUAL | RD_QUAD) }, #endif {}, /* Empty entry to terminate the list */ /* -- 2.18.0

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[U-Boot] [PATCH v3 00/17] riscv: Add QEMU virt board support
by Bin Meng 04 Oct '18

04 Oct '18

This series adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. Some existing RISC-V codes have been changed to make it easily to support new targets. Some spotted coding style issues are fixed. This series is available at u-boot-x86/riscv-working for testing. Changes in v3: - net patch to print the relocation address in cmd 'bdinfo' - new patch to imply DM support for some common drivers - reword the reset message a little, and call hang() in the end Changes in v2: - Change Linux kernel entry parameters' type to support 32/64 bit - new patch to remove CSR read/write defines in encoding.h - new patch to pass mhartid CSR value to kernel - new patch to move do_reset() to a common place Bin Meng (17): riscv: kconfig: Normalize architecture name spelling riscv: Remove setup.h riscv: bootm: Correct the 1st kernel argument to hart id riscv: Remove mach type riscv: cmd: bdinfo: Print the relocation address riscv: Move the linker script to the CPU root directory riscv: Fix coding style issues in the linker script riscv: Explicitly pass -march and -mabi to the compiler riscv: Add a helper routine to print CPU information riscv: Remove CSR read/write defines in encoding.h riscv: bootm: Pass mhartid CSR value to kernel riscv: Make start.S available for all targets riscv: ae350: Clean up mixed tabs and spaces in the dts riscv: kconfig: Select DM and OF_CONTROL riscv: kconfig: Imply DM support for some common drivers riscv: Add QEMU virt board support riscv: Move do_reset() to a common place arch/Kconfig | 14 ++- arch/riscv/Kconfig | 10 +- arch/riscv/Makefile | 3 +- arch/riscv/config.mk | 8 +- arch/riscv/cpu/Makefile | 7 ++ arch/riscv/cpu/ax25/Makefile | 2 - arch/riscv/cpu/ax25/cpu.c | 9 -- arch/riscv/cpu/cpu.c | 49 ++++++++ arch/riscv/cpu/qemu/Makefile | 6 + arch/riscv/cpu/qemu/cpu.c | 21 ++++ arch/riscv/cpu/qemu/dram.c | 17 +++ arch/riscv/cpu/{ax25 => }/start.S | 0 arch/riscv/cpu/{ax25 => }/u-boot.lds | 60 +++++----- arch/riscv/dts/ae350.dts | 177 +++++++++++++++-------------- arch/riscv/include/asm/bootm.h | 13 --- arch/riscv/include/asm/csr.h | 124 ++++++++++++++++++++ arch/riscv/include/asm/encoding.h | 50 +------- arch/riscv/include/asm/mach-types.h | 29 ----- arch/riscv/include/asm/setup.h | 194 -------------------------------- arch/riscv/include/asm/u-boot.h | 1 - arch/riscv/lib/Makefile | 1 + arch/riscv/lib/bootm.c | 20 +--- arch/riscv/lib/reset.c | 17 +++ board/AndesTech/ax25-ae350/ax25-ae350.c | 2 - board/emulation/qemu-riscv/Kconfig | 22 ++++ board/emulation/qemu-riscv/MAINTAINERS | 7 ++ board/emulation/qemu-riscv/Makefile | 5 + board/emulation/qemu-riscv/qemu-riscv.c | 23 ++++ cmd/bdinfo.c | 3 +- configs/ax25-ae350_defconfig | 10 -- configs/qemu-riscv32_defconfig | 6 + configs/qemu-riscv64_defconfig | 7 ++ doc/README.qemu-riscv | 46 ++++++++ include/configs/qemu-riscv.h | 21 ++++ 34 files changed, 538 insertions(+), 446 deletions(-) create mode 100644 arch/riscv/cpu/Makefile create mode 100644 arch/riscv/cpu/cpu.c create mode 100644 arch/riscv/cpu/qemu/Makefile create mode 100644 arch/riscv/cpu/qemu/cpu.c create mode 100644 arch/riscv/cpu/qemu/dram.c rename arch/riscv/cpu/{ax25 => }/start.S (100%) rename arch/riscv/cpu/{ax25 => }/u-boot.lds (54%) delete mode 100644 arch/riscv/include/asm/bootm.h create mode 100644 arch/riscv/include/asm/csr.h delete mode 100644 arch/riscv/include/asm/mach-types.h delete mode 100644 arch/riscv/include/asm/setup.h create mode 100644 arch/riscv/lib/reset.c create mode 100644 board/emulation/qemu-riscv/Kconfig create mode 100644 board/emulation/qemu-riscv/MAINTAINERS create mode 100644 board/emulation/qemu-riscv/Makefile create mode 100644 board/emulation/qemu-riscv/qemu-riscv.c create mode 100644 configs/qemu-riscv32_defconfig create mode 100644 configs/qemu-riscv64_defconfig create mode 100644 doc/README.qemu-riscv create mode 100644 include/configs/qemu-riscv.h -- 2.7.4

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