August 2018 - U-Boot

[U-Boot] [PATCH v2 1/2] power: regulator: add driver for the FAN53555 family
by Philipp Tomsich 16 Nov '18

16 Nov '18

This adds a driver for the FAN53555 family of regulators. While these devices support a 'normal' and 'suspend' mode (controlled via an external pin) to switch between two programmable voltages, this incarnation of the driver assumes that the device is always operating in 'normal' mode. Only setting/reading the programmed voltage is supported at this time and the following device functionality remains unsupported: - switching the selected voltage (via a GPIO) - disabling the voltage output via software-control This matches the functionality of the Linux driver. Tested on a RK3399-Q7 (with 'option 5' devices): setting voltages from the U-Boot shell and verifying output voltages on the board. Signed-off-by: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger(a)theobroma-systems.com> --- Changes in v2: - adapted documentation on the device-tree binding from Linux doc/device-tree-bindings/regulator/fan53555.txt | 23 +++ drivers/power/regulator/Kconfig | 14 ++ drivers/power/regulator/Makefile | 1 + drivers/power/regulator/fan53555.c | 255 ++++++++++++++++++++++++ 4 files changed, 293 insertions(+) create mode 100644 doc/device-tree-bindings/regulator/fan53555.txt create mode 100644 drivers/power/regulator/fan53555.c diff --git a/doc/device-tree-bindings/regulator/fan53555.txt b/doc/device-tree-bindings/regulator/fan53555.txt new file mode 100644 index 0000000..b183738 --- /dev/null +++ b/doc/device-tree-bindings/regulator/fan53555.txt @@ -0,0 +1,23 @@ +Binding for Fairchild FAN53555 regulators + +Required properties: + - compatible: "fcs,fan53555" + - reg: I2C address + +Optional properties: + - fcs,suspend-voltage-selector: declare which of the two available + voltage selector registers should be used for the suspend + voltage. The other one is used for the runtime voltage setting + Possible values are either <0> or <1> + - vin-supply: regulator supplying the vin pin + +Example: + + regulator@40 { + compatible = "fcs,fan53555"; + regulator-name = "fan53555"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&parent_reg>; + fcs,suspend-voltage-selector = <1>; + }; diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index 8892fa1..c26a765 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -69,6 +69,20 @@ config DM_REGULATOR_MAX77686 features for REGULATOR MAX77686. The driver implements get/set api for: value, enable and mode. +config DM_REGULATOR_FAN53555 + bool "Enable Driver Model for REGULATOR FAN53555" + depends on DM_REGULATOR && DM_I2C + ---help--- + This config enables implementation of driver-model regulator uclass + features for the FAN53555 regulator. The FAN53555 is a (family of) + single-output regulators that supports transitioning between two + different output voltages based on an voltage selection pin. + + The driver implements a get/set api for the voltage of the 'normal + mode' voltage only. Switching to 'suspend mode' (i.e. the alternate + voltage), disabling output via software, or switching the mode is + not supported by this driver (at this time). + config DM_REGULATOR_FIXED bool "Enable Driver Model for REGULATOR Fixed value" depends on DM_REGULATOR diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index 6c149a9..21040ea 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o +obj-$(CONFIG_$(SPL_)DM_REGULATOR_FAN53555) += fan53555.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o obj-$(CONFIG_REGULATOR_RK8XX) += rk8xx.o diff --git a/drivers/power/regulator/fan53555.c b/drivers/power/regulator/fan53555.c new file mode 100644 index 0000000..3f0b4e9 --- /dev/null +++ b/drivers/power/regulator/fan53555.c @@ -0,0 +1,255 @@ +/* + * (C) 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <bitfield.h> +#include <errno.h> +#include <dm.h> +#include <fdtdec.h> +#include <i2c.h> +#include <asm/gpio.h> +#include <power/pmic.h> +#include <power/regulator.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * The voltage ramp (i.e. minimum voltage and step) is defined by the + * combination of 2 nibbles: DIE_ID and DIE_REV. + * + * See http://www.onsemi.com/pub/Collateral/FAN53555-D.pdf for details. + */ +static const struct { + u8 die_id; + u8 die_rev; + u32 vsel_min; + u32 vsel_step; +} ic_types[] = { + { 0x0, 0x3, 600000, 10000 }, /* Option 00 */ + { 0x0, 0xf, 800000, 10000 }, /* Option 13 */ + { 0x0, 0xc, 600000, 12500 }, /* Option 23 */ + { 0x1, 0x3, 600000, 10000 }, /* Option 01 */ + { 0x3, 0x3, 600000, 10000 }, /* Option 03 */ + { 0x4, 0xf, 603000, 12826 }, /* Option 04 */ + { 0x5, 0x3, 600000, 10000 }, /* Option 05 */ + { 0x8, 0x1, 600000, 10000 }, /* Option 08 */ + { 0x8, 0xf, 600000, 10000 }, /* Option 08 */ + { 0xc, 0xf, 603000, 12826 }, /* Option 09 */ +}; + +/* I2C-accessible byte-sized registers */ +enum { + /* Voltage setting */ + FAN53555_VSEL0 = 0x00, + FAN53555_VSEL1, + /* Control register */ + FAN53555_CONTROL, + /* IC Type */ + FAN53555_ID1, + /* IC mask version */ + FAN53555_ID2, + /* Monitor register */ + FAN53555_MONITOR, +}; + +struct fan53555_platdata { + /* Voltage setting register */ + unsigned int vol_reg; + unsigned int sleep_reg; + +}; + +struct fan53555_priv { + /* IC Vendor */ + unsigned int vendor; + /* IC Type and Rev */ + unsigned int die_id; + unsigned int die_rev; + /* Voltage range and step(linear) */ + unsigned int vsel_min; + unsigned int vsel_step; + /* Voltage slew rate limiting */ + unsigned int slew_rate; + /* Sleep voltage cache */ + unsigned int sleep_vol_cache; +}; + +static int fan53555_write(struct udevice *dev, uint reg, u8 *buff, int len) +{ + int ret; + + ret = dm_i2c_write(dev, reg, buff, len); + if (ret) { + debug("%s: %s() failed to read reg %d\n", + dev->name, __func__, reg); + return ret; + } + + return 0; +} + +static int fan53555_read(struct udevice *dev, uint reg, u8 *buff, int len) +{ + int ret; + + ret = dm_i2c_read(dev, reg, buff, len); + if (ret) { + debug("%s: %s() failed to read reg %d\n", + dev->name, __func__, reg); + return ret; + } + + return 0; +} + +static int fan53555_regulator_ofdata_to_platdata(struct udevice *dev) +{ + struct fan53555_platdata *dev_pdata = dev_get_platdata(dev); + struct dm_regulator_uclass_platdata *uc_pdata; + u32 sleep_vsel; + + uc_pdata = dev_get_uclass_platdata(dev); + if (!uc_pdata) + return -ENXIO; + + /* This is a buck regulator */ + uc_pdata->type = REGULATOR_TYPE_BUCK; + + sleep_vsel = dev_read_u32_default(dev, "fcs,suspend-voltage-selector", + FAN53555_VSEL1); + + /* + * Depending on the device-tree settings, the 'normal mode' + * voltage is either controlled by VSEL0 or VSEL1. + */ + switch (sleep_vsel) { + case FAN53555_VSEL0: + dev_pdata->sleep_reg = FAN53555_VSEL0; + dev_pdata->vol_reg = FAN53555_VSEL1; + break; + case FAN53555_VSEL1: + dev_pdata->sleep_reg = FAN53555_VSEL1; + dev_pdata->vol_reg = FAN53555_VSEL0; + break; + default: + pr_err("%s: invalid vsel id %d\n", dev->name, sleep_vsel); + return -EINVAL; + } + + return 0; +} + +static int fan53555_regulator_get_value(struct udevice *dev) +{ + struct fan53555_platdata *pdata = dev_get_platdata(dev); + struct fan53555_priv *priv = dev_get_priv(dev); + u8 vol; + int voltage; + + /* We only support a single voltage selector (i.e. 'normal' mode). */ + fan53555_read(dev, pdata->vol_reg, &vol, 1); + voltage = priv->vsel_min + (vol & 0x3f) * priv->vsel_step; + + debug("%s: %d uV\n", __func__, voltage); + return voltage; +} + +static int fan53555_regulator_set_value(struct udevice *dev, int uV) +{ + struct fan53555_platdata *pdata = dev_get_platdata(dev); + struct fan53555_priv *priv = dev_get_priv(dev); + u8 vol, oldbits, newbits; + + vol = (uV - priv->vsel_min) / priv->vsel_step; + fan53555_read(dev, pdata->vol_reg, &oldbits, 1); + newbits = bitfield_replace(oldbits, 0, 6, vol); + fan53555_write(dev, pdata->vol_reg, &newbits, 1); + + debug("%s: uV=%d; reg %d: %02x -> %02x\n", + __func__, uV, pdata->vol_reg, oldbits, newbits); + + return 0; +} + +static int fan53555_voltages_setup(struct udevice *dev) +{ + struct fan53555_priv *priv = dev_get_priv(dev); + struct dm_regulator_uclass_platdata *uc_pdata; + int i; + + uc_pdata = dev_get_uclass_platdata(dev); + if (!uc_pdata) + return -ENXIO; + + /* Init voltage range and step */ + for (i = 0; i < ARRAY_SIZE(ic_types); ++i) { + if (ic_types[i].die_id != priv->die_id) + continue; + + if (ic_types[i].die_rev != priv->die_rev) + continue; + + priv->vsel_min = ic_types[i].vsel_min; + priv->vsel_step = ic_types[i].vsel_step; + + return 0; + } + + pr_err("%s: %s: die id %d rev %d not supported!\n", + dev->name, __func__, priv->die_id, priv->die_rev); + return -EINVAL; +} + +enum { + DIE_ID_SHIFT = 0, + DIE_ID_WIDTH = 4, + DIE_REV_SHIFT = 0, + DIE_REV_WIDTH = 4, +}; + + +static int fan53555_probe(struct udevice *dev) +{ + struct fan53555_priv *priv = dev_get_priv(dev); + u8 id1, id2; + + /* read chip id: vendor, die-id and die-revision */ + fan53555_read(dev, FAN53555_ID1, &id1, 1); + fan53555_read(dev, FAN53555_ID2, &id2, 1); + + priv->vendor = bitfield_extract(id1, 5, 3); + priv->die_id = id1 & GENMASK(3, 0); + priv->die_rev = id2 & GENMASK(3, 0); + + if (fan53555_voltages_setup(dev) < 0) + return -ENODATA; + + debug("%s: FAN53555 option %d rev %d detected\n", + __func__, priv->die_id, priv->die_rev); + + return 0; +} + +static const struct dm_regulator_ops fan53555_regulator_ops = { + .get_value = fan53555_regulator_get_value, + .set_value = fan53555_regulator_set_value, +}; + +static const struct udevice_id fan53555_regulator_ids[] = { + { .compatible = "fcs,fan53555" }, + { }, +}; + +U_BOOT_DRIVER(fan53555_regulator) = { + .name = "fan53555 regulator", + .id = UCLASS_REGULATOR, + .ops = &fan53555_regulator_ops, + .of_match = fan53555_regulator_ids, + .ofdata_to_platdata = fan53555_regulator_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct fan53555_platdata), + .priv_auto_alloc_size = sizeof(struct fan53555_priv), + .probe = fan53555_probe, +}; -- 2.1.4

4 7

[U-Boot] [PATCH] common: add board specific hook for os preboot config
by Gerard Salvatella 15 Nov '18

15 Nov '18

Some boards require specific configuration prior to booting the kernel. For instance, our boards require shutting down the display to avoid fading transitions before the drivers are reloaded by the kernel. This could be facilitated by adding an extra hook during the os booting process. Signed-off-by: Gerard Salvatella <gerard.salvatella(a)toradex.com> --- common/bootm_os.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/common/bootm_os.c b/common/bootm_os.c index f4bd905909..1e7af56b64 100644 --- a/common/bootm_os.c +++ b/common/bootm_os.c @@ -505,9 +505,16 @@ __weak void arch_preboot_os(void) /* please define platform specific arch_preboot_os() */ } +/* Allow for board specific config before we boot */ +__weak void board_preboot_os(void) +{ + /* please define board specific board_preboot_os() */ +} + int boot_selected_os(int argc, char * const argv[], int state, bootm_headers_t *images, boot_os_fn *boot_fn) { + board_preboot_os(); arch_preboot_os(); boot_fn(state, argc, argv, images); -- 2.18.0 [Toradex Logo]<http://toradex.com> Global Leader in Arm® Embedded Computer Modules Choose Us<https://www.toradex.com/how-to-choose-system-computer-on-module-partner> | Products<https://www.toradex.com/products> | Developer Center<http://developer.toradex.com/> | Community<https://www.toradex.com/community> | Careers<https://careers.toradex.com/> Meet our engineers at<https://www.toradex.com/events>:<https://www.toradex.com/events> - Linux Developer Conference, Brazil, Aug 25-26, 2018 - NXP Technology Days 2018, United States, Aug 28, 2018 - IoT Latin America, Brazil, Aug 29-30, 2018

5 9

[U-Boot] [PATCH] common: build ymodem only on need
by Jun Nie 10 Nov '18

10 Nov '18

Build ymodem only on need to shrink spl image size. Signed-off-by: Jun Nie <jun.nie(a)linaro.org> --- common/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common/Makefile b/common/Makefile index c7bde23..0614348 100644 --- a/common/Makefile +++ b/common/Makefile @@ -133,4 +133,5 @@ obj-y += command.o obj-$(CONFIG_$(SPL_)LOG) += log.o obj-$(CONFIG_$(SPL_)LOG_CONSOLE) += log_console.o obj-y += s_record.o -obj-y += xyzModem.o +obj-$(CONFIG_CMD_LOADB) += xyzModem.o +obj-$(CONFIG_$(SPL_TPL_)YMODEM_SUPPORT) += xyzModem.o -- 1.9.1

2 1

[U-Boot] [PATCH] spi: Zap mpc8xx_spi driver
by Jagan Teki 06 Nov '18

06 Nov '18

- Driver not used by any boards - No update on 'dm conversion' Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- drivers/spi/Kconfig | 6 - drivers/spi/Makefile | 1 - drivers/spi/mpc8xx_spi.c | 336 ----------------------------------------------- 3 files changed, 343 deletions(-) delete mode 100644 drivers/spi/mpc8xx_spi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 235a8c7d73..fd3f115ccf 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -274,12 +274,6 @@ config LPC32XX_SSP help Enable support for SPI on LPC32xx -config MPC8XX_SPI - bool "MPC8XX SPI Driver" - depends on 8xx - help - Enable support for SPI on MPC8XX - config MPC8XXX_SPI bool "MPC8XXX SPI Driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 4b6000fd9a..f104836630 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -31,7 +31,6 @@ obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o -obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o diff --git a/drivers/spi/mpc8xx_spi.c b/drivers/spi/mpc8xx_spi.c deleted file mode 100644 index b5bd558526..0000000000 --- a/drivers/spi/mpc8xx_spi.c +++ /dev/null @@ -1,336 +0,0 @@ -/* - * Copyright (c) 2001 Navin Boppuri / Prashant Patel - * <nboppuri(a)trinetcommunication.com>, - * <pmpatel(a)trinetcommunication.com> - * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen(a)icn.siemens.de> - * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd(a)denx.de>. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * MPC8xx CPM SPI interface. - * - * Parts of this code are probably not portable and/or specific to - * the board which I used for the tests. Please send fixes/complaints - * to wd(a)denx.de - * - */ - -#include <common.h> -#include <mpc8xx.h> -#include <commproc.h> -#include <linux/ctype.h> -#include <malloc.h> -#include <post.h> -#include <serial.h> - -#define SPI_EEPROM_WREN 0x06 -#define SPI_EEPROM_RDSR 0x05 -#define SPI_EEPROM_READ 0x03 -#define SPI_EEPROM_WRITE 0x02 - -/* --------------------------------------------------------------- - * Offset for initial SPI buffers in DPRAM: - * We need a 520 byte scratch DPRAM area to use at an early stage. - * It is used between the two initialization calls (spi_init_f() - * and spi_init_r()). - * The value 0xb00 makes it far enough from the start of the data - * area (as well as from the stack pointer). - * --------------------------------------------------------------- */ -#ifndef CONFIG_SYS_SPI_INIT_OFFSET -#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00 -#endif - -#define CPM_SPI_BASE_RX CPM_SPI_BASE -#define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t)) - -/* ------------------- - * Function prototypes - * ------------------- */ -ssize_t spi_xfer(size_t); - -/* ------------------- - * Variables - * ------------------- */ - -#define MAX_BUFFER 0x104 - -/* ---------------------------------------------------------------------- - * Initially we place the RX and TX buffers at a fixed location in DPRAM! - * ---------------------------------------------------------------------- */ -static uchar *rxbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem - [CONFIG_SYS_SPI_INIT_OFFSET]; -static uchar *txbuf = - (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem - [CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER]; - -/* ************************************************************************** - * - * Function: spi_init_f - * - * Description: Init SPI-Controller (ROM part) - * - * return: --- - * - * *********************************************************************** */ -void spi_init_f(void) -{ - immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; - cpm8xx_t __iomem *cp = &immr->im_cpm; - spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; - cbd_t __iomem *tbdf, *rbdf; - - /* Disable relocation */ - out_be16(&spi->spi_rpbase, 0); - -/* 1 */ - /* ------------------------------------------------ - * Initialize Port B SPI pins -> page 34-8 MPC860UM - * (we are only in Master Mode !) - * ------------------------------------------------ */ - - /* -------------------------------------------- - * GPIO or per. Function - * PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO) - * PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI) - * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK) - * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM) - * -------------------------------------------- */ - clrsetbits_be32(&cp->cp_pbpar, 0x00000001, 0x0000000E); /* set bits */ - - /* ---------------------------------------------- - * In/Out or per. Function 0/1 - * PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO - * PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI - * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK - * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM - * ---------------------------------------------- */ - setbits_be32(&cp->cp_pbdir, 0x0000000F); - - /* ---------------------------------------------- - * open drain or active output - * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO - * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI - * PBODR[30] = 0 [0x00000002] -> active output: SPICLK - * PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM - * ---------------------------------------------- */ - - clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008); - - /* Initialize the parameter ram. - * We need to make sure many things are initialized to zero - */ - out_be32(&spi->spi_rstate, 0); - out_be32(&spi->spi_rdp, 0); - out_be16(&spi->spi_rbptr, 0); - out_be16(&spi->spi_rbc, 0); - out_be32(&spi->spi_rxtmp, 0); - out_be32(&spi->spi_tstate, 0); - out_be32(&spi->spi_tdp, 0); - out_be16(&spi->spi_tbptr, 0); - out_be16(&spi->spi_tbc, 0); - out_be32(&spi->spi_txtmp, 0); - -/* 3 */ - /* Set up the SPI parameters in the parameter ram */ - out_be16(&spi->spi_rbase, CPM_SPI_BASE_RX); - out_be16(&spi->spi_tbase, CPM_SPI_BASE_TX); - - /***********IMPORTANT******************/ - - /* - * Setting transmit and receive buffer descriptor pointers - * initially to rbase and tbase. Only the microcode patches - * documentation talks about initializing this pointer. This - * is missing from the sample I2C driver. If you dont - * initialize these pointers, the kernel hangs. - */ - out_be16(&spi->spi_rbptr, CPM_SPI_BASE_RX); - out_be16(&spi->spi_tbptr, CPM_SPI_BASE_TX); - -/* 4 */ - /* Init SPI Tx + Rx Parameters */ - while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) - ; - - out_be16(&cp->cp_cpcr, mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | - CPM_CR_FLG); - while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) - ; - -/* 5 */ - /* Set SDMA configuration register */ - out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001); - -/* 6 */ - /* Set to big endian. */ - out_8(&spi->spi_tfcr, SMC_EB); - out_8(&spi->spi_rfcr, SMC_EB); - -/* 7 */ - /* Set maximum receive size. */ - out_be16(&spi->spi_mrblr, MAX_BUFFER); - -/* 8 + 9 */ - /* tx and rx buffer descriptors */ - tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; - rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; - - clrbits_be16(&tbdf->cbd_sc, BD_SC_READY); - clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY); - - /* Set the bd's rx and tx buffer address pointers */ - out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf); - out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf); - -/* 10 + 11 */ - out_8(&cp->cp_spim, 0); /* Mask all SPI events */ - out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */ - - return; -} - -/* ************************************************************************** - * - * Function: spi_init_r - * - * Description: Init SPI-Controller (RAM part) - - * The malloc engine is ready and we can move our buffers to - * normal RAM - * - * return: --- - * - * *********************************************************************** */ -void spi_init_r(void) -{ - immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; - cpm8xx_t __iomem *cp = &immr->im_cpm; - spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; - cbd_t __iomem *tbdf, *rbdf; - - /* Disable relocation */ - out_be16(&spi->spi_rpbase, 0); - - /* tx and rx buffer descriptors */ - tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; - rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; - - /* Allocate memory for RX and TX buffers */ - rxbuf = (uchar *)malloc(MAX_BUFFER); - txbuf = (uchar *)malloc(MAX_BUFFER); - - out_be32(&rbdf->cbd_bufaddr, (ulong)rxbuf); - out_be32(&tbdf->cbd_bufaddr, (ulong)txbuf); - - return; -} - -/**************************************************************************** - * Function: spi_write - **************************************************************************** */ -ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) -{ - int i; - - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - *txbuf = SPI_EEPROM_WREN; /* write enable */ - spi_xfer(1); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_WRITE; /* WRITE memory array */ - memcpy(alen + txbuf, buffer, len); - spi_xfer(alen + len); - /* ignore received data */ - for (i = 0; i < 1000; i++) { - *txbuf = SPI_EEPROM_RDSR; /* read status */ - txbuf[1] = 0; - spi_xfer(2); - if (!(rxbuf[1] & 1)) - break; - udelay(1000); - } - if (i >= 1000) - printf("*** spi_write: Time out while writing!\n"); - - return len; -} - -/**************************************************************************** - * Function: spi_read - **************************************************************************** */ -ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) -{ - memset(rxbuf, 0, MAX_BUFFER); - memset(txbuf, 0, MAX_BUFFER); - memcpy(txbuf, addr, alen); - *txbuf = SPI_EEPROM_READ; /* READ memory array */ - - /* - * There is a bug in 860T (?) that cuts the last byte of input - * if we're reading into DPRAM. The solution we choose here is - * to always read len+1 bytes (we have one extra byte at the - * end of the buffer). - */ - spi_xfer(alen + len + 1); - memcpy(buffer, alen + rxbuf, len); - - return len; -} - -/**************************************************************************** - * Function: spi_xfer - **************************************************************************** */ -ssize_t spi_xfer(size_t count) -{ - immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; - cpm8xx_t __iomem *cp = &immr->im_cpm; - spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI]; - cbd_t __iomem *tbdf, *rbdf; - int tm; - - /* Disable relocation */ - out_be16(&spi->spi_rpbase, 0); - - tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX]; - rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX]; - - /* Set CS for device */ - clrbits_be32(&cp->cp_pbdat, 0x0001); - - /* Setting tx bd status and data length */ - out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP); - out_be16(&tbdf->cbd_datlen, count); - - /* Setting rx bd status and data length */ - out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP); - out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */ - - clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR | - SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8)); - out_8(&cp->cp_spim, 0); /* Mask all SPI events */ - out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */ - - /* start spi transfer */ - setbits_8(&cp->cp_spcom, SPI_STR); /* Start transmit */ - - /* -------------------------------- - * Wait for SPI transmit to get out - * or time out (1 second = 1000 ms) - * -------------------------------- */ - for (tm = 0; tm < 1000; ++tm) { - if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */ - break; - if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0) - break; - udelay(1000); - } - if (tm >= 1000) - printf("*** spi_xfer: Time out while xferring to/from SPI!\n"); - - /* Clear CS for device */ - setbits_be32(&cp->cp_pbdat, 0x0001); - - return count; -} -- 2.14.3

4 4

[U-Boot] [PATCH] power: regulator: denied disable on always-on regulator
by Patrice Chotard 05 Nov '18

05 Nov '18

From: Patrick Delaunay <patrick.delaunay(a)st.com> Don't disable regulator which are tagged as "regulator-always-on" in DT. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)st.com> Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> --- drivers/power/regulator/regulator-uclass.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 4da8e43259fc..4511625ff251 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -106,10 +106,15 @@ int regulator_get_enable(struct udevice *dev) int regulator_set_enable(struct udevice *dev, bool enable) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + struct dm_regulator_uclass_platdata *uc_pdata; if (!ops || !ops->set_enable) return -ENOSYS; + uc_pdata = dev_get_uclass_platdata(dev); + if (!enable && uc_pdata->always_on) + return -EACCES; + return ops->set_enable(dev, enable); } -- 1.9.1

4 6

[U-Boot] [PATCH v1 1/1] spi: lpc32xx_ssp: DM conversion
by Akash Gajjar 05 Nov '18

05 Nov '18

From: Akash Gajjar <gajjar04akash(a)gmail.com> This patch adds support for DM to the LPC32xx SSP SPI driver. Some TODOs are left over for later, These would be enhancements to the original functionality, and can come later. The legacy functionality is removed in this version. Signed-off-by: Akash Gajjar <akash(a)openedev.com> --- drivers/spi/Kconfig | 10 +- drivers/spi/lpc32xx_ssp.c | 145 +++++++++++++++-------------- include/dm/platform_data/spi_lpc32xx_ssp.h | 15 +++ 3 files changed, 93 insertions(+), 77 deletions(-) create mode 100644 include/dm/platform_data/spi_lpc32xx_ssp.h diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index ec92b84..2297d4a 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -99,6 +99,11 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config LPC32XX_SSP + bool "LPC32XX SPI Driver" + help + Enable support for SPI on LPC32xx + config MVEBU_A3700_SPI bool "Marvell Armada 3700 SPI driver" help @@ -277,11 +282,6 @@ config KIRKWOOD_SPI Enable support for SPI on various Marvell SoCs, such as Kirkwood and Armada 375. -config LPC32XX_SSP - bool "LPC32XX SPI Driver" - help - Enable support for SPI on LPC32xx - config MPC8XX_SPI bool "MPC8XX SPI Driver" depends on MPC8xx diff --git a/drivers/spi/lpc32xx_ssp.c b/drivers/spi/lpc32xx_ssp.c index e2a593b..ae41b57 100644 --- a/drivers/spi/lpc32xx_ssp.c +++ b/drivers/spi/lpc32xx_ssp.c @@ -4,6 +4,9 @@ * (C) Copyright 2014 DENX Software Engineering GmbH * Written-by: Albert ARIBAUD <albert.aribaud(a)3adev.fr> * + * Support for device model: + * Copyright (C) 2018 Akash Gajjar <akash(a)openedev.com> + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -13,6 +16,8 @@ #include <malloc.h> #include <spi.h> #include <asm/arch/clk.h> +#include <dm.h> +#include <dm/platform_data/spi_lpc32xx_ssp.h> /* SSP chip registers */ struct ssp_regs { @@ -36,90 +41,36 @@ struct ssp_regs { /* SSP status RX FIFO not empty bit */ #define SSP_SR_RNE 0x0004 -/* lpc32xx spi slave */ -struct lpc32xx_spi_slave { - struct spi_slave slave; +struct lpc32xx_ssp_spi_priv { struct ssp_regs *regs; }; -static inline struct lpc32xx_spi_slave *to_lpc32xx_spi_slave( - struct spi_slave *slave) +static int lpc32xx_ssp_spi_claim_bus(struct udevice *dev) { - return container_of(slave, struct lpc32xx_spi_slave, slave); -} - -/* spi_init is called during boot when CONFIG_CMD_SPI is defined */ -void spi_init(void) -{ - /* - * nothing to do: clocking was enabled in lpc32xx_ssp_enable() - * and configuration will be done in spi_setup_slave() - */ + return 0; } -/* the following is called in sequence by do_spi_xfer() */ - -struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode) +static int lpc32xx_ssp_spi_release_bus(struct udevice *dev) { - struct lpc32xx_spi_slave *lslave; - - /* we only set up SSP0 for now, so ignore bus */ - - if (mode & SPI_3WIRE) { - pr_err("3-wire mode not supported"); - return NULL; - } - - if (mode & SPI_SLAVE) { - pr_err("slave mode not supported\n"); - return NULL; - } - - if (mode & SPI_PREAMBLE) { - pr_err("preamble byte skipping not supported\n"); - return NULL; - } - - lslave = spi_alloc_slave(struct lpc32xx_spi_slave, bus, cs); - if (!lslave) { - printf("SPI_error: Fail to allocate lpc32xx_spi_slave\n"); - return NULL; - } - - lslave->regs = (struct ssp_regs *)SSP0_BASE; - - /* - * 8 bit frame, SPI fmt, 500kbps -> clock divider is 26. - * Set SCR to 0 and CPSDVSR to 26. - */ - - writel(0x7, &lslave->regs->cr0); /* 8-bit chunks, SPI, 1 clk/bit */ - writel(26, &lslave->regs->cpsr); /* SSP clock = HCLK/26 = 500kbps */ - writel(0, &lslave->regs->imsc); /* do not raise any interrupts */ - writel(0, &lslave->regs->icr); /* clear any pending interrupt */ - writel(0, &lslave->regs->dmacr); /* do not do DMAs */ - writel(SSP_CR1_SSP_ENABLE, &lslave->regs->cr1); /* enable SSP0 */ - return &lslave->slave; + return 0; } -void spi_free_slave(struct spi_slave *slave) +static int lpc32xx_ssp_spi_set_speed(struct udevice *bus, uint hz) { - struct lpc32xx_spi_slave *lslave = to_lpc32xx_spi_slave(slave); - - debug("(lpc32xx) spi_free_slave: 0x%08x\n", (u32)lslave); - free(lslave); + return 0; } -int spi_claim_bus(struct spi_slave *slave) +static int lpc32xx_ssp_spi_set_mode(struct udevice *bus, uint mode) { - /* only one bus and slave so far, always available */ return 0; } -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) +static int lpc32xx_ssp_spi_xfer(struct udevice *dev, uint bitlen, + const void *dout, void *din, ulong flags) { - struct lpc32xx_spi_slave *lslave = to_lpc32xx_spi_slave(slave); + struct udevice *bus = dev->parent; + struct lpc32xx_ssp_priv *priv = dev_get_priv(bus); + struct ssp_regs *regs = priv->regs; int bytelen = bitlen >> 3; int idx_out = 0; int idx_in = 0; @@ -127,18 +78,68 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, start_time = get_timer(0); while ((idx_out < bytelen) || (idx_in < bytelen)) { - int status = readl(&lslave->regs->sr); + int status = readl(&regs->sr); if ((idx_out < bytelen) && (status & SSP_SR_TNF)) - writel(((u8 *)dout)[idx_out++], &lslave->regs->data); + writel(((u8 *)dout)[idx_out++], &regs->data); if ((idx_in < bytelen) && (status & status & SSP_SR_RNE)) - ((u8 *)din)[idx_in++] = readl(&lslave->regs->data); + ((u8 *)din)[idx_in++] = readl(&regs->data); if (get_timer(start_time) >= CONFIG_LPC32XX_SSP_TIMEOUT) return -1; } + + return 0; +} + +static int lpc32xx_ssp_spi_probe(struct udevice *bus) +{ + struct lpc32xx_ssp_spi_platdata *plat = bus->platdata; + struct lpc32xx_ssp_spi_priv = dev_get_priv(bus); + + priv->regs = plat->regs; + return 0; } -void spi_release_bus(struct spi_slave *slave) +static const struct dm_spi_ops lpc32xx_ssp_spi_ops = { + .claim_bus = lpc32xx_ssp_spi_claim_bus, + .release_bus = lpc32xx_ssp_spi_release_bus, + .xfer = lpc32xx_ssp_spi_xfer, + .set_speed = lpc32xx_ssp_spi_set_speed, + .set_mode = lpc32xx_ssp_spi_set_mode, +}; + +#if CONFIG_IS_ENABLED(OF_CONTROL) +static int lpc32xx_ssp_spi_ofdata_to_platadata(struct udevice *bus) { - /* do nothing */ + struct lpc32xx_ssp_spi_platdata *plat = bus->platdata; + fdt_addr_t addr; + + addr = devfdt_get_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->regs = (struct struct ssp_regs *)addr; + + return 0; } + +/* TODO: update compatibel device tree */ +static const struct udevice_id lpc32xx_ssp_spi_ids[] = { + { .compatible = "" }, + {} +}; +#endif + +U_BOOT_DRIVER(lpc32xx_ssp_spi) = { + .name = "lpc32xx_ssp_spi", + .id = UCLASS_SPI, +#if CONFIG_IS_ENABLED(OF_CONTROL) + .of_match = lpc32xx_ssp_spi_ids, + .ofdata_to_platdata = lpc32xx_ssp_spi_ofdata_to_platadata, + .platdata_auto_alloc_size = sizeof(struct lpc32xx_ssp_spi_platdata), +#endif + .ops = &lpc32xx_ssp_spi_ops, + .priv_auto_alloc_size = sizeof(struct lpc32xx_ssp_spi_priv), + .probe = lpc32xx_ssp_spi_probe, +}; +#endif diff --git a/include/dm/platform_data/spi_lpc32xx_ssp.h b/include/dm/platform_data/spi_lpc32xx_ssp.h new file mode 100644 index 0000000..ea5cccf --- /dev/null +++ b/include/dm/platform_data/spi_lpc32xx_ssp.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2018 Akash Gajjar <akash(a)openedev.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __lpc32xx_ssp_h +#define __lpc32xx_ssp_h + +struct lpc32xx_ssp_spi_platdata { + struct ssp_regs *regs; +}; + +#endif /* __lpc32xx_ssp_h */ + -- 2.7.4

3 3

[U-Boot] [PATCH v4 01/17] ram: Add driver for MPC83xx
by Mario Six 04 Nov '18

04 Nov '18

Add a RAM driver for the MPC83xx architecture. Reviewed-by: Simon Glass <sjg(a)chromium.org> Signed-off-by: Mario Six <mario.six(a)gdsys.cc> --- Notes: v3 -> v4: * Switched preprocessor constants to C constants * Improved error reporting * Added driver binding file * Added full documentation v2 -> v3: * Converted some #ifdefs to if (IS_ENABLED(...)) * Added driver files to MAINTAINERS v1 -> v2: No changes .../bindings/ram/fsl,mpc83xx-mem-controller.txt | 314 ++++++ MAINTAINERS | 2 + arch/powerpc/cpu/mpc83xx/spd_sdram.c | 4 + drivers/ram/Kconfig | 9 + drivers/ram/Makefile | 1 + drivers/ram/mpc83xx_sdram.c | 1096 ++++++++++++++++++++ include/dt-bindings/memory/mpc83xx-sdram.h | 161 +++ include/mpc83xx.h | 6 + 8 files changed, 1593 insertions(+) create mode 100644 Documentation/devicetree/bindings/ram/fsl,mpc83xx-mem-controller.txt create mode 100644 drivers/ram/mpc83xx_sdram.c create mode 100644 include/dt-bindings/memory/mpc83xx-sdram.h diff --git a/Documentation/devicetree/bindings/ram/fsl,mpc83xx-mem-controller.txt b/Documentation/devicetree/bindings/ram/fsl,mpc83xx-mem-controller.txt new file mode 100644 index 00000000000..da01fe908de --- /dev/null +++ b/Documentation/devicetree/bindings/ram/fsl,mpc83xx-mem-controller.txt @@ -0,0 +1,314 @@ +MPC83xx RAM controller + +This driver supplies support for the embedded RAM controller on MCP83xx-series +SoCs. + +For static configuration mode, each controller node should have child nodes +describing the actual RAM modules installed. + +Controller node +=============== + +Required properties: +- compatible: Must be "fsl,mpc83xx-mem-controller" +- reg: The address of the RAM controller's register space +- #address-cells: Must be 2 +- #size-cells: Must be 1 +- driver_software_override: DDR driver software override is enabled (1) or + disabled (0) +- p_impedance_override: DDR driver software p-impedance override; possible + values: + * DSO_P_IMPEDANCE_HIGHEST_Z + * DSO_P_IMPEDANCE_MUCH_HIGHER_Z + * DSO_P_IMPEDANCE_HIGHER_Z + * DSO_P_IMPEDANCE_NOMINAL + * DSO_P_IMPEDANCE_LOWER_Z +- n_impedance_override: DDR driver software n-impedance override; possible + values: + * DSO_N_IMPEDANCE_HIGHEST_Z + * DSO_N_IMPEDANCE_MUCH_HIGHER_Z + * DSO_N_IMPEDANCE_HIGHER_Z + * DSO_N_IMPEDANCE_NOMINAL + * DSO_N_IMPEDANCE_LOWER_Z +- odt_termination_value: ODT termination value for I/Os; possible values: + * ODT_TERMINATION_75_OHM + * ODT_TERMINATION_150_OHM +- ddr_type: Selects voltage level for DDR pads; possible + values: + * DDR_TYPE_DDR2_1_8_VOLT + * DDR_TYPE_DDR1_2_5_VOLT +- mvref_sel: Determine where MVREF_SEL signal is generated; + possible values: + * MVREF_SEL_EXTERNAL + * MVREF_SEL_INTERNAL_GVDD +- m_odr: Disable memory transaction reordering; possible + values: + * M_ODR_ENABLE + * M_ODR_DISABLE +- clock_adjust: Clock adjust; possible values: + * CLOCK_ADJUST_025 + * CLOCK_ADJUST_05 + * CLOCK_ADJUST_075 + * CLOCK_ADJUST_1 +- ext_refresh_rec: Extended refresh recovery time; possible values: + 0, 16, 32, 48, 64, 80, 96, 112 +- read_to_write: Read-to-write turnaround; possible values: + 0, 1, 2, 3 +- write_to_read: Write-to-read turnaround; possible values: + 0, 1, 2, 3 +- read_to_read: Read-to-read turnaround; possible values: + 0, 1, 2, 3 +- write_to_write: Write-to-write turnaround; possible values: + 0, 1, 2, 3 +- active_powerdown_exit: Active powerdown exit timing; possible values: + 1, 2, 3, 4, 5, 6, 7 +- precharge_powerdown_exit: Precharge powerdown exit timing; possible values: + 1, 2, 3, 4, 5, 6, 7 +- odt_powerdown_exit: ODT powerdown exit timing; possible values: + 0, 1, 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 13, 14, 15 +- mode_reg_set_cycle: Mode register set cycle time; possible values: + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +- precharge_to_activate: Precharge-to-acitvate interval; possible values: + 1, 2, 3, 4, 5, 6, 7 +- activate_to_precharge: Activate to precharge interval; possible values: + 4, 5, 6, 7, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 19 +- activate_to_readwrite: Activate to read/write interval for SDRAM; + possible values: + 1, 2, 3, 4, 5, 6, 7 +- mcas_latency: MCAS latency from READ command; possible values: + * CASLAT_20 + * CASLAT_25 + * CASLAT_30 + * CASLAT_35 + * CASLAT_40 + * CASLAT_45 + * CASLAT_50 + * CASLAT_55 + * CASLAT_60 + * CASLAT_65 + * CASLAT_70 + * CASLAT_75 + * CASLAT_80 +- refresh_recovery: Refresh recovery time; possible values: + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23 +- last_data_to_precharge: Last data to precharge minimum interval; possible + values: + 1, 2, 3, 4, 5, 6, 7 +- activate_to_activate: Activate-to-activate interval; possible values: + 1, 2, 3, 4, 5, 6, 7 +- last_write_data_to_read: Last write data pair to read command issue + interval; possible values: + 1, 2, 3, 4, 5, 6, 7 +- additive_latency: Additive latency; possible values: + 0, 1, 2, 3, 4, 5 +- mcas_to_preamble_override: MCAS-to-preamble-override; possible values: + * READ_LAT + * READ_LAT_PLUS_1_4 + * READ_LAT_PLUS_1_2 + * READ_LAT_PLUS_3_4 + * READ_LAT_PLUS_1 + * READ_LAT_PLUS_5_4 + * READ_LAT_PLUS_3_2 + * READ_LAT_PLUS_7_4 + * READ_LAT_PLUS_2 + * READ_LAT_PLUS_9_4 + * READ_LAT_PLUS_5_2 + * READ_LAT_PLUS_11_4 + * READ_LAT_PLUS_3 + * READ_LAT_PLUS_13_4 + * READ_LAT_PLUS_7_2 + * READ_LAT_PLUS_15_4 + * READ_LAT_PLUS_4 + * READ_LAT_PLUS_17_4 + * READ_LAT_PLUS_9_2 + * READ_LAT_PLUS_19_4 +- write_latency: Write latency; possible values: + 1, 2, 3, 4, 5, 6, 7 +- read_to_precharge: Read to precharge; possible values: + 1, 2, 3, 4 +- write_cmd_to_write_data: Write command to write data strobe timing + adjustment; possible values: + * CLOCK_DELAY_0 + * CLOCK_DELAY_1_4 + * CLOCK_DELAY_1_2 + * CLOCK_DELAY_3_4 + * CLOCK_DELAY_1 + * CLOCK_DELAY_5_4 + * CLOCK_DELAY_3_2 +- minimum_cke_pulse_width: Minimum CKE pulse width; possible values: + 1, 2, 3, 4 +- four_activates_window: Window for four activates; possible values: + 1, 2, 3, 4 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 19 +- self_refresh: Self refresh (during sleep); possible values: + * SREN_DISABLE + * SREN_ENABLE +- ecc: Support for ECC; possible values: + * ECC_DISABLE + * ECC_ENABLE +- registered_dram: Support for registered DRAM; possible values: + * RD_DISABLE + * RD_ENABLE +- sdram_type: Type of SDRAM device to be used; possible values: + * TYPE_DDR1 + * TYPE_DDR2 +- dynamic_power_management: Dynamic power management mode; possible values: + * DYN_PWR_DISABLE + * DYN_PWR_ENABLE +- databus_width: DRAM data bus width; possible values + * DATA_BUS_WIDTH_16 + * DATA_BUS_WIDTH_32 +- nc_auto_precharge: Non-concurrent auto-precharge; possible values: + * NCAP_DISABLE + * NCAP_ENABLE +- timing_2t: 2T timing; possible values: + * TIMING_1T + * TIMING_2T +- bank_interleaving_ctrl: Bank (chip select) interleaving control; possible + values: + * INTERLEAVE_NONE + * INTERLEAVE_1_AND_2 +- precharge_bit_8: Precharge bin 8; possible values + * PRECHARGE_MA_10 + * PRECHARGE_MA_8 +- half_strength: Global half-strength override; possible values: + * STRENGTH_FULL + * STRENGTH_HALF +- bypass_initialization: Bypass initialization; possible values: + * INITIALIZATION_DONT_BYPASS + * INITIALIZATION_BYPASS +- force_self_refresh: Force self refresh; possible values: + * MODE_NORMAL + * MODE_REFRESH +- dll_reset: DLL reset; possible values: + * DLL_RESET_ENABLE + * DLL_RESET_DISABLE +- dqs_config: DQS configuration; possible values: + * DQS_TRUE +- odt_config: ODT configuration; possible values: + * ODT_ASSERT_NEVER + * ODT_ASSERT_WRITES + * ODT_ASSERT_READS + * ODT_ASSERT_ALWAYS +- posted_refreshes: Number of posted refreshes + 1, 2, 3, 4, 5, 6, 7, 8 +- sdmode: Initial value loaded into the DDR SDRAM mode + register +- esdmode: Initial value loaded into the DDR SDRAM extended + mode register +- esdmode2: Initial value loaded into the DDR SDRAM extended + mode 2 register +- esdmode3: Initial value loaded into the DDR SDRAM extended + mode 3 register +- refresh_interval: Refresh interval; possible values: + 0 - 65535 +- precharge_interval: Precharge interval; possible values: + 0 - 16383 + +RAM module node: +================ + +Required properties: +- reg: A triple <cs addr size>, which consists of: + * cs - the chipselect used to drive this RAM module + * addr - the address where this RAM module's memory is map + to in the global memory space + * size - the size of the RAM module's memory in bytes +- auto_precharge: Chip select auto-precharge; possible values: + * AUTO_PRECHARGE_ENABLE + * AUTO_PRECHARGE_DISABLE +- odt_rd_cfg: ODT for reads configuration; possible values: + * ODT_RD_NEVER + * ODT_RD_ONLY_CURRENT + * ODT_RD_ONLY_OTHER_CS + * ODT_RD_ONLY_OTHER_DIMM + * ODT_RD_ALL +- odt_wr_cfg: ODT for writes configuration; possible values: + * ODT_WR_NEVER + * ODT_WR_ONLY_CURRENT + * ODT_WR_ONLY_OTHER_CS + * ODT_WR_ONLY_OTHER_DIMM + * ODT_WR_ALL +- bank_bits: Number of bank bits for SDRAM on chip select; possible + values: + 2, 3 +- row_bits: Number of row bits for SDRAM on chip select; possible values: + 12, 13, 14 +- col_bits: Number of column bits for SDRAM on chip select; possible + values: + 8, 9, 10, 11 + +Example: + +memory@2000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc83xx-mem-controller"; + reg = <0x2000 0x1000>; + device_type = "memory"; + u-boot,dm-pre-reloc; + + driver_software_override = <DSO_ENABLE>; + p_impedance_override = <DSO_P_IMPEDANCE_NOMINAL>; + n_impedance_override = <DSO_N_IMPEDANCE_NOMINAL>; + odt_termination_value = <ODT_TERMINATION_150_OHM>; + ddr_type = <DDR_TYPE_DDR2_1_8_VOLT>; + + clock_adjust = <CLOCK_ADJUST_05>; + + read_to_write = <0>; + write_to_read = <0>; + read_to_read = <0>; + write_to_write = <0>; + active_powerdown_exit = <2>; + precharge_powerdown_exit = <6>; + odt_powerdown_exit = <8>; + mode_reg_set_cycle = <2>; + + precharge_to_activate = <2>; + activate_to_precharge = <6>; + activate_to_readwrite = <2>; + mcas_latency = <CASLAT_40>; + refresh_recovery = <17>; + last_data_to_precharge = <2>; + activate_to_activate = <2>; + last_write_data_to_read = <2>; + + additive_latency = <0>; + mcas_to_preamble_override = <READ_LAT_PLUS_1_2>; + write_latency = <3>; + read_to_precharge = <2>; + write_cmd_to_write_data = <CLOCK_DELAY_1_2>; + minimum_cke_pulse_width = <3>; + four_activates_window = <5>; + + self_refresh = <SREN_ENABLE>; + sdram_type = <TYPE_DDR2>; + databus_width = <DATA_BUS_WIDTH_32>; + + force_self_refresh = <MODE_NORMAL>; + dll_reset = <DLL_RESET_ENABLE>; + dqs_config = <DQS_TRUE>; + odt_config = <ODT_ASSERT_READS>; + posted_refreshes = <1>; + + refresh_interval = <2084>; + precharge_interval = <256>; + + sdmode = <0x0242>; + esdmode = <0x0440>; + + ram@0 { + reg = <0x0 0x0 0x8000000>; + compatible = "nanya,nt5tu64m16hg"; + + odt_rd_cfg = <ODT_RD_NEVER>; + odt_wr_cfg = <ODT_WR_ONLY_CURRENT>; + bank_bits = <3>; + row_bits = <13>; + col_bits = <10>; + }; +}; diff --git a/MAINTAINERS b/MAINTAINERS index 1bd583c9753..57329e878ae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -495,6 +495,8 @@ POWERPC MPC83XX M: Mario Six <mario.six(a)gdsys.cc> S: Maintained T: git git://git.denx.de/u-boot-mpc83xx.git +F: drivers/ram/mpc83xx_sdram.c +F: include/dt-bindings/memory/mpc83xx-sdram.h F: arch/powerpc/cpu/mpc83xx/ F: arch/powerpc/include/asm/arch-mpc83xx/ diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index bbc8ef03c7b..328a018eb6f 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -10,6 +10,8 @@ * Xianghua Xiao (X.Xiao(a)motorola.com) */ +#ifndef CONFIG_MPC83XX_SDRAM + #include <common.h> #include <asm/processor.h> #include <asm/io.h> @@ -924,3 +926,5 @@ void ddr_enable_ecc(unsigned int dram_size) __asm__ __volatile__ ("isync"); } #endif /* CONFIG_DDR_ECC */ + +#endif /* !CONFIG_MPC83XX_SDRAM */ diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 496e2b793bd..54bb4b419f0 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -34,4 +34,13 @@ config STM32_SDRAM support external memories like sdram, psram & nand. This driver is for the sdram memory interface with the FMC. +config MPC83XX_SDRAM + bool "Enable MPC83XX SDRAM support" + depends on RAM + help + Enable support for the internal DDR Memory Controller of the MPC83xx + family of SoCs. Both static configurations, as well as configuring + the RAM through the use of SPD (Serial Presence Detect) is supported + via device tree settings. + source "drivers/ram/stm32mp1/Kconfig" diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 3820d03aa41..4ad3604d163 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # obj-$(CONFIG_RAM) += ram-uclass.o +obj-$(CONFIG_MPC83XX_SDRAM) += mpc83xx_sdram.o obj-$(CONFIG_SANDBOX) += sandbox_ram.o obj-$(CONFIG_STM32MP1_DDR) += stm32mp1/ obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c new file mode 100644 index 00000000000..441baeb6f1a --- /dev/null +++ b/drivers/ram/mpc83xx_sdram.c @@ -0,0 +1,1096 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six(a)gdsys.cc + */ + +#include <common.h> +#include <dm.h> +#include <ram.h> +#include <dt-bindings/memory/mpc83xx-sdram.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Masks for the CS config register */ +static const u32 CSCONFIG_ENABLE = 0x80000000; + +static const u32 BANK_BITS_2; +static const u32 BANK_BITS_3 = 0x00004000; + +static const u32 ROW_BITS_12; +static const u32 ROW_BITS_13 = 0x00000100; +static const u32 ROW_BITS_14 = 0x00000200; + +static const u32 COL_BITS_8; +static const u32 COL_BITS_9 = 0x00000001; +static const u32 COL_BITS_10 = 0x00000002; +static const u32 COL_BITS_11 = 0x00000003; + +/* Shifts for the DDR SDRAM Timing Configuration 3 register */ +static const uint TIMING_CFG3_EXT_REFREC_SHIFT = (31 - 15); + +/* Shifts for the DDR SDRAM Timing Configuration 0 register */ +static const uint TIMING_CFG0_RWT_SHIFT = (31 - 1); +static const uint TIMING_CFG0_WRT_SHIFT = (31 - 3); +static const uint TIMING_CFG0_RRT_SHIFT = (31 - 5); +static const uint TIMING_CFG0_WWT_SHIFT = (31 - 7); +static const uint TIMING_CFG0_ACT_PD_EXIT_SHIFT = (31 - 11); +static const uint TIMING_CFG0_PRE_PD_EXIT_SHIFT = (31 - 15); +static const uint TIMING_CFG0_ODT_PD_EXIT_SHIFT = (31 - 23); +static const uint TIMING_CFG0_MRS_CYC_SHIFT = (31 - 31); + +/* Shifts for the DDR SDRAM Timing Configuration 1 register */ +static const uint TIMING_CFG1_PRETOACT_SHIFT = (31 - 3); +static const uint TIMING_CFG1_ACTTOPRE_SHIFT = (31 - 7); +static const uint TIMING_CFG1_ACTTORW_SHIFT = (31 - 11); +static const uint TIMING_CFG1_CASLAT_SHIFT = (31 - 15); +static const uint TIMING_CFG1_REFREC_SHIFT = (31 - 19); +static const uint TIMING_CFG1_WRREC_SHIFT = (31 - 23); +static const uint TIMING_CFG1_ACTTOACT_SHIFT = (31 - 27); +static const uint TIMING_CFG1_WRTORD_SHIFT = (31 - 31); + +/* Shifts for the DDR SDRAM Timing Configuration 2 register */ +static const uint TIMING_CFG2_CPO_SHIFT = (31 - 8); +static const uint TIMING_CFG2_WR_DATA_DELAY_SHIFT = (31 - 21); +static const uint TIMING_CFG2_ADD_LAT_SHIFT = (31 - 3); +static const uint TIMING_CFG2_WR_LAT_DELAY_SHIFT = (31 - 12); +static const uint TIMING_CFG2_RD_TO_PRE_SHIFT = (31 - 18); +static const uint TIMING_CFG2_CKE_PLS_SHIFT = (31 - 25); +static const uint TIMING_CFG2_FOUR_ACT_SHIFT; + +/* Shifts for the DDR SDRAM Control Configuration register */ +static const uint SDRAM_CFG_SREN_SHIFT = (31 - 1); +static const uint SDRAM_CFG_ECC_EN_SHIFT = (31 - 2); +static const uint SDRAM_CFG_RD_EN_SHIFT = (31 - 3); +static const uint SDRAM_CFG_SDRAM_TYPE_SHIFT = (31 - 7); +static const uint SDRAM_CFG_DYN_PWR_SHIFT = (31 - 10); +static const uint SDRAM_CFG_DBW_SHIFT = (31 - 12); +static const uint SDRAM_CFG_NCAP_SHIFT = (31 - 14); +static const uint SDRAM_CFG_2T_EN_SHIFT = (31 - 16); +static const uint SDRAM_CFG_BA_INTLV_CTL_SHIFT = (31 - 23); +static const uint SDRAM_CFG_PCHB8_SHIFT = (31 - 27); +static const uint SDRAM_CFG_HSE_SHIFT = (31 - 28); +static const uint SDRAM_CFG_BI_SHIFT = (31 - 31); + +/* Shifts for the DDR SDRAM Control Configuration 2 register */ +static const uint SDRAM_CFG2_FRC_SR_SHIFT = (31 - 0); +static const uint SDRAM_CFG2_DLL_RST_DIS = (31 - 2); +static const uint SDRAM_CFG2_DQS_CFG = (31 - 5); +static const uint SDRAM_CFG2_ODT_CFG = (31 - 10); +static const uint SDRAM_CFG2_NUM_PR = (31 - 19); + +/* Shifts for the DDR SDRAM Mode register */ +static const uint SDRAM_MODE_ESD_SHIFT = (31 - 15); +static const uint SDRAM_MODE_SD_SHIFT = (31 - 31); + +/* Shifts for the DDR SDRAM Mode 2 register */ +static const uint SDRAM_MODE2_ESD2_SHIFT = (31 - 15); +static const uint SDRAM_MODE2_ESD3_SHIFT = (31 - 31); + +/* Shifts for the DDR SDRAM Interval Configuration register */ +static const uint SDRAM_INTERVAL_REFINT_SHIFT = (31 - 15); +static const uint SDRAM_INTERVAL_BSTOPRE_SHIFT = (31 - 31); + +/* Mask for the DDR SDRAM Mode Control register */ +static const u32 SDRAM_CFG_MEM_EN = 0x80000000; + +int dram_init(void) +{ + struct udevice *ram_ctrl; + int ret; + + /* Current assumption: There is only one RAM controller */ + ret = uclass_first_device_err(UCLASS_RAM, &ram_ctrl); + if (ret) { + debug("%s: uclass_first_device_err failed: %d\n", + __func__, ret); + return ret; + } + + /* FIXME(mario.six(a)gdsys.cc): Set gd->ram_size? */ + + return 0; +} + +phys_size_t get_effective_memsize(void) +{ + if (!IS_ENABLED(CONFIG_VERY_BIG_RAM)) + return gd->ram_size; + + /* Limit stack to what we can reasonable map */ + return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? + CONFIG_MAX_MEM_MAPPED : gd->ram_size); +} + +/** + * struct mpc83xx_sdram_priv - Private data for MPC83xx RAM controllers + * @total_size: The total size of all RAM modules associated with this RAM + * controller in bytes + */ +struct mpc83xx_sdram_priv { + ulong total_size; +}; + +/** + * mpc83xx_sdram_static_init() - Statically initialize a RAM module. + * @node: Device tree node associated with ths module in question + * @cs: The chip select to use for this RAM module + * @mapaddr: The address where the RAM module should be mapped + * @size: The size of the RAM module to be mapped in bytes + * + * Return: 0 if OK, -ve on error + */ +static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = size; + u32 msize_log2 = __ilog2(msize); + u32 auto_precharge, odt_rd_cfg, odt_wr_cfg, bank_bits, row_bits, + col_bits; + u32 bank_bits_mask, row_bits_mask, col_bits_mask; + + /* Configure the DDR local access window */ + out_be32(&im->sysconf.ddrlaw[cs].bar, mapaddr & 0xfffff000); + out_be32(&im->sysconf.ddrlaw[cs].ar, LBLAWAR_EN | (msize_log2 - 1)); + + out_be32(&im->ddr.csbnds[cs].csbnds, (msize - 1) >> 24); + + auto_precharge = ofnode_read_u32_default(node, "auto_precharge", 0); + switch (auto_precharge) { + case AUTO_PRECHARGE_ENABLE: + case AUTO_PRECHARGE_DISABLE: + break; + default: + debug("%s: auto_precharge value %d invalid.\n", + ofnode_get_name(node), auto_precharge); + return -EINVAL; + } + + odt_rd_cfg = ofnode_read_u32_default(node, "odt_rd_cfg", 0); + switch (odt_rd_cfg) { + case ODT_RD_ONLY_OTHER_DIMM: + if (!IS_ENABLED(CONFIG_MPC8360) && + !IS_ENABLED(CONFIG_MPC837x)) { + debug("%s: odt_rd_cfg value %d invalid.\n", + ofnode_get_name(node), odt_rd_cfg); + return -EINVAL; + } + /* fall through */ + case ODT_RD_NEVER: + case ODT_RD_ONLY_CURRENT: + case ODT_RD_ONLY_OTHER_CS: + if (!IS_ENABLED(CONFIG_MPC830x) && + !IS_ENABLED(CONFIG_MPC831x) && + !IS_ENABLED(CONFIG_MPC8360) && + !IS_ENABLED(CONFIG_MPC837x)) { + debug("%s: odt_rd_cfg value %d invalid.\n", + ofnode_get_name(node), odt_rd_cfg); + return -EINVAL; + } + /* fall through */ + /* Only MPC832x knows this value */ + case ODT_RD_ALL: + break; + default: + debug("%s: odt_rd_cfg value %d invalid.\n", + ofnode_get_name(node), odt_rd_cfg); + return -EINVAL; + } + + odt_wr_cfg = ofnode_read_u32_default(node, "odt_wr_cfg", 0); + switch (odt_wr_cfg) { + case ODT_WR_ONLY_OTHER_DIMM: + if (!IS_ENABLED(CONFIG_MPC8360) && + !IS_ENABLED(CONFIG_MPC837x)) { + debug("%s: odt_wr_cfg value %d invalid.\n", + ofnode_get_name(node), odt_wr_cfg); + return -EINVAL; + } + /* fall through */ + case ODT_WR_NEVER: + case ODT_WR_ONLY_CURRENT: + case ODT_WR_ONLY_OTHER_CS: + if (!IS_ENABLED(CONFIG_MPC830x) && + !IS_ENABLED(CONFIG_MPC831x) && + !IS_ENABLED(CONFIG_MPC8360) && + !IS_ENABLED(CONFIG_MPC837x)) { + debug("%s: odt_wr_cfg value %d invalid.\n", + ofnode_get_name(node), odt_wr_cfg); + return -EINVAL; + } + /* fall through */ + /* MPC832x only knows this value */ + case ODT_WR_ALL: + break; + default: + debug("%s: odt_wr_cfg value %d invalid.\n", + ofnode_get_name(node), odt_wr_cfg); + return -EINVAL; + } + + bank_bits = ofnode_read_u32_default(node, "bank_bits", 0); + switch (bank_bits) { + case 2: + bank_bits_mask = BANK_BITS_2; + break; + case 3: + bank_bits_mask = BANK_BITS_3; + break; + default: + debug("%s: bank_bits value %d invalid.\n", + ofnode_get_name(node), bank_bits); + return -EINVAL; + } + + row_bits = ofnode_read_u32_default(node, "row_bits", 0); + switch (row_bits) { + case 12: + row_bits_mask = ROW_BITS_12; + break; + case 13: + row_bits_mask = ROW_BITS_13; + break; + case 14: + row_bits_mask = ROW_BITS_14; + break; + default: + debug("%s: row_bits value %d invalid.\n", + ofnode_get_name(node), row_bits); + return -EINVAL; + } + + col_bits = ofnode_read_u32_default(node, "col_bits", 0); + switch (col_bits) { + case 8: + col_bits_mask = COL_BITS_8; + break; + case 9: + col_bits_mask = COL_BITS_9; + break; + case 10: + col_bits_mask = COL_BITS_10; + break; + case 11: + col_bits_mask = COL_BITS_11; + break; + default: + debug("%s: col_bits value %d invalid.\n", + ofnode_get_name(node), col_bits); + return -EINVAL; + } + + /* Write CS config value */ + out_be32(&im->ddr.cs_config[cs], CSCONFIG_ENABLE | auto_precharge | + odt_rd_cfg | odt_wr_cfg | + bank_bits_mask | row_bits_mask | + col_bits_mask); + return 0; +} + +/** + * mpc83xx_sdram_spd_init() - Initialize a RAM module using a SPD flash. + * @node: Device tree node associated with ths module in question + * @cs: The chip select to use for this RAM module + * @mapaddr: The address where the RAM module should be mapped + * @size: The size of the RAM module to be mapped in bytes + * + * Return: 0 if OK, -ve on error + */ +static int mpc83xx_sdram_spd_init(ofnode node, u32 cs, u32 mapaddr, u32 size) +{ + /* TODO(mario.six(a)gdsys.cc): Implement */ + return 0; +} + +static int mpc83xx_sdram_ofdata_to_platdata(struct udevice *dev) +{ + return 0; +} + +static int mpc83xx_sdram_probe(struct udevice *dev) +{ + struct mpc83xx_sdram_priv *priv = dev_get_priv(dev); + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + int ret = 0; + ofnode subnode; + /* DDR control driver register values */ + u32 dso, pz_override, nz_override, odt_term, ddr_type, mvref_sel, m_odr; + u32 ddrcdr; + /* DDR SDRAM Clock Control register values */ + u32 clock_adjust; + /* DDR SDRAM Timing Configuration 3 register values */ + u32 ext_refresh_rec, ext_refresh_rec_mask; + /* DDR SDRAM Timing Configuration 0 register values */ + u32 read_to_write, write_to_read, read_to_read, write_to_write, + active_powerdown_exit, precharge_powerdown_exit, + odt_powerdown_exit, mode_reg_set_cycle; + u32 timing_cfg_0; + /* DDR SDRAM Timing Configuration 1 register values */ + u32 precharge_to_activate, activate_to_precharge, + activate_to_readwrite, mcas_latency, refresh_recovery, + last_data_to_precharge, activate_to_activate, + last_write_data_to_read; + u32 timing_cfg_1; + /* DDR SDRAM Timing Configuration 2 register values */ + u32 additive_latency, mcas_to_preamble_override, write_latency, + read_to_precharge, write_cmd_to_write_data, + minimum_cke_pulse_width, four_activates_window; + u32 timing_cfg_2; + /* DDR SDRAM Control Configuration register values */ + u32 self_refresh, ecc, registered_dram, sdram_type, + dynamic_power_management, databus_width, nc_auto_precharge, + timing_2t, bank_interleaving_ctrl, precharge_bit_8, half_strength, + bypass_initialization; + u32 sdram_cfg; + /* DDR SDRAM Control Configuration 2 register values */ + u32 force_self_refresh, dll_reset, dqs_config, odt_config, + posted_refreshes; + u32 sdram_cfg2; + /* DDR SDRAM Mode Configuration register values */ + u32 sdmode, esdmode; + u32 sdram_mode; + /* DDR SDRAM Mode Configuration 2 register values */ + u32 esdmode2, esdmode3; + u32 sdram_mode2; + /* DDR SDRAM Interval Configuration register values */ + u32 refresh_interval, precharge_interval; + u32 sdram_interval; + + priv->total_size = 0; + + /* Disable both banks initially (might be re-enabled in loop below) */ + out_be32(&im->ddr.cs_config[0], 0); + out_be32(&im->ddr.cs_config[1], 0); + + dso = dev_read_u32_default(dev, "driver_software_override", 0); + if (dso > 1) { + debug("%s: driver_software_override value %d invalid.\n", + dev->name, dso); + return -EINVAL; + } + + pz_override = dev_read_u32_default(dev, "p_impedance_override", 0); + + switch (pz_override) { + case DSO_P_IMPEDANCE_HIGHEST_Z: + case DSO_P_IMPEDANCE_MUCH_HIGHER_Z: + case DSO_P_IMPEDANCE_HIGHER_Z: + case DSO_P_IMPEDANCE_NOMINAL: + case DSO_P_IMPEDANCE_LOWER_Z: + break; + default: + debug("%s: p_impedance_override value %d invalid.\n", + dev->name, pz_override); + return -EINVAL; + } + + nz_override = dev_read_u32_default(dev, "n_impedance_override", 0); + + switch (nz_override) { + case DSO_N_IMPEDANCE_HIGHEST_Z: + case DSO_N_IMPEDANCE_MUCH_HIGHER_Z: + case DSO_N_IMPEDANCE_HIGHER_Z: + case DSO_N_IMPEDANCE_NOMINAL: + case DSO_N_IMPEDANCE_LOWER_Z: + break; + default: + debug("%s: n_impedance_override value %d invalid.\n", + dev->name, nz_override); + return -EINVAL; + } + + odt_term = dev_read_u32_default(dev, "odt_termination_value", 0); + if (odt_term > 1) { + debug("%s: odt_termination_value value %d invalid.\n", + dev->name, odt_term); + return -EINVAL; + } + + ddr_type = dev_read_u32_default(dev, "ddr_type", 0); + if (ddr_type > 1) { + debug("%s: ddr_type value %d invalid.\n", + dev->name, ddr_type); + return -EINVAL; + } + + mvref_sel = dev_read_u32_default(dev, "mvref_sel", 0); + if (mvref_sel > 1) { + debug("%s: mvref_sel value %d invalid.\n", + dev->name, mvref_sel); + return -EINVAL; + } + + m_odr = dev_read_u32_default(dev, "m_odr", 0); + if (mvref_sel > 1) { + debug("%s: m_odr value %d invalid.\n", + dev->name, m_odr); + return -EINVAL; + } + + ddrcdr = dso << (31 - 1) | + pz_override << (31 - 5) | + nz_override << (31 - 9) | + odt_term << (31 - 12) | + ddr_type << (31 - 13) | + mvref_sel << (31 - 29) | + m_odr << (31 - 30) | 1; + + /* Configure the DDR control driver register */ + out_be32(&im->sysconf.ddrcdr, ddrcdr); + + dev_for_each_subnode(subnode, dev) { + u32 val[3]; + u32 cs, addr, size; + + /* CS, map address, size -> three values */ + ofnode_read_u32_array(subnode, "reg", val, 3); + + cs = val[0]; + addr = val[1]; + size = val[2]; + + if (cs > 1) { + debug("%s: chip select value %d invalid.\n", + dev->name, cs); + return -EINVAL; + } + + /* TODO(mario.six(a)gdsys.cc): Sanity check for size. */ + + if (ofnode_read_bool(subnode, "read-spd")) + ret = mpc83xx_sdram_spd_init(subnode, cs, addr, size); + else + ret = mpc83xx_sdram_static_init(subnode, cs, addr, + size); + if (ret) { + debug("%s: RAM init failed.\n", dev->name); + return ret; + } + }; + + /* + * TODO(mario.six(a)gdsys.cc): This should only occur for static + * configuration + */ + + clock_adjust = dev_read_u32_default(dev, "clock_adjust", 0); + switch (clock_adjust) { + case CLOCK_ADJUST_025: + case CLOCK_ADJUST_05: + case CLOCK_ADJUST_075: + case CLOCK_ADJUST_1: + break; + default: + debug("%s: clock_adjust value %d invalid.\n", + dev->name, clock_adjust); + return -EINVAL; + } + + /* Configure the DDR SDRAM Clock Control register */ + out_be32(&im->ddr.sdram_clk_cntl, clock_adjust); + + ext_refresh_rec = dev_read_u32_default(dev, "ext_refresh_rec", 0); + switch (ext_refresh_rec) { + case 0: + ext_refresh_rec_mask = 0 << TIMING_CFG3_EXT_REFREC_SHIFT; + break; + case 16: + ext_refresh_rec_mask = 1 << TIMING_CFG3_EXT_REFREC_SHIFT; + break; + case 32: + ext_refresh_rec_mask = 2 << TIMING_CFG3_EXT_REFREC_SHIFT; + break; + case 48: + ext_refresh_rec_mask = 3 << TIMING_CFG3_EXT_REFREC_SHIFT; + break; + case 64: + ext_refresh_rec_mask = 4 << TIMING_CFG3_EXT_REFREC_SHIFT; + break; + case 80: + ext_refresh_rec_mask = 5 << TIMING_CFG3_EXT_REFREC_SHIFT; + break; + case 96: + ext_refresh_rec_mask = 6 << TIMING_CFG3_EXT_REFREC_SHIFT; + break; + case 112: + ext_refresh_rec_mask = 7 << TIMING_CFG3_EXT_REFREC_SHIFT; + break; + default: + debug("%s: ext_refresh_rec value %d invalid.\n", + dev->name, ext_refresh_rec); + return -EINVAL; + } + + /* Configure the DDR SDRAM Timing Configuration 3 register */ + out_be32(&im->ddr.timing_cfg_3, ext_refresh_rec_mask); + + read_to_write = dev_read_u32_default(dev, "read_to_write", 0); + if (read_to_write > 3) { + debug("%s: read_to_write value %d invalid.\n", + dev->name, read_to_write); + return -EINVAL; + } + + write_to_read = dev_read_u32_default(dev, "write_to_read", 0); + if (write_to_read > 3) { + debug("%s: write_to_read value %d invalid.\n", + dev->name, write_to_read); + return -EINVAL; + } + + read_to_read = dev_read_u32_default(dev, "read_to_read", 0); + if (read_to_read > 3) { + debug("%s: read_to_read value %d invalid.\n", + dev->name, read_to_read); + return -EINVAL; + } + + write_to_write = dev_read_u32_default(dev, "write_to_write", 0); + if (write_to_write > 3) { + debug("%s: write_to_write value %d invalid.\n", + dev->name, write_to_write); + return -EINVAL; + } + + active_powerdown_exit = + dev_read_u32_default(dev, "active_powerdown_exit", 0); + if (active_powerdown_exit > 7) { + debug("%s: active_powerdown_exit value %d invalid.\n", + dev->name, active_powerdown_exit); + return -EINVAL; + } + + precharge_powerdown_exit = + dev_read_u32_default(dev, "precharge_powerdown_exit", 0); + if (precharge_powerdown_exit > 7) { + debug("%s: precharge_powerdown_exit value %d invalid.\n", + dev->name, precharge_powerdown_exit); + return -EINVAL; + } + + odt_powerdown_exit = dev_read_u32_default(dev, "odt_powerdown_exit", 0); + if (odt_powerdown_exit > 15) { + debug("%s: odt_powerdown_exit value %d invalid.\n", + dev->name, odt_powerdown_exit); + return -EINVAL; + } + + mode_reg_set_cycle = dev_read_u32_default(dev, "mode_reg_set_cycle", 0); + if (mode_reg_set_cycle > 15) { + debug("%s: mode_reg_set_cycle value %d invalid.\n", + dev->name, mode_reg_set_cycle); + return -EINVAL; + } + + timing_cfg_0 = read_to_write << TIMING_CFG0_RWT_SHIFT | + write_to_read << TIMING_CFG0_WRT_SHIFT | + read_to_read << TIMING_CFG0_RRT_SHIFT | + write_to_write << TIMING_CFG0_WWT_SHIFT | + active_powerdown_exit << TIMING_CFG0_ACT_PD_EXIT_SHIFT | + precharge_powerdown_exit << TIMING_CFG0_PRE_PD_EXIT_SHIFT | + odt_powerdown_exit << TIMING_CFG0_ODT_PD_EXIT_SHIFT | + mode_reg_set_cycle << TIMING_CFG0_MRS_CYC_SHIFT; + + out_be32(&im->ddr.timing_cfg_0, timing_cfg_0); + + precharge_to_activate = + dev_read_u32_default(dev, "precharge_to_activate", 0); + if (precharge_to_activate > 7 || precharge_to_activate == 0) { + debug("%s: precharge_to_activate value %d invalid.\n", + dev->name, precharge_to_activate); + return -EINVAL; + } + + activate_to_precharge = + dev_read_u32_default(dev, "activate_to_precharge", 0); + if (activate_to_precharge > 19) { + debug("%s: activate_to_precharge value %d invalid.\n", + dev->name, activate_to_precharge); + return -EINVAL; + } + + activate_to_readwrite = + dev_read_u32_default(dev, "activate_to_readwrite", 0); + if (activate_to_readwrite > 7 || activate_to_readwrite == 0) { + debug("%s: activate_to_readwrite value %d invalid.\n", + dev->name, activate_to_readwrite); + return -EINVAL; + } + + mcas_latency = dev_read_u32_default(dev, "mcas_latency", 0); + switch (mcas_latency) { + case CASLAT_20: + case CASLAT_25: + if (!IS_ENABLED(CONFIG_ARCH_MPC8308)) { + debug("%s: MCAS latency < 3.0 unsupported on MPC8308\n", + dev->name); + return -EINVAL; + } + /* fall through */ + case CASLAT_30: + case CASLAT_35: + case CASLAT_40: + case CASLAT_45: + case CASLAT_50: + case CASLAT_55: + case CASLAT_60: + case CASLAT_65: + case CASLAT_70: + case CASLAT_75: + case CASLAT_80: + break; + default: + debug("%s: mcas_latency value %d invalid.\n", + dev->name, mcas_latency); + return -EINVAL; + } + + refresh_recovery = dev_read_u32_default(dev, "refresh_recovery", 0); + if (refresh_recovery > 23 || refresh_recovery < 8) { + debug("%s: refresh_recovery value %d invalid.\n", + dev->name, refresh_recovery); + return -EINVAL; + } + + last_data_to_precharge = + dev_read_u32_default(dev, "last_data_to_precharge", 0); + if (last_data_to_precharge > 7 || last_data_to_precharge == 0) { + debug("%s: last_data_to_precharge value %d invalid.\n", + dev->name, last_data_to_precharge); + return -EINVAL; + } + + activate_to_activate = + dev_read_u32_default(dev, "activate_to_activate", 0); + if (activate_to_activate > 7 || activate_to_activate == 0) { + debug("%s: activate_to_activate value %d invalid.\n", + dev->name, activate_to_activate); + return -EINVAL; + } + + last_write_data_to_read = + dev_read_u32_default(dev, "last_write_data_to_read", 0); + if (last_write_data_to_read > 7 || last_write_data_to_read == 0) { + debug("%s: last_write_data_to_read value %d invalid.\n", + dev->name, last_write_data_to_read); + return -EINVAL; + } + + timing_cfg_1 = precharge_to_activate << TIMING_CFG1_PRETOACT_SHIFT | + (activate_to_precharge > 15 ? + activate_to_precharge - 16 : + activate_to_precharge) << TIMING_CFG1_ACTTOPRE_SHIFT | + activate_to_readwrite << TIMING_CFG1_ACTTORW_SHIFT | + mcas_latency << TIMING_CFG1_CASLAT_SHIFT | + (refresh_recovery - 8) << TIMING_CFG1_REFREC_SHIFT | + last_data_to_precharge << TIMING_CFG1_WRREC_SHIFT | + activate_to_activate << TIMING_CFG1_ACTTOACT_SHIFT | + last_write_data_to_read << TIMING_CFG1_WRTORD_SHIFT; + + /* Configure the DDR SDRAM Timing Configuration 1 register */ + out_be32(&im->ddr.timing_cfg_1, timing_cfg_1); + + additive_latency = dev_read_u32_default(dev, "additive_latency", 0); + if (additive_latency > 5) { + debug("%s: additive_latency value %d invalid.\n", + dev->name, additive_latency); + return -EINVAL; + } + + mcas_to_preamble_override = + dev_read_u32_default(dev, "mcas_to_preamble_override", 0); + switch (mcas_to_preamble_override) { + case READ_LAT_PLUS_1: + case READ_LAT: + case READ_LAT_PLUS_1_4: + case READ_LAT_PLUS_1_2: + case READ_LAT_PLUS_3_4: + case READ_LAT_PLUS_5_4: + case READ_LAT_PLUS_3_2: + case READ_LAT_PLUS_7_4: + case READ_LAT_PLUS_2: + case READ_LAT_PLUS_9_4: + case READ_LAT_PLUS_5_2: + case READ_LAT_PLUS_11_4: + case READ_LAT_PLUS_3: + case READ_LAT_PLUS_13_4: + case READ_LAT_PLUS_7_2: + case READ_LAT_PLUS_15_4: + case READ_LAT_PLUS_4: + case READ_LAT_PLUS_17_4: + case READ_LAT_PLUS_9_2: + case READ_LAT_PLUS_19_4: + break; + default: + debug("%s: mcas_to_preamble_override value %d invalid.\n", + dev->name, mcas_to_preamble_override); + return -EINVAL; + } + + write_latency = dev_read_u32_default(dev, "write_latency", 0); + if (write_latency > 7 || write_latency == 0) { + debug("%s: write_latency value %d invalid.\n", + dev->name, write_latency); + return -EINVAL; + } + + read_to_precharge = dev_read_u32_default(dev, "read_to_precharge", 0); + if (read_to_precharge > 4 || read_to_precharge == 0) { + debug("%s: read_to_precharge value %d invalid.\n", + dev->name, read_to_precharge); + return -EINVAL; + } + + write_cmd_to_write_data = + dev_read_u32_default(dev, "write_cmd_to_write_data", 0); + switch (write_cmd_to_write_data) { + case CLOCK_DELAY_0: + case CLOCK_DELAY_1_4: + case CLOCK_DELAY_1_2: + case CLOCK_DELAY_3_4: + case CLOCK_DELAY_1: + case CLOCK_DELAY_5_4: + case CLOCK_DELAY_3_2: + break; + default: + debug("%s: write_cmd_to_write_data value %d invalid.\n", + dev->name, write_cmd_to_write_data); + return -EINVAL; + } + + minimum_cke_pulse_width = + dev_read_u32_default(dev, "minimum_cke_pulse_width", 0); + if (minimum_cke_pulse_width > 4 || minimum_cke_pulse_width == 0) { + debug("%s: minimum_cke_pulse_width value %d invalid.\n", + dev->name, minimum_cke_pulse_width); + return -EINVAL; + } + + four_activates_window = + dev_read_u32_default(dev, "four_activates_window", 0); + if (four_activates_window > 20 || four_activates_window == 0) { + debug("%s: four_activates_window value %d invalid.\n", + dev->name, four_activates_window); + return -EINVAL; + } + + timing_cfg_2 = additive_latency << TIMING_CFG2_ADD_LAT_SHIFT | + mcas_to_preamble_override << TIMING_CFG2_CPO_SHIFT | + write_latency << TIMING_CFG2_WR_LAT_DELAY_SHIFT | + read_to_precharge << TIMING_CFG2_RD_TO_PRE_SHIFT | + write_cmd_to_write_data << TIMING_CFG2_WR_DATA_DELAY_SHIFT | + minimum_cke_pulse_width << TIMING_CFG2_CKE_PLS_SHIFT | + four_activates_window << TIMING_CFG2_FOUR_ACT_SHIFT; + + out_be32(&im->ddr.timing_cfg_2, timing_cfg_2); + + self_refresh = dev_read_u32_default(dev, "self_refresh", 0); + switch (self_refresh) { + case SREN_DISABLE: + case SREN_ENABLE: + break; + default: + debug("%s: self_refresh value %d invalid.\n", + dev->name, self_refresh); + return -EINVAL; + } + + ecc = dev_read_u32_default(dev, "ecc", 0); + switch (ecc) { + case ECC_DISABLE: + case ECC_ENABLE: + break; + default: + debug("%s: ecc value %d invalid.\n", dev->name, ecc); + return -EINVAL; + } + + registered_dram = dev_read_u32_default(dev, "registered_dram", 0); + switch (registered_dram) { + case RD_DISABLE: + case RD_ENABLE: + break; + default: + debug("%s: registered_dram value %d invalid.\n", + dev->name, registered_dram); + return -EINVAL; + } + + sdram_type = dev_read_u32_default(dev, "sdram_type", 0); + switch (sdram_type) { + case TYPE_DDR1: + case TYPE_DDR2: + break; + default: + debug("%s: sdram_type value %d invalid.\n", + dev->name, sdram_type); + return -EINVAL; + } + + dynamic_power_management = + dev_read_u32_default(dev, "dynamic_power_management", 0); + switch (dynamic_power_management) { + case DYN_PWR_DISABLE: + case DYN_PWR_ENABLE: + break; + default: + debug("%s: dynamic_power_management value %d invalid.\n", + dev->name, dynamic_power_management); + return -EINVAL; + } + + databus_width = dev_read_u32_default(dev, "databus_width", 0); + switch (databus_width) { + case DATA_BUS_WIDTH_16: + case DATA_BUS_WIDTH_32: + break; + default: + debug("%s: databus_width value %d invalid.\n", + dev->name, databus_width); + return -EINVAL; + } + + nc_auto_precharge = dev_read_u32_default(dev, "nc_auto_precharge", 0); + switch (nc_auto_precharge) { + case NCAP_DISABLE: + case NCAP_ENABLE: + break; + default: + debug("%s: nc_auto_precharge value %d invalid.\n", + dev->name, nc_auto_precharge); + return -EINVAL; + } + + timing_2t = dev_read_u32_default(dev, "timing_2t", 0); + switch (timing_2t) { + case TIMING_1T: + case TIMING_2T: + break; + default: + debug("%s: timing_2t value %d invalid.\n", + dev->name, timing_2t); + return -EINVAL; + } + + bank_interleaving_ctrl = + dev_read_u32_default(dev, "bank_interleaving_ctrl", 0); + switch (bank_interleaving_ctrl) { + case INTERLEAVE_NONE: + case INTERLEAVE_1_AND_2: + break; + default: + debug("%s: bank_interleaving_ctrl value %d invalid.\n", + dev->name, bank_interleaving_ctrl); + return -EINVAL; + } + + precharge_bit_8 = dev_read_u32_default(dev, "precharge_bit_8", 0); + switch (precharge_bit_8) { + case PRECHARGE_MA_10: + case PRECHARGE_MA_8: + break; + default: + debug("%s: precharge_bit_8 value %d invalid.\n", + dev->name, precharge_bit_8); + return -EINVAL; + } + + half_strength = dev_read_u32_default(dev, "half_strength", 0); + switch (half_strength) { + case STRENGTH_FULL: + case STRENGTH_HALF: + break; + default: + debug("%s: half_strength value %d invalid.\n", + dev->name, half_strength); + return -EINVAL; + } + + bypass_initialization = + dev_read_u32_default(dev, "bypass_initialization", 0); + switch (bypass_initialization) { + case INITIALIZATION_DONT_BYPASS: + case INITIALIZATION_BYPASS: + break; + default: + debug("%s: bypass_initialization value %d invalid.\n", + dev->name, bypass_initialization); + return -EINVAL; + } + + sdram_cfg = self_refresh << SDRAM_CFG_SREN_SHIFT | + ecc << SDRAM_CFG_ECC_EN_SHIFT | + registered_dram << SDRAM_CFG_RD_EN_SHIFT | + sdram_type << SDRAM_CFG_SDRAM_TYPE_SHIFT | + dynamic_power_management << SDRAM_CFG_DYN_PWR_SHIFT | + databus_width << SDRAM_CFG_DBW_SHIFT | + nc_auto_precharge << SDRAM_CFG_NCAP_SHIFT | + timing_2t << SDRAM_CFG_2T_EN_SHIFT | + bank_interleaving_ctrl << SDRAM_CFG_BA_INTLV_CTL_SHIFT | + precharge_bit_8 << SDRAM_CFG_PCHB8_SHIFT | + half_strength << SDRAM_CFG_HSE_SHIFT | + bypass_initialization << SDRAM_CFG_BI_SHIFT; + + out_be32(&im->ddr.sdram_cfg, sdram_cfg); + + force_self_refresh = dev_read_u32_default(dev, "force_self_refresh", 0); + switch (force_self_refresh) { + case MODE_NORMAL: + case MODE_REFRESH: + break; + default: + debug("%s: force_self_refresh value %d invalid.\n", + dev->name, force_self_refresh); + return -EINVAL; + } + + dll_reset = dev_read_u32_default(dev, "dll_reset", 0); + switch (dll_reset) { + case DLL_RESET_ENABLE: + case DLL_RESET_DISABLE: + break; + default: + debug("%s: dll_reset value %d invalid.\n", + dev->name, dll_reset); + return -EINVAL; + } + + dqs_config = dev_read_u32_default(dev, "dqs_config", 0); + switch (dqs_config) { + case DQS_TRUE: + break; + default: + debug("%s: dqs_config value %d invalid.\n", + dev->name, dqs_config); + return -EINVAL; + } + + odt_config = dev_read_u32_default(dev, "odt_config", 0); + switch (odt_config) { + case ODT_ASSERT_NEVER: + case ODT_ASSERT_WRITES: + case ODT_ASSERT_READS: + case ODT_ASSERT_ALWAYS: + break; + default: + debug("%s: odt_config value %d invalid.\n", + dev->name, odt_config); + return -EINVAL; + } + + posted_refreshes = dev_read_u32_default(dev, "posted_refreshes", 0); + if (posted_refreshes > 8 || posted_refreshes == 0) { + debug("%s: posted_refreshes value %d invalid.\n", + dev->name, posted_refreshes); + return -EINVAL; + } + + sdram_cfg2 = force_self_refresh << SDRAM_CFG2_FRC_SR_SHIFT | + dll_reset << SDRAM_CFG2_DLL_RST_DIS | + dqs_config << SDRAM_CFG2_DQS_CFG | + odt_config << SDRAM_CFG2_ODT_CFG | + posted_refreshes << SDRAM_CFG2_NUM_PR; + + out_be32(&im->ddr.sdram_cfg2, sdram_cfg2); + + sdmode = dev_read_u32_default(dev, "sdmode", 0); + if (sdmode > 0xFFFF) { + debug("%s: sdmode value %d invalid.\n", + dev->name, sdmode); + return -EINVAL; + } + + esdmode = dev_read_u32_default(dev, "esdmode", 0); + if (esdmode > 0xFFFF) { + debug("%s: esdmode value %d invalid.\n", dev->name, esdmode); + return -EINVAL; + } + + sdram_mode = sdmode << SDRAM_MODE_SD_SHIFT | + esdmode << SDRAM_MODE_ESD_SHIFT; + + out_be32(&im->ddr.sdram_mode, sdram_mode); + + esdmode2 = dev_read_u32_default(dev, "esdmode2", 0); + if (esdmode2 > 0xFFFF) { + debug("%s: esdmode2 value %d invalid.\n", dev->name, esdmode2); + return -EINVAL; + } + + esdmode3 = dev_read_u32_default(dev, "esdmode3", 0); + if (esdmode3 > 0xFFFF) { + debug("%s: esdmode3 value %d invalid.\n", dev->name, esdmode3); + return -EINVAL; + } + + sdram_mode2 = esdmode2 << SDRAM_MODE2_ESD2_SHIFT | + esdmode3 << SDRAM_MODE2_ESD3_SHIFT; + + out_be32(&im->ddr.sdram_mode2, sdram_mode2); + + refresh_interval = dev_read_u32_default(dev, "refresh_interval", 0); + if (refresh_interval > 0xFFFF) { + debug("%s: refresh_interval value %d invalid.\n", + dev->name, refresh_interval); + return -EINVAL; + } + + precharge_interval = dev_read_u32_default(dev, "precharge_interval", 0); + if (precharge_interval > 0x3FFF) { + debug("%s: precharge_interval value %d invalid.\n", + dev->name, precharge_interval); + return -EINVAL; + } + + sdram_interval = refresh_interval << SDRAM_INTERVAL_REFINT_SHIFT | + precharge_interval << SDRAM_INTERVAL_BSTOPRE_SHIFT; + + out_be32(&im->ddr.sdram_interval, sdram_interval); + sync(); + + /* Enable DDR controller */ + setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); + sync(); + + dev_for_each_subnode(subnode, dev) { + u32 val[3]; + u32 addr, size; + + /* CS, map address, size -> three values */ + ofnode_read_u32_array(subnode, "reg", val, 3); + + addr = val[1]; + size = val[2]; + + priv->total_size += get_ram_size((long int *)addr, size); + }; + + gd->ram_size = priv->total_size; + + return 0; +} + +static int mpc83xx_sdram_get_info(struct udevice *dev, struct ram_info *info) +{ + /* TODO(mario.six(a)gdsys.cc): Implement */ + return 0; +} + +static struct ram_ops mpc83xx_sdram_ops = { + .get_info = mpc83xx_sdram_get_info, +}; + +static const struct udevice_id mpc83xx_sdram_ids[] = { + { .compatible = "fsl,mpc83xx-mem-controller" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mpc83xx_sdram) = { + .name = "mpc83xx_sdram", + .id = UCLASS_RAM, + .of_match = mpc83xx_sdram_ids, + .ops = &mpc83xx_sdram_ops, + .ofdata_to_platdata = mpc83xx_sdram_ofdata_to_platdata, + .probe = mpc83xx_sdram_probe, + .priv_auto_alloc_size = sizeof(struct mpc83xx_sdram_priv), +}; diff --git a/include/dt-bindings/memory/mpc83xx-sdram.h b/include/dt-bindings/memory/mpc83xx-sdram.h new file mode 100644 index 00000000000..7d4ce01cc48 --- /dev/null +++ b/include/dt-bindings/memory/mpc83xx-sdram.h @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six(a)gdsys.cc + */ + +#ifndef DT_BINDINGS_MPC83XX_SDRAM_H +#define DT_BINDINGS_MPC83XX_SDRAM_H + +/* DDR Control Driver register */ + +#define DSO_DISABLE 0 +#define DSO_ENABLE 1 + +#define DSO_P_IMPEDANCE_HIGHEST_Z 0x0 +#define DSO_P_IMPEDANCE_MUCH_HIGHER_Z 0x8 +#define DSO_P_IMPEDANCE_HIGHER_Z 0xC +#define DSO_P_IMPEDANCE_NOMINAL 0xE +#define DSO_P_IMPEDANCE_LOWER_Z 0xF + +#define DSO_N_IMPEDANCE_HIGHEST_Z 0x0 +#define DSO_N_IMPEDANCE_MUCH_HIGHER_Z 0x8 +#define DSO_N_IMPEDANCE_HIGHER_Z 0xC +#define DSO_N_IMPEDANCE_NOMINAL 0xE +#define DSO_N_IMPEDANCE_LOWER_Z 0xF + +#define ODT_TERMINATION_75_OHM 0 +#define ODT_TERMINATION_150_OHM 1 + +#define DDR_TYPE_DDR2_1_8_VOLT 0 +#define DDR_TYPE_DDR1_2_5_VOLT 1 + +#define MVREF_SEL_EXTERNAL 0 +#define MVREF_SEL_INTERNAL_GVDD 1 + +#define M_ODR_ENABLE 0 +#define M_ODR_DISABLE 1 + +/* CS config register */ + +#define AUTO_PRECHARGE_ENABLE 0x00800000 +#define AUTO_PRECHARGE_DISABLE 0x00000000 + +#define ODT_RD_NEVER 0x00000000 +#define ODT_RD_ONLY_CURRENT 0x00100000 +#define ODT_RD_ONLY_OTHER_CS 0x00200000 +#define ODT_RD_ONLY_OTHER_DIMM 0x00300000 +#define ODT_RD_ALL 0x00400000 + +#define ODT_WR_NEVER 0x00000000 +#define ODT_WR_ONLY_CURRENT 0x00010000 +#define ODT_WR_ONLY_OTHER_CS 0x00020000 +#define ODT_WR_ONLY_OTHER_DIMM 0x00030000 +#define ODT_WR_ALL 0x00040000 + +/* DDR SDRAM Clock Control register */ + +#define CLOCK_ADJUST_025 0x01000000 +#define CLOCK_ADJUST_05 0x02000000 +#define CLOCK_ADJUST_075 0x03000000 +#define CLOCK_ADJUST_1 0x04000000 + +#define CASLAT_20 0x3 /* CAS latency = 2.0 */ +#define CASLAT_25 0x4 /* CAS latency = 2.5 */ +#define CASLAT_30 0x5 /* CAS latency = 3.0 */ +#define CASLAT_35 0x6 /* CAS latency = 3.5 */ +#define CASLAT_40 0x7 /* CAS latency = 4.0 */ +#define CASLAT_45 0x8 /* CAS latency = 4.5 */ +#define CASLAT_50 0x9 /* CAS latency = 5.0 */ +#define CASLAT_55 0xa /* CAS latency = 5.5 */ +#define CASLAT_60 0xb /* CAS latency = 6.0 */ +#define CASLAT_65 0xc /* CAS latency = 6.5 */ +#define CASLAT_70 0xd /* CAS latency = 7.0 */ +#define CASLAT_75 0xe /* CAS latency = 7.5 */ +#define CASLAT_80 0xf /* CAS latency = 8.0 */ + +/* DDR SDRAM Timing Configuration 2 register */ + +#define READ_LAT_PLUS_1 0x0 +#define READ_LAT 0x2 +#define READ_LAT_PLUS_1_4 0x3 +#define READ_LAT_PLUS_1_2 0x4 +#define READ_LAT_PLUS_3_4 0x5 +#define READ_LAT_PLUS_5_4 0x7 +#define READ_LAT_PLUS_3_2 0x8 +#define READ_LAT_PLUS_7_4 0x9 +#define READ_LAT_PLUS_2 0xA +#define READ_LAT_PLUS_9_4 0xB +#define READ_LAT_PLUS_5_2 0xC +#define READ_LAT_PLUS_11_4 0xD +#define READ_LAT_PLUS_3 0xE +#define READ_LAT_PLUS_13_4 0xF +#define READ_LAT_PLUS_7_2 0x10 +#define READ_LAT_PLUS_15_4 0x11 +#define READ_LAT_PLUS_4 0x12 +#define READ_LAT_PLUS_17_4 0x13 +#define READ_LAT_PLUS_9_2 0x14 +#define READ_LAT_PLUS_19_4 0x15 + +#define CLOCK_DELAY_0 0x0 +#define CLOCK_DELAY_1_4 0x1 +#define CLOCK_DELAY_1_2 0x2 +#define CLOCK_DELAY_3_4 0x3 +#define CLOCK_DELAY_1 0x4 +#define CLOCK_DELAY_5_4 0x5 +#define CLOCK_DELAY_3_2 0x6 + +/* DDR SDRAM Control Configuration */ + +#define SREN_DISABLE 0x0 +#define SREN_ENABLE 0x1 + +#define ECC_DISABLE 0x0 +#define ECC_ENABLE 0x1 + +#define RD_DISABLE 0x0 +#define RD_ENABLE 0x1 + +#define TYPE_DDR1 0x2 +#define TYPE_DDR2 0x3 + +#define DYN_PWR_DISABLE 0x0 +#define DYN_PWR_ENABLE 0x1 + +#define DATA_BUS_WIDTH_16 0x1 +#define DATA_BUS_WIDTH_32 0x2 + +#define NCAP_DISABLE 0x0 +#define NCAP_ENABLE 0x1 + +#define TIMING_1T 0x0 +#define TIMING_2T 0x1 + +#define INTERLEAVE_NONE 0x0 +#define INTERLEAVE_1_AND_2 0x1 + +#define PRECHARGE_MA_10 0x0 +#define PRECHARGE_MA_8 0x1 + +#define STRENGTH_FULL 0x0 +#define STRENGTH_HALF 0x1 + +#define INITIALIZATION_DONT_BYPASS 0x0 +#define INITIALIZATION_BYPASS 0x1 + +/* DDR SDRAM Control Configuration 2 register */ + +#define MODE_NORMAL 0x0 +#define MODE_REFRESH 0x1 + +#define DLL_RESET_ENABLE 0x0 +#define DLL_RESET_DISABLE 0x1 + +#define DQS_TRUE 0x0 + +#define ODT_ASSERT_NEVER 0x0 +#define ODT_ASSERT_WRITES 0x1 +#define ODT_ASSERT_READS 0x2 +#define ODT_ASSERT_ALWAYS 0x3 + +#endif diff --git a/include/mpc83xx.h b/include/mpc83xx.h index e1e50ab6b50..a4c5bd38376 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -1110,6 +1110,8 @@ #define CSBNDS_EA 0x000000FF #define CSBNDS_EA_SHIFT 24 +#ifndef CONFIG_MPC83XX_SDRAM + /* * CSn_CONFIG - Chip Select Configuration Register */ @@ -1407,6 +1409,8 @@ #define ECC_ERROR_MAN_SBEC (0xff000000 >> 24) #define ECC_ERROR_MAN_SBEC_SHIFT 0 +#endif /* !CONFIG_MPC83XX_SDRAM */ + /* * CONFIG_ADDRESS - PCI Config Address Register */ @@ -1510,6 +1514,7 @@ */ #define PMCCR1_POWER_OFF 0x00000020 +#ifndef CONFIG_RAM /* * DDRCDR - DDR Control Driver Register */ @@ -1531,6 +1536,7 @@ #define DDRCDR_DDR_CFG 0x00040000 #define DDRCDR_M_ODR 0x00000002 #define DDRCDR_Q_DRN 0x00000001 +#endif /* !CONFIG_RAM */ /* * PCIE Bridge Register -- 2.11.0

5 42

[U-Boot] [PATCH] sunxi: lower the DDR frequency of Orange Pi Prime
by Icenowy Zheng 29 Oct '18

29 Oct '18

When I use Orange Pi Prime to do some heavy compliation tasks, the gcc compiler sometimes mysteriously segfaults, and memtester catches memory error. As the lima-memtester cannot support H5 (Mali-450 GPU equipped), there's no really reliable way to detect DRAM stability except try and error. Lower the DDR frequency to 624MHz seems to solved the issue. Set the default frequency to 624MHz in the defconfig, as 672MHz is observed to be unstable at least on my board. Signed-off-by: Icenowy Zheng <icenowy(a)aosc.io> --- configs/orangepi_prime_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig index 3d87374002..88eaf12741 100644 --- a/configs/orangepi_prime_defconfig +++ b/configs/orangepi_prime_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN50I_H5=y -CONFIG_DRAM_CLK=672 +CONFIG_DRAM_CLK=624 CONFIG_DRAM_ZQ=3881977 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -- 2.13.6

5 9

[U-Boot] [PATCH] cmd: mii: don't check address for 'device' subcommand
by Hector Palacios 24 Oct '18

24 Oct '18

All mii operations require a valid PHY address except the 'device' command, which expects the PHY name rather than the address. Signed-off-by: Hector Palacios <hector.palacios(a)digi.com> --- cmd/mii.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/mii.c b/cmd/mii.c index ce7b393eeaae..c0c42a851f90 100644 --- a/cmd/mii.c +++ b/cmd/mii.c @@ -313,7 +313,7 @@ static int do_mii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) mask = simple_strtoul(argv[5], NULL, 16); } - if (addrhi > 31) { + if (addrhi > 31 && strncmp(op, "de", 2)) { printf("Incorrect PHY address. Range should be 0-31\n"); return CMD_RET_USAGE; }

3 2

[U-Boot] [PATCH 0/5] Get socfpga gen5 SPL working again.
by Simon Goldschmidt 24 Oct '18

24 Oct '18

Socfpga gen5 SPL has been broken since moving to DM serial with v2018.07.. Also, U-Boot console output has been broken since then. This series fixes this and makes some related small improvements. Simon Goldschmidt (5): arm: socfpga: fix SPL on gen5 after moving to DM serial arm: socfpga: fix device trees to work with DM serial arm: socfpga: cyclone5: handle debug uart board_init.c: fix simple malloc by storing malloc_limit malloc_simple: calloc: don't call memset if malloc failed arch/arm/dts/socfpga.dtsi | 1 + arch/arm/dts/socfpga_arria5_socdk.dts | 1 + arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 1 + arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts | 1 + arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 1 + arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 1 + arch/arm/dts/socfpga_cyclone5_is1.dts | 1 + arch/arm/dts/socfpga_cyclone5_socdk.dts | 1 + arch/arm/dts/socfpga_cyclone5_sockit.dts | 1 + arch/arm/dts/socfpga_cyclone5_socrates.dts | 6 ++++++ arch/arm/dts/socfpga_cyclone5_sr1500.dts | 1 + arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 1 + arch/arm/mach-socfpga/reset_manager_gen5.c | 5 +++-- arch/arm/mach-socfpga/spl_gen5.c | 16 +++++++++++++--- common/init/board_init.c | 1 + common/malloc_simple.c | 3 ++- 16 files changed, 36 insertions(+), 6 deletions(-) -- 2.17.1

7 43