August 2018 - U-Boot

[U-Boot] [PATCH 0/1] mtd: nand: fsl-ifc: Fix handling of bitflips
by Kurt Kanzenbach 13 Aug '18

13 Aug '18

Hi, this is a resend of the following patch: https://patchwork.ozlabs.org/patch/774424/ It seems like that patch hasn't been merged, yet. However, I stumbled across the same issue. Linux has an equivalent patch already upstream. Furthermore, I've tested the patch on hardware and it seems to work fine. Thanks, Kurt Darwin Dingel (1): mtd: nand: fsl_ifc: Fix handling of bitflips in erased pages drivers/mtd/nand/fsl_ifc_nand.c | 69 +++++++++++++++++++++++------------------ 1 file changed, 39 insertions(+), 30 deletions(-) -- 2.11.0

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[U-Boot] [PATCH v8 0/8] NXP LS1046A SMMU enabling patches
by laurentiu.tudor＠nxp.com 13 Aug '18

13 Aug '18

From: Laurentiu Tudor <laurentiu.tudor(a)nxp.com> This patch series adds the required devices setup and device tree fixups for SMMU enablement on NXP LS1046A chips. The approach taken tries to mimic the implementation of PAMU LIODN setup on booke powerpc. First 4 patches contain some fixes and add some missing bits & pieces. Last 4 patches add the actual infrastructure for ICID setup, qman portals, fman ICID and SEC configuration. Changes in v8: - fix link error introduced by patch [6/8] on LS1043A targets: "drivers/built-in.o: relocation R_AARCH64_ADR_PREL_PG_HI21 against external symbol `qp_info' can not be used when making a shared object;" - added missed "Reviewed-By:" tags except patch [6/8] which changed - compile tested all frescale boards with buildman Changes in v7: - fix this build breakage introduced by patch [6/8] on booke ppc appearing with certain tool chain versions: "drivers/misc/fsl_portals.c: In function 'fdt_fixup_qportals': drivers/misc/fsl_portals.c:256:3: error: 'for' loop initial declarations are only allowed in C99 or C11 mode" - fixed linker error on LS1012A targets: "arch/arm/cpu/armv8/built-in.o: In function `fsl_lsch2_early_init_f': arch/arm/cpu/armv8/fsl-layerscape/soc.c:691: undefined reference to `set_icids'" Changes in v6: - distinct ICIDs for all SEC blocks (Horia, Bharat) Changes in v5: - use distinct ICID for SEC JRs (Horia, Bharat) - moved an #include in the file it's used (Horia) - fix broken compilation of multiple targets due to removal of SEC related config (Horia) - add a missing #include in qds board file - drop few uses of CONFIG_SYS_FMAN_V3 and consistently use CONFIG_SYS_DPAA_FMAN everywhere Changes in v4: - added missing SEC ICID config - updated macro params to match arguments - supplemental comments Changes in v3: - cleaner QMAN_BAR setup - moved SoC specific bits from generic ICID arch setup to board code Changes in v2: - drop CONFIG_SYS_ prefix from newly introduced defines in patch [1/8] Laurentiu Tudor (8): armv8: fsl-layerscape: add missing register blocks base address defines armv8: ls1046a: advertise QMan v3 in configuration misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms armv8: fsl-layerscape: add missing debug stream ID armv8: ls1046a: initial icid setup support armv8: ls1046a: add icid setup for qman portals armv8: ls1046a: setup fman ports ICIDs and device tree armv8: ls1046a: setup SEC ICIDs and fix up device tree arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + arch/arm/cpu/armv8/fsl-layerscape/icid.c | 192 ++++++++++++++++++ .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 89 ++++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 5 + .../include/asm/arch-fsl-layerscape/config.h | 1 + .../asm/arch-fsl-layerscape/fsl_icid.h | 115 +++++++++++ .../asm/arch-fsl-layerscape/fsl_portals.h | 24 +++ .../asm/arch-fsl-layerscape/immap_lsch2.h | 15 +- .../asm/arch-fsl-layerscape/stream_id_lsch2.h | 1 + board/freescale/ls1046aqds/ls1046aqds.c | 3 + board/freescale/ls1046ardb/ls1046ardb.c | 3 + drivers/misc/fsl_portals.c | 45 +++- 12 files changed, 486 insertions(+), 8 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/icid.c create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h -- 2.17.1

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[U-Boot] [PATCH 0/2] Ethernet name length changes
by Pankaj Bansal 13 Aug '18

13 Aug '18

The ethernet name should be within the ETH_NAME_LEN, as this is the buffer space allocated to ethernet name. Otherwise, this causes buffer overflow. At the same time the 16 char ethernet name size is inadequate to hold the name of ethernet "DPMAC17@rgmii-id", which is a valid name in upcoming LX2160AQDS/LX2160ARDB boards. These patches try to solve the above two issues: 1. first patch honors the limit imposed by ETH_NAME_LEN on ethernet name 2. second patch increases this limit to accommodate the requirements of LX2160AQDS/LX2160ARDB Cc: Varun Sethi <V.Sethi(a)nxp.com> Pankaj Bansal (2): fsl/mc: Limit the ethernet name to ETH_NAME_LEN net: Increase ethernet name string size to 20 chars drivers/net/fsl-mc/mc.c | 6 +++--- drivers/net/ldpaa_eth/ldpaa_eth.c | 4 ++-- include/net.h | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) -- 2.17.1

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[U-Boot] [PATCH] FSL PCI: Configure PCIe reference ratio
by Joakim Tjernlund 13 Aug '18

13 Aug '18

Most FSL PCIe controllers expects 333 MHz PCI reference clock. This clock is derived from the CCB but in many cases the ref. clock is not 333 MHz and a divisor needs to be configured. This adds PEX_CCB_DIV #define which can be defined for each type of CPU/platform. Signed-off-by: Joakim Tjernlund <joakim.tjernlund(a)infinera.com> --- drivers/pci/fsl_pci_init.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 52792dcd59..4d00b3f26c 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) pci_setup_indirect(hose, cfg_addr, cfg_data); +#ifdef PEX_CCB_DIV + /* Configure the PCIE controller core clock ratio */ + pci_hose_write_config_dword(hose, dev, 0x440, + ((gd->bus_clk / 1000000) * + (16 / PEX_CCB_DIV)) / 333); +#endif block_rev = in_be32(&pci->block_rev1); if (PEX_IP_BLK_REV_2_2 <= block_rev) { pi = &pci->pit[2]; /* 0xDC0 */ -- 2.13.5

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[U-Boot] [PATCH v2] Board: ls1088ardb: Enable PCIe config for Secure boot defconfigs
by Vinitha V Pillai 13 Aug '18

13 Aug '18

Enable PCIe config options in LS1088 SD Secure Boot defconfig Signed-off-by: Vinitha V Pillai <vinitha.pillai(a)nxp.com> --- Changes in v2: Changed the commit message and added reviewers configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 7341fef..974b8fb 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -43,6 +43,10 @@ CONFIG_FSL_SPI_ALIGNED_TXFIFO=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y CONFIG_SYS_NS16550=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y -- 1.9.1

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[U-Boot] [PATCH] arm: ls102xa: Fix RGMII phy-connection-type FDT fixup
by Brendan Shanks 13 Aug '18

13 Aug '18

In ft_fixup_enet_phy_connect_type(), use strlen() instead of sizeof() on the pointer result of phy_string_for_interface(). sizeof() was returning the size of the pointer (4 bytes), resulting in the phy-connection-type being set to "rgmi" rather than "rgmii-id". Signed-off-by: Brendan Shanks <brendan.shanks(a)teradek.com> Cc: York Sun <york.sun(a)nxp.com> --- arch/arm/cpu/armv7/ls102xa/fdt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 6c3caf8..8bf9c42 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -64,8 +64,8 @@ void ft_fixup_enet_phy_connect_type(void *fdt) do_fixup_by_path(fdt, enet_path, "phy-connection-type", phy_string_for_interface( PHY_INTERFACE_MODE_RGMII_ID), - sizeof(phy_string_for_interface( - PHY_INTERFACE_MODE_RGMII_ID)), + strlen(phy_string_for_interface( + PHY_INTERFACE_MODE_RGMII_ID)) + 1, 1); } } -- 2.7.4

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[U-Boot] [PATCH] board: freescale: ls1012ardb: Add command to switch QSPI bank
by Jagdish Gediya 13 Aug '18

13 Aug '18

Add command "boot_bank X" to switch the boot bank to either 1 or 2. Signed-off-by: Jagdish Gediya <jagdish.gediya(a)nxp.com> --- board/freescale/ls1012ardb/ls1012ardb.c | 85 +++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index ed5a8e6..4d4f6fb 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -26,6 +26,9 @@ DECLARE_GLOBAL_DATA_PTR; +#define BOOT_FROM_UPPER_BANK 0x2 +#define BOOT_FROM_LOWER_BANK 0x1 + int checkboard(void) { #ifdef CONFIG_TARGET_LS1012ARDB @@ -212,3 +215,85 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } + +static int switch_to_bank1(void) +{ + u8 data; + int ret; + + i2c_set_bus_num(0); + + data = 0xf4; + ret = i2c_write(0x24, 0x3, 1, &data, 1); + if (ret) { + printf("i2c write error to chip : %u, addr : %u, data : %u\n", + 0x24, 0x3, data); + } + + return ret; +} + +static int switch_to_bank2(void) +{ + u8 data; + int ret; + + i2c_set_bus_num(0); + + data = 0xfc; + ret = i2c_write(0x24, 0x7, 1, &data, 1); + if (ret) { + printf("i2c write error to chip : %u, addr : %u, data : %u\n", + 0x24, 0x7, data); + goto err; + } + + data = 0xf5; + ret = i2c_write(0x24, 0x3, 1, &data, 1); + if (ret) { + printf("i2c write error to chip : %u, addr : %u, data : %u\n", + 0x24, 0x3, data); + } +err: + return ret; +} + +static int convert_flash_bank(int bank) +{ + int ret = 0; + + switch (bank) { + case BOOT_FROM_UPPER_BANK: + ret = switch_to_bank2(); + break; + case BOOT_FROM_LOWER_BANK: + ret = switch_to_bank1(); + break; + default: + ret = CMD_RET_USAGE; + break; + }; + + return ret; +} + +static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + if (strcmp(argv[1], "1") == 0) + convert_flash_bank(BOOT_FROM_LOWER_BANK); + else if (strcmp(argv[1], "2") == 0) + convert_flash_bank(BOOT_FROM_UPPER_BANK); + else + return CMD_RET_USAGE; + + return 0; +} + +U_BOOT_CMD( + boot_bank, 2, 0, flash_bank_cmd, + "Flash bank Selection Control", + "bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)" +); -- 1.9.1

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[U-Boot] [PATCH v3 0/8] Get socfpga gen5 SPL working again.
by Simon Goldschmidt 13 Aug '18

13 Aug '18

Socfpga gen5 SPL has been broken since moving to DM serial with v2018.07. Also, U-Boot console output has been broken since then. This series fixes this and makes some related small improvements. Changes in v3: - moved uart0's "u-boot,dm-pre-reloc;" from socfpga.dtsi to board specific dts files since this can change per board - added patches 5-7 to boot SPL and U-Boot from fpga OnChip RAM - dropped Patch 5/6 "serial: ns16550: fix debug uart putc called before init" (this needs a more generic fix) Changes in v2: - Improved comment on patch 1 - Removing gd->malloc_base assignment at the end of board_init_f() moved to an extra patch - don't change printf() to debug() in reset_manager_gen5.c socfpga_bridges_reset() (instead make debug uart handle this) - make ns16550 debug uart handle putc being called before init - removed the assignment of gd->malloc_limit from board_init() Simon Goldschmidt (8): arm: socfpga: fix SPL on gen5 after moving to DM serial arm: socfpga: fix device trees to work with DM serial arm: socfpga: spl_gen5: clean up malloc_base assignment arm: socfpga: cyclone5: handle debug uart arm: socfpga: fix U-Boot running from fpga OnChip RAM arm: socfpga: gen5: combine some init code for SPL and U-Boot arm: socfpga: fix SPL booting from fpga OnChip RAM malloc_simple: calloc: don't call memset if malloc failed arch/arm/dts/socfpga_arria5_socdk.dts | 5 ++ arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 5 ++ .../arm/dts/socfpga_cyclone5_de0_nano_soc.dts | 5 ++ arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 5 ++ arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 5 ++ arch/arm/dts/socfpga_cyclone5_is1.dts | 5 ++ arch/arm/dts/socfpga_cyclone5_socdk.dts | 5 ++ arch/arm/dts/socfpga_cyclone5_sockit.dts | 5 ++ arch/arm/dts/socfpga_cyclone5_socrates.dts | 5 ++ arch/arm/dts/socfpga_cyclone5_sr1500.dts | 2 + arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 5 ++ arch/arm/mach-socfpga/Kconfig | 12 +++++ arch/arm/mach-socfpga/include/mach/misc.h | 4 ++ arch/arm/mach-socfpga/misc_gen5.c | 40 +++++++++------ arch/arm/mach-socfpga/spl_gen5.c | 49 ++++++------------- common/malloc_simple.c | 3 +- include/configs/socfpga_common.h | 13 +++++ 17 files changed, 125 insertions(+), 48 deletions(-) -- 2.17.1

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[U-Boot] [PATCH v2] cmd: fastboot: Validate user input
by Sam Protsenko 13 Aug '18

13 Aug '18

In case when user provides '-' as USB controller index, like this: => fastboot - data abort occurs in strcmp() function in do_fastboot(), here: if (!strcmp(argv[1], "udp")) (tested on BeagleBone Black). That's because argv[1] is NULL when user types in the '-', and null pointer dereference occurs in strcmp() (which is ok according to C standard specification). So we must validate user input to prevent such behavior. While at it, check also the result of strtoul() function and handle error cases properly. Signed-off-by: Sam Protsenko <semen.protsenko(a)linaro.org> --- Changes for v2: - replace argv check with argc check - add mentioning of testing platform in commit message cmd/fastboot.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/cmd/fastboot.c b/cmd/fastboot.c index e6ae0570d5..ae3a5f627f 100644 --- a/cmd/fastboot.c +++ b/cmd/fastboot.c @@ -38,13 +38,18 @@ static int do_fastboot_usb(int argc, char *const argv[], #if CONFIG_IS_ENABLED(USB_FUNCTION_FASTBOOT) int controller_index; char *usb_controller; + char *endp; int ret; if (argc < 2) return CMD_RET_USAGE; usb_controller = argv[1]; - controller_index = simple_strtoul(usb_controller, NULL, 0); + controller_index = simple_strtoul(usb_controller, &endp, 0); + if (*endp != '\0') { + pr_err("Error: Wrong USB controller index format\n"); + return CMD_RET_FAILURE; + } ret = board_usb_init(controller_index, USB_INIT_DEVICE); if (ret) { @@ -120,6 +125,12 @@ NXTARG: ; } + /* Handle case when USB controller param is just '-' */ + if (argc == 1) { + pr_err("Error: Incorrect USB controller index\n"); + return CMD_RET_USAGE; + } + fastboot_init((void *)buf_addr, buf_size); if (!strcmp(argv[1], "udp")) -- 2.17.1

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[U-Boot] [PATCH] sunxi: A64: fix default DRAM_ODT_EN symbol
by Andre Przywara 13 Aug '18

13 Aug '18

"default" lines in Kconfig are processed in order, the first hit will stop considering subsequent lines. In the case of the DRAM_ODT_EN symbol that means that everything following the first two lines will never be checked: ------------ config DRAM_ODT_EN bool "sunxi dram odt enable" default n if !MACH_SUN8I_A23 default y if MACH_SUN8I_A23 default y if MACH_SUN8I_R40 default y if MACH_SUN50I ------------ Assuming that the "default y" for the A64 and the R40 were a deliberate choice, fix the Kconfig stanza to take this into account. Also remove the now redundant lines from the respective defconfigs. Signed-off-by: Andre Przywara <andre.przywara(a)arm.com> --- Hi, I would be grateful if people could test this and find out whether enabling ODT works reliably. Thanks! Andre. arch/arm/mach-sunxi/Kconfig | 2 +- configs/Bananapi_M2_Ultra_defconfig | 1 - configs/amarula_a64_relic_defconfig | 1 - configs/bananapi_m2_berry_defconfig | 1 - configs/sopine_baseboard_defconfig | 1 - 5 files changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 678e33dd40..7ff0347e20 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -405,10 +405,10 @@ config DRAM_ZQ config DRAM_ODT_EN bool "sunxi dram odt enable" - default n if !MACH_SUN8I_A23 default y if MACH_SUN8I_A23 default y if MACH_SUN8I_R40 default y if MACH_SUN50I + default n ---help--- Select this to enable dram odt (on die termination). diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig index edcbb16cf6..914ca09708 100644 --- a/configs/Bananapi_M2_Ultra_defconfig +++ b/configs/Bananapi_M2_Ultra_defconfig @@ -4,7 +4,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_R40=y CONFIG_DRAM_CLK=576 CONFIG_DRAM_ZQ=3881979 -CONFIG_DRAM_ODT_EN=y CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra" diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig index b72cbfabc6..9ab4c0c1de 100644 --- a/configs/amarula_a64_relic_defconfig +++ b/configs/amarula_a64_relic_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y -CONFIG_DRAM_ODT_EN=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_VIDEO_DE2 is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic" diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig index 9d75108d04..0ebb1c38da 100644 --- a/configs/bananapi_m2_berry_defconfig +++ b/configs/bananapi_m2_berry_defconfig @@ -4,7 +4,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_R40=y CONFIG_DRAM_CLK=576 CONFIG_DRAM_ZQ=3881979 -CONFIG_DRAM_ODT_EN=y CONFIG_MMC0_CD_PIN="PH13" CONFIG_DEFAULT_DEVICE_TREE="sun8i-v40-bananapi-m2-berry" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig index c79c111b5d..1d0b3fbbc7 100644 --- a/configs/sopine_baseboard_defconfig +++ b/configs/sopine_baseboard_defconfig @@ -6,7 +6,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=3881949 -CONFIG_DRAM_ODT_EN=y CONFIG_MMC0_CD_PIN="" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y -- 2.14.4

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