August 2018 - U-Boot

[U-Boot] [PATCH] armv8: lsch3: Add support of serdes3 module
by Priyanka Jain 24 Sep '18

24 Sep '18

Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 3 + .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 71 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 + 3 files changed, 76 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f2111fa..fd31ae1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -348,6 +348,9 @@ config SYS_FSL_SRDS_1 config SYS_FSL_SRDS_2 bool +config SYS_FSL_SRDS_3 + bool + config SYS_HAS_SERDES bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index 2bef841..bfd2868 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * Copyright 2018 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. */ @@ -16,6 +17,9 @@ static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; #ifdef CONFIG_SYS_FSL_SRDS_2 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; #endif +#ifdef CONFIG_SYS_FSL_SRDS_3 +static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT]; +#endif #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) int xfi_dpmac[XFI8 + 1]; @@ -57,6 +61,12 @@ int is_serdes_configured(enum srds_prtcl device) ret |= serdes2_prtcl_map[device]; #endif +#ifdef CONFIG_SYS_FSL_SRDS_3 + if (!serdes3_prtcl_map[NONE]) + fsl_serdes_init(); + + ret |= serdes3_prtcl_map[device]; +#endif return !!ret; } @@ -82,6 +92,13 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device) cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT; break; #endif +#ifdef CONFIG_SYS_FSL_SRDS_3 + case FSL_SRDS_3: + cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]); + cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT; + break; +#endif default: printf("invalid SerDes%d\n", sd); break; @@ -201,6 +218,12 @@ struct serdes_prctl_info srds_prctl_info[] = { .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT }, #endif +#ifdef CONFIG_SYS_FSL_SRDS_3 + {.id = 3, + .mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK, + .shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT + }, +#endif {} /* NULL ENTRY */ }; @@ -341,6 +364,11 @@ int setup_serdes_volt(u32 svdd) (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000); u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]); #endif +#ifdef CONFIG_SYS_FSL_SRDS_3 + struct ccsr_serdes __iomem *serdes3_base = + (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000); + u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]); +#endif u32 cfg_tmp; int svdd_cur, svdd_tar; int ret = 1; @@ -370,6 +398,9 @@ int setup_serdes_volt(u32 svdd) #ifdef CONFIG_SYS_FSL_SRDS_2 do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false); #endif +#ifdef CONFIG_SYS_FSL_SRDS_3 + do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false); +#endif /* Put the all enabled PLL in reset */ #ifdef CONFIG_SYS_FSL_SRDS_1 @@ -383,6 +414,12 @@ int setup_serdes_volt(u32 svdd) do_pll_reset(cfg_tmp, serdes2_base); #endif +#ifdef CONFIG_SYS_FSL_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_pll_reset(cfg_tmp, serdes3_base); +#endif + /* Put the Rx/Tx calibration into reset */ #ifdef CONFIG_SYS_FSL_SRDS_1 do_rx_tx_cal_reset(serdes1_base); @@ -392,6 +429,10 @@ int setup_serdes_volt(u32 svdd) do_rx_tx_cal_reset(serdes2_base); #endif +#ifdef CONFIG_SYS_FSL_SRDS_3 + do_rx_tx_cal_reset(serdes3_base); +#endif + ret = set_serdes_volt(svdd); if (ret < 0) { printf("could not change SVDD\n"); @@ -408,6 +449,11 @@ int setup_serdes_volt(u32 svdd) cfg_tmp >>= 2; do_serdes_enable(cfg_tmp, serdes2_base); #endif +#ifdef CONFIG_SYS_FSL_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_serdes_enable(cfg_tmp, serdes3_base); +#endif /* Wait for at at least 625us, ensure the PLLs being reset are locked */ udelay(800); @@ -422,6 +468,13 @@ int setup_serdes_volt(u32 svdd) cfg_tmp >>= 2; do_pll_lock(cfg_tmp, serdes2_base); #endif + +#ifdef CONFIG_SYS_FSL_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_pll_lock(cfg_tmp, serdes3_base); +#endif + /* Take the all enabled lanes out of reset */ #ifdef CONFIG_SYS_FSL_SRDS_1 do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true); @@ -430,6 +483,10 @@ int setup_serdes_volt(u32 svdd) do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true); #endif +#ifdef CONFIG_SYS_FSL_SRDS_3 + do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true); +#endif + /* For each PLL being reset, and achieved PLL lock set RST_DONE */ #ifdef CONFIG_SYS_FSL_SRDS_1 cfg_tmp = cfg_rcwsrds1 & 0x3; @@ -441,6 +498,12 @@ int setup_serdes_volt(u32 svdd) do_pll_reset_done(cfg_tmp, serdes2_base); #endif +#ifdef CONFIG_SYS_FSL_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_pll_reset_done(cfg_tmp, serdes3_base); +#endif + return ret; } @@ -472,4 +535,12 @@ void fsl_serdes_init(void) FSL_CHASSIS3_SRDS2_PRTCL_SHIFT, serdes2_prtcl_map); #endif +#ifdef CONFIG_SYS_FSL_SRDS_3 + serdes_init(FSL_SRDS_3, + CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_3 * 0x10000, + FSL_CHASSIS3_SRDS3_REGSR, + FSL_CHASSIS3_SRDS3_PRTCL_MASK, + FSL_CHASSIS3_SRDS3_PRTCL_SHIFT, + serdes3_prtcl_map); +#endif } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 6981076..bec35e8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright 2018 NXP * Copyright 2015 Freescale Semiconductor, Inc. */ @@ -57,6 +58,7 @@ enum srds_prtcl { enum srds { FSL_SRDS_1 = 0, FSL_SRDS_2 = 1, + FSL_SRDS_3 = 2, }; #elif defined(CONFIG_FSL_LSCH2) enum srds_prtcl { -- 2.7.4

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[U-Boot] [PATCH v3 0/3] efi_loader: ARM: add support for ARMV7_NONSEC=y
by Mark Kettenis 23 Sep '18

23 Sep '18

This series makes it possible to run EFI applications in non-secure mode. It allows me to run OpenBSD on the Technexion PICO-PI-IMX7 and Banana Pi boards using the PSCI implementation provided by U-Boot. The second version avoids using r3 to pass the original stack pointer. For some reason that register gets clobbered on the Banana Pi. Instead this version just migrates SP_svc to SP_hyp. This third version avoids saving r3 on the stack and fixes an include guard as suggested by Alexander Graf. Mark Kettenis (3): ARM: HYP/non-sec: migrate stack efi_loader: ARM: run EFI payloads non-secure Revert "efi_loader: no support for ARMV7_NONSEC=y" arch/arm/cpu/armv7/nonsec_virt.S | 2 ++ cmd/bootefi.c | 32 ++++++++++++++++++++++++++++++++ doc/README.uefi | 2 -- lib/efi_loader/Kconfig | 2 -- 4 files changed, 34 insertions(+), 4 deletions(-) -- 2.16.2

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[U-Boot] mainline u-boot on radxarock (rockchip rk3188) from SDcard
by Trevor Woerner 21 Sep '18

21 Sep '18

Hello, I am able to generate a bootable image (bootloader, parameter, kernel, filesystem) for my radxarock (pro) on an SDcard if I use the bootloader from https://github.com/radxa/u-boot-rockchip. When I try to use mainline u-boot_2008.01 it doesn't seem to be able to find or boot from the SDcard: U-Boot SPL 2018.01-dirty (Apr 29 2018 - 05:19:18) Returning to boot ROM... U-Boot 2018.01-dirty (Apr 29 2018 - 05:19:18 +0000) Model: Radxa Rock DRAM: 2 GiB MMC: MMC Device 0 not found *** Warning - No MMC card found, using default environment In: serial@20064000 Out: serial@20064000 Err: serial@20064000 Model: Radxa Rock rockchip_dnl_key_pressed: adc_channel_single_shot fail! Net: Net Initialization Skipped No ethernet found. Hit any key to stop autoboot: 0 No MMC device available No MMC device available No ethernet found. missing environment variable: pxeuuid missing environment variable: bootfile Retrieving file: pxelinux.cfg/00000000 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/0000000 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/000000 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/00000 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/0000 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/000 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/00 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/0 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/default-arm-rockchip No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/default-arm No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/default No ethernet found. Config file not found No ethernet found. No ethernet found. => Any thoughts? Best regards, Trevor

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[U-Boot] [PATCH 1/2 v2] board: freescale: ls1012afrx:Common files to support
by Pramod Kumar 21 Sep '18

21 Sep '18

LS1012A-FRDM and LS1012A-FRWY board. 1-Move all common files applicable for both boards LS1012A-FRDM and LS1012A-FRWY into board directory ls1012afrx. 2-Restructure LS1012A-FRDM code. Only board specific files are in LS1012A-FRDM board directory. Signed-off-by: Pramod Kumar <pramod.kumar_1(a)nxp.com> --- Depends on: http://patchwork.ozlabs.org/patch/918935/ http://patchwork.ozlabs.org/patch/918933/ http://patchwork.ozlabs.org/patch/918932/ Changes for v2: - Rebased patch to above dependency patches arch/arm/Kconfig | 2 + board/freescale/ls1012afrdm/Kconfig | 60 ---------------------- board/freescale/ls1012afrdm/MAINTAINERS | 12 +---- board/freescale/ls1012afrdm/Makefile | 4 +- board/freescale/ls1012afrx/Kconfig | 27 ++++++++++ board/freescale/{ls1012afrdm => ls1012afrx}/eth.c | 0 .../ls1012afrdm.c => ls1012afrx/ls1012afrx.c} | 0 7 files changed, 32 insertions(+), 73 deletions(-) create mode 100644 board/freescale/ls1012afrx/Kconfig rename board/freescale/{ls1012afrdm => ls1012afrx}/eth.c (100%) rename board/freescale/{ls1012afrdm/ls1012afrdm.c => ls1012afrx/ls1012afrx.c} (100%) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 22234cd..ffff190 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1417,6 +1417,8 @@ source "board/freescale/ls1046ardb/Kconfig" source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/ls1012afrdm/Kconfig" +source "board/freescale/ls1012afrx/Kconfig" +source "board/freescale/ls1012afrwy/Kconfig" source "board/freescale/mx35pdk/Kconfig" source "board/freescale/s32v234evb/Kconfig" source "board/gdsys/a38x/Kconfig" diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig index f52a896..58e592d 100644 --- a/board/freescale/ls1012afrdm/Kconfig +++ b/board/freescale/ls1012afrdm/Kconfig @@ -21,63 +21,3 @@ config SYS_LS_PPA_FW_ADDR default 0x40400000 endif - -if FSL_PFE - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select PHYLIB - imply PHY_REALTEK - imply PHY_ATHEROS - -config DDR_PFE_PHYS_BASEADDR - hex "PFE DDR physical base address" - default 0x03800000 - -config DDR_PFE_BASEADDR - hex "PFE DDR base address" - default 0x83800000 - -config PFE_EMAC1_PHY_ADDR - hex "PFE DDR base address" - default 0x2 - -config PFE_EMAC2_PHY_ADDR - hex "PFE DDR base address" - default 0x1 - -endif - -if TARGET_LS1012AFRWY - -config SYS_BOARD - default "ls1012afrdm" - -config SYS_VENDOR - default "freescale" - -config SYS_SOC - default "fsl-layerscape" - -config SYS_CONFIG_NAME - default "ls1012afrwy" - -config SYS_LS_PFE_FW_ADDR - hex "Flash address of PFE firmware" - default 0x40020000 - -config SYS_LS_PPA_FW_ADDR - hex "PPA Firmware Addr" - default 0x40060000 - -config SYS_LS_PPA_ESBC_ADDR - hex "PPA Firmware HDR Addr" - default 0x401f4000 - -config SYS_LS_PFE_ESBC_ADDR - hex "PFE Firmware HDR Addr" - default 0x401f8000 - -endif - -source "board/freescale/common/Kconfig" diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS index f3fcdb8..b618d78 100644 --- a/board/freescale/ls1012afrdm/MAINTAINERS +++ b/board/freescale/ls1012afrdm/MAINTAINERS @@ -1,17 +1,7 @@ LS1012AFRDM BOARD M: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> S: Maintained +F: board/freescale/ls1012afrx/ F: board/freescale/ls1012afrdm/ F: include/configs/ls1012afrdm.h F: configs/ls1012afrdm_qspi_defconfig - -LS1012AFRWY BOARD -M: Bhaskar Upadhaya <bhaskar.upadhaya(a)nxp.com> -S: Maintained -F: board/freescale/ls1012afrwy/ -F: include/configs/ls1012afrwy.h -F: configs/ls1012afrwy_qspi_defconfig - -M: Vinitha V Pillai <vinitha.pillai(a)nxp.com> -S: Maintained -F: configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile index 1e53c96..a318506 100644 --- a/board/freescale/ls1012afrdm/Makefile +++ b/board/freescale/ls1012afrdm/Makefile @@ -4,5 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += ls1012afrdm.o -obj-$(CONFIG_FSL_PFE) += eth.o +obj-y += ../ls1012afrx/ls1012afrx.o +obj-$(CONFIG_FSL_PFE) += ../ls1012afrx/eth.o diff --git a/board/freescale/ls1012afrx/Kconfig b/board/freescale/ls1012afrx/Kconfig new file mode 100644 index 0000000..a2884e5 --- /dev/null +++ b/board/freescale/ls1012afrx/Kconfig @@ -0,0 +1,27 @@ +if FSL_PFE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select PHYLIB + imply PHY_REALTEK + imply PHY_ATHEROS + +config DDR_PFE_PHYS_BASEADDR + hex "PFE DDR physical base address" + default 0x03800000 + +config DDR_PFE_BASEADDR + hex "PFE DDR base address" + default 0x83800000 + +config PFE_EMAC1_PHY_ADDR + hex "PFE DDR base address" + default 0x2 + +config PFE_EMAC2_PHY_ADDR + hex "PFE DDR base address" + default 0x1 + +endif + +source "board/freescale/common/Kconfig" diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrx/eth.c similarity index 100% rename from board/freescale/ls1012afrdm/eth.c rename to board/freescale/ls1012afrx/eth.c diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrx/ls1012afrx.c similarity index 100% rename from board/freescale/ls1012afrdm/ls1012afrdm.c rename to board/freescale/ls1012afrx/ls1012afrx.c -- 2.7.4

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[U-Boot] [PATCH] nios2: 10m50: Add CPU pre-relocation in device tree
by Gan, Yau Wai 20 Sep '18

20 Sep '18

Tag CPU with dm-pre-reloc to enable driver before relocation. Signed-off-by: Gan, Yau Wai <yau.wai.gan(a)intel.com> Cc: Thomas Chou <thomas(a)wytron.com.tw> --- arch/nios2/dts/10m50_devboard.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/nios2/dts/10m50_devboard.dts b/arch/nios2/dts/10m50_devboard.dts index 05eac30..461ae68 100644 --- a/arch/nios2/dts/10m50_devboard.dts +++ b/arch/nios2/dts/10m50_devboard.dts @@ -19,6 +19,7 @@ #size-cells = <0>; cpu: cpu@0 { + u-boot,dm-pre-reloc; device_type = "cpu"; compatible = "altr,nios2-1.1"; reg = <0x00000000>; -- 2.7.4

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[U-Boot] [PATCH 1/3] net: designware: socfpga: Add Arria10 extras
by Marek Vasut 19 Sep '18

19 Sep '18

Add wrapper around the designware MAC driver to handle the SoCFPGA specific configuration bits. On Arria10, this is configuration of syscon phy_intf. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <chin.liang.see(a)intel.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> Cc: Ley Foon Tan <ley.foon.tan(a)intel.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> --- NOTE: This driver is not enabled on Gen5 or Stratix10 as the implementation for its specifics is missing thus far. The driver can be safely enabled though, as the behavior of the plain designware mac driver will be retained. --- drivers/net/Kconfig | 8 +++ drivers/net/Makefile | 1 + drivers/net/dwmac_socfpga.c | 143 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 152 insertions(+) create mode 100644 drivers/net/dwmac_socfpga.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index f762b0898d..d86da7760e 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -150,6 +150,14 @@ config ETH_DESIGNWARE 100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to provide the PHY (physical media interface). +config ETH_DESIGNWARE_SOCFPGA + bool "Altera SoCFPGA extras for Synopsys Designware Ethernet MAC" + depends on DM_ETH && ETH_DESIGNWARE + help + The Altera SoCFPGA requires additional configuration of the + Altera system manager to correctly interface with the PHY. + This code handles those SoC specifics. + config ETHOC bool "OpenCores 10/100 Mbps Ethernet MAC" help diff --git a/drivers/net/Makefile b/drivers/net/Makefile index c1ed44e21f..48a2878071 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o obj-$(CONFIG_CS8900) += cs8900.o obj-$(CONFIG_TULIP) += dc2114x.o obj-$(CONFIG_ETH_DESIGNWARE) += designware.o +obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o obj-$(CONFIG_DNET) += dnet.o obj-$(CONFIG_E1000) += e1000.o diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c new file mode 100644 index 0000000000..08fc9677c4 --- /dev/null +++ b/drivers/net/dwmac_socfpga.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Marek Vasut <marex(a)denx.de> + * + * Altera SoCFPGA EMAC extras + */ + +#include <common.h> +#include <asm/io.h> +#include <dm.h> +#include <clk.h> +#include <phy.h> +#include <regmap.h> +#include <reset.h> +#include <syscon.h> +#include "designware.h" + +#include <asm/arch/system_manager.h> + +enum dwmac_type { + DWMAC_SOCFPGA_GEN5 = 0, + DWMAC_SOCFPGA_ARRIA10, + DWMAC_SOCFPGA_STRATIX10, +}; + +struct dwmac_socfpga_platdata { + struct dw_eth_pdata dw_eth_pdata; + enum dwmac_type type; + void *phy_intf; +}; + +static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev) +{ + struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev); + struct regmap *regmap; + struct ofnode_phandle_args args; + void *range; + int ret; + + ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL, + 2, 0, &args); + if (ret) { + dev_err(dev, "Failed to get syscon: %d\n", ret); + return ret; + } + + if (args.args_count != 2) { + dev_err(dev, "Invalid number of syscon args\n"); + return -EINVAL; + } + + regmap = syscon_node_to_regmap(args.node); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + dev_err(dev, "Failed to get regmap: %d\n", ret); + return ret; + } + + range = regmap_get_range(regmap, 0); + if (!range) { + dev_err(dev, "Failed to get regmap range\n"); + return -ENOMEM; + } + + pdata->phy_intf = range + args.args[0]; + + /* + * Sadly, the Altera DT bindings don't have SoC-specific compatibles, + * so we have to guesstimate which SoC we are running on from the + * DWMAC version. Luckily, Altera at least updated the DWMAC with + * each SoC. + */ + if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.70a")) + pdata->type = DWMAC_SOCFPGA_GEN5; + + if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.72a")) + pdata->type = DWMAC_SOCFPGA_ARRIA10; + + if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.74a")) + pdata->type = DWMAC_SOCFPGA_STRATIX10; + + return designware_eth_ofdata_to_platdata(dev); +} + +static int dwmac_socfpga_probe(struct udevice *dev) +{ + struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev); + struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata; + struct reset_ctl_bulk reset_bulk; + int ret; + u8 modereg; + + if (pdata->type == DWMAC_SOCFPGA_ARRIA10) { + switch (edata->phy_interface) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; + break; + case PHY_INTERFACE_MODE_RMII: + modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; + break; + case PHY_INTERFACE_MODE_RGMII: + modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + break; + default: + dev_err(dev, "Unsupported PHY mode\n"); + return -EINVAL; + } + + ret = reset_get_bulk(dev, &reset_bulk); + if (ret) { + dev_err(dev, "Failed to get reset: %d\n", ret); + return ret; + } + + reset_assert_bulk(&reset_bulk); + + clrsetbits_le32(pdata->phy_intf, + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, + modereg); + + reset_release_bulk(&reset_bulk); + } + + return designware_eth_probe(dev); +} + +static const struct udevice_id dwmac_socfpga_ids[] = { + { .compatible = "altr,socfpga-stmmac" }, + { } +}; + +U_BOOT_DRIVER(dwmac_socfpga) = { + .name = "dwmac_socfpga", + .id = UCLASS_ETH, + .of_match = dwmac_socfpga_ids, + .ofdata_to_platdata = dwmac_socfpga_ofdata_to_platdata, + .probe = dwmac_socfpga_probe, + .ops = &designware_eth_ops, + .priv_auto_alloc_size = sizeof(struct dw_eth_dev), + .platdata_auto_alloc_size = sizeof(struct dwmac_socfpga_platdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; -- 2.16.2

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[U-Boot] [PATCH] dts: mvebu: mcbin: drop redundant SD slot node
by Baruch Siach 19 Sep '18

19 Sep '18

Commit 61dccf73d302 (dts: mvebu: a80x0: Enable SD/eMMC interfaces) added a redundant DT node for SD card slot. Drop it. Cc: Konstantin Porotchkin <kostap(a)marvell.com> Signed-off-by: Baruch Siach <baruch(a)tkos.co.il> --- arch/arm/dts/armada-8040-mcbin.dts | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index 08f1d7df69aa..f912596c2cde 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -154,14 +154,6 @@ status = "okay"; }; -/* uSD slot */ -&cpm_sdhci0 { - pinctrl-names = "default"; - pinctrl-0 = <&cpm_sdhci_pins>; - bus-width = <4>; - status = "okay"; -}; - &cpm_comphy { /* * CP0 Serdes Configuration: -- 2.18.0

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[U-Boot] [PATCH v2 1/2] Revert "arm: mvebu: fix boot from UART when in fallback mode"
by Chris Packham 19 Sep '18

19 Sep '18

This reverts commit e83e2b390038c9075642cb243a6292241beb8d73. This prevents kwboot from overriding the hardware strapped boot source. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- Changes in v2: None arch/arm/mach-mvebu/include/mach/soc.h | 6 ------ arch/arm/mach-mvebu/spl.c | 9 --------- 2 files changed, 15 deletions(-) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 623ab4eb8d93..660dd148abc5 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -110,16 +110,10 @@ #define COMPHY_REFCLK_ALIGNMENT (MVEBU_REGISTER(0x182f8)) /* BootROM error register (also includes some status infos) */ -#if defined(CONFIG_ARMADA_38X) -#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0)) -#define BOOTROM_ERR_MODE_OFFS 0 -#define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS) -#else #define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0)) #define BOOTROM_ERR_MODE_OFFS 28 #define BOOTROM_ERR_MODE_MASK (0xf << BOOTROM_ERR_MODE_OFFS) #define BOOTROM_ERR_MODE_UART 0x6 -#endif #if defined(CONFIG_ARMADA_375) /* SAR values for Armada 375 */ diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 50b24f5760b7..4c3933b8354d 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -25,16 +25,7 @@ static u32 get_boot_device(void) val = readl(CONFIG_BOOTROM_ERR_REG); boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS; debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device); -#if defined(CONFIG_ARMADA_38X) - /* - * If the bootrom error register contains any else than zeros - * in the first 8 bits it's an error condition. And in that case - * try to boot from UART. - */ - if (boot_device) -#else if (boot_device == BOOTROM_ERR_MODE_UART) -#endif return BOOT_DEVICE_UART; /* -- 2.18.0

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[U-Boot] [PATCH] arm64: mvebu: armada-8k: support environment in SD/eMMC
by Baruch Siach 19 Sep '18

19 Sep '18

Detect the SD/eMMC boot device at run-time. Load the environment from the boot deice, as well as save to it. Leave the environment offset the same as in the SPI flash. Make SD/eMMC 0 the default environment device when the boot device is not detected. Cc: Konstantin Porotchkin <kostap(a)marvell.com> Signed-off-by: Baruch Siach <baruch(a)tkos.co.il> --- arch/arm/mach-mvebu/armada8k/cpu.c | 24 ++++++++++++++++++++++++ include/configs/mvebu_armada-8k.h | 3 +++ 2 files changed, 27 insertions(+) diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c index f8e8e73610d2..959a7cff7641 100644 --- a/arch/arm/mach-mvebu/armada8k/cpu.c +++ b/arch/arm/mach-mvebu/armada8k/cpu.c @@ -18,6 +18,10 @@ #define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84) #define RFU_SW_RESET_OFFSET 0 +#define SAR0_REG (MVEBU_REGISTER(0x2400200)) +#define BOOT_MODE_MASK 0x3f +#define BOOT_MODE_OFFSET 4 + /* * The following table includes all memory regions for Armada 7k and * 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets @@ -125,3 +129,23 @@ u32 mvebu_get_nand_clock(void) else return 250 * 1000000; } + +int mmc_get_env_dev(void) +{ + u32 reg; + unsigned int boot_mode; + + reg = readl(SAR0_REG); + boot_mode = (reg >> BOOT_MODE_OFFSET) & BOOT_MODE_MASK; + + switch (boot_mode) { + case 0x28: + case 0x2a: + return 0; + case 0x29: + case 0x2b: + return 1; + } + + return CONFIG_SYS_MMC_ENV_DEV; +} diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index 9205bd9632c3..b84ce670e8b3 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -66,6 +66,9 @@ #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ +/* When runtime detection fails this is the default */ +#define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_ONFI_DETECTION -- 2.18.0

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[U-Boot] [PATCH] tools: kwboot: Make kwboot more robust on a38x
by Baruch Siach 19 Sep '18

19 Sep '18

From: Jon Nettleton <jon(a)solid-run.com> This patch accomplishes 2 things to make the kwboot procedure on the a38x more reliable. 1) We fill the tty with 1K of the magic bootparam. This helps with the timing of where the microcode picks up in the read of the line to ensure we actually catch the break to go into recovery mode 2) Before starting the xmodem transfer we sleep for 2 seconds and then flush the line. This allows all the magic bootparam to be flushed from the line and makes the xmodem transfer reliable and removes the Bad message failures. Signed-off-by: Jon Nettleton <jon(a)solid-run.com> Signed-off-by: Baruch Siach <baruch(a)tkos.co.il> --- tools/kwboot.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/tools/kwboot.c b/tools/kwboot.c index 50ae2b4b77b1..4be094c9c8d8 100644 --- a/tools/kwboot.c +++ b/tools/kwboot.c @@ -286,6 +286,7 @@ kwboot_bootmsg(int tty, void *msg) { int rc; char c; + int count; if (msg == NULL) kwboot_printv("Please reboot the target into UART boot mode..."); @@ -297,10 +298,12 @@ kwboot_bootmsg(int tty, void *msg) if (rc) break; - rc = kwboot_tty_send(tty, msg, 8); - if (rc) { - usleep(msg_req_delay * 1000); - continue; + for (count = 0; count < 128; count++) { + rc = kwboot_tty_send(tty, msg, 8); + if (rc) { + usleep(msg_req_delay * 1000); + continue; + } } rc = kwboot_tty_recv(tty, &c, 1, msg_rsp_timeo); @@ -426,6 +429,9 @@ kwboot_xmodem(int tty, const void *_data, size_t size) kwboot_printv("Sending boot image...\n"); + sleep(2); /* flush isn't effective without it */ + tcflush(tty, TCIOFLUSH); + do { struct kwboot_block block; int n; -- 2.18.0

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