August 2018 - U-Boot

[U-Boot] [PATCH v2 00/30] Add support for 1wire protocol and 1wire eeproms
by Eugen Hristev 09 Aug '18

09 Aug '18

This is a patch series originally written by Maxime Ripard, https://lists.denx.de/pipermail/u-boot/2016-November/272138.html titled: [U-Boot] [PATCH RESEND 0/9] sunxi: chip: Enable the DIP auto-detection and reworked to include support for the EEPROMs on the PDAs connected to the sama xplained boards. This is the version 2 of the rework, version 1 was titled: [PATCH 00/20] Add support for 1wire protocol and 1wire eeproms It addresses feedback received in the first version. The patch series adds first a driver for onewire uclass, and onewire over gpio bitbanging driver. Then it adds a uclass for onewire EEPROMS, and specific driver for Maxim EEPROMs. I have added some sandbox support, configuration and device tree for it and for boards sama5d2_xplained, sama5d3_xplained, sama5d2_ptc_ek and sama5d27_som1_ek. Also added common code for PDA detection, as the memory on the PDAs is connected to the SoC on the onewire bus. Thanks to everyone for the review and feedback. Below is a short summary of the commits: The series adds a w1-uclass driver for the onewire interface u-class. This is done in patch: [PATCH v2 01/30] w1: Add 1-Wire uclass Also, we add a driver for the w1-uclass specific to the onewire over bitbanged gpio, this is done in patch: [PATCH v2 02/30] w1: Add 1-Wire gpio driver Add the bindings documentation in: [PATCH v2 03/30] dt-bindings: W1: w1-gpio: added bindings for w1-gpio A uclass driver is added for one wire eeproms, in patch : [PATCH v2 04/30] W1-EEPROM: Add an W1-EEPROM uclass for 1 wire EEPROMs Connection between memories and the bus is done in the patch: [PATCH v2 05/30] w1: identify devices with w1-eeprom uclas Specific driver for the DS24 Maxim EEPROMs is added in the patch: [PATCH v2 06/30] W1-EEPROM: add support for Maxim DS24 eeprom families Bindings for the DS24xxx driver added in the patch: [PATCH v2 07/30] dt-bindings: w1-eeprom: ds24xxx: create bindings A sandbox driver for a onewire EEPROM is added in patch: [PATCH v2 08/30] W1-EEPROM: add sandbox driver Bindings for the sandbox eeprom driver added in patch: [PATCH v2 09/30] dt-bindings: w1-eeprom: eep_sandbox: create bindings A command is added for the onewire protocol in patch: [PATCH v2 10/30] w1: add command for onewire protocol Pinctrl driver for sandbox was updated to add a new group and function for w1: [PATCH v2 11/30] pinctrl: sandbox: add gpio onewire w1 group Add a node in sandbox DT to have a test node for sandbox. [PATCH v2 12/30] sandbox: DTS: w1: add node for one wire interface on GPIO The defconfig for sandbox is updated to include the drivers: [PATCH v2 13/30] configs: sandbox: add onewire w1 and sandbox eeprom Configuration for sama5d2 xplained is updated in patch: [PATCH v2 14/30] configs: sama5d2_xplained: add onewire and eeprom Configuration for sama5d3 xplained is updated in patch: [PATCH v2 15/30] configs: sama5d3_xplained: add onewire and eeprom Configuration for sama5d27_som1_ek is updated in patch: [PATCH v2 16/30] configs: sama5d27_som1_ek: add onewire and eeprom drivers Configuration for sama5d2 ptc is updated in patch: [PATCH v2 17/30] configs: sama5d2_ptc_ek: add onewire and eeprom drivers Pda detection is added in the common part for atmel boards: [PATCH v2 18/30] board: atmel: add support for pda detection Specifically add it for Sama5d2 xplained board in patch: [PATCH v2 19/30] board: sama5d2_xplained: add pda detect call at init time Specifically add it for Sama5d3 xplained board in patch: [PATCH v2 20/30] board: sama5d3_xplained: add pda detect call at init time Specifically add it for Sama5d27 som1 ek board in patch: [PATCH v2 21/30] board: sama5d27_som1_ek: add pda detect call at init time Specifically add it for Sama5d27 ptc ek board in patch: [PATCH v2 22/30] board: sama5d2_ptc_ek: add pda detect call at init time Add support for overlays for sama5d2 xplained config in patch: [PATCH v2 23/30] configs: sama5d2_xplained: add fdt overlay support Add support for overlays for sama5d3 xplained config in patch: [PATCH v2 24/30] configs: sama5d3_xplained: add fdt overlay support Add support for overlays for sama5d2 ptc ek config in patch: [PATCH v2 25/30] configs: sama5d2_ptc_ek: add fdt overlay support Add support for overlays for sama5d2 som1 ek config in patch: [PATCH v2 26/30] configs: sama5d27_som1_ek: add fdt overlay support The DT for the SAMA5D2 Soc and xplained is updated to include a onewire node. This is done in patch: [PATCH v2 27/30] ARM: dts: at91: sama5d2_xplained: add onewire connector The DT for the SAMA5D3 Soc and xplained is updated to include a onewire node. This is done in patch: [PATCH v2 28/30] ARM: dts: at91: sama5d3_xplained: add onewire connector The DT for sama5d27 som1 ek is updated to include a onewire node. This is done in patch: [PATCH v2 29/30] ARM: dts: at91: sama5d27_som1_ek: add onewire connector for LCD eeprom The DT for sama5d2 ptc ek is updated to include a onewire node. This is done in patch: [PATCH v2 30/30] ARM: dts: at91: sama5d2_ptc: add onewire connector for LCD eeprom Changes in v2: - added support for two more boards: the PTC ek and the SOM1 ek. - modified the enumerate mechanism, to search through devicetree nodes, the memories are now in device tree, as suggested by Simon Glass. When a serial number is read from the bus, the driver will match it with a corresponding node in device tree. - modified the probe mechanism for the bus, when trying to get the bus use a different get function that will also probe the driver, regardless of present aliases in DT. - added bindings for ds24xxx driver and eep_sandbox, because they are referenced from devicetree now. Eugen Hristev (26): dt-bindings: W1: w1-gpio: added bindings for w1-gpio w1: identify devices with w1-eeprom uclass dt-bindings: w1-eeprom: ds24xxx: create bindings W1-EEPROM: add sandbox driver dt-bindings: w1-eeprom: eep_sandbox: create bindings w1: add command for onewire protocol pinctrl: sandbox: add gpio onewire w1 group sandbox: DTS: w1: add node for one wire interface on GPIO configs: sandbox: add onewire w1 and sandbox eeprom configs: sama5d2_xplained: add onewire and eeprom drivers configs: sama5d3_xplained: add onewire and eeprom drivers configs: sama5d27_som1_ek: add onewire and eeprom drivers configs: sama5d2_ptc_ek: add onewire and eeprom drivers board: atmel: add support for pda detection board: sama5d2_xplained: add pda detect call at init time board: sama5d3_xplained: add pda detect call at init time board: sama5d27_som1_ek: add pda detect call at init time board: sama5d2_ptc_ek: add pda detect call at init time configs: sama5d2_xplained: add fdt overlay support configs: sama5d3_xplained: add fdt overlay support configs: sama5d2_ptc_ek: add fdt overlay support configs: sama5d27_som1_ek: add fdt overlay support ARM: dts: at91: sama5d2_xplained: add onewire connector for LCD eeprom ARM: dts: at91: sama5d3_xplained: add onewire connector for LCD eeprom ARM: dts: at91: sama5d27_som1_ek: add onewire connector for LCD eeprom ARM: dts: at91: sama5d2_ptc: add onewire connector for LCD eeprom Maxime Ripard (4): w1: Add 1-Wire uclass w1: Add 1-Wire gpio driver W1-EEPROM: Add an W1-EEPROM uclass for 1 wire EEPROMs W1-EEPROM: add support for Maxim DS24 eeprom families arch/arm/dts/at91-sama5d27_som1_ek.dts | 17 ++ arch/arm/dts/at91-sama5d2_ptc_ek.dts | 17 ++ arch/arm/dts/at91-sama5d2_xplained.dts | 17 ++ arch/arm/dts/at91-sama5d3_xplained.dts | 17 ++ arch/arm/dts/sama5d2.dtsi | 5 + arch/arm/dts/sama5d3.dtsi | 5 + arch/arm/mach-at91/Kconfig | 2 + arch/sandbox/dts/sandbox.dts | 20 ++ board/atmel/common/board.c | 55 +++++ board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c | 3 + board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c | 10 + board/atmel/sama5d2_xplained/sama5d2_xplained.c | 3 + board/atmel/sama5d3_xplained/sama5d3_xplained.c | 10 + cmd/Kconfig | 7 + cmd/Makefile | 1 + cmd/w1.c | 121 +++++++++++ configs/sama5d27_som1_ek_mmc_defconfig | 5 + configs/sama5d2_ptc_ek_mmc_defconfig | 5 + configs/sama5d2_ptc_ek_nandflash_defconfig | 5 + configs/sama5d2_xplained_mmc_defconfig | 5 + configs/sama5d2_xplained_spiflash_defconfig | 5 + configs/sama5d3_xplained_mmc_defconfig | 5 + configs/sama5d3_xplained_nandflash_defconfig | 5 + configs/sandbox_defconfig | 4 + doc/device-tree-bindings/w1-eeprom/ds24xxx.txt | 37 ++++ doc/device-tree-bindings/w1-eeprom/eep_sandbox.txt | 34 +++ doc/device-tree-bindings/w1/w1-gpio.txt | 40 ++++ drivers/Kconfig | 4 + drivers/Makefile | 2 + drivers/pinctrl/pinctrl-sandbox.c | 3 + drivers/w1-eeprom/Kconfig | 29 +++ drivers/w1-eeprom/Makefile | 5 + drivers/w1-eeprom/ds24xxx.c | 55 +++++ drivers/w1-eeprom/eep_sandbox.c | 61 ++++++ drivers/w1-eeprom/w1-eeprom-uclass.c | 109 ++++++++++ drivers/w1/Kconfig | 25 +++ drivers/w1/Makefile | 3 + drivers/w1/w1-gpio.c | 158 ++++++++++++++ drivers/w1/w1-uclass.c | 239 +++++++++++++++++++++ include/dm/uclass-id.h | 2 + include/w1-eeprom.h | 33 +++ include/w1.h | 37 ++++ 42 files changed, 1225 insertions(+) create mode 100644 cmd/w1.c create mode 040000 doc/device-tree-bindings/w1-eeprom create mode 100644 doc/device-tree-bindings/w1-eeprom/ds24xxx.txt create mode 100644 doc/device-tree-bindings/w1-eeprom/eep_sandbox.txt create mode 040000 doc/device-tree-bindings/w1 create mode 100644 doc/device-tree-bindings/w1/w1-gpio.txt create mode 040000 drivers/w1-eeprom create mode 100644 drivers/w1-eeprom/Kconfig create mode 100644 drivers/w1-eeprom/Makefile create mode 100644 drivers/w1-eeprom/ds24xxx.c create mode 100644 drivers/w1-eeprom/eep_sandbox.c create mode 100644 drivers/w1-eeprom/w1-eeprom-uclass.c create mode 040000 drivers/w1 create mode 100644 drivers/w1/Kconfig create mode 100644 drivers/w1/Makefile create mode 100644 drivers/w1/w1-gpio.c create mode 100644 drivers/w1/w1-uclass.c create mode 100644 include/w1-eeprom.h create mode 100644 include/w1.h -- 2.7.4

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[U-Boot] [PATCH v3] usb: ehci-generic: Add vbus-supply regulator support
by Patrice Chotard 09 Aug '18

09 Aug '18

Add vbus-supply regulator support. On some board vbus is not controlled by the phy but by an external regulator. Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> --- Changes in v3: - Update test on device_get_supply_regulator() call - Replace pr_err() by dev_err() - Replace debug() by dev_dbg() Changes in v2: - Add test on device_get_supply_regulator() call drivers/usb/host/ehci-generic.c | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c index 5a56f66cfaa6..dc7d23e95f5e 100644 --- a/drivers/usb/host/ehci-generic.c +++ b/drivers/usb/host/ehci-generic.c @@ -11,6 +11,7 @@ #include <asm/io.h> #include <dm.h> #include "ehci.h" +#include <power/regulator.h> /* * Even though here we don't explicitly use "struct ehci_ctrl" @@ -22,6 +23,9 @@ struct generic_ehci { struct clk *clocks; struct reset_ctl *resets; struct phy phy; +#ifdef CONFIG_DM_REGULATOR + struct udevice *vbus_supply; +#endif int clock_count; int reset_count; }; @@ -145,9 +149,26 @@ static int ehci_usb_probe(struct udevice *dev) } } +#ifdef CONFIG_DM_REGULATOR + err = device_get_supply_regulator(dev, "vbus-supply", + &priv->vbus_supply); + if (err && err != -ENOENT) + goto reset_err; + + if (priv->vbus_supply) { + err = regulator_set_enable(priv->vbus_supply, true); + if (err) { + dev_err(dev, "Error enabling VBUS supply\n"); + goto reset_err; + } + } else { + dev_dbg(dev, "%s: No vbus supply\n", dev->name); + } +#endif + err = ehci_setup_phy(dev, 0); if (err) - goto reset_err; + goto regulator_err; hccr = map_physmem(dev_read_addr(dev), 0x100, MAP_NOCACHE); hcor = (struct ehci_hcor *)((uintptr_t)hccr + @@ -164,6 +185,15 @@ phy_err: if (ret) dev_err(dev, "failed to shutdown usb phy\n"); +regulator_err: +#ifdef CONFIG_DM_REGULATOR + if (priv->vbus_supply) { + ret = regulator_set_enable(priv->vbus_supply, false); + if (ret) + dev_err(dev, "Error disabling VBUS supply\n"); + } +#endif + reset_err: ret = reset_release_all(priv->resets, priv->reset_count); if (ret) @@ -189,6 +219,13 @@ static int ehci_usb_remove(struct udevice *dev) if (ret) return ret; +#ifdef CONFIG_DM_REGULATOR + if (priv->vbus_supply) { + ret = regulator_set_enable(priv->vbus_supply, false); + if (ret) + return ret; + } +#endif ret = reset_release_all(priv->resets, priv->reset_count); if (ret) return ret; -- 1.9.1

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[U-Boot] [PATCH v2] usb: ehci-generic: Add vbus-supply regulator support
by Patrice Chotard 09 Aug '18

09 Aug '18

Add vbus-supply regulator support. On some board vbus is not controlled by the phy but by an external regulator. Signed-off-by: Patrice Chotard <patrice.chotard(a)st.com> --- Changes in v2: - Add test on device_get_supply_regulator() call drivers/usb/host/ehci-generic.c | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c index 5a56f66cfaa6..ad926d05ac3e 100644 --- a/drivers/usb/host/ehci-generic.c +++ b/drivers/usb/host/ehci-generic.c @@ -11,6 +11,7 @@ #include <asm/io.h> #include <dm.h> #include "ehci.h" +#include <power/regulator.h> /* * Even though here we don't explicitly use "struct ehci_ctrl" @@ -22,6 +23,9 @@ struct generic_ehci { struct clk *clocks; struct reset_ctl *resets; struct phy phy; +#ifdef CONFIG_DM_REGULATOR + struct udevice *vbus_supply; +#endif int clock_count; int reset_count; }; @@ -145,10 +149,27 @@ static int ehci_usb_probe(struct udevice *dev) } } - err = ehci_setup_phy(dev, 0); +#ifdef CONFIG_DM_REGULATOR + err = device_get_supply_regulator(dev, "vbus-supply", + &priv->vbus_supply); if (err) goto reset_err; + if (priv->vbus_supply) { + err = regulator_set_enable(priv->vbus_supply, true); + if (err) { + pr_err("Error enabling VBUS supply\n"); + goto reset_err; + } + } else { + debug("%s: No vbus supply\n", dev->name); + } +#endif + + err = ehci_setup_phy(dev, 0); + if (err) + goto regulator_err; + hccr = map_physmem(dev_read_addr(dev), 0x100, MAP_NOCACHE); hcor = (struct ehci_hcor *)((uintptr_t)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); @@ -164,6 +185,15 @@ phy_err: if (ret) dev_err(dev, "failed to shutdown usb phy\n"); +regulator_err: +#ifdef CONFIG_DM_REGULATOR + if (priv->vbus_supply) { + ret = regulator_set_enable(priv->vbus_supply, false); + if (ret) + pr_err("Error disabling VBUS supply\n"); + } +#endif + reset_err: ret = reset_release_all(priv->resets, priv->reset_count); if (ret) @@ -189,6 +219,13 @@ static int ehci_usb_remove(struct udevice *dev) if (ret) return ret; +#ifdef CONFIG_DM_REGULATOR + if (priv->vbus_supply) { + ret = regulator_set_enable(priv->vbus_supply, false); + if (ret) + return ret; + } +#endif ret = reset_release_all(priv->resets, priv->reset_count); if (ret) return ret; -- 1.9.1

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[U-Boot] [PATCH v2 00/17] cmd: fpga: Fix fpga command handling and add some fpga tests
by Michal Simek 09 Aug '18

09 Aug '18

Hi, We are using this framework for a while and by adding more and more features it requires small redesigned how commands are handled. This is something what I have put together to improve readability of this code and also remove code which is bogus and completely untested. The patch https://lists.denx.de/pipermail/u-boot/2018-June/330651.html is also included in this series to have full picture. Thanks, Michal Changes in v2: - Extend non complete commit message Changes in v1: - Remove debug message checking (unfortunatelly we can't parse them) - Add dependency on image_format_legacy and gzip - Setup all FIT tests and legacy uimage tests - New patch from RFC Michal Simek (17): cmd: fpga: Remove fit image support passed without fpga device test/py: Extend fpga command to test all fpga load types cmd: fpga: Move error handling to do_fpga() cmd: fpga: Move fpga_get_op to avoid local function declaration cmd: fpga: Cleanup error handling in connection to FPGA_NONE cmd: fpga: Move parameter checking for loadfs/loads cmd: fpga: Remove parameter checking from fpga loadfs command cmd: fpga: Clean wrong_parms handling cmd: fpga: Create new do_fpga_wrapper for using u-boot subcommands cmd: fpga: Extract fpga info command to separate function cmd: fpga: Fix dump and all direct fpga load commands cmd: fpga: Fix loadfs command cmd: fpga: Fix loadmk command cmd: fpga: Add support for missing fpga loadmk commands cmd: fpga: Use CMD_RET_FAILURE instead of simple 1 cmd: fpga: Fix loads command MAINTAINERS: Add myself as the FPGA maintainer MAINTAINERS | 8 + cmd/fpga.c | 652 +++++++++++++++++++++++---------------------- test/py/tests/test_fpga.py | 552 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 896 insertions(+), 316 deletions(-) create mode 100644 test/py/tests/test_fpga.py -- 1.9.1

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[U-Boot] [PATCH V2 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM
by Marek Vasut 09 Aug '18

09 Aug '18

Bind fixed clock driver to the base clock instantiated in the handoff DT and use DM clock framework to get their clock rate. This replaces the ad-hoc DT parsing present thus far. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <chin.liang.see(a)intel.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> Cc: Ley Foon Tan <ley.foon.tan(a)intel.com> --- V2: Drop device_probe() which is unneeded because it's performed by uclass_get_device_by_name() already --- arch/arm/mach-socfpga/Kconfig | 2 ++ arch/arm/mach-socfpga/clock_manager_arria10.c | 37 ++++++++++++++++++--------- 2 files changed, 27 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 5c1df2cf1f..2655289a72 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -11,6 +11,8 @@ config TARGET_SOCFPGA_ARRIA10 bool select ALTERA_SDRAM select SPL_BOARD_INIT if SPL + select CLK + select SPL_CLK if SPL config TARGET_SOCFPGA_CYCLONE5 bool diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c index defa2f6261..cadb090387 100644 --- a/arch/arm/mach-socfpga/clock_manager_arria10.c +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -7,6 +7,8 @@ #include <fdtdec.h> #include <asm/io.h> #include <dm.h> +#include <clk.h> +#include <dm/device-internal.h> #include <asm/arch/clock_manager.h> static const struct socfpga_clock_manager *clock_manager_base = @@ -141,9 +143,9 @@ struct strtopu32 { }; const struct strtopu32 dt_to_val[] = { - { "/clocks/altera_arria10_hps_eosc1", &eosc1_hz}, - { "/clocks/altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz}, - { "/clocks/altera_arria10_hps_f2h_free", &f2s_free_hz}, + { "altera_arria10_hps_eosc1", &eosc1_hz }, + { "altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz }, + { "altera_arria10_hps_f2h_free", &f2s_free_hz }, }; static int of_to_struct(const void *blob, int node, const struct strtou32 *cfg_tab, @@ -163,28 +165,39 @@ static int of_to_struct(const void *blob, int node, const struct strtou32 *cfg_t return 0; } -static void of_get_input_clks(const void *blob) +static int of_get_input_clks(const void *blob) { - int node, i; + struct udevice *dev; + struct clk clk; + int i, ret; for (i = 0; i < ARRAY_SIZE(dt_to_val); i++) { - node = fdt_path_offset(blob, dt_to_val[i].str); + memset(&clk, 0, sizeof(clk)); - if (node < 0) - continue; + ret = uclass_get_device_by_name(UCLASS_CLK, dt_to_val[i].str, + &dev); + if (ret) + return ret; - fdtdec_get_int_array(blob, node, "clock-frequency", - dt_to_val[i].p, 1); + ret = clk_request(dev, &clk); + if (ret) + return ret; + + *dt_to_val[i].p = clk_get_rate(&clk); } + + return 0; } static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) { - int node, child, len; + int ret, node, child, len; const char *node_name; - of_get_input_clks(blob); + ret = of_get_input_clks(blob); + if (ret) + return ret; node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK_INIT); -- 2.16.2

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[U-Boot] [PATCH 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM
by Marek Vasut 09 Aug '18

09 Aug '18

Bind fixed clock driver to the base clock instantiated in the handoff DT and use DM clock framework to get their clock rate. This replaces the ad-hoc DT parsing present thus far. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <chin.liang.see(a)intel.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> Cc: Ley Foon Tan <ley.foon.tan(a)intel.com> --- arch/arm/mach-socfpga/Kconfig | 2 ++ arch/arm/mach-socfpga/clock_manager_arria10.c | 41 +++++++++++++++++++-------- 2 files changed, 31 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 5c1df2cf1f..2655289a72 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -11,6 +11,8 @@ config TARGET_SOCFPGA_ARRIA10 bool select ALTERA_SDRAM select SPL_BOARD_INIT if SPL + select CLK + select SPL_CLK if SPL config TARGET_SOCFPGA_CYCLONE5 bool diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c index defa2f6261..59d3f9d50a 100644 --- a/arch/arm/mach-socfpga/clock_manager_arria10.c +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -7,6 +7,8 @@ #include <fdtdec.h> #include <asm/io.h> #include <dm.h> +#include <clk.h> +#include <dm/device-internal.h> #include <asm/arch/clock_manager.h> static const struct socfpga_clock_manager *clock_manager_base = @@ -141,9 +143,9 @@ struct strtopu32 { }; const struct strtopu32 dt_to_val[] = { - { "/clocks/altera_arria10_hps_eosc1", &eosc1_hz}, - { "/clocks/altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz}, - { "/clocks/altera_arria10_hps_f2h_free", &f2s_free_hz}, + { "altera_arria10_hps_eosc1", &eosc1_hz }, + { "altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz }, + { "altera_arria10_hps_f2h_free", &f2s_free_hz }, }; static int of_to_struct(const void *blob, int node, const struct strtou32 *cfg_tab, @@ -163,28 +165,43 @@ static int of_to_struct(const void *blob, int node, const struct strtou32 *cfg_t return 0; } -static void of_get_input_clks(const void *blob) +static int of_get_input_clks(const void *blob) { - int node, i; + struct udevice *dev; + struct clk clk; + int i, ret; for (i = 0; i < ARRAY_SIZE(dt_to_val); i++) { - node = fdt_path_offset(blob, dt_to_val[i].str); + memset(&clk, 0, sizeof(clk)); - if (node < 0) - continue; + ret = uclass_get_device_by_name(UCLASS_CLK, dt_to_val[i].str, + &dev); + if (ret) + return ret; - fdtdec_get_int_array(blob, node, "clock-frequency", - dt_to_val[i].p, 1); + ret = device_probe(dev); + if (ret) + return ret; + + ret = clk_request(dev, &clk); + if (ret) + return ret; + + *dt_to_val[i].p = clk_get_rate(&clk); } + + return 0; } static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) { - int node, child, len; + int ret, node, child, len; const char *node_name; - of_get_input_clks(blob); + ret = of_get_input_clks(blob); + if (ret) + return ret; node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK_INIT); -- 2.16.2

2 8

[U-Boot] [PATCH] ARM: dts: socfpga: Add u-boot, dm-pre-reloc to necessary clock nodes
by Marek Vasut 09 Aug '18

09 Aug '18

Add the pre-reloc DT markers to clock nodes needed in SPL and early U-Boot stages. This is required to let the Arria10 clock driver start early and provide clock information for UART and SDMMC. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <chin.liang.see(a)intel.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> Cc: Ley Foon Tan <ley.foon.tan(a)intel.com> --- arch/arm/dts/socfpga_arria10.dtsi | 9 +++++++++ arch/arm/dts/socfpga_arria10_socdk.dtsi | 25 +++++++++++++++++++++++++ arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 +++++++++++++++++ 3 files changed, 51 insertions(+) diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi index 2f935a21e9..a428922f8e 100644 --- a/arch/arm/dts/socfpga_arria10.dtsi +++ b/arch/arm/dts/socfpga_arria10.dtsi @@ -55,6 +55,7 @@ device_type = "soc"; interrupt-parent = <&intc>; ranges; + u-boot,dm-pre-reloc; amba { compatible = "simple-bus"; @@ -93,29 +94,35 @@ clkmgr@ffd04000 { compatible = "altr,clk-mgr"; reg = <0xffd04000 0x1000>; + u-boot,dm-pre-reloc; clocks { #address-cells = <1>; #size-cells = <0>; + u-boot,dm-pre-reloc; cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { #clock-cells = <0>; compatible = "fixed-clock"; + u-boot,dm-pre-reloc; }; cb_intosc_ls_clk: cb_intosc_ls_clk { #clock-cells = <0>; compatible = "fixed-clock"; + u-boot,dm-pre-reloc; }; f2s_free_clk: f2s_free_clk { #clock-cells = <0>; compatible = "fixed-clock"; + u-boot,dm-pre-reloc; }; osc1: osc1 { #clock-cells = <0>; compatible = "fixed-clock"; + u-boot,dm-pre-reloc; }; main_pll: main_pll@40 { @@ -126,6 +133,7 @@ clocks = <&osc1>, <&cb_intosc_ls_clk>, <&f2s_free_clk>; reg = <0x40>; + u-boot,dm-pre-reloc; main_mpu_base_clk: main_mpu_base_clk { #clock-cells = <0>; @@ -214,6 +222,7 @@ clocks = <&osc1>, <&cb_intosc_ls_clk>, <&f2s_free_clk>, <&main_periph_ref_clk>; reg = <0xC0>; + u-boot,dm-pre-reloc; peri_mpu_base_clk: peri_mpu_base_clk { #clock-cells = <0>; diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi index 3f59f02577..ae54de6990 100644 --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi @@ -166,3 +166,28 @@ &watchdog1 { status = "okay"; }; + +/* Clock available early */ +&main_noc_base_clk { + u-boot,dm-pre-reloc; +}; + +&main_periph_ref_clk { + u-boot,dm-pre-reloc; +}; + +&peri_noc_base_clk { + u-boot,dm-pre-reloc; +}; + +&noc_free_clk { + u-boot,dm-pre-reloc; +}; + +&l4_mp_clk { + u-boot,dm-pre-reloc; +}; + +&l4_sp_clk { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts index 9c6070ded9..998d811210 100644 --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts @@ -38,3 +38,20 @@ <48 IRQ_TYPE_LEVEL_HIGH>; }; }; + +/* Clock available early */ +&main_sdmmc_clk { + u-boot,dm-pre-reloc; +}; + +&peri_sdmmc_clk { + u-boot,dm-pre-reloc; +}; + +&sdmmc_free_clk { + u-boot,dm-pre-reloc; +}; + +&sdmmc_clk { + u-boot,dm-pre-reloc; +}; -- 2.16.2

2 3

[U-Boot] [PATCH] clk: socfpga: Add initial Arria10 clock driver
by Marek Vasut 09 Aug '18

09 Aug '18

Add clock driver for the Arria10, which allows reading the clock frequency from all the clock described in the DT. The driver also allows enabling and disabling the clock. Reconfiguring frequency is not supported thus far. Since the DT bindings for the SoCFPGA clock are massively misdesigned and the handoff DT adds additional incorrectly described entries to the DT, the driver contains workarounds which attempt to rectify all of those problems. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <chin.liang.see(a)intel.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> Cc: Ley Foon Tan <ley.foon.tan(a)intel.com> --- drivers/clk/Makefile | 1 + drivers/clk/altera/Makefile | 7 + drivers/clk/altera/clk-arria10.c | 363 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 371 insertions(+) create mode 100644 drivers/clk/altera/Makefile create mode 100644 drivers/clk/altera/clk-arria10.c diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 146283c723..034bf44078 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -11,6 +11,7 @@ obj-y += tegra/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_MESON) += clk_meson.o obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ +obj-$(CONFIG_ARCH_SOCFPGA) += altera/ obj-$(CONFIG_CLK_AT91) += at91/ obj-$(CONFIG_CLK_MVEBU) += mvebu/ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile new file mode 100644 index 0000000000..2542b7f51b --- /dev/null +++ b/drivers/clk/altera/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2018 Marek Vasut <marex(a)denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o diff --git a/drivers/clk/altera/clk-arria10.c b/drivers/clk/altera/clk-arria10.c new file mode 100644 index 0000000000..78102c760d --- /dev/null +++ b/drivers/clk/altera/clk-arria10.c @@ -0,0 +1,363 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marek Vasut <marex(a)denx.de> + */ + +#include <common.h> +#include <asm/io.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/lists.h> +#include <dm/util.h> + +#include <asm/arch/clock_manager.h> + +enum socfpga_a10_clk_type { + SOCFPGA_A10_CLK_MAIN_PLL, + SOCFPGA_A10_CLK_PER_PLL, + SOCFPGA_A10_CLK_PERIP_CLK, + SOCFPGA_A10_CLK_GATE_CLK, + SOCFPGA_A10_CLK_UNKNOWN_CLK, +}; + +struct socfpga_a10_clk_platdata { + enum socfpga_a10_clk_type type; + struct clk_bulk clks; + u32 regs; + /* Fixed divider */ + u16 fix_div; + /* Control register */ + u16 ctl_reg; + /* Divider register */ + u16 div_reg; + u8 div_len; + u8 div_off; + /* Clock gating register */ + u16 gate_reg; + u8 gate_bit; +}; + +static int socfpga_a10_clk_get_upstream(struct clk *clk, struct clk **upclk) +{ + struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev); + u32 reg, maxval; + + if (plat->clks.count == 0) + return 0; + + if (plat->clks.count == 1) { + *upclk = &plat->clks.clks[0]; + return 0; + } + + if (!plat->ctl_reg) { + dev_err(clk->dev, "Invalid control register\n"); + return -EINVAL; + } + + reg = readl(plat->regs + plat->ctl_reg); + + /* Assume PLLs are ON for now */ + if (plat->type == SOCFPGA_A10_CLK_MAIN_PLL) { + reg = (reg >> 8) & 0x3; + maxval = 2; + } else if (plat->type == SOCFPGA_A10_CLK_PER_PLL) { + reg = (reg >> 8) & 0x3; + maxval = 3; + } else { + reg = (reg >> 16) & 0x7; + maxval = 4; + } + + if (reg > maxval) { + dev_err(clk->dev, "Invalid clock source\n"); + return -EINVAL; + } + + *upclk = &plat->clks.clks[reg]; + return 0; +} + +static int socfpga_a10_clk_endisable(struct clk *clk, bool enable) +{ + struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev); + struct clk *upclk = NULL; + int ret; + + if (!enable && plat->gate_reg) + clrbits_le32(plat->regs + plat->gate_reg, BIT(plat->gate_bit)); + + ret = socfpga_a10_clk_get_upstream(clk, &upclk); + if (ret) + return ret; + + if (upclk) { + if (enable) + clk_enable(upclk); + else + clk_disable(upclk); + } + + if (enable && plat->gate_reg) + setbits_le32(plat->regs + plat->gate_reg, BIT(plat->gate_bit)); + + return 0; +} + +static int socfpga_a10_clk_enable(struct clk *clk) +{ + return socfpga_a10_clk_endisable(clk, true); +} + +static int socfpga_a10_clk_disable(struct clk *clk) +{ + return socfpga_a10_clk_endisable(clk, false); +} + +static ulong socfpga_a10_clk_get_rate(struct clk *clk) +{ + struct socfpga_a10_clk_platdata *plat = dev_get_platdata(clk->dev); + struct clk *upclk = NULL; + ulong rate = 0, reg, numer, denom; + int ret; + + ret = socfpga_a10_clk_get_upstream(clk, &upclk); + if (ret || !upclk) + return 0; + + rate = clk_get_rate(upclk); + + if (plat->type == SOCFPGA_A10_CLK_MAIN_PLL) { + reg = readl(plat->regs + plat->ctl_reg + 4); /* VCO1 */ + numer = reg & CLKMGR_MAINPLL_VCO1_NUMER_MSK; + denom = (reg >> CLKMGR_MAINPLL_VCO1_DENOM_LSB) & + CLKMGR_MAINPLL_VCO1_DENOM_MSK; + + rate /= denom + 1; + rate *= numer + 1; + } else if (plat->type == SOCFPGA_A10_CLK_PER_PLL) { + reg = readl(plat->regs + plat->ctl_reg + 4); /* VCO1 */ + numer = reg & CLKMGR_PERPLL_VCO1_NUMER_MSK; + denom = (reg >> CLKMGR_PERPLL_VCO1_DENOM_LSB) & + CLKMGR_PERPLL_VCO1_DENOM_MSK; + + rate /= denom + 1; + rate *= numer + 1; + } else { + rate /= plat->fix_div; + + if (plat->fix_div == 1 && plat->ctl_reg) { + reg = readl(plat->regs + plat->ctl_reg); + reg &= 0x7ff; + rate /= reg + 1; + } + + if (plat->div_reg) { + reg = readl(plat->regs + plat->div_reg); + reg >>= plat->div_off; + reg &= (1 << plat->div_len) - 1; + if (plat->type == SOCFPGA_A10_CLK_PERIP_CLK) + rate /= reg + 1; + if (plat->type == SOCFPGA_A10_CLK_GATE_CLK) + rate /= 1 << reg; + } + } + + return rate; +} + +static struct clk_ops socfpga_a10_clk_ops = { + .enable = socfpga_a10_clk_enable, + .disable = socfpga_a10_clk_disable, + .get_rate = socfpga_a10_clk_get_rate, +}; + +/* + * This workaround tries to fix the massively broken generated "handoff" DT, + * which contains duplicate clock nodes without any connection to the clock + * manager DT node. Yet, those "handoff" DT nodes contain configuration of + * the fixed input clock of the Arria10 which are missing from the base DT + * for Arria10. + * + * This workaround sets up upstream clock for the fixed input clocks of the + * A10 described in the base DT such that they map to the fixed clock from + * the "handoff" DT. This does not fully match how the clock look on the + * A10, but it is the least intrusive way to fix this mess. + */ +static void socfpga_a10_handoff_workaround(struct udevice *dev) +{ + struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev); + const void *fdt = gd->fdt_blob; + struct clk_bulk *bulk = &plat->clks; + int i, ret, offset = dev_of_offset(dev); + static const char * const socfpga_a10_fixedclk_map[] = { + "osc1", "altera_arria10_hps_eosc1", + "cb_intosc_ls_clk", "altera_arria10_hps_cb_intosc_ls", + "f2s_free_clk", "altera_arria10_hps_f2h_free", + }; + + if (fdt_node_check_compatible(fdt, offset, "fixed-clock")) + return; + + for (i = 0; i < ARRAY_SIZE(socfpga_a10_fixedclk_map); i += 2) + if (!strcmp(dev->name, socfpga_a10_fixedclk_map[i])) + break; + + if (i == ARRAY_SIZE(socfpga_a10_fixedclk_map)) + return; + + ret = uclass_get_device_by_name(UCLASS_CLK, + socfpga_a10_fixedclk_map[i + 1], &dev); + if (ret) + return; + + bulk->count = 1; + bulk->clks = devm_kcalloc(dev, bulk->count, + sizeof(struct clk), GFP_KERNEL); + if (!bulk->clks) + return; + + ret = clk_request(dev, &bulk->clks[0]); + if (ret) + free(bulk->clks); +} + +static int socfpga_a10_clk_bind(struct udevice *dev) +{ + const void *fdt = gd->fdt_blob; + int offset = dev_of_offset(dev); + bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC); + const char *name; + int ret; + + for (offset = fdt_first_subnode(fdt, offset); + offset > 0; + offset = fdt_next_subnode(fdt, offset)) { + name = fdt_get_name(fdt, offset, NULL); + if (!name) + return -EINVAL; + + if (!strcmp(name, "clocks")) { + offset = fdt_first_subnode(fdt, offset); + name = fdt_get_name(fdt, offset, NULL); + if (!name) + return -EINVAL; + } + + /* Filter out supported sub-clock */ + if (fdt_node_check_compatible(fdt, offset, + "altr,socfpga-a10-pll-clock") && + fdt_node_check_compatible(fdt, offset, + "altr,socfpga-a10-perip-clk") && + fdt_node_check_compatible(fdt, offset, + "altr,socfpga-a10-gate-clk") && + fdt_node_check_compatible(fdt, offset, "fixed-clock")) + continue; + + if (pre_reloc_only && !dm_fdt_pre_reloc(fdt, offset)) + continue; + + ret = device_bind_driver_to_node(dev, "clk-a10", name, + offset_to_ofnode(offset), + NULL); + if (ret) + return ret; + } + + return 0; +} + +static int socfpga_a10_clk_probe(struct udevice *dev) +{ + struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev); + const void *fdt = gd->fdt_blob; + int offset = dev_of_offset(dev); + + clk_get_bulk(dev, &plat->clks); + + socfpga_a10_handoff_workaround(dev); + + if (!fdt_node_check_compatible(fdt, offset, + "altr,socfpga-a10-pll-clock")) { + /* Main PLL has 3 upstream clock */ + if (plat->clks.count == 3) + plat->type = SOCFPGA_A10_CLK_MAIN_PLL; + else + plat->type = SOCFPGA_A10_CLK_PER_PLL; + } else if (!fdt_node_check_compatible(fdt, offset, + "altr,socfpga-a10-perip-clk")) { + plat->type = SOCFPGA_A10_CLK_PERIP_CLK; + } else if (!fdt_node_check_compatible(fdt, offset, + "altr,socfpga-a10-gate-clk")) { + plat->type = SOCFPGA_A10_CLK_GATE_CLK; + } else { + plat->type = SOCFPGA_A10_CLK_UNKNOWN_CLK; + } + + return 0; +} + +static int socfpga_a10_ofdata_to_platdata(struct udevice *dev) +{ + struct socfpga_a10_clk_platdata *plat = dev_get_platdata(dev); + struct socfpga_a10_clk_platdata *pplat; + struct udevice *pdev; + const void *fdt = gd->fdt_blob; + unsigned int divreg[3], gatereg[2]; + int ret, offset = dev_of_offset(dev); + u32 regs; + + regs = dev_read_u32_default(dev, "reg", 0x0); + + if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) { + plat->regs = devfdt_get_addr(dev); + } else { + pdev = dev_get_parent(dev); + if (!pdev) + return -ENODEV; + + pplat = dev_get_platdata(pdev); + if (!pplat) + return -EINVAL; + + plat->ctl_reg = regs; + plat->regs = pplat->regs; + } + + plat->type = SOCFPGA_A10_CLK_UNKNOWN_CLK; + + plat->fix_div = dev_read_u32_default(dev, "fixed-divider", 1); + + ret = dev_read_u32_array(dev, "div-reg", divreg, ARRAY_SIZE(divreg)); + if (!ret) { + plat->div_reg = divreg[0]; + plat->div_len = divreg[2]; + plat->div_off = divreg[1]; + } + + ret = dev_read_u32_array(dev, "clk-gate", gatereg, ARRAY_SIZE(gatereg)); + if (!ret) { + plat->gate_reg = gatereg[0]; + plat->gate_bit = gatereg[1]; + } + + return 0; +} + +static const struct udevice_id socfpga_a10_clk_match[] = { + { .compatible = "altr,clk-mgr" }, + {} +}; + +U_BOOT_DRIVER(socfpga_a10_clk) = { + .name = "clk-a10", + .id = UCLASS_CLK, + .flags = DM_FLAG_PRE_RELOC, + .of_match = socfpga_a10_clk_match, + .ops = &socfpga_a10_clk_ops, + .bind = socfpga_a10_clk_bind, + .probe = socfpga_a10_clk_probe, + .ofdata_to_platdata = socfpga_a10_ofdata_to_platdata, + + .platdata_auto_alloc_size = sizeof(struct socfpga_a10_clk_platdata), +}; -- 2.16.2

2 1

[U-Boot] [PATCH 0/1] distro_bootcmd: Switch bootefi to use loadaddr by default.
by Kristian Amlie 09 Aug '18

09 Aug '18

This patch fixes the issue that CONFIG_LOADADDR is not respected when booting via distro_bootcmd and bootefi, and follows from the thread "Thoughts on EFI, CONFIG_LOADADDR and kernel_addr_r". Since there was no reply, I opted for altering the behavior and providing a fallback. Kristian Amlie (1): distro_bootcmd: Switch bootefi to use loadaddr by default. include/config_distro_bootcmd.h | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) -- 2.7.4

2 6

[U-Boot] [PATCH] mmc: socfpga: Add clock framework support
by Marek Vasut 09 Aug '18

09 Aug '18

Add support for fetching the clock frequency both using the legacy method in case clock framework is disabled as well as via the clock framework if it is enabled. This allows for migration to the clock framework on platforms which supports it while not breaking legacy platforms. That said, the legacy method must be removed eventually. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <chin.liang.see(a)intel.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> Cc: Ley Foon Tan <ley.foon.tan(a)intel.com> --- drivers/mmc/socfpga_dw_mmc.c | 40 +++++++++++++++++++++++++++++++--------- 1 file changed, 31 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index ed8ba10c93..739c1629a2 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -6,6 +6,7 @@ #include <common.h> #include <asm/arch/clock_manager.h> #include <asm/arch/system_manager.h> +#include <clk.h> #include <dm.h> #include <dwmmc.h> #include <errno.h> @@ -70,20 +71,39 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host) CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); } -static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev) +static int socfpga_dwmmc_get_clk_rate(struct udevice *dev) { - /* FIXME: probe from DT eventually too/ */ - const unsigned long clk = cm_get_mmc_controller_clk_hz(); - struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; - int fifo_depth; +#if CONFIG_IS_ENABLED(CLK) + struct clk clk; + int ret; + + ret = clk_get_by_index(dev, 1, &clk); + if (ret) + return ret; - if (clk == 0) { + host->bus_hz = clk_get_rate(&clk); + + clk_free(&clk); +#else + /* Fixed clock divide by 4 which due to the SDMMC wrapper */ + host->bus_hz = cm_get_mmc_controller_clk_hz(); +#endif + if (host->bus_hz == 0) { printf("DWMMC: MMC clock is zero!"); return -EINVAL; } + return 0; +} + +static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev) +{ + struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + int fifo_depth; + fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "fifo-depth", 0); if (fifo_depth < 0) { @@ -102,8 +122,6 @@ static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev) * We only have one dwmmc block on gen5 SoCFPGA. */ host->dev_index = 0; - /* Fixed clock divide by 4 which due to the SDMMC wrapper */ - host->bus_hz = clk; host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2); priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), @@ -123,6 +141,11 @@ static int socfpga_dwmmc_probe(struct udevice *dev) struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; + int ret; + + ret = socfpga_dwmmc_get_clk_rate(dev); + if (ret) + return ret; socfpga_dwmci_reset(dev); @@ -130,7 +153,6 @@ static int socfpga_dwmmc_probe(struct udevice *dev) dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000); host->mmc = &plat->mmc; #else - int ret; ret = add_dwmci(host, host->bus_hz, 400000); if (ret) -- 2.16.2

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