August 2018 - U-Boot

[U-Boot] [PATCH V3 1/2] mmc: add HS400 support
by Peng Fan 10 Aug '18

10 Aug '18

Add HS400 support. Selecting HS400 needs first select HS199 according to spec, so use a dedicated function for HS400. Add HS400 related macros. Remove the restriction of only using the low 6 bits of EXT_CSD_CARD_TYPE, using all the 8 bits. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Jean-Jacques Hiblot <jjhiblot(a)ti.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Kishon Vijay Abraham I <kishon(a)ti.com> Cc: Bin Meng <bmeng.cn(a)gmail.com> --- V3: Simplify code add error msg V2: remove 4bits support from HS400, as HS400 does not support 4bits per spec. drivers/mmc/Kconfig | 7 +++ drivers/mmc/mmc.c | 137 +++++++++++++++++++++++++++++++++++++++++----------- include/mmc.h | 11 +++++ 3 files changed, 128 insertions(+), 27 deletions(-) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 3f15f85efd..a535a87a8e 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -104,6 +104,13 @@ config SPL_MMC_UHS_SUPPORT cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus frequency can go up to 208MHz (SDR104) +config MMC_HS400_SUPPORT + bool "enable HS400 support" + select MMC_HS200_SUPPORT + help + The HS400 mode is support by some eMMC. The bus frequency is up to + 200MHz. This mode requires tuning the IO. + config MMC_HS200_SUPPORT bool "enable HS200 support" help diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index f7827f527a..3bb6a68513 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -147,6 +147,7 @@ const char *mmc_mode_name(enum bus_mode mode) [MMC_HS_52] = "MMC High Speed (52MHz)", [MMC_DDR_52] = "MMC DDR52 (52MHz)", [MMC_HS_200] = "HS200 (200MHz)", + [MMC_HS_400] = "HS400 (200MHz)", }; if (mode >= MMC_MODES_END) @@ -171,6 +172,7 @@ static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode) [UHS_DDR50] = 50000000, [UHS_SDR104] = 208000000, [MMC_HS_200] = 200000000, + [MMC_HS_400] = 200000000, }; if (mode == MMC_LEGACY) @@ -769,6 +771,11 @@ static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode) case MMC_HS_200: speed_bits = EXT_CSD_TIMING_HS200; break; +#endif +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + case MMC_HS_400: + speed_bits = EXT_CSD_TIMING_HS400; + break; #endif case MMC_LEGACY: speed_bits = EXT_CSD_TIMING_LEGACY; @@ -816,7 +823,7 @@ static int mmc_get_capabilities(struct mmc *mmc) mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; - cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f; + cardtype = ext_csd[EXT_CSD_CARD_TYPE]; mmc->cardtype = cardtype; #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) @@ -824,6 +831,12 @@ static int mmc_get_capabilities(struct mmc *mmc) EXT_CSD_CARD_TYPE_HS200_1_8V)) { mmc->card_caps |= MMC_MODE_HS200; } +#endif +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V | + EXT_CSD_CARD_TYPE_HS400_1_8V)) { + mmc->card_caps |= MMC_MODE_HS400; + } #endif if (cardtype & EXT_CSD_CARD_TYPE_52) { if (cardtype & EXT_CSD_CARD_TYPE_DDR_52) @@ -1734,10 +1747,13 @@ static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode, u32 card_mask = 0; switch (mode) { + case MMC_HS_400: case MMC_HS_200: - if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_8V) + if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V | + EXT_CSD_CARD_TYPE_HS400_1_8V)) card_mask |= MMC_SIGNAL_VOLTAGE_180; - if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_2V) + if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V | + EXT_CSD_CARD_TYPE_HS400_1_2V)) card_mask |= MMC_SIGNAL_VOLTAGE_120; break; case MMC_DDR_52: @@ -1773,6 +1789,13 @@ static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode, #endif static const struct mode_width_tuning mmc_modes_by_pref[] = { +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + { + .mode = MMC_HS_400, + .widths = MMC_MODE_8BIT, + .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200 + }, +#endif #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) { .mode = MMC_HS_200, @@ -1816,6 +1839,54 @@ static const struct ext_csd_bus_width { {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1}, }; +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) +static int mmc_select_hs400(struct mmc *mmc) +{ + int err; + + /* Set timing to HS200 for tuning */ + err = mmc_set_card_speed(mmc, MMC_HS_200); + if (err) + return err; + + /* configure the bus mode (host) */ + mmc_select_mode(mmc, MMC_HS_200); + mmc_set_clock(mmc, mmc->tran_speed, false); + + /* execute tuning if needed */ + err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200); + if (err) { + debug("tuning failed\n"); + return err; + } + + /* Set back to HS */ + mmc_set_card_speed(mmc, MMC_HS); + mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false); + + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, + EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG); + if (err) + return err; + + err = mmc_set_card_speed(mmc, MMC_HS_400); + if (err) + return err; + + mmc_select_mode(mmc, MMC_HS_400); + err = mmc_set_clock(mmc, mmc->tran_speed, false); + if (err) + return err; + + return 0; +} +#else +static int mmc_select_hs400(struct mmc *mmc) +{ + return -ENOTSUPP; +} +#endif + #define for_each_supported_width(caps, ddr, ecbv) \ for (ecbv = ext_csd_bus_width;\ ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\ @@ -1869,37 +1940,49 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps) goto error; mmc_set_bus_width(mmc, bus_width(ecbw->cap)); - /* configure the bus speed (card) */ - err = mmc_set_card_speed(mmc, mwt->mode); - if (err) - goto error; - - /* - * configure the bus width AND the ddr mode (card) - * The host side will be taken care of in the next step - */ - if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) { - err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, - EXT_CSD_BUS_WIDTH, - ecbw->ext_csd_bits); + if (mwt->mode == MMC_HS_400) { + err = mmc_select_hs400(mmc); + if (err) { + printf("Select HS400 failed %d\n", err); + goto error; + } + } else { + /* configure the bus speed (card) */ + err = mmc_set_card_speed(mmc, mwt->mode); if (err) goto error; - } - /* configure the bus mode (host) */ - mmc_select_mode(mmc, mwt->mode); - mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE); + /* + * configure the bus width AND the ddr mode + * (card). The host side will be taken care + * of in the next step + */ + if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) { + err = mmc_switch(mmc, + EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BUS_WIDTH, + ecbw->ext_csd_bits); + if (err) + goto error; + } + + /* configure the bus mode (host) */ + mmc_select_mode(mmc, mwt->mode); + mmc_set_clock(mmc, mmc->tran_speed, + MMC_CLK_ENABLE); #ifdef MMC_SUPPORTS_TUNING - /* execute tuning if needed */ - if (mwt->tuning) { - err = mmc_execute_tuning(mmc, mwt->tuning); - if (err) { - pr_debug("tuning failed\n"); - goto error; + /* execute tuning if needed */ + if (mwt->tuning) { + err = mmc_execute_tuning(mmc, + mwt->tuning); + if (err) { + pr_debug("tuning failed\n"); + goto error; + } } - } #endif + } /* do a transfer to check the configuration */ err = mmc_read_and_compare_ext_csd(mmc); diff --git a/include/mmc.h b/include/mmc.h index 534c317b43..e12323b7cf 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -64,6 +64,7 @@ #define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52) #define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52) #define MMC_MODE_HS200 MMC_CAP(MMC_HS_200) +#define MMC_MODE_HS400 MMC_CAP(MMC_HS_400) #define MMC_MODE_8BIT BIT(30) #define MMC_MODE_4BIT BIT(29) @@ -248,6 +249,10 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) /* SDR mode @1.2V I/O */ #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ EXT_CSD_CARD_TYPE_HS200_1_2V) +#define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6) +#define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7) +#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ + EXT_CSD_CARD_TYPE_HS400_1_2V) #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ @@ -259,6 +264,7 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) #define EXT_CSD_TIMING_LEGACY 0 /* no high speed */ #define EXT_CSD_TIMING_HS 1 /* HS */ #define EXT_CSD_TIMING_HS200 2 /* HS200 */ +#define EXT_CSD_TIMING_HS400 3 /* HS400 */ #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) @@ -519,6 +525,7 @@ enum bus_mode { UHS_DDR50, UHS_SDR104, MMC_HS_200, + MMC_HS_400, MMC_MODES_END }; @@ -532,6 +539,10 @@ static inline bool mmc_is_mode_ddr(enum bus_mode mode) #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) else if (mode == UHS_DDR50) return true; +#endif +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + else if (mode == MMC_HS_400) + return true; #endif else return false; -- 2.14.1

4 13

[U-Boot] [PATCH 1/2] spi: add support for ARM PL022 SPI controller
by Quentin Schulz 10 Aug '18

10 Aug '18

This adds support for the ARM PL022 SPI controller for the standard variant (0x00041022) which has a 16bit wide and 8 locations deep TX/RX FIFO. A few parts were borrowed from the Linux kernel driver. Cc: Armando Visconti <armando.visconti(a)st.com> Cc: Vipin Kumar <vipin.kumar(a)st.com> Signed-off-by: Quentin Schulz <quentin.schulz(a)bootlin.com> --- Based on "[PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller" from Armando Visconti sent about 5 years ago. Modifications: - use readw/writew instead of readl/writel functions since the registers are 16bit wide and not 32, - flush the RX FIFO before claiming and releasing the bus (taken from the Linux kernel driver), - migrate to DM, - rework the register access (defines instead of a structure), - fix the set_speed function (taken from Linux kernel driver), drivers/spi/Kconfig | 8 +- drivers/spi/Makefile | 1 +- drivers/spi/pl022_spi.c | 337 +++++++++++++++++++++++++++++++++++++++++- include/pl022_spi.h | 28 +++- 4 files changed, 374 insertions(+) create mode 100644 drivers/spi/pl022_spi.c create mode 100644 include/pl022_spi.h diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index dcd719f..7d4d47d 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -125,6 +125,14 @@ config PIC32_SPI to access the SPI NOR flash, MMC-over-SPI on platforms based on Microchip PIC32 family devices. +config PL022_SPI + bool "ARM AMBA PL022 SSP controller driver" + depends on ARM + help + This selects the ARM(R) AMBA(R) PrimeCell PL022 SSP + controller. If you have an embedded system with an AMBA(R) + bus and a PL022 controller, say Y or M here. + config RENESAS_RPC_SPI bool "Renesas RPC SPI driver" depends on RCAR_GEN3 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 728e30c..6679987 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o obj-$(CONFIG_PIC32_SPI) += pic32_spi.o +obj-$(CONFIG_PL022_SPI) += pl022_spi.o obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c new file mode 100644 index 0000000..dc494a5 --- /dev/null +++ b/drivers/spi/pl022_spi.c @@ -0,0 +1,337 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2012 + * Armando Visconti, ST Microelectronics, armando.visconti(a)st.com. + * + * (C) Copyright 2018 + * Quentin Schulz, Bootlin, quentin.schulz(a)bootlin.com + * + * Driver for ARM PL022 SPI Controller. + */ + +#include <asm/io.h> +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <linux/bitops.h> +#include <linux/bug.h> +#include <linux/io.h> +#include <pl022_spi.h> +#include <spi.h> + +#define SSP_CR0(r) (r + 0x000) +#define SSP_CR1(r) (r + 0x004) +#define SSP_DR(r) (r + 0x008) +#define SSP_SR(r) (r + 0x00C) +#define SSP_CPSR(r) (r + 0x010) +#define SSP_IMSC(r) (r + 0x014) +#define SSP_RIS(r) (r + 0x018) +#define SSP_MIS(r) (r + 0x01C) +#define SSP_ICR(r) (r + 0x020) +#define SSP_DMACR(r) (r + 0x024) +#define SSP_CSR(r) (r + 0x030) /* vendor extension */ +#define SSP_ITCR(r) (r + 0x080) +#define SSP_ITIP(r) (r + 0x084) +#define SSP_ITOP(r) (r + 0x088) +#define SSP_TDR(r) (r + 0x08C) + +#define SSP_PID0(r) (r + 0xFE0) +#define SSP_PID1(r) (r + 0xFE4) +#define SSP_PID2(r) (r + 0xFE8) +#define SSP_PID3(r) (r + 0xFEC) + +#define SSP_CID0(r) (r + 0xFF0) +#define SSP_CID1(r) (r + 0xFF4) +#define SSP_CID2(r) (r + 0xFF8) +#define SSP_CID3(r) (r + 0xFFC) + +/* SSP Control Register 0 - SSP_CR0 */ +#define SSP_CR0_SPO (0x1 << 6) +#define SSP_CR0_SPH (0x1 << 7) +#define SSP_CR0_BIT_MODE(x) ((x) - 1) +#define SSP_SCR_MIN (0x00) +#define SSP_SCR_MAX (0xFF) +#define SSP_SCR_SHFT 8 +#define DFLT_CLKRATE 2 + +/* SSP Control Register 1 - SSP_CR1 */ +#define SSP_CR1_MASK_SSE (0x1 << 1) + +#define SSP_CPSR_MIN (0x02) +#define SSP_CPSR_MAX (0xFE) +#define DFLT_PRESCALE (0x40) + +/* SSP Status Register - SSP_SR */ +#define SSP_SR_MASK_TFE (0x1 << 0) /* Transmit FIFO empty */ +#define SSP_SR_MASK_TNF (0x1 << 1) /* Transmit FIFO not full */ +#define SSP_SR_MASK_RNE (0x1 << 2) /* Receive FIFO not empty */ +#define SSP_SR_MASK_RFF (0x1 << 3) /* Receive FIFO full */ +#define SSP_SR_MASK_BSY (0x1 << 4) /* Busy Flag */ + +struct pl022_spi_slave { + void *base; +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct clk clk; +#else + unsigned int freq; +#endif +}; + +/* + * ARM PL022 exists in different 'flavors'. + * This drivers currently support the standard variant (0x00041022), that has a + * 16bit wide and 8 locations deep TX/RX FIFO. + */ +static int pl022_is_supported(struct pl022_spi_slave *ps) +{ + /* PL022 version is 0x00041022 */ + if ((readw(SSP_PID0(ps->base)) == 0x22) && + (readw(SSP_PID1(ps->base)) == 0x10) && + ((readw(SSP_PID2(ps->base)) & 0xf) == 0x04) && + (readw(SSP_PID3(ps->base)) == 0x00)) + return 1; + + return 0; +} + +static int pl022_spi_ofdata_to_platdata(struct udevice *bus) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct pl022_spi_pdata *plat = bus->platdata; + const void *fdt = gd->fdt_blob; + int node = dev_of_offset(bus); + + plat->addr = fdtdec_get_addr_size(fdt, node, "reg", &plat->size); + + return clk_get_by_index(bus, 0, &plat->clk); +#else + return 0; +#endif +} + +static int pl022_spi_probe(struct udevice *bus) +{ + struct pl022_spi_pdata *plat = dev_get_platdata(bus); + struct pl022_spi_slave *ps = dev_get_priv(bus); + + ps->base = ioremap(plat->addr, plat->size); +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + ps->clk = plat->clk; +#else + ps->freq = plat->freq; +#endif + + /* Check the PL022 version */ + if (!pl022_is_supported(ps)) + return -ENOTSUPP; + + /* 12 bits per word, high polarity and default clock rate */ + writew(SSP_CR0_BIT_MODE(8) | SSP_CR0_SPH | + (DFLT_CLKRATE << SSP_SCR_SHFT), SSP_CR0(ps->base)); + writew(DFLT_PRESCALE, SSP_CPSR(ps->base)); + + return 0; +} + +static void flush(struct pl022_spi_slave *ps) +{ + do { + while (readw(SSP_SR(ps->base)) & SSP_SR_MASK_RNE) + readw(SSP_DR(ps->base)); + } while (readw(SSP_SR(ps->base)) & SSP_SR_MASK_BSY); +} + +static int pl022_spi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct pl022_spi_slave *ps = dev_get_priv(bus); + u16 reg; + + flush(ps); + + /* Enable the SPI hardware */ + reg = readw(SSP_CR1(ps->base)); + reg |= SSP_CR1_MASK_SSE; + writew(reg, SSP_CR1(ps->base)); + + return 0; +} + +static int pl022_spi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct pl022_spi_slave *ps = dev_get_priv(bus); + u16 reg; + + /* Disable the SPI hardware */ + reg = readw(SSP_CR1(ps->base)); + reg &= ~SSP_CR1_MASK_SSE; + writew(reg, SSP_CR1(ps->base)); + + flush(ps); + + return 0; +} + +static int pl022_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct pl022_spi_slave *ps = dev_get_priv(bus); + u32 len_tx = 0, len_rx = 0, len; + u32 ret = 0; + const u8 *txp = dout; + u8 *rxp = din, value; + + if (bitlen == 0) + /* Finish any previously submitted transfers */ + return 0; + + /* + * TODO: The controller can do non-multiple-of-8 bit + * transfers, but this driver currently doesn't support it. + * + * It's also not clear how such transfers are supposed to be + * represented as a stream of bytes...this is a limitation of + * the current SPI interface. + */ + if (bitlen % 8) { + /* Errors always terminate an ongoing transfer */ + flags |= SPI_XFER_END; + return -1; + } + + len = bitlen / 8; + + while (len_tx < len) { + if (readw(SSP_SR(ps->base)) & SSP_SR_MASK_TNF) { + value = (txp) ? *txp++ : 0; + writew(value, SSP_DR(ps->base)); + len_tx++; + } + + if (readw(SSP_SR(ps->base)) & SSP_SR_MASK_RNE) { + value = readw(SSP_DR(ps->base)); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + + while (len_rx < len_tx) { + if (readw(SSP_SR(ps->base)) & SSP_SR_MASK_RNE) { + value = readw(SSP_DR(ps->base)); + if (rxp) + *rxp++ = value; + len_rx++; + } + } + + return ret; +} + +static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr) +{ + return rate / (cpsdvsr * (1 + scr)); +} + +static int pl022_spi_set_speed(struct udevice *bus, uint speed) +{ + struct pl022_spi_slave *ps = dev_get_priv(bus); + u16 scr = SSP_SCR_MIN, tmp, cr0 = 0, cpsr = SSP_CPSR_MIN, best_scr, + best_cpsr; + u32 min, max, best_freq = 0; +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + u32 rate = clk_get_rate(&ps->clk); +#else + u32 rate = ps->freq; +#endif + bool found = false; + + max = spi_rate(rate, SSP_CPSR_MIN, SSP_SCR_MIN); + min = spi_rate(rate, SSP_CPSR_MAX, SSP_SCR_MAX); + + if (speed > max || speed < min) { + pr_err("Tried to set speed to %dHz but min=%d and max=%d\n", + speed, min, max); + return -EINVAL; + } + + while (cpsr <= SSP_CPSR_MAX && !found) { + while (scr <= SSP_SCR_MAX) { + tmp = spi_rate(rate, cpsr, scr); + + if (tmp > speed) { + scr++; + continue; + } + + if (tmp > best_freq) { + best_freq = tmp; + best_cpsr = cpsr; + best_scr = scr; + + if (tmp == speed) + found = true; + } + + break; + } + cpsr += 2; + scr = SSP_SCR_MIN; + } + + writew(best_cpsr, SSP_CPSR(ps->base)); + cr0 = readw(SSP_CR0(ps->base)); + writew(cr0 | (best_scr << SSP_SCR_SHFT), SSP_CR0(ps->base)); + + return 0; +} + +static int pl022_spi_set_mode(struct udevice *bus, uint mode) +{ + struct pl022_spi_slave *ps = dev_get_priv(bus); + u16 reg; + + reg = readw(SSP_CR0(ps->base)); + reg &= ~(SSP_CR0_SPH | SSP_CR0_SPO); + if (mode & SPI_CPHA) + reg |= SSP_CR0_SPH; + if (mode & SPI_CPOL) + reg |= SSP_CR0_SPO; + writew(reg, SSP_CR0(ps->base)); + + return 0; +} + +static int pl022_cs_info(struct udevice *bus, uint cs, + struct spi_cs_info *info) +{ + return 0; +} + +static const struct dm_spi_ops pl022_spi_ops = { + .claim_bus = pl022_spi_claim_bus, + .release_bus = pl022_spi_release_bus, + .xfer = pl022_spi_xfer, + .set_speed = pl022_spi_set_speed, + .set_mode = pl022_spi_set_mode, + .cs_info = pl022_cs_info, +}; + +static const struct udevice_id pl022_spi_ids[] = { + { .compatible = "arm,pl022-spi" }, + { } +}; + +U_BOOT_DRIVER(pl022_spi) = { + .name = "pl022_spi", + .id = UCLASS_SPI, + .of_match = pl022_spi_ids, + .ops = &pl022_spi_ops, + .ofdata_to_platdata = pl022_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct pl022_spi_pdata), + .priv_auto_alloc_size = sizeof(struct pl022_spi_slave), + .probe = pl022_spi_probe, +}; diff --git a/include/pl022_spi.h b/include/pl022_spi.h new file mode 100644 index 0000000..e707b23 --- /dev/null +++ b/include/pl022_spi.h @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2018 + * Quentin Schulz, Bootlin, quentin.schulz(a)bootlin.com + * + * Structure for use with U_BOOT_DEVICE for pl022 SPI devices or to use + * in ofdata_to_platdata. + */ + +#ifndef __PL022_SPI_H__ +#define __PL022_SPI_H__ + +#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#include <clk.h> +#endif +#include <fdtdec.h> + +struct pl022_spi_pdata { + fdt_addr_t addr; + fdt_size_t size; +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct clk clk; +#else + unsigned int freq; +#endif +}; + +#endif base-commit: bb694d4e898b1368ba96e01481dc0a79c491e77c -- git-series 0.9.1

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[U-Boot] [PATCH v4 1/8] armv8: enable BLK code configuration
by Yinbo Zhu 10 Aug '18

10 Aug '18

This patch is to enable BLK code configuration for SD boot. Signed-off-by: Yinbo Zhu <yinbo.zhu(a)nxp.com> --- Change in v4: keep the same revision v4 for the entire set. include/mmc.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/mmc.h b/include/mmc.h index 534c317..66e69b7 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -604,7 +604,7 @@ struct mmc { u64 enh_user_start; u64 enh_user_size; #endif -#if !CONFIG_IS_ENABLED(BLK) +#if CONFIG_IS_ENABLED(BLK) struct blk_desc block_dev; #endif char op_cond_pending; /* 1 if we are waiting on an op_cond command */ -- 1.7.1

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[U-Boot] [PATCH] bcm968380gerg: Add MAINTAINERS file
by Tom Rini 10 Aug '18

10 Aug '18

Add an initial MAINTAINERS file based on author of the code. Cc: Philippe Reynes <philippe.reynes(a)softathome.com> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- board/broadcom/bcm968380gerg/MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 board/broadcom/bcm968380gerg/MAINTAINERS diff --git a/board/broadcom/bcm968380gerg/MAINTAINERS b/board/broadcom/bcm968380gerg/MAINTAINERS new file mode 100644 index 000000000000..52747cd9ea1d --- /dev/null +++ b/board/broadcom/bcm968380gerg/MAINTAINERS @@ -0,0 +1,6 @@ +BCM968380GERG BOARD +M: Philippe Reynes <philippe.reynes(a)softathome.com> +S: Maintained +F: board/broadcom/bcm968380gerg/ +F: include/configs/broadcom_bcm968380gerg.h +F: configs/bcm968380gerg_ram_defconfig -- 2.7.4

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[U-Boot] Please pull u-boot-dm
by Simon Glass 10 Aug '18

10 Aug '18

Hi Tom, This includes Bin's PCI improvements, a patman fix and moving pylibfdt over to match upstream. The following changes since commit b1aad8dbe28415695b290726199681ced969c118: zynqmp: Add avnet_ultra96_rev1_defconfig to the lits of boards (2018-08-07 11:36:39 -0400) are available in the Git repository at: git://git.denx.de/u-boot-dm.git for you to fetch changes up to 41d7535cba42cd88f3b04f8fbd4409e5a479076f: patman: Correct unit test failure (2018-08-08 12:49:36 +0100) ---------------------------------------------------------------- Bin Meng (21): pci: Remove 440ep-specific macros dm: Correct typos in uclass_first/next_device_check() dm: core: Add ofnode function to read PCI vendor and device id dm: pci: Extract vendor/device id in child_post_bind() dm: pci: Fix scanning multi-function device test: dm: pci: Remove unnecessary steps in dm_test_pci_swapcase() test: dm: pci: Test more than one device on the same bus pci: sandbox: swap_case: Preserve space indicator bit in BAR registers test: dm: pci: Test more than one PCI host controller test: dm: pci: Add tests for configuration space access pci: sandbox: emul: Fix the call to pci_bus_find_devfn() dm: pci: Assign correct driver data when binding a driver pci: sandbox: Support dynamically binding device driver pci: sandbox: swap_case: Declare dynamic driver matching sandbox: Update test.dts for dynamic PCI device driver matching test: dm: pci: Test driver binding with driver data provided pci: sandbox: emul: Rename priv structure test: dm: pci: Add tests for mixed static and dynamic devices on the same bus pci: Add all known capability and extended capability ids dm: pci: Add APIs to find capability and extended capability test: dm: pci: Add cases for finding PCI capability APIs Simon Glass (2): libfdt: Update to latest pylibfdt implementation patman: Correct unit test failure arch/sandbox/dts/test.dts | 41 ++- arch/sandbox/include/asm/test.h | 12 + doc/driver-model/pci-info.txt | 28 ++ drivers/core/ofnode.c | 36 ++ drivers/misc/swap_case.c | 36 +- drivers/pci/pci-emul-uclass.c | 24 +- drivers/pci/pci-uclass.c | 83 ++++- drivers/pci/pci_sandbox.c | 78 +++- include/dm/ofnode.h | 13 + include/dm/uclass.h | 4 +- include/pci.h | 84 ++++- scripts/dtc/pylibfdt/libfdt.i_shipped | 464 ++++++++++++------------ test/dm/pci.c | 170 ++++++++- tools/dtoc/fdt.py | 2 +- tools/dtoc/test_fdt.py | 2 +- ...rrect-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch} | 0 16 files changed, 797 insertions(+), 280 deletions(-) rename tools/patman/test/{0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_memory_.patch => 0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch} (100%) Regards, Simon

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[U-Boot] [GIT PULL] u-boot-mips/master
by Daniel Schwierzeck 10 Aug '18

10 Aug '18

Hi Tom, I hope it's okay for post RC1, but I wanted to wait until you had the Kconfig sorting stuff merged. Travis CI: https://travis-ci.org/danielschwierzeck/u-boot/builds/413538994 The following changes since commit b1aad8dbe28415695b290726199681ced969c118: zynqmp: Add avnet_ultra96_rev1_defconfig to the lits of boards (2018-08-07 11:36:39 -0400) are available in the Git repository at: git://git.denx.de/u-boot-mips.git master for you to fetch changes up to 990cebf0a2c2e4dd9033c56acf7b1404a0c0f698: bcm968380gerg: add initial support (2018-08-08 13:38:17 +0200) ---------------------------------------------------------------- Philippe Reynes (3): bmips: ram: add an option to force the size of the ram bcm6838: add initial support bcm968380gerg: add initial support Tom Rini (2): mips: dbau1x00: Remove this board mips: au1x00: Remove support for these SoCs arch/mips/Kconfig | 21 -- arch/mips/Makefile | 1 - arch/mips/dts/brcm,bcm6838.dtsi | 75 +++++ arch/mips/dts/brcm,bcm968380gerg.dts | 40 +++ arch/mips/include/asm/addrspace.h | 6 +- arch/mips/mach-au1x00/Makefile | 6 - arch/mips/mach-au1x00/au1x00_eth.c | 312 -------------------- arch/mips/mach-au1x00/au1x00_ide.c | 14 - arch/mips/mach-au1x00/au1x00_serial.c | 130 --------- arch/mips/mach-au1x00/au1x00_usb_ohci.c | 1609 -------------------------------------------------------------------------------------------------------- arch/mips/mach-au1x00/au1x00_usb_ohci.h | 416 --------------------------- arch/mips/mach-au1x00/include/mach/au1x00.h | 1071 --------------------------------------------------------------------- arch/mips/mach-bmips/Kconfig | 25 ++ board/broadcom/bcm968380gerg/Kconfig | 12 + board/broadcom/bcm968380gerg/Makefile | 3 + board/broadcom/bcm968380gerg/bcm968380gerg.c | 6 + board/broadcom/bcm968380gerg/board.c | 6 + board/dbau1x00/Kconfig | 46 --- board/dbau1x00/MAINTAINERS | 10 - board/dbau1x00/Makefile | 7 - board/dbau1x00/README | 63 ----- board/dbau1x00/dbau1x00.c | 118 -------- board/dbau1x00/lowlevel_init.S | 589 -------------------------------------- board/pb1x00/Kconfig | 27 -- board/pb1x00/MAINTAINERS | 6 - board/pb1x00/Makefile | 7 - board/pb1x00/README | 63 ----- board/pb1x00/flash.c | 26 -- board/pb1x00/lowlevel_init.S | 391 -------------------------- board/pb1x00/pb1x00.c | 108 ------- configs/bcm968380gerg_ram_defconfig | 48 ++++ configs/dbau1000_defconfig | 21 -- configs/dbau1100_defconfig | 21 -- configs/dbau1500_defconfig | 21 -- configs/dbau1550_defconfig | 16 -- configs/dbau1550_el_defconfig | 17 -- configs/pb1000_defconfig | 20 -- drivers/cpu/bmips_cpu.c | 33 +++ drivers/ram/bmips_ram.c | 8 +- drivers/serial/serial.c | 2 - drivers/usb/gadget/gadget_chips.h | 8 - include/configs/bmips_bcm6838.h | 24 ++ include/configs/broadcom_bcm968380gerg.h | 9 + include/configs/dbau1x00.h | 172 ------------ include/configs/pb1x00.h | 138 --------- include/netdev.h | 1 - include/serial.h | 1 - 47 files changed, 291 insertions(+), 5483 deletions(-) create mode 100644 arch/mips/dts/brcm,bcm6838.dtsi create mode 100644 arch/mips/dts/brcm,bcm968380gerg.dts delete mode 100644 arch/mips/mach-au1x00/Makefile delete mode 100644 arch/mips/mach-au1x00/au1x00_eth.c delete mode 100644 arch/mips/mach-au1x00/au1x00_ide.c delete mode 100644 arch/mips/mach-au1x00/au1x00_serial.c delete mode 100644 arch/mips/mach-au1x00/au1x00_usb_ohci.c delete mode 100644 arch/mips/mach-au1x00/au1x00_usb_ohci.h delete mode 100644 arch/mips/mach-au1x00/include/mach/au1x00.h create mode 100644 board/broadcom/bcm968380gerg/Kconfig create mode 100644 board/broadcom/bcm968380gerg/Makefile create mode 100644 board/broadcom/bcm968380gerg/bcm968380gerg.c create mode 100644 board/broadcom/bcm968380gerg/board.c delete mode 100644 board/dbau1x00/Kconfig delete mode 100644 board/dbau1x00/MAINTAINERS delete mode 100644 board/dbau1x00/Makefile delete mode 100644 board/dbau1x00/README delete mode 100644 board/dbau1x00/dbau1x00.c delete mode 100644 board/dbau1x00/lowlevel_init.S delete mode 100644 board/pb1x00/Kconfig delete mode 100644 board/pb1x00/MAINTAINERS delete mode 100644 board/pb1x00/Makefile delete mode 100644 board/pb1x00/README delete mode 100644 board/pb1x00/flash.c delete mode 100644 board/pb1x00/lowlevel_init.S delete mode 100644 board/pb1x00/pb1x00.c create mode 100644 configs/bcm968380gerg_ram_defconfig delete mode 100644 configs/dbau1000_defconfig delete mode 100644 configs/dbau1100_defconfig delete mode 100644 configs/dbau1500_defconfig delete mode 100644 configs/dbau1550_defconfig delete mode 100644 configs/dbau1550_el_defconfig delete mode 100644 configs/pb1000_defconfig create mode 100644 include/configs/bmips_bcm6838.h create mode 100644 include/configs/broadcom_bcm968380gerg.h delete mode 100644 include/configs/dbau1x00.h delete mode 100644 include/configs/pb1x00.h

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[U-Boot] [PATCH v3 1/2] armv8: layerscape: Enable EHCI access for LS1012A
by Ran Wang 10 Aug '18

10 Aug '18

Program Central Security Unit (CSU) to grant access permission for USB 2.0 controller, otherwiase EHCI funciton will down. Signed-off-by: Ran Wang <ran.wang_1(a)nxp.com> --- Change in v3: - None Change in v2: - Add EL checking code to make sure related programming only happen in EL3 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 9 +++++++++ arch/arm/include/asm/arch-fsl-layerscape/ns_access.h | 1 + 2 files changed, 10 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 6a56269..d8c3083 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -14,6 +14,7 @@ #include <asm/io.h> #include <asm/global_data.h> #include <asm/arch-fsl-layerscape/config.h> +#include <asm/arch-fsl-layerscape/ns_access.h> #ifdef CONFIG_LAYERSCAPE_NS_ACCESS #include <fsl_csu.h> #endif @@ -668,6 +669,14 @@ void fsl_lsch2_early_init_f(void) CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); } + /* + * Program Central Security Unit (CSU) to grant access + * permission for USB 2.0 controller + */ +#if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL) + if (current_el() == 3) + set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW); +#endif /* Erratum */ erratum_a008850_early(); /* part 1 of 2 */ erratum_a009929(); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h index fe97a93..d1b8efa 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h @@ -40,6 +40,7 @@ enum csu_cslx_ind { CSU_CSLX_ESDHC, CSU_CSLX_IFC = 45, CSU_CSLX_I2C1, + CSU_CSLX_USB_2, CSU_CSLX_I2C3 = 48, CSU_CSLX_I2C2, CSU_CSLX_DUART2 = 50, -- 2.7.4

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[U-Boot] [RFC] efi_loader: workaround for EDK2's shell.efi
by AKASHI Takahiro 10 Aug '18

10 Aug '18

The commit 21b3edfc964 ("efi_loader: check parameters of CreateEvent") enforces a strict parameter check at CreateEvent(). Unfortunately, however, EDK2's Shell.efi calls this function with notify_tpl == 0. The patch above does right thing and we'd better fix the issue on EDK2 side, and yet we might want a workaround allowing for running un-modified version of EDK2 in short-term solution. The patch provides a minimum mitigation of parameter check. Signed-off-by: AKASHI Takahiro <takahiro.akashi(a)linaro.org> --- lib/efi_loader/efi_boottime.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 2281703f261..e7a19c35415 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -627,7 +627,8 @@ efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl, return EFI_INVALID_PARAMETER; } - if (is_valid_tpl(notify_tpl) != EFI_SUCCESS) + /* notify_tpl == 0: workaround for EDK2's Shell.efi */ + if (notify_tpl && (is_valid_tpl(notify_tpl) != EFI_SUCCESS)) return EFI_INVALID_PARAMETER; evt = calloc(1, sizeof(struct efi_event)); -- 2.18.0

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[U-Boot] [PATCH 1/4 v2] spi: spi-mem: Use 2 SPI messages instead of a single full-duplex one
by Stefan Roese 09 Aug '18

09 Aug '18

Some SPI controller do not support full-duplex SPI transfers. This patch changes the SPI transfer into 2 separate transfers - or 1, if no data is to transmitted. With this change, no buffers need to be allocated anymore. We use the TX and RX buffers that are passed to spi_mem_exec_op() directly. Signed-off-by: Stefan Roese <sr(a)denx.de> Suggested-by: Boris Brezillon <boris.brezillon(a)bootlin.com> Cc: Miquel Raynal <miquel.raynal(a)bootlin.com> Cc: Boris Brezillon <boris.brezillon(a)bootlin.com> Cc: Jagan Teki <jagan(a)openedev.com> --- v2: - Replaces patch "spi: spi-mem: Add optional half-duplex SPI transfer mode" from first patchset version - No compile-time option but the default to use 2 separate SPI messages to transfer the command and data drivers/spi/spi-mem.c | 74 +++++++++++++++++++++++-------------------- 1 file changed, 39 insertions(+), 35 deletions(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 07ce799170..84e33aa979 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -15,6 +15,8 @@ #include <spi-mem.h> #endif +#define OP_BUFFER_SIZE_MAX 16 /* Max size for cmd + addr + dummy */ + #ifndef __UBOOT__ /** * spi_controller_dma_map_mem_op_data() - DMA-map the buffer attached to a @@ -200,8 +202,12 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) bool tx_data = op->data.nbytes && (op->data.dir == SPI_MEM_DATA_OUT); struct udevice *bus = slave->dev->parent; struct dm_spi_ops *ops = spi_get_ops(bus); - unsigned int xfer_len, pos = 0; - u8 *tx_buf, *rx_buf = NULL; + unsigned int pos = 0; + const u8 *tx_buf; + u8 *rx_buf; + u8 op_buf[OP_BUFFER_SIZE_MAX]; + int op_len; + u32 flag; int ret; int i; @@ -330,67 +336,65 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) return -ENOTSUPP; } - xfer_len = sizeof(op->cmd.opcode) + op->addr.nbytes + - op->dummy.nbytes + op->data.nbytes; + tx_buf = op->data.buf.out; + rx_buf = op->data.buf.in; - /* - * Allocate a buffer to transmit the CMD, ADDR cycles with kmalloc() so - * we're guaranteed that this buffer is DMA-able, as required by the - * SPI layer. - */ - tx_buf = kzalloc(xfer_len, GFP_KERNEL); - if (!tx_buf) - return -ENOMEM; - - if (rx_data) { - rx_buf = kzalloc(xfer_len, GFP_KERNEL); - if (!rx_buf) - return -ENOMEM; + op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes; + if (op_len > OP_BUFFER_SIZE_MAX) { + printf("Length for cmd+addr+dummy too big (%d)\n", op_len); + return -EIO; } + memset(op_buf, 0x00, op_len); ret = spi_claim_bus(slave); if (ret < 0) return ret; - tx_buf[pos++] = op->cmd.opcode; + op_buf[pos++] = op->cmd.opcode; if (op->addr.nbytes) { for (i = 0; i < op->addr.nbytes; i++) - tx_buf[pos + i] = op->addr.val >> - (8 * (op->addr.nbytes - i - 1)); + op_buf[pos + i] = op->addr.val >> + (8 * (op->addr.nbytes - i - 1)); pos += op->addr.nbytes; } - if (op->dummy.nbytes) { - memset(tx_buf + pos, 0xff, op->dummy.nbytes); - pos += op->dummy.nbytes; + if (op->dummy.nbytes) + memset(op_buf + pos, 0xff, op->dummy.nbytes); + + /* 1st transfer: opcode + address + dummy cycles */ + flag = SPI_XFER_BEGIN; + /* Make sure to set END bit if no tx or rx data messages follow */ + if (!tx_data && !rx_data) + flag |= SPI_XFER_END; + ret = spi_xfer(slave, op_len * 8, op_buf, NULL, flag); + + if (tx_data) { + /* 2nd transfer a: tx data path */ + ret = spi_xfer(slave, op->data.nbytes * 8, tx_buf, NULL, + SPI_XFER_END); } - if (tx_data) - memcpy(tx_buf + pos, op->data.buf.out, op->data.nbytes); + if (rx_data) { + /* 2nd transfer b: rx data path */ + ret = spi_xfer(slave, op->data.nbytes * 8, NULL, rx_buf, + SPI_XFER_END); + } - ret = spi_xfer(slave, xfer_len * 8, tx_buf, rx_buf, - SPI_XFER_BEGIN | SPI_XFER_END); spi_release_bus(slave); for (i = 0; i < pos; i++) - debug("%02x ", tx_buf[i]); + debug("%02x ", op_buf[i]); debug("| [%dB %s] ", tx_data || rx_data ? op->data.nbytes : 0, tx_data || rx_data ? (tx_data ? "out" : "in") : "-"); - for (; i < xfer_len; i++) + for (i = 0; i < op->data.nbytes; i++) debug("%02x ", tx_data ? tx_buf[i] : rx_buf[i]); debug("[ret %d]\n", ret); if (ret < 0) return ret; - - if (rx_data) - memcpy(op->data.buf.in, rx_buf + pos, op->data.nbytes); - - kfree(tx_buf); - kfree(rx_buf); #endif /* __UBOOT__ */ return 0; -- 2.18.0

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[U-Boot] [PATCH v3 0/7] Fixes/Addition to use the USB Ethernet gadget with the DWC3 gadget controller
by Jean-Jacques Hiblot 09 Aug '18

09 Aug '18

This series implements 2 fixes to be able to use USB Ethernet gadget with the dwc3 driver. It also adds new commands to bind/unbind a device to/from a driver and update the 'dm tree' command to make it easier to use those new commands. The bind/unbind commands can be used to bind the DWC3 USB gadget to the usb_ether driver from the command line instead of relying on platform code. Changes in v3: - update some commit logs - factorize code based on comments from ML - remove the devices before unbinding them - use device_find_global_by_ofnode() to get a device by its node. Changes in v2: - Make the bind/unbind command generic, not specific to usb device. - Update the API to be able to bind/unbind based on DTS node path - Add a Kconfig option to select the bind/unbind commands Jean-Jacques Hiblot (7): usb: gadget: Add bcdDevice for the DWC3 USB Gadget Controller net: eth-uclass: Fix for DM USB ethernet support uclass: Add dev_get_uclass_index() to get the uclass/index of a device dm: print the index of the device when dumping the dm tree dm: convert device_get_global_by_of_offset() to device_get_global_by_ofnode() device: expose the functions used to remove and unbind children of a device cmd: Add bind/unbind commands to bind a device to a driver from the command line arch/arm/mach-rockchip/rk3188-board-spl.c | 2 +- arch/arm/mach-rockchip/rk3288-board-spl.c | 2 +- arch/sandbox/dts/test.dts | 11 ++ cmd/Kconfig | 9 ++ cmd/Makefile | 1 + cmd/bind.c | 255 ++++++++++++++++++++++++++++++ configs/sandbox_defconfig | 1 + drivers/core/device-remove.c | 30 ++-- drivers/core/device.c | 19 ++- drivers/core/dump.c | 16 +- drivers/core/uclass.c | 21 +++ drivers/usb/gadget/gadget_chips.h | 2 + include/dm/device-internal.h | 38 +++++ include/dm/device.h | 23 ++- include/dm/uclass-internal.h | 11 ++ net/eth-uclass.c | 3 +- test/py/tests/test_bind.py | 178 +++++++++++++++++++++ 17 files changed, 584 insertions(+), 38 deletions(-) create mode 100644 cmd/bind.c create mode 100644 test/py/tests/test_bind.py -- 2.7.4

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