August 2018 - U-Boot

[U-Boot] [PATCH] Revert "Revert "fdt_support: Use CONFIG_NR_DRAM_BANKS if defined""
by Vagrant Cascadian 16 Aug '18

16 Aug '18

This reverts commit 2a1f4f1758b55589395f90f583aacb07ae6fcafe. Maybe there's a better way to fix this, but reverting this got odroid-xu4 booting agian: U-Boot 2018.09-rc2+dfsg-1~20180814~1 (Aug 14 2018 - 18:33:28 +0000) for ODROID-XU3/XU4/HC1 CPU: Exynos5422 @ 800 MHz Model: Odroid XU3 based on EXYNOS5422 Board: Odroid XU3 based on EXYNOS5422 Type: xu4 DRAM: 2 GiB MMC: EXYNOS DWMMC: 0, EXYNOS DWMMC: 2 Loading Environment from MMC... *** Warning - No block device, using default environment In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 MMC Device 1 not found no mmc device at slot 1 switch to partitions #0, OK mmc2 is current device Scanning mmc 2:2... Found U-Boot script /boot.scr 2445 bytes read in 3 ms (795.9 KiB/s) 3819744 bytes read in 364 ms (10 MiB/s) 54655 bytes read in 12 ms (4.3 MiB/s) 17611313 bytes read in 1676 ms (10 MiB/s) Booting Debian 4.9.0-7-armmp-lpae from mmc 2:2... Kernel image @ 0x42000000 [ 0x000000 - 0x3a48e0 ] Booting using the fdt blob at 0x43000000 Loading Ramdisk to 4ef34000, end 4ffffa31 ... OK Loading Device Tree to 4ef23000, end 4ef3357e ... OK fdt_fixup_memory_banks: num banks 8 exceeds hardcoded limit 4. Recompile with higher MEMORY_BANKS_MAX? ERROR: arch-specific fdt fixup failed - must RESET the board to recover. FDT creation failed! hanging...### ERROR ### Please RESET the board ### Signed-off-by: Vagrant Cascadian <vagrant(a)debian.org> --- common/fdt_support.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/common/fdt_support.c b/common/fdt_support.c index 34d2bd59c4..be8cdfbeb3 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -409,7 +409,11 @@ static int fdt_pack_reg(const void *fdt, void *buf, u64 *address, u64 *size, return p - (char *)buf; } +#ifdef CONFIG_NR_DRAM_BANKS +#define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS +#else #define MEMORY_BANKS_MAX 4 +#endif int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks) { int err, nodeoffset; -- 2.11.0

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[U-Boot] Problem with v2018-09-rc2 to boot EFI on Arndale board
by Guillaume GARDET 16 Aug '18

16 Aug '18

Hi, While trying to boot Grub2/EFI on Arndale board, I got the following error: ********************************************************************** fdt_fixup_memory_banks: num banks 8 exceeds hardcoded limit 4. Recompile with higher MEMORY_BANKS_MAX? ERROR: arch-specific fdt fixup failed - must RESET the board to recover. ERROR: failed to process device tree ERROR: failed to install device tree 812544 bytes read in 77 ms (10.1 MiB/s) fdt_fixup_memory_banks: num banks 8 exceeds hardcoded limit 4. Recompile with higher MEMORY_BANKS_MAX? ERROR: arch-specific fdt fixup failed - must RESET the board to recover. ERROR: failed to process device tree ERROR: failed to install device tree EFI LOAD FAILED: continuing... ********************************************************************** If I set MEMORY_BANKS_MAX to 8 in common/fdt_support.c , then it boots fine. Is there any reason to stick this to 4, or could I send a patch to rise it to 8? Would be great to get it fixed for v2018.09. Guillaume

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[U-Boot] [PATCH v2] usb: dwc2: Add reset ctrl to driver
by Ley Foon Tan 16 Aug '18

16 Aug '18

Add code to reset all reset signals as in usb DT node. A reset property is an optional feature, so only print out a warning and do not fail if a reset property is not present. If a reset property is discovered, then use it to deassert, thus bringing the IP out of reset. Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> --- v2: - Assert reset when .remove. --- drivers/usb/host/dwc2.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index cbe065b..bee3b33 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -15,6 +15,7 @@ #include <wait_bit.h> #include <asm/io.h> #include <power/regulator.h> +#include <reset.h> #include "dwc2.h" @@ -49,6 +50,8 @@ struct dwc2_priv { */ bool hnp_srp_disable; bool oc_disable; + + struct reset_ctl_bulk resets; }; #ifndef CONFIG_DM_USB @@ -1124,11 +1127,37 @@ int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev, } } +static int dwc2_reset(struct udevice *dev) +{ + int ret; + struct dwc2_priv *priv = dev_get_priv(dev); + + ret = reset_get_bulk(dev, &priv->resets); + if (ret) { + dev_warn(dev, "Can't get reset: %d\n", ret); + return ret; + } + + ret = reset_deassert_bulk(&priv->resets); + if (ret) { + reset_release_bulk(&priv->resets); + dev_err(dev, "Failed to reset: %d\n", ret); + return ret; + } + + return 0; +} + static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv) { struct dwc2_core_regs *regs = priv->regs; uint32_t snpsid; int i, j; + int ret; + + ret = dwc2_reset(dev); + if (ret) + return ret; snpsid = readl(&regs->gsnpsid); dev_info(dev, "Core Release: %x.%03x\n", @@ -1303,6 +1332,8 @@ static int dwc2_usb_remove(struct udevice *dev) dwc2_uninit_common(priv->regs); + reset_release_bulk(&priv->resets); + return 0; } -- 2.2.2

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[U-Boot] [PATCH v2] gpio: dwapb_gpio: Add reset ctrl to driver
by Ley Foon Tan 16 Aug '18

16 Aug '18

Add code to reset all reset signals as in gpio DT node. A reset property is an optional feature, so only print out a warning and do not fail if a reset property is not present. If a reset property is discovered, then use it to deassert, thus bringing the IP out of reset. Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> --- v2: - Move reset to probe() function. --- drivers/gpio/dwapb_gpio.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/dwapb_gpio.c b/drivers/gpio/dwapb_gpio.c index 7cf2d47..dfe1e6d 100644 --- a/drivers/gpio/dwapb_gpio.c +++ b/drivers/gpio/dwapb_gpio.c @@ -15,6 +15,7 @@ #include <dm/lists.h> #include <dm/root.h> #include <errno.h> +#include <reset.h> DECLARE_GLOBAL_DATA_PTR; @@ -99,13 +100,30 @@ static const struct dm_gpio_ops gpio_dwapb_ops = { .get_function = dwapb_gpio_get_function, }; +static void gpio_dwapb_reset(struct udevice *dev) +{ + struct reset_ctl_bulk reset_bulk; + int ret; + + ret = reset_get_bulk(dev, &reset_bulk); + if (ret) { + dev_warn(dev, "Can't get reset: %d\n", ret); + return; + } + + reset_deassert_bulk(&reset_bulk); +} + static int gpio_dwapb_probe(struct udevice *dev) { struct gpio_dev_priv *priv = dev_get_uclass_priv(dev); struct gpio_dwapb_platdata *plat = dev->platdata; - if (!plat) + if (!plat) { + /* Reset on parent device only */ + gpio_dwapb_reset(dev); return 0; + } priv->gpio_count = plat->pins; priv->bank_name = plat->name; -- 2.2.2

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[U-Boot] [PATCH v4] spi: Add SPI driver for MT76xx SoCs
by Stefan Roese 16 Aug '18

16 Aug '18

This patch adds the SPI driver for the MediaTek MT7688 SoC (and derivates). Its been tested on the LinkIt Smart 7688 and the Gardena Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart Gateway additionally with an SPI NAND on CS1. Note that the SPI controller only supports a max transfer size of 32 bytes. This driver implementes a workaround to enable bigger xfer sizes to speed up the transfer especially for the SPI NAND support. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Jagan Teki <jagan(a)openedev.com> Cc: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> Reviewed-by: Jagan Teki <jagan(a)openedev.com> --- v4: - Rename functions and macros from mt7621 to mt76xx to better reflect the SoC usage and match the driver name v3: - Drop IO wrappers completely as suggested by Daniel - Read "clock-frequency" DT property instead of using CONFIG_SYS_MIPS_TIMER_FREQ v2: - Add some macros instead of hardcoded numbers - Move compatible DT struct down in the file drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/mt76xx_spi.c | 312 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 321 insertions(+) create mode 100644 drivers/spi/mt76xx_spi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 9fbd26740d..6c4e50d3e9 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -116,6 +116,14 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config MT76XX_SPI + bool "MediaTek MT76XX SPI driver" + depends on ARCH_MT7620 + help + Enable the MT76XX SPI driver. This driver can be used to access + the SPI NOR flash on platforms embedding these MediaTek + SPI cores. + config MVEBU_A3700_SPI bool "Marvell Armada 3700 SPI driver" select CLK_ARMADA_3720 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index bdb5b5a02f..3d13ba1b21 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o +obj-$(CONFIG_MT76XX_SPI) += mt76xx_spi.o obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o diff --git a/drivers/spi/mt76xx_spi.c b/drivers/spi/mt76xx_spi.c new file mode 100644 index 0000000000..71ded3fe71 --- /dev/null +++ b/drivers/spi/mt76xx_spi.c @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Stefan Roese <sr(a)denx.de> + * + * Derived from the Linux driver version drivers/spi/spi-mt7621.c + * Copyright (C) 2011 Sergiy <piratfm(a)gmail.com> + * Copyright (C) 2011-2013 Gabor Juhos <juhosg(a)openwrt.org> + * Copyright (C) 2014-2015 Felix Fietkau <nbd(a)nbd.name> + */ + +#include <common.h> +#include <dm.h> +#include <spi.h> +#include <wait_bit.h> +#include <linux/io.h> + +#define SPI_MSG_SIZE_MAX 32 /* SPI message chunk size */ +/* Enough for SPI NAND page read / write with page size 2048 bytes */ +#define SPI_MSG_SIZE_OVERALL (2048 + 16) + +#define MT76XX_SPI_TRANS 0x00 +#define MT76XX_SPI_TRANS_START BIT(8) +#define MT76XX_SPI_TRANS_BUSY BIT(16) + +#define MT76XX_SPI_OPCODE 0x04 +#define MT76XX_SPI_DATA0 0x08 +#define MT76XX_SPI_DATA4 0x18 +#define MT76XX_SPI_MASTER 0x28 +#define MT76XX_SPI_MOREBUF 0x2c +#define MT76XX_SPI_POLAR 0x38 + +#define MT76XX_LSB_FIRST BIT(3) +#define MT76XX_CPOL BIT(4) +#define MT76XX_CPHA BIT(5) + +#define MASTER_MORE_BUFMODE BIT(2) +#define MASTER_RS_CLK_SEL GENMASK(27, 16) +#define MASTER_RS_CLK_SEL_SHIFT 16 +#define MASTER_RS_SLAVE_SEL GENMASK(31, 29) + +struct mt76xx_spi { + void __iomem *base; + unsigned int sys_freq; + u32 data[(SPI_MSG_SIZE_OVERALL / 4) + 1]; + int tx_len; +}; + +static void mt76xx_spi_reset(struct mt76xx_spi *rs, int duplex) +{ + setbits_le32(rs->base + MT76XX_SPI_MASTER, + MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE); +} + +static void mt76xx_spi_set_cs(struct mt76xx_spi *rs, int cs, int enable) +{ + u32 val = 0; + + debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" : "disable"); + if (enable) + val = BIT(cs); + iowrite32(val, rs->base + MT76XX_SPI_POLAR); +} + +static int mt76xx_spi_set_mode(struct udevice *bus, uint mode) +{ + struct mt76xx_spi *rs = dev_get_priv(bus); + u32 reg; + + debug("%s: mode=0x%08x\n", __func__, mode); + reg = ioread32(rs->base + MT76XX_SPI_MASTER); + + reg &= ~MT76XX_LSB_FIRST; + if (mode & SPI_LSB_FIRST) + reg |= MT76XX_LSB_FIRST; + + reg &= ~(MT76XX_CPHA | MT76XX_CPOL); + switch (mode & (SPI_CPOL | SPI_CPHA)) { + case SPI_MODE_0: + break; + case SPI_MODE_1: + reg |= MT76XX_CPHA; + break; + case SPI_MODE_2: + reg |= MT76XX_CPOL; + break; + case SPI_MODE_3: + reg |= MT76XX_CPOL | MT76XX_CPHA; + break; + } + iowrite32(reg, rs->base + MT76XX_SPI_MASTER); + + return 0; +} + +static int mt76xx_spi_set_speed(struct udevice *bus, uint speed) +{ + struct mt76xx_spi *rs = dev_get_priv(bus); + u32 rate; + u32 reg; + + debug("%s: speed=%d\n", __func__, speed); + rate = DIV_ROUND_UP(rs->sys_freq, speed); + debug("rate:%u\n", rate); + + if (rate > 4097) + return -EINVAL; + + if (rate < 2) + rate = 2; + + reg = ioread32(rs->base + MT76XX_SPI_MASTER); + reg &= ~MASTER_RS_CLK_SEL; + reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT; + iowrite32(reg, rs->base + MT76XX_SPI_MASTER); + + return 0; +} + +static inline int mt76xx_spi_wait_till_ready(struct mt76xx_spi *rs) +{ + int ret; + + ret = wait_for_bit_le32(rs->base + MT76XX_SPI_TRANS, + MT76XX_SPI_TRANS_BUSY, 0, 10, 0); + if (ret) + pr_err("Timeout in %s!\n", __func__); + + return ret; +} + +static int mt76xx_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct mt76xx_spi *rs = dev_get_priv(bus); + const u8 *tx_buf = dout; + u8 *ptr = (u8 *)dout; + u8 *rx_buf = din; + int total_size = bitlen >> 3; + int chunk_size; + int rx_len = 0; + u32 data[(SPI_MSG_SIZE_MAX / 4) + 1] = { 0 }; + u32 val; + int i; + + debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din, + total_size, flags); + + /* + * This driver only supports half-duplex, so complain and bail out + * upon full-duplex messages + */ + if (dout && din) { + printf("Only half-duplex SPI transfer supported\n"); + return -EIO; + } + + if (dout) { + debug("TX-DATA: "); + for (i = 0; i < total_size; i++) + debug("%02x ", *ptr++); + debug("\n"); + } + + mt76xx_spi_wait_till_ready(rs); + + /* + * Set CS active upon start of SPI message. This message can + * be split upon multiple calls to this xfer function + */ + if (flags & SPI_XFER_BEGIN) + mt76xx_spi_set_cs(rs, spi_chip_select(dev), 1); + + while (total_size > 0) { + /* Don't exceed the max xfer size */ + chunk_size = min_t(int, total_size, SPI_MSG_SIZE_MAX); + + /* + * We might have some TX data buffered from the last xfer + * message. Make sure, that this does not exceed the max + * xfer size + */ + if (rs->tx_len > 4) + chunk_size -= rs->tx_len; + if (din) + rx_len = chunk_size; + + if (tx_buf) { + /* Check if this message does not exceed the buffer */ + if ((chunk_size + rs->tx_len) > SPI_MSG_SIZE_OVERALL) { + printf("TX message size too big (%d)\n", + chunk_size + rs->tx_len); + return -EMSGSIZE; + } + + /* + * Write all TX data into internal buffer to collect + * all TX messages into one buffer (might be split into + * multiple calls to this function) + */ + for (i = 0; i < chunk_size; i++, rs->tx_len++) { + rs->data[rs->tx_len / 4] |= + tx_buf[i] << (8 * (rs->tx_len & 3)); + } + } + + if (flags & SPI_XFER_END) { + /* Write TX data into controller */ + if (rs->tx_len) { + rs->data[0] = swab32(rs->data[0]); + if (rs->tx_len < 4) + rs->data[0] >>= (4 - rs->tx_len) * 8; + + for (i = 0; i < rs->tx_len; i += 4) { + iowrite32(rs->data[i / 4], rs->base + + MT76XX_SPI_OPCODE + i); + } + } + + /* Write length into controller */ + val = (min_t(int, rs->tx_len, 4) * 8) << 24; + if (rs->tx_len > 4) + val |= (rs->tx_len - 4) * 8; + val |= (rx_len * 8) << 12; + iowrite32(val, rs->base + MT76XX_SPI_MOREBUF); + + /* Start the xfer */ + setbits_le32(rs->base + MT76XX_SPI_TRANS, + MT76XX_SPI_TRANS_START); + + /* Wait until xfer is finished on bus */ + mt76xx_spi_wait_till_ready(rs); + + /* Reset TX length and TX buffer for next xfer */ + rs->tx_len = 0; + memset(rs->data, 0, sizeof(rs->data)); + } + + for (i = 0; i < rx_len; i += 4) + data[i / 4] = ioread32(rs->base + MT76XX_SPI_DATA0 + i); + + if (rx_len) { + debug("RX-DATA: "); + for (i = 0; i < rx_len; i++) { + rx_buf[i] = data[i / 4] >> (8 * (i & 3)); + debug("%02x ", rx_buf[i]); + } + debug("\n"); + } + + if (tx_buf) + tx_buf += chunk_size; + if (rx_buf) + rx_buf += chunk_size; + total_size -= chunk_size; + } + + /* Wait until xfer is finished on bus and de-assert CS */ + mt76xx_spi_wait_till_ready(rs); + if (flags & SPI_XFER_END) + mt76xx_spi_set_cs(rs, spi_chip_select(dev), 0); + + return 0; +} + +static int mt76xx_spi_probe(struct udevice *dev) +{ + struct mt76xx_spi *rs = dev_get_priv(dev); + + rs->base = dev_remap_addr(dev); + if (!rs->base) + return -EINVAL; + + /* + * Read input clock via DT for now. At some point this should be + * replaced by implementing a clock driver for this SoC and getting + * the SPI frequency via this clock driver. + */ + rs->sys_freq = dev_read_u32_default(dev, "clock-frequency", 0); + if (!rs->sys_freq) { + printf("Please provide clock-frequency!\n"); + return -EINVAL; + } + + mt76xx_spi_reset(rs, 0); + + return 0; +} + +static const struct dm_spi_ops mt76xx_spi_ops = { + .set_mode = mt76xx_spi_set_mode, + .set_speed = mt76xx_spi_set_speed, + .xfer = mt76xx_spi_xfer, + /* + * cs_info is not needed, since we require all chip selects to be + * in the device tree explicitly + */ +}; + +static const struct udevice_id mt76xx_spi_ids[] = { + { .compatible = "ralink,mt76xx-spi" }, + { } +}; + +U_BOOT_DRIVER(mt76xx_spi) = { + .name = "mt76xx_spi", + .id = UCLASS_SPI, + .of_match = mt76xx_spi_ids, + .ops = &mt76xx_spi_ops, + .priv_auto_alloc_size = sizeof(struct mt76xx_spi), + .probe = mt76xx_spi_probe, +}; -- 2.18.0

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[U-Boot] [RFC PATCH] arm: zynq: read mac address from SPI flash memory
by Luis Araneda 16 Aug '18

16 Aug '18

Implement a method for reading the MAC address from an SPI flash memory. In particular, this method is used by the Zybo Z7 board to read the MAC address from the OTP region in the SPI NOR memory Signed-off-by: Luis Araneda <luaraneda(a)gmail.com> --- I'm trying to implement the reading of the MAC address of the Zybo Z7 board from the OTP region of its SPI NOR memory. I took some ideas from Digilent's fork, but the commit was marked as not upstremeable. That's why I'm asking for comments. If the code can't be merged, ideas on how this can be implemented are welcome. Thanks, Luis Araneda. --- board/xilinx/zynq/board.c | 28 ++++++++++++++++++++++++++++ configs/zynq_zybo_z7_defconfig | 3 +++ drivers/misc/Kconfig | 17 +++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 614d93c082..a252c38956 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -6,9 +6,12 @@ #include <common.h> #include <dm/uclass.h> +#include <dm/device.h> +#include <dm/device-internal.h> #include <fdtdec.h> #include <fpga.h> #include <mmc.h> +#include <spi_flash.h> #include <watchdog.h> #include <wdt.h> #include <zynqpl.h> @@ -87,6 +90,31 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) printf("I2C EEPROM MAC address read failed\n"); #endif +#if defined(CONFIG_MAC_ADDR_IN_SPI_FLASH) + struct spi_flash *flash; + struct udevice *dev; + int ret; + + ret = spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, + CONFIG_SF_DEFAULT_CS, + 0, 0, &dev); + if (ret) { + printf("SPI(bus:%u cs:%u) probe failed\n", + CONFIG_SF_DEFAULT_BUS, + CONFIG_SF_DEFAULT_CS); + return 0; + } + + flash = dev_get_uclass_priv(dev); + flash->read_cmd = CONFIG_MAC_ADDR_SPI_FLASH_READ_CMD; + + if (spi_flash_read_dm(dev, + CONFIG_MAC_ADDR_SPI_FLASH_DATA_OFFSET, + 6, ethaddr)) + printf("SPI MAC address read failed\n"); + + device_remove(dev, DM_REMOVE_NORMAL); +#endif return 0; } diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig index ad44e772aa..ca402e3231 100644 --- a/configs/zynq_zybo_z7_defconfig +++ b/configs/zynq_zybo_z7_defconfig @@ -44,6 +44,9 @@ CONFIG_DM_GPIO=y CONFIG_SYS_I2C_ZYNQ=y CONFIG_ZYNQ_I2C0=y CONFIG_ZYNQ_I2C1=y +CONFIG_MAC_ADDR_IN_SPI_FLASH=y +CONFIG_MAC_ADDR_SPI_FLASH_READ_CMD=0x4b +CONFIG_MAC_ADDR_SPI_FLASH_DATA_OFFSET=0x20 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index c031dfde9d..40cec81e66 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -272,6 +272,23 @@ config SYS_I2C_EEPROM_ADDR_OVERFLOW endif +config MAC_ADDR_IN_SPI_FLASH + bool "MAC address in SPI flash" + help + Read MAC address from an SPI flash memory + +if MAC_ADDR_IN_SPI_FLASH + +config MAC_ADDR_SPI_FLASH_READ_CMD + hex "Read command for the SPI flash memory" + default 0 + +config MAC_ADDR_SPI_FLASH_DATA_OFFSET + hex "Offset of MAC data in SPI flash memory" + default 0 + +endif + config GDSYS_RXAUI_CTRL bool "Enable gdsys RXAUI control driver" depends on MISC -- 2.18.0

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[U-Boot] [PATCH 1/5 v2] mips: Add basic MediaTek MT7620/88 support
by Stefan Roese 16 Aug '18

16 Aug '18

This patch adds basic support for the MediaTek MT7620/88 SoCs. Parts of the code is copied from the MediaTek GitHub repository: https://github.com/MediaTek-Labs/linkit-smart-uboot.git Support for the LinkIt Smart 7688 module and the Gardena Smart Gateway both based on the MT7688 will be added in further patches. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> --- v2: - Sort Kconfig symbols alphabetically - Use MIPS_TUNE_24KC - Use imply for SPI support - Dont' add LinkIt module support yet (is added with the board support) - Move SKIP_LOWLEVEL_INIT from Kconfig to config header - Use DT to get the base address of the system controller (for display_cpuinfo) - Remove _machine_restart - a separate driver is provided in a new patch - Remove cachop_op() and cal_invalidate_dcache_range and use the generic invalidate_dcache_range function instead Daniel I tried to change to CPU_HAS PREFETCH, but this did not work smoothly. It seems this option is very old and outdated. Perhaps I can revisit this again, once this patchset has settled a bit. arch/mips/Kconfig | 15 ++ arch/mips/Makefile | 1 + arch/mips/mach-mt7620/Kconfig | 113 +++++++++ arch/mips/mach-mt7620/Makefile | 8 + arch/mips/mach-mt7620/cpu.c | 72 ++++++ arch/mips/mach-mt7620/ddr_calibrate.c | 307 +++++++++++++++++++++++ arch/mips/mach-mt7620/lowlevel_init.S | 337 ++++++++++++++++++++++++++ arch/mips/mach-mt7620/mt76xx.h | 38 +++ 8 files changed, 891 insertions(+) create mode 100644 arch/mips/mach-mt7620/Kconfig create mode 100644 arch/mips/mach-mt7620/Makefile create mode 100644 arch/mips/mach-mt7620/cpu.c create mode 100644 arch/mips/mach-mt7620/ddr_calibrate.c create mode 100644 arch/mips/mach-mt7620/lowlevel_init.S create mode 100644 arch/mips/mach-mt7620/mt76xx.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 31b622ff51..b7c5fa3114 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -87,6 +87,20 @@ config ARCH_BMIPS select SYSRESET imply CMD_DM +config ARCH_MT7620 + bool "Support MT7620/7688 SoCs" + select DISPLAY_CPUINFO + select DM + select DM_SERIAL + imply DM_SPI + imply DM_SPI_FLASH + select MIPS_TUNE_24KC + select OF_CONTROL + select ROM_EXCEPTION_VECTORS + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SUPPORTS_LITTLE_ENDIAN + config MACH_PIC32 bool "Support Microchip PIC32" select DM @@ -141,6 +155,7 @@ source "board/qemu-mips/Kconfig" source "arch/mips/mach-ath79/Kconfig" source "arch/mips/mach-bmips/Kconfig" source "arch/mips/mach-pic32/Kconfig" +source "arch/mips/mach-mt7620/Kconfig" if MIPS diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 5deec9a202..cc8ea5d7d4 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -15,6 +15,7 @@ machine-$(CONFIG_SOC_AU1X00) += au1x00 machine-$(CONFIG_ARCH_ATH79) += ath79 machine-$(CONFIG_ARCH_BMIPS) += bmips machine-$(CONFIG_MACH_PIC32) += pic32 +machine-$(CONFIG_ARCH_MT7620) += mt7620 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) libs-y += $(machdirs) diff --git a/arch/mips/mach-mt7620/Kconfig b/arch/mips/mach-mt7620/Kconfig new file mode 100644 index 0000000000..396fbd0141 --- /dev/null +++ b/arch/mips/mach-mt7620/Kconfig @@ -0,0 +1,113 @@ +menu "MediaTek MIPS platforms" + depends on ARCH_MT7620 + +config SYS_MALLOC_F_LEN + default 0x1000 + +config SYS_SOC + default "mt7620" if SOC_MT7620 + +choice + prompt "MediaTek MIPS SoC select" + +config SOC_MT7620 + bool "MT7620/8" + select MIPS_L1_CACHE_SHIFT_5 + help + This supports MediaTek MIPS MT7620 family. + +endchoice + +choice + prompt "Board select" + +endchoice + +choice + prompt "Boot mode" + +config BOOT_RAM + bool "RAM boot" + depends on SUPPORTS_BOOT_RAM + help + This builds an image that is linked to a RAM address. It can be used + for booting from CFE via TFTP using an ELF image, but it can also be + booted from RAM by other bootloaders using a BIN image. + +config BOOT_ROM + bool "ROM boot" + depends on SUPPORTS_BOOT_RAM + help + This builds an image that is linked to a ROM address. It can be + used as main bootloader image which is programmed onto the onboard + flash storage (SPI NOR). + +endchoice + +choice + prompt "DDR2 size" + +config ONBOARD_DDR2_SIZE_256MBIT + bool "256MBit (32MByte) total size" + depends on BOOT_ROM + help + Use 256MBit (32MByte) of DDR total size + +config ONBOARD_DDR2_SIZE_512MBIT + bool "512MBit (64MByte) total size" + depends on BOOT_ROM + help + Use 512MBit (64MByte) of DDR total size + +config ONBOARD_DDR2_SIZE_1024MBIT + bool "1024MBit (128MByte) total size" + depends on BOOT_ROM + help + Use 1024MBit (128MByte) of DDR total size + +config ONBOARD_DDR2_SIZE_2048MBIT + bool "2048MBit (256MByte) total size" + depends on BOOT_ROM + help + Use 2048MBit (256MByte) of DDR total size + +endchoice + +choice + prompt "DDR2 chip width" + +config ONBOARD_DDR2_CHIP_WIDTH_8BIT + bool "8bit DDR chip width" + depends on BOOT_ROM + help + Use DDR chips with 8bit width + +config ONBOARD_DDR2_CHIP_WIDTH_16BIT + bool "16bit DDR chip width" + depends on BOOT_ROM + help + Use DDR chips with 16bit width + +endchoice + +choice + prompt "DDR2 bus width" + +config ONBOARD_DDR2_BUS_WIDTH_16BIT + bool "16bit DDR bus width" + depends on BOOT_ROM + help + Use 16bit DDR bus width + +config ONBOARD_DDR2_BUS_WIDTH_32BIT + bool "32bit DDR bus width" + depends on BOOT_ROM + help + Use 32bit DDR bus width + +endchoice + +config SUPPORTS_BOOT_RAM + bool + +endmenu diff --git a/arch/mips/mach-mt7620/Makefile b/arch/mips/mach-mt7620/Makefile new file mode 100644 index 0000000000..1f3e65e8a5 --- /dev/null +++ b/arch/mips/mach-mt7620/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += cpu.o + +ifndef CONFIG_SKIP_LOWLEVEL_INIT +obj-y += ddr_calibrate.o +obj-y += lowlevel_init.o +endif diff --git a/arch/mips/mach-mt7620/cpu.c b/arch/mips/mach-mt7620/cpu.c new file mode 100644 index 0000000000..f21209522b --- /dev/null +++ b/arch/mips/mach-mt7620/cpu.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Stefan Roese <sr(a)denx.de> + */ + +#include <common.h> +#include <dm.h> +#include <ram.h> +#include <asm/io.h> +#include <linux/io.h> +#include <linux/sizes.h> +#include "mt76xx.h" + +#define STR_LEN 6 + +#ifdef CONFIG_BOOT_ROM +int mach_cpu_init(void) +{ + void (*ptr)(void); + + /* + * DDR calibration routine needs to be called very early. This + * function also configures the clock to run at full speed. + */ + ptr = (void *)CKSEG0ADDR(ddr_calibrate); + (*ptr)(); + + return 0; +} +#endif + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_256M); + + return 0; +} + +int print_cpuinfo(void) +{ + static const char * const boot_str[] = { "PLL (3-Byte SPI Addr)", + "PLL (4-Byte SPI Addr)", + "XTAL (3-Byte SPI Addr)", + "XTAL (4-Byte SPI Addr)" }; + const void *blob = gd->fdt_blob; + char buf[STR_LEN + 1]; + fdt_addr_t base; + char *str; + int node; + u32 val; + + /* Get system controller base address */ + node = fdt_node_offset_by_compatible(blob, -1, "ralink,mt7620a-sysc"); + if (node < 0) + return -FDT_ERR_NOTFOUND; + + base = fdtdec_get_addr_size_auto_noparent(blob, node, "reg", + 0, NULL, true); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + str = (char *)base + MT76XX_CHIPID_OFFS; + snprintf(buf, STR_LEN + 1, "%s", str); + val = readl((void *)base + MT76XX_CHIP_REV_ID_OFFS); + printf("CPU: %-*s Rev %ld.%ld - ", STR_LEN, buf, + (val & GENMASK(11, 8)) >> 8, val & GENMASK(3, 0)); + + val = (readl((void *)base + MT76XX_SYSCFG0_OFFS) & GENMASK(3, 1)) >> 1; + printf("Boot from %s\n", boot_str[val]); + + return 0; +} diff --git a/arch/mips/mach-mt7620/ddr_calibrate.c b/arch/mips/mach-mt7620/ddr_calibrate.c new file mode 100644 index 0000000000..623816019b --- /dev/null +++ b/arch/mips/mach-mt7620/ddr_calibrate.c @@ -0,0 +1,307 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Stefan Roese <sr(a)denx.de> + * + * This code is mostly based on the code extracted from this MediaTek + * github repository: + * + * https://github.com/MediaTek-Labs/linkit-smart-uboot.git + * + * I was not able to find a specific license or other developers + * copyrights here, so I can't add them here. + * + * Most functions in this file are copied from the MediaTek U-Boot + * repository. Without any documentation, it was impossible to really + * implement this differently. So its mostly a cleaned-up version of + * the original code, with only support for the MT7628 / MT7688 SoC. + */ + +#include <common.h> +#include <linux/io.h> +#include <asm/cacheops.h> +#include <asm/io.h> +#include "mt76xx.h" + +#define NUM_OF_CACHELINE 64 +#define MIN_START 6 +#define MIN_FINE_START 0xf +#define MAX_START 7 +#define MAX_FINE_START 0x0 + +#define CPU_FRAC_DIV 1 + +#if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT) +#define DRAM_BUTTOM 0x02000000 +#endif +#if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT) +#define DRAM_BUTTOM 0x04000000 +#endif +#if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT) +#define DRAM_BUTTOM 0x08000000 +#endif +#if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT) +#define DRAM_BUTTOM 0x10000000 +#endif + +static inline void cal_memcpy(void *src, void *dst, u32 size) +{ + u8 *psrc = (u8 *)src; + u8 *pdst = (u8 *)dst; + int i; + + for (i = 0; i < size; i++, psrc++, pdst++) + *pdst = *psrc; +} + +static inline void cal_memset(void *src, u8 pat, u32 size) +{ + u8 *psrc = (u8 *)src; + int i; + + for (i = 0; i < size; i++, psrc++) + *psrc = pat; +} + +#define pref_op(hint, addr) \ + __asm__ __volatile__( \ + ".set push\n" \ + ".set noreorder\n" \ + "pref %0, %1\n" \ + ".set pop\n" \ + : \ + : "i" (hint), "R" (*(u8 *)(addr))) + +static inline void cal_patgen(u32 start_addr, u32 size, u32 bias) +{ + u32 *addr = (u32 *)start_addr; + int i; + + for (i = 0; i < size; i++) + addr[i] = start_addr + i + bias; +} + +static inline int test_loop(int k, int dqs, u32 test_dqs, u32 *coarse_dqs, + u32 offs, u32 pat, u32 val) +{ + u32 nc_addr; + u32 *c_addr; + int i; + + for (nc_addr = 0xa0000000; + nc_addr < (0xa0000000 + DRAM_BUTTOM - NUM_OF_CACHELINE * 32); + nc_addr += (DRAM_BUTTOM >> 6) + offs) { + writel(0x00007474, MT76XX_MEMCTRL_BASE + 0x64); + wmb(); /* Make sure store if finished */ + + c_addr = (u32 *)(nc_addr & 0xdfffffff); + cal_memset(((u8 *)c_addr), 0x1F, NUM_OF_CACHELINE * 32); + cal_patgen(nc_addr, NUM_OF_CACHELINE * 8, pat); + + if (dqs > 0) + writel(0x00000074 | + (((k == 1) ? coarse_dqs[dqs] : test_dqs) << 12) | + (((k == 0) ? val : test_dqs) << 8), + MT76XX_MEMCTRL_BASE + 0x64); + else + writel(0x00007400 | + (((k == 1) ? coarse_dqs[dqs] : test_dqs) << 4) | + (((k == 0) ? val : test_dqs) << 0), + MT76XX_MEMCTRL_BASE + 0x64); + wmb(); /* Make sure store if finished */ + + invalidate_dcache_range((u32)c_addr, + (u32)c_addr + + NUM_OF_CACHELINE * 32); + wmb(); /* Make sure store if finished */ + + for (i = 0; i < NUM_OF_CACHELINE * 8; i++) { + if (i % 8 == 0) + pref_op(0, &c_addr[i]); + } + + for (i = 0; i < NUM_OF_CACHELINE * 8; i++) { + if (c_addr[i] != nc_addr + i + pat) + return -1; + } + } + + return 0; +} + +void ddr_calibrate(void) +{ + u32 min_coarse_dqs[2]; + u32 max_coarse_dqs[2]; + u32 min_fine_dqs[2]; + u32 max_fine_dqs[2]; + u32 coarse_dqs[2]; + u32 fine_dqs[2]; + int reg = 0, ddr_cfg2_reg; + int flag; + int i, k; + int dqs = 0; + u32 min_coarse_dqs_bnd, min_fine_dqs_bnd, coarse_dqs_dll, fine_dqs_dll; + u32 val; + u32 fdiv = 0, frac = 0; + + /* Setup clock to run at full speed */ + val = readl(MT76XX_DYN_CFG0_REG); + fdiv = (u32)((val >> 8) & 0x0F); + if (CPU_FRAC_DIV < 1 || CPU_FRAC_DIV > 10) + frac = val & 0x0f; + else + frac = CPU_FRAC_DIV; + + while (frac < fdiv) { + val = readl(MT76XX_DYN_CFG0_REG); + fdiv = (val >> 8) & 0x0f; + fdiv--; + val &= ~(0x0f << 8); + val |= (fdiv << 8); + writel(val, MT76XX_DYN_CFG0_REG); + udelay(500); + val = readl(MT76XX_DYN_CFG0_REG); + fdiv = (val >> 8) & 0x0f; + } + + clrbits_le32(MT76XX_MEMCTRL_BASE + 0x10, BIT(4)); + ddr_cfg2_reg = readl(MT76XX_MEMCTRL_BASE + 0x48); + clrbits_le32(MT76XX_MEMCTRL_BASE + 0x48, (0x3 << 28) | (0x3 << 26)); + + min_coarse_dqs[0] = MIN_START; + min_coarse_dqs[1] = MIN_START; + min_fine_dqs[0] = MIN_FINE_START; + min_fine_dqs[1] = MIN_FINE_START; + max_coarse_dqs[0] = MAX_START; + max_coarse_dqs[1] = MAX_START; + max_fine_dqs[0] = MAX_FINE_START; + max_fine_dqs[1] = MAX_FINE_START; + dqs = 0; + + /* Add by KP, DQS MIN boundary */ + reg = readl(MT76XX_MEMCTRL_BASE + 0x20); + coarse_dqs_dll = (reg & 0xf00) >> 8; + fine_dqs_dll = (reg & 0xf0) >> 4; + if (coarse_dqs_dll <= 8) + min_coarse_dqs_bnd = 8 - coarse_dqs_dll; + else + min_coarse_dqs_bnd = 0; + + if (fine_dqs_dll <= 8) + min_fine_dqs_bnd = 8 - fine_dqs_dll; + else + min_fine_dqs_bnd = 0; + /* DQS MIN boundary */ + +DQS_CAL: + + for (k = 0; k < 2; k++) { + u32 test_dqs; + + if (k == 0) + test_dqs = MAX_START; + else + test_dqs = MAX_FINE_START; + + do { + flag = test_loop(k, dqs, test_dqs, max_coarse_dqs, + 0x400, 0x3, 0xf); + if (flag == -1) + break; + + test_dqs++; + } while (test_dqs <= 0xf); + + if (k == 0) { + max_coarse_dqs[dqs] = test_dqs; + } else { + test_dqs--; + + if (test_dqs == MAX_FINE_START - 1) { + max_coarse_dqs[dqs]--; + max_fine_dqs[dqs] = 0xf; + } else { + max_fine_dqs[dqs] = test_dqs; + } + } + } + + for (k = 0; k < 2; k++) { + u32 test_dqs; + + if (k == 0) + test_dqs = MIN_START; + else + test_dqs = MIN_FINE_START; + + do { + flag = test_loop(k, dqs, test_dqs, min_coarse_dqs, + 0x480, 0x1, 0x0); + if (k == 0) { + if (flag == -1 || + test_dqs == min_coarse_dqs_bnd) + break; + + test_dqs--; + + if (test_dqs < min_coarse_dqs_bnd) + break; + } else { + if (flag == -1) { + test_dqs++; + break; + } else if (test_dqs == min_fine_dqs_bnd) { + break; + } + + test_dqs--; + + if (test_dqs < min_fine_dqs_bnd) + break; + } + } while (test_dqs >= 0); + + if (k == 0) { + min_coarse_dqs[dqs] = test_dqs; + } else { + if (test_dqs == MIN_FINE_START + 1) { + min_coarse_dqs[dqs]++; + min_fine_dqs[dqs] = 0x0; + } else { + min_fine_dqs[dqs] = test_dqs; + } + } + } + + if (dqs == 0) { + dqs = 1; + goto DQS_CAL; + } + + for (i = 0; i < 2; i++) { + u32 temp; + + coarse_dqs[i] = (max_coarse_dqs[i] + min_coarse_dqs[i]) >> 1; + temp = + (((max_coarse_dqs[i] + min_coarse_dqs[i]) % 2) * 4) + + ((max_fine_dqs[i] + min_fine_dqs[i]) >> 1); + if (temp >= 0x10) { + coarse_dqs[i]++; + fine_dqs[i] = (temp - 0x10) + 0x8; + } else { + fine_dqs[i] = temp; + } + } + reg = (coarse_dqs[1] << 12) | (fine_dqs[1] << 8) | + (coarse_dqs[0] << 4) | fine_dqs[0]; + + clrbits_le32(MT76XX_MEMCTRL_BASE + 0x10, BIT(4)); + writel(reg, MT76XX_MEMCTRL_BASE + 0x64); + writel(ddr_cfg2_reg, MT76XX_MEMCTRL_BASE + 0x48); + setbits_le32(MT76XX_MEMCTRL_BASE + 0x10, BIT(4)); + + for (i = 0; i < 2; i++) + debug("[%02X%02X%02X%02X]", min_coarse_dqs[i], + min_fine_dqs[i], max_coarse_dqs[i], max_fine_dqs[i]); + debug("\nDDR Calibration DQS reg = %08X\n", reg); +} diff --git a/arch/mips/mach-mt7620/lowlevel_init.S b/arch/mips/mach-mt7620/lowlevel_init.S new file mode 100644 index 0000000000..92b2fcd2bb --- /dev/null +++ b/arch/mips/mach-mt7620/lowlevel_init.S @@ -0,0 +1,337 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (c) 2018 Stefan Roese <sr(a)denx.de> + * + * This code is mostly based on the code extracted from this MediaTek + * github repository: + * + * https://github.com/MediaTek-Labs/linkit-smart-uboot.git + * + * I was not able to find a specific license or other developers + * copyrights here, so I can't add them here. + */ + +#include <config.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/asm.h> +#include "mt76xx.h" + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +#define DELAY_USEC(us) ((us) / 100) + +#define DDR_CFG1_CHIP_WIDTH_MASK (0x3 << 16) +#define DDR_CFG1_BUS_WIDTH_MASK (0x3 << 12) + +#if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT) +#define DDR_CFG1_SIZE_VAL 0x222e2323 +#define DDR_CFG4_SIZE_VAL 7 +#endif +#if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT) +#define DDR_CFG1_SIZE_VAL 0x22322323 +#define DDR_CFG4_SIZE_VAL 9 +#endif +#if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT) +#define DDR_CFG1_SIZE_VAL 0x22362323 +#define DDR_CFG4_SIZE_VAL 9 +#endif +#if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT) +#define DDR_CFG1_SIZE_VAL 0x223a2323 +#define DDR_CFG4_SIZE_VAL 9 +#endif + +#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_8BIT) +#define DDR_CFG1_CHIP_WIDTH_VAL (0x1 << 16) +#endif +#if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT) +#define DDR_CFG1_CHIP_WIDTH_VAL (0x2 << 16) +#endif + +#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_16BIT) +#define DDR_CFG1_BUS_WIDTH_VAL (0x2 << 12) +#endif +#if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_32BIT) +#define DDR_CFG1_BUS_WIDTH_VAL (0x3 << 12) +#endif + +LEAF(lowlevel_init) + /* polling CPLL is ready */ + li t1, DELAY_USEC(1000000) + la t5, MT76XX_ROM_STATUS_REG +1: + lw t2, 0(t5) + andi t2, t2, 0x1 + bnez t2, CPLL_READY + subu t1, t1, 1 + bgtz t1, 1b + nop + la t0, MT76XX_CLKCFG0_REG + lw t3, 0(t0) + ori t3, t3, 0x1 + sw t3, 0(t0) + j CPLL_DONE + nop +CPLL_READY: + la t0, MT76XX_CLKCFG0_REG + lw t1, 0(t0) + li t2, ~0x0c + and t1, t1, t2 + ori t1, t1, 0xc + sw t1, 0(t0) + la t0, MT76XX_DYN_CFG0_REG + lw t3, 0(t0) + li t5, ~((0x0f << 8) | (0x0f << 0)) + and t3, t3, t5 + li t5, (10 << 8) | (1 << 0) + or t3, t3, t5 + sw t3, 0(t0) + la t0, MT76XX_CLKCFG0_REG + lw t3, 0(t0) + li t4, ~0x0F + and t3, t3, t4 + ori t3, t3, 0xc + sw t3, 0(t0) + lw t3, 0(t0) + ori t3, t3, 0x08 + sw t3, 0(t0) + +CPLL_DONE: + /* + * SDR and DDR initialization: delay 200us + */ + li t0, DELAY_USEC(200 + 40) + li t1, 0x1 +1: + sub t0, t0, t1 + bnez t0, 1b + nop + + /* set DRAM IO PAD for MT7628IC */ + /* DDR LDO Enable */ + li t1, MT76XX_RGCTRL_BASE+0x100 + lw t4, 0(t1) + li t2, BIT(31) + or t4, t4, t2 + sw t4, 0(t1) + li t1, MT76XX_RGCTRL_BASE+0x10c + lw t4, 0(t1) + j LDO_1P8V + nop +LDO_1P8V: + li t2, ~BIT(6) + and t4, t4, t2 + li t1, MT76XX_RGCTRL_BASE+0x10c + sw t4, 0(t1) + j DDRLDO_SOFT_START +LDO_2P5V: + /* suppose external DDR1 LDO 2.5V */ + li t2, BIT(6) + or t4, t4, t2 + li t1, MT76XX_RGCTRL_BASE+0x10c + sw t4, 0(t1) + +DDRLDO_SOFT_START: + li t1, MT76XX_RGCTRL_BASE+0x10c + lw t2, 0(t1) + li t3, BIT(16) + or t2, t2, t3 + sw t2, 0(t1) + li t3, DELAY_USEC(250*50) +LDO_DELAY: + subu t3, t3, 1 + bnez t3, LDO_DELAY + nop + + li t1, MT76XX_RGCTRL_BASE+0x10c + lw t2, 0(t1) + li t3, BIT(18) + or t2, t2, t3 + sw t2, 0(t1) + +SET_RG_BUCK_FPWM: + li t1, MT76XX_RGCTRL_BASE+0x104 + lw t2, 0(t1) + ori t2, t2, BIT(10) + sw t2, 0(t1) + +DDR_PAD_CFG: + /* clean CLK PAD */ + li t1, MT76XX_RGCTRL_BASE+0x704 + lw t2, 0(t1) + li t8, 0xfffff0f0 + and t2, t2, t8 + /* clean CMD PAD */ + li t1, MT76XX_RGCTRL_BASE+0x70c + lw t3, 0(t1) + li t8, 0xfffff0f0 + and t3, t3, t8 + /* clean DQ IPAD */ + li t1, MT76XX_RGCTRL_BASE+0x710 + lw t4, 0(t1) + li t8, 0xfffff8ff + and t4, t4, t8 + /* clean DQ OPAD */ + li t1, MT76XX_RGCTRL_BASE+0x714 + lw t5, 0(t1) + li t8, 0xfffff0f0 + and t5, t5, t8 + /* clean DQS IPAD */ + li t1, MT76XX_RGCTRL_BASE+0x718 + lw t6, 0(t1) + li t8, 0xfffff8ff + and t6, t6, t8 + /* clean DQS OPAD */ + li t1, MT76XX_RGCTRL_BASE+0x71c + lw t7, 0(t1) + li t8, 0xfffff0f0 + and t7, t7, t8 + + li t1, MT76XX_SYSCTL_BASE+0xC + lw t9, 0(t1) + srl t9, t9, 16 + andi t9, t9, 0x1 + bnez t9, MT7628_AN_DDR1_PAD +MT7628_KN_PAD: + li t8, 0x00000303 + or t2, t2, t8 + or t3, t3, t8 + or t5, t5, t8 + or t7, t7, t8 + li t8, 0x00000000 + or t4, t4, t8 + or t6, t6, t8 + j SET_PAD_CFG +MT7628_AN_DDR1_PAD: + li t1, MT76XX_SYSCTL_BASE+0x10 + lw t1, 0(t1) + andi t1, t1, 0x1 + beqz t1, MT7628_AN_DDR2_PAD + li t8, 0x00000c0c + or t2, t2, t8 + li t8, 0x00000202 + or t3, t3, t8 + li t8, 0x00000707 + or t5, t5, t8 + li t8, 0x00000c0c + or t7, t7, t8 + li t8, 0x00000000 + or t4, t4, t8 + or t6, t6, t8 + j SET_PAD_CFG +MT7628_AN_DDR2_PAD: + li t8, 0x00000c0c + or t2, t2, t8 + li t8, 0x00000202 + or t3, t3, t8 + li t8, 0x00000404 + or t5, t5, t8 + li t8, 0x00000c0c + or t7, t7, t8 + li t8, 0x00000000 /* ODT off */ + or t4, t4, t8 + or t6, t6, t8 + +SET_PAD_CFG: + li t1, MT76XX_RGCTRL_BASE+0x704 + sw t2, 0(t1) + li t1, MT76XX_RGCTRL_BASE+0x70c + sw t3, 0(t1) + li t1, MT76XX_RGCTRL_BASE+0x710 + sw t4, 0(t1) + li t1, MT76XX_RGCTRL_BASE+0x714 + sw t5, 0(t1) + li t1, MT76XX_RGCTRL_BASE+0x718 + sw t6, 0(t1) + li t1, MT76XX_RGCTRL_BASE+0x71c + sw t7, 0(t1) + + /* + * DDR initialization: reset pin to 0 + */ + li t1, MT76XX_SYSCTL_BASE + 0x34 + lw t2, 0(t1) + and t2, ~BIT(10) + sw t2, 0(t1) + nop + + /* + * DDR initialization: wait til reg DDR_CFG1 bit 21 equal to 1 (ready) + */ +DDR_READY: + li t1, DDR_CFG1_REG + lw t0, 0(t1) + nop + and t2, t0, BIT(21) + beqz t2, DDR_READY + nop + + /* + * DDR initialization + * + * Only DDR2 supported right now. DDR2 support can be added, once + * boards using it will get added to mainline U-Boot. + */ + li t1, DDR_CFG2_REG + lw t0, 0(t1) + nop + and t0, ~BIT(30) + and t0, ~(7 << 4) + or t0, (4 << 4) + or t0, BIT(30) + or t0, BIT(11) + sw t0, 0(t1) + nop + + li t1, DDR_CFG3_REG + lw t2, 0(t1) + /* Disable ODT; reference board ok, ev board fail */ + and t2, ~BIT(6) + or t2, BIT(2) + li t0, DDR_CFG4_REG + lw t1, 0(t0) + li t2, ~(0x01f | 0x0f0) + and t1, t1, t2 + ori t1, t1, DDR_CFG4_SIZE_VAL + sw t1, 0(t0) + nop + + /* + * DDR initialization: config size and width on reg DDR_CFG1 + */ + li t6, DDR_CFG1_SIZE_VAL + + and t6, ~DDR_CFG1_CHIP_WIDTH_MASK + or t6, DDR_CFG1_CHIP_WIDTH_VAL + + /* CONFIG DDR_CFG1[13:12] about TOTAL WIDTH */ + and t6, ~DDR_CFG1_BUS_WIDTH_MASK + or t6, DDR_CFG1_BUS_WIDTH_VAL + + li t5, DDR_CFG1_REG + sw t6, 0(t5) + nop + + /* + * DDR: enable self auto refresh for power saving + * enable it by default for both RAM and ROM version (for CoC) + */ + li t0, MT76XX_MEMCTRL_BASE + 0x14 + lw t1, 0(t0) + nop + and t1, 0xff000000 + or t1, 0x01 + sw t1, 0(t0) + nop + li t0, MT76XX_MEMCTRL_BASE + 0x10 + lw t1, 0(t0) + nop + or t1, 0x10 + sw t1, 0(t0) + nop + + jr ra + nop + END(lowlevel_init) diff --git a/arch/mips/mach-mt7620/mt76xx.h b/arch/mips/mach-mt7620/mt76xx.h new file mode 100644 index 0000000000..fb3d4582bf --- /dev/null +++ b/arch/mips/mach-mt7620/mt76xx.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Stefan Roese <sr(a)denx.de> + */ + +#ifndef __MT76XX_H +#define __MT76XX_H + +#ifdef __ASSEMBLY__ +#define VOID_PTR +#else +#define VOID_PTR (void *) +#endif + +#define MT76XX_SYSCTL_BASE 0xb0000000 + +#define MT76XX_CHIPID_OFFS 0x00 +#define MT76XX_CHIP_REV_ID_OFFS 0x0c +#define MT76XX_SYSCFG0_OFFS 0x10 + +#define MT76XX_MEMCTRL_BASE (VOID_PTR(MT76XX_SYSCTL_BASE + 0x0300)) +#define MT76XX_RGCTRL_BASE (VOID_PTR(MT76XX_SYSCTL_BASE + 0x1000)) + +#define MT76XX_ROM_STATUS_REG (VOID_PTR(MT76XX_SYSCTL_BASE + 0x0028)) +#define MT76XX_CLKCFG0_REG (VOID_PTR(MT76XX_SYSCTL_BASE + 0x002c)) +#define MT76XX_DYN_CFG0_REG (VOID_PTR(MT76XX_SYSCTL_BASE + 0x0440)) + +#define DDR_CFG1_REG (MT76XX_MEMCTRL_BASE + 0x44) +#define DDR_CFG2_REG (MT76XX_MEMCTRL_BASE + 0x48) +#define DDR_CFG3_REG (MT76XX_MEMCTRL_BASE + 0x4c) +#define DDR_CFG4_REG (MT76XX_MEMCTRL_BASE + 0x50) + +#ifndef __ASSEMBLY__ +/* Prototypes */ +void ddr_calibrate(void); +#endif + +#endif -- 2.18.0

2 10

[U-Boot] [PATCH] i2c: Drop CONFIG_SYS_I2C_MXS
by Tuomas Tynkkynen 16 Aug '18

16 Aug '18

Last user of this driver went away in May 2017, in commit eb5ba3aefdf0f6 ("i2c: Drop use of CONFIG_I2C_HARD") Signed-off-by: Tuomas Tynkkynen <tuomas(a)tuxera.com> --- drivers/i2c/Makefile | 1 - drivers/i2c/mxs_i2c.c | 319 -------------------------------------------------- 2 files changed, 320 deletions(-) delete mode 100644 drivers/i2c/mxs_i2c.c diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index da368cc02a..f2cbe78c53 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -24,7 +24,6 @@ obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o -obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c deleted file mode 100644 index 6766d37547..0000000000 --- a/drivers/i2c/mxs_i2c.c +++ /dev/null @@ -1,319 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Freescale i.MX28 I2C Driver - * - * Copyright (C) 2011 Marek Vasut <marek.vasut(a)gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Partly based on Linux kernel i2c-mxs.c driver: - * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K. - * - * Which was based on a (non-working) driver which was: - * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#include <common.h> -#include <malloc.h> -#include <i2c.h> -#include <linux/errno.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -#define MXS_I2C_MAX_TIMEOUT 1000000 - -static struct mxs_i2c_regs *mxs_i2c_get_base(struct i2c_adapter *adap) -{ - if (adap->hwadapnr == 0) - return (struct mxs_i2c_regs *)MXS_I2C0_BASE; - else - return (struct mxs_i2c_regs *)MXS_I2C1_BASE; -} - -static unsigned int mxs_i2c_get_bus_speed(struct i2c_adapter *adap) -{ - struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); - uint32_t clk = mxc_get_clock(MXC_XTAL_CLK); - uint32_t timing0; - - timing0 = readl(&i2c_regs->hw_i2c_timing0); - /* - * This is a reverse version of the algorithm presented in - * i2c_set_bus_speed(). Please refer there for details. - */ - return clk / ((((timing0 >> 16) - 3) * 2) + 38); -} - -static uint mxs_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) -{ - struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); - /* - * The timing derivation algorithm. There is no documentation for this - * algorithm available, it was derived by using the scope and fiddling - * with constants until the result observed on the scope was good enough - * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be - * possible to assume the algorithm works for other frequencies as well. - * - * Note it was necessary to cap the frequency on both ends as it's not - * possible to configure completely arbitrary frequency for the I2C bus - * clock. - */ - uint32_t clk = mxc_get_clock(MXC_XTAL_CLK); - uint32_t base = ((clk / speed) - 38) / 2; - uint16_t high_count = base + 3; - uint16_t low_count = base - 3; - uint16_t rcv_count = (high_count * 3) / 4; - uint16_t xmit_count = low_count / 4; - - if (speed > 540000) { - printf("MXS I2C: Speed too high (%d Hz)\n", speed); - return -EINVAL; - } - - if (speed < 12000) { - printf("MXS I2C: Speed too low (%d Hz)\n", speed); - return -EINVAL; - } - - writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0); - writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1); - - writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) | - (0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET), - &i2c_regs->hw_i2c_timing2); - - return 0; -} - -static void mxs_i2c_reset(struct i2c_adapter *adap) -{ - struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); - int ret; - int speed = mxs_i2c_get_bus_speed(adap); - - ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg); - if (ret) { - debug("MXS I2C: Block reset timeout\n"); - return; - } - - writel(I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | I2C_CTRL1_NO_SLAVE_ACK_IRQ | - I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ | - I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ, - &i2c_regs->hw_i2c_ctrl1_clr); - - writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set); - - mxs_i2c_set_bus_speed(adap, speed); -} - -static void mxs_i2c_setup_read(struct i2c_adapter *adap, uint8_t chip, int len) -{ - struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); - - writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START | - I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION | - (1 << I2C_QUEUECMD_XFER_COUNT_OFFSET), - &i2c_regs->hw_i2c_queuecmd); - - writel((chip << 1) | 1, &i2c_regs->hw_i2c_data); - - writel(I2C_QUEUECMD_SEND_NAK_ON_LAST | I2C_QUEUECMD_MASTER_MODE | - (len << I2C_QUEUECMD_XFER_COUNT_OFFSET) | - I2C_QUEUECMD_POST_SEND_STOP, &i2c_regs->hw_i2c_queuecmd); - - writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set); -} - -static int mxs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *buf, int blen, int stop) -{ - struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); - uint32_t data, tmp; - int i, remain, off; - int timeout = MXS_I2C_MAX_TIMEOUT; - - if ((alen > 4) || (alen == 0)) { - debug("MXS I2C: Invalid address length\n"); - return -EINVAL; - } - - if (stop) - stop = I2C_QUEUECMD_POST_SEND_STOP; - - writel(I2C_QUEUECMD_PRE_SEND_START | - I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION | - ((blen + alen + 1) << I2C_QUEUECMD_XFER_COUNT_OFFSET) | stop, - &i2c_regs->hw_i2c_queuecmd); - - data = (chip << 1) << 24; - - for (i = 0; i < alen; i++) { - data >>= 8; - data |= ((char *)&addr)[alen - i - 1] << 24; - if ((i & 3) == 2) - writel(data, &i2c_regs->hw_i2c_data); - } - - off = i; - for (; i < off + blen; i++) { - data >>= 8; - data |= buf[i - off] << 24; - if ((i & 3) == 2) - writel(data, &i2c_regs->hw_i2c_data); - } - - remain = 24 - ((i & 3) * 8); - if (remain) - writel(data >> remain, &i2c_regs->hw_i2c_data); - - writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set); - - while (--timeout) { - tmp = readl(&i2c_regs->hw_i2c_queuestat); - if (tmp & I2C_QUEUESTAT_WR_QUEUE_EMPTY) - break; - } - - if (!timeout) { - debug("MXS I2C: Failed transmitting data!\n"); - return -EINVAL; - } - - return 0; -} - -static int mxs_i2c_wait_for_ack(struct i2c_adapter *adap) -{ - struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); - uint32_t tmp; - int timeout = MXS_I2C_MAX_TIMEOUT; - - for (;;) { - tmp = readl(&i2c_regs->hw_i2c_ctrl1); - if (tmp & I2C_CTRL1_NO_SLAVE_ACK_IRQ) { - debug("MXS I2C: No slave ACK\n"); - goto err; - } - - if (tmp & ( - I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ | - I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ)) { - debug("MXS I2C: Error (CTRL1 = %08x)\n", tmp); - goto err; - } - - if (tmp & I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ) - break; - - if (!timeout--) { - debug("MXS I2C: Operation timed out\n"); - goto err; - } - - udelay(1); - } - - return 0; - -err: - mxs_i2c_reset(adap); - return 1; -} - -static int mxs_i2c_if_read(struct i2c_adapter *adap, uint8_t chip, - uint addr, int alen, uint8_t *buffer, - int len) -{ - struct mxs_i2c_regs *i2c_regs = mxs_i2c_get_base(adap); - uint32_t tmp = 0; - int timeout = MXS_I2C_MAX_TIMEOUT; - int ret; - int i; - - ret = mxs_i2c_write(adap, chip, addr, alen, NULL, 0, 0); - if (ret) { - debug("MXS I2C: Failed writing address\n"); - return ret; - } - - ret = mxs_i2c_wait_for_ack(adap); - if (ret) { - debug("MXS I2C: Failed writing address\n"); - return ret; - } - - mxs_i2c_setup_read(adap, chip, len); - ret = mxs_i2c_wait_for_ack(adap); - if (ret) { - debug("MXS I2C: Failed reading address\n"); - return ret; - } - - for (i = 0; i < len; i++) { - if (!(i & 3)) { - while (--timeout) { - tmp = readl(&i2c_regs->hw_i2c_queuestat); - if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY)) - break; - } - - if (!timeout) { - debug("MXS I2C: Failed receiving data!\n"); - return -ETIMEDOUT; - } - - tmp = readl(&i2c_regs->hw_i2c_queuedata); - } - buffer[i] = tmp & 0xff; - tmp >>= 8; - } - - return 0; -} - -static int mxs_i2c_if_write(struct i2c_adapter *adap, uint8_t chip, - uint addr, int alen, uint8_t *buffer, - int len) -{ - int ret; - ret = mxs_i2c_write(adap, chip, addr, alen, buffer, len, 1); - if (ret) { - debug("MXS I2C: Failed writing address\n"); - return ret; - } - - ret = mxs_i2c_wait_for_ack(adap); - if (ret) - debug("MXS I2C: Failed writing address\n"); - - return ret; -} - -static int mxs_i2c_probe(struct i2c_adapter *adap, uint8_t chip) -{ - int ret; - ret = mxs_i2c_write(adap, chip, 0, 1, NULL, 0, 1); - if (!ret) - ret = mxs_i2c_wait_for_ack(adap); - mxs_i2c_reset(adap); - return ret; -} - -static void mxs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) -{ - mxs_i2c_reset(adap); - mxs_i2c_set_bus_speed(adap, speed); - - return; -} - -U_BOOT_I2C_ADAP_COMPLETE(mxs0, mxs_i2c_init, mxs_i2c_probe, - mxs_i2c_if_read, mxs_i2c_if_write, - mxs_i2c_set_bus_speed, - CONFIG_SYS_I2C_SPEED, 0, 0) -U_BOOT_I2C_ADAP_COMPLETE(mxs1, mxs_i2c_init, mxs_i2c_probe, - mxs_i2c_if_read, mxs_i2c_if_write, - mxs_i2c_set_bus_speed, - CONFIG_SYS_I2C_SPEED, 0, 1) -- 2.16.3

1 0

[U-Boot] [PATCH] arm: dts: socfpga: stratix10: Move reset manager node to top
by Ley Foon Tan 15 Aug '18

15 Aug '18

Move reset manager node to top, so reset driver can be load before other drivers. Peripheral drivers have dependency on reset framework to reset the hardware. Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> --- arch/arm/dts/socfpga_stratix10.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index ccd3f32..748a436 100644 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -87,6 +87,14 @@ reg = <0xffd10000 0x1000>; }; + rst: rstmgr@ffd11000 { + #reset-cells = <1>; + compatible = "altr,rst-mgr"; + reg = <0xffd11000 0x1000>; + altr,modrst-offset = <0x20>; + u-boot,dm-pre-reloc; + }; + gmac0: ethernet@ff800000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; reg = <0xff800000 0x2000>; @@ -234,14 +242,6 @@ reg = <0xffe00000 0x100000>; }; - rst: rstmgr@ffd11000 { - #reset-cells = <1>; - compatible = "altr,rst-mgr"; - reg = <0xffd11000 0x1000>; - altr,modrst-offset = <0x20>; - u-boot,dm-pre-reloc; - }; - spi0: spi@ffda4000 { compatible = "snps,dw-apb-ssi"; #address-cells = <1>; -- 2.2.2

3 7

[U-Boot] [PATCH] spi: davinci: Full dm conversion
by Jagan Teki 15 Aug '18

15 Aug '18

davinci_spi now support dt along with platform data, respective boards need to switch into dm for the same. Cc: Adam Ford <aford173(a)gmail.com> Cc: Vitaly Andrianov <vitalya(a)ti.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Peter Howard <phoward(a)gme.net.au> Cc: Tom Rini <trini(a)konsulko.com> Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- drivers/spi/Kconfig | 12 +- drivers/spi/davinci_spi.c | 289 +++++++------------------ include/dm/platform_data/spi_davinci.h | 15 ++ 3 files changed, 97 insertions(+), 219 deletions(-) create mode 100644 include/dm/platform_data/spi_davinci.h diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index d046e919b4..18ebff0231 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -80,6 +80,12 @@ config CADENCE_QSPI used to access the SPI NOR flash on platforms embedding this Cadence IP core. +config DAVINCI_SPI + bool "Davinci & Keystone SPI driver" + depends on ARCH_DAVINCI || ARCH_KEYSTONE + help + Enable the Davinci SPI driver + config DESIGNWARE_SPI bool "Designware SPI driver" help @@ -281,12 +287,6 @@ config FSL_QSPI used to access the SPI NOR flash on platforms embedding this Freescale IP core. -config DAVINCI_SPI - bool "Davinci & Keystone SPI driver" - depends on ARCH_DAVINCI || ARCH_KEYSTONE - help - Enable the Davinci SPI driver - config SH_SPI bool "SuperH SPI driver" help diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index a822858323..5007e6c618 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -14,6 +14,7 @@ #include <asm/io.h> #include <asm/arch/hardware.h> #include <dm.h> +#include <dm/platform_data/spi_davinci.h> /* SPIGCR0 */ #define SPIGCR0_SPIENA_MASK 0x1 @@ -118,9 +119,6 @@ struct davinci_spi_regs { /* davinci spi slave */ struct davinci_spi_slave { -#ifndef CONFIG_DM_SPI - struct spi_slave slave; -#endif struct davinci_spi_regs *regs; unsigned int freq; /* current SPI bus frequency */ unsigned int mode; /* current SPI mode used */ @@ -240,11 +238,43 @@ static int davinci_spi_read_write(struct davinci_spi_slave *ds, unsigned return 0; } +static int davinci_spi_set_speed(struct udevice *bus, uint max_hz) +{ + struct davinci_spi_slave *ds = dev_get_priv(bus); -static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs) + debug("%s speed %u\n", __func__, max_hz); + if (max_hz > CONFIG_SYS_SPI_CLK / 2) + return -EINVAL; + + ds->freq = max_hz; + + return 0; +} + +static int davinci_spi_set_mode(struct udevice *bus, uint mode) +{ + struct davinci_spi_slave *ds = dev_get_priv(bus); + + debug("%s mode %u\n", __func__, mode); + ds->mode = mode; + + return 0; +} + +static int davinci_spi_claim_bus(struct udevice *dev) { + struct dm_spi_slave_platdata *slave_plat = + dev_get_parent_platdata(dev); + struct udevice *bus = dev->parent; + struct davinci_spi_slave *ds = dev_get_priv(bus); unsigned int mode = 0, scalar; + if (slave_plat->cs >= ds->num_cs) { + printf("Invalid SPI chipselect\n"); + return -EINVAL; + } + ds->half_duplex = slave_plat->mode & SPI_PREAMBLE; + /* Enable the SPI hardware */ writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); udelay(1000); @@ -254,7 +284,7 @@ static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs) writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1); /* CS, CLK, SIMO and SOMI are functional pins */ - writel(((1 << cs) | SPIPC0_CLKFUN_MASK | + writel(((1 << slave_plat->cs) | SPIPC0_CLKFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0); /* setup format */ @@ -292,20 +322,32 @@ static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs) return 0; } -static int __davinci_spi_release_bus(struct davinci_spi_slave *ds) +static int davinci_spi_release_bus(struct udevice *dev) { + struct davinci_spi_slave *ds = dev_get_priv(dev->parent); + /* Disable the SPI hardware */ writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); return 0; } -static int __davinci_spi_xfer(struct davinci_spi_slave *ds, - unsigned int bitlen, const void *dout, void *din, - unsigned long flags) +static int davinci_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, + unsigned long flags) { + struct dm_spi_slave_platdata *slave = + dev_get_parent_platdata(dev); + struct udevice *bus = dev->parent; + struct davinci_spi_slave *ds = dev_get_priv(bus); unsigned int len; + if (slave->cs >= ds->num_cs) { + printf("Invalid SPI chipselect\n"); + return -EINVAL; + } + ds->cur_cs = slave->cs; + if (bitlen == 0) /* Finish any previously submitted transfers */ goto out; @@ -339,240 +381,61 @@ out: u8 dummy = 0; davinci_spi_write(ds, 1, &dummy, flags); } - return 0; -} - -#ifndef CONFIG_DM_SPI - -static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave) -{ - return container_of(slave, struct davinci_spi_slave, slave); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - int ret = 0; - - switch (bus) { - case SPI0_BUS: - if (cs < SPI0_NUM_CS) - ret = 1; - break; -#ifdef CONFIG_SYS_SPI1 - case SPI1_BUS: - if (cs < SPI1_NUM_CS) - ret = 1; - break; -#endif -#ifdef CONFIG_SYS_SPI2 - case SPI2_BUS: - if (cs < SPI2_NUM_CS) - ret = 1; - break; -#endif - default: - /* Invalid bus number. Do nothing */ - break; - } - return ret; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - /* do nothing */ -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - /* do nothing */ -} - -void spi_init(void) -{ - /* do nothing */ -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct davinci_spi_slave *ds; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs); - if (!ds) - return NULL; - - switch (bus) { - case SPI0_BUS: - ds->regs = (struct davinci_spi_regs *)SPI0_BASE; - break; -#ifdef CONFIG_SYS_SPI1 - case SPI1_BUS: - ds->regs = (struct davinci_spi_regs *)SPI1_BASE; - break; -#endif -#ifdef CONFIG_SYS_SPI2 - case SPI2_BUS: - ds->regs = (struct davinci_spi_regs *)SPI2_BASE; - break; -#endif - default: /* Invalid bus number */ - return NULL; - } - - ds->freq = max_hz; - ds->mode = mode; - - return &ds->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct davinci_spi_slave *ds = to_davinci_spi(slave); - - free(ds); -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - struct davinci_spi_slave *ds = to_davinci_spi(slave); - - ds->cur_cs = slave->cs; - - return __davinci_spi_xfer(ds, bitlen, dout, din, flags); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct davinci_spi_slave *ds = to_davinci_spi(slave); - -#ifdef CONFIG_SPI_HALF_DUPLEX - ds->half_duplex = true; -#else - ds->half_duplex = false; -#endif - return __davinci_spi_claim_bus(ds, ds->slave.cs); -} - -void spi_release_bus(struct spi_slave *slave) -{ - struct davinci_spi_slave *ds = to_davinci_spi(slave); - - __davinci_spi_release_bus(ds); -} - -#else -static int davinci_spi_set_speed(struct udevice *bus, uint max_hz) -{ - struct davinci_spi_slave *ds = dev_get_priv(bus); - - debug("%s speed %u\n", __func__, max_hz); - if (max_hz > CONFIG_SYS_SPI_CLK / 2) - return -EINVAL; - - ds->freq = max_hz; return 0; } -static int davinci_spi_set_mode(struct udevice *bus, uint mode) -{ - struct davinci_spi_slave *ds = dev_get_priv(bus); - - debug("%s mode %u\n", __func__, mode); - ds->mode = mode; - - return 0; -} - -static int davinci_spi_claim_bus(struct udevice *dev) -{ - struct dm_spi_slave_platdata *slave_plat = - dev_get_parent_platdata(dev); - struct udevice *bus = dev->parent; - struct davinci_spi_slave *ds = dev_get_priv(bus); - - if (slave_plat->cs >= ds->num_cs) { - printf("Invalid SPI chipselect\n"); - return -EINVAL; - } - ds->half_duplex = slave_plat->mode & SPI_PREAMBLE; - - return __davinci_spi_claim_bus(ds, slave_plat->cs); -} - -static int davinci_spi_release_bus(struct udevice *dev) -{ - struct davinci_spi_slave *ds = dev_get_priv(dev->parent); - - return __davinci_spi_release_bus(ds); -} +static const struct dm_spi_ops davinci_spi_ops = { + .claim_bus = davinci_spi_claim_bus, + .release_bus = davinci_spi_release_bus, + .xfer = davinci_spi_xfer, + .set_speed = davinci_spi_set_speed, + .set_mode = davinci_spi_set_mode, +}; -static int davinci_spi_xfer(struct udevice *dev, unsigned int bitlen, - const void *dout, void *din, - unsigned long flags) +static int davinci_spi_probe(struct udevice *bus) { - struct dm_spi_slave_platdata *slave = - dev_get_parent_platdata(dev); - struct udevice *bus = dev->parent; struct davinci_spi_slave *ds = dev_get_priv(bus); + struct davinci_spi_platdata *plat = bus->platdata; + ds->regs = plat->regs; + ds->num_cs = plat->num_cs; - if (slave->cs >= ds->num_cs) { - printf("Invalid SPI chipselect\n"); - return -EINVAL; - } - ds->cur_cs = slave->cs; - - return __davinci_spi_xfer(ds, bitlen, dout, din, flags); -} - -static int davinci_spi_probe(struct udevice *bus) -{ - /* Nothing to do */ return 0; } +#if CONFIG_IS_ENABLED(OF_CONTROL) static int davinci_ofdata_to_platadata(struct udevice *bus) { - struct davinci_spi_slave *ds = dev_get_priv(bus); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(bus); + struct davinci_spi_platdata *plat = bus->platdata; + fdt_addr_t addr; - ds->regs = devfdt_map_physmem(bus, sizeof(struct davinci_spi_regs)); - if (!ds->regs) { - printf("%s: could not map device address\n", __func__); + addr = devfdt_get_addr(bus); + if (addr == FDT_ADDR_T_NONE) return -EINVAL; - } - ds->num_cs = fdtdec_get_int(blob, node, "num-cs", 4); + + plat->regs = (struct davinci_spi_regs *)addr; + plat->num_cs = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), "num-cs", 4); return 0; } -static const struct dm_spi_ops davinci_spi_ops = { - .claim_bus = davinci_spi_claim_bus, - .release_bus = davinci_spi_release_bus, - .xfer = davinci_spi_xfer, - .set_speed = davinci_spi_set_speed, - .set_mode = davinci_spi_set_mode, -}; - static const struct udevice_id davinci_spi_ids[] = { { .compatible = "ti,keystone-spi" }, { .compatible = "ti,dm6441-spi" }, { .compatible = "ti,da830-spi" }, { } }; +#endif U_BOOT_DRIVER(davinci_spi) = { .name = "davinci_spi", .id = UCLASS_SPI, +#if CONFIG_IS_ENABLED(OF_CONTROL) .of_match = davinci_spi_ids, - .ops = &davinci_spi_ops, .ofdata_to_platdata = davinci_ofdata_to_platadata, - .priv_auto_alloc_size = sizeof(struct davinci_spi_slave), + .platdata_auto_alloc_size = sizeof(struct davinci_spi_platdata), +#endif .probe = davinci_spi_probe, + .ops = &davinci_spi_ops, + .priv_auto_alloc_size = sizeof(struct davinci_spi_slave), }; -#endif diff --git a/include/dm/platform_data/spi_davinci.h b/include/dm/platform_data/spi_davinci.h new file mode 100644 index 0000000000..fbc62c262a --- /dev/null +++ b/include/dm/platform_data/spi_davinci.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2018 Jagan Teki <jagan(a)amarulasolutions.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __spi_davinci_h +#define __spi_davinci_h + +struct davinci_spi_platdata { + struct davinci_spi_regs *regs; + u8 num_cs; /* total no. of CS available */ +}; + +#endif /* __spi_davinci_h */ -- 2.18.0.321.gffc6fa0e3

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