August 2018 - U-Boot

[U-Boot] [PATCH u-boot 0/3] amlogic: clean up board files
by Beniamino Galvani 24 Aug '18

24 Aug '18

Hi, this series simplifies Amlogic board files by factorizing common code and removing unneeded parts. Also, it fixes printing the serial number read from efuse. Beniamino Galvani (3): boards: amlogic: remove ethernet gpio reset code from boards boards: amlogic: use common function for environment initialization arm: meson: null-terminate the serial number arch/arm/include/asm/arch-meson/sm.h | 1 + arch/arm/mach-meson/sm.c | 29 +++++++++++++++++++++ board/amlogic/khadas-vim/khadas-vim.c | 25 +----------------- board/amlogic/libretech-cc/libretech-cc.c | 25 +----------------- board/amlogic/nanopi-k2/nanopi-k2.c | 31 +---------------------- board/amlogic/odroid-c2/odroid-c2.c | 31 +---------------------- board/amlogic/p212/p212.c | 25 +----------------- 7 files changed, 35 insertions(+), 132 deletions(-) -- 2.17.1

3 6

[U-Boot] [PATCH 1/7] libavb: Handle wrong hashtree_error_mode in avb_append_options()
by Eugeniu Rosca 24 Aug '18

24 Aug '18

From: Ievgen Maliarenko <ievgen.maliarenko(a)globallogic.com> Exit with AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT when hashtree_error_mode value passed to avb_append_options() is unknown (not from AvbHashtreeErrorMode enum). Otherwise, default value is not handled in the switch(hashtree_error_mode), which causes below compile warning: lib/libavb/avb_cmdline.c: In function ‘avb_append_options’: lib/libavb/avb_cmdline.c:354:13: warning: ‘dm_verity_mode’ may be used uninitialized in this function [-Wmaybe-uninitialized] new_ret = avb_replace( ~~~~~~~~^~~~~~~~~~~~~~ slot_data->cmdline, "$(ANDROID_VERITY_MODE)", dm_verity_mode); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ lib/libavb/avb_cmdline.c:363:8: warning: ‘verity_mode’ may be used uninitialized in this function [-Wmaybe-uninitialized] if (!cmdline_append_option( ^~~~~~~~~~~~~~~~~~~~~~ slot_data, "androidboot.veritymode", verity_mode)) { Signed-off-by: Ievgen Maliarenko <ievgen.maliarenko(a)globallogic.com> Signed-off-by: Eugeniu Rosca <erosca(a)de.adit-jv.com> --- lib/libavb/avb_cmdline.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lib/libavb/avb_cmdline.c b/lib/libavb/avb_cmdline.c index 91a6615c740d..d24669927203 100644 --- a/lib/libavb/avb_cmdline.c +++ b/lib/libavb/avb_cmdline.c @@ -331,6 +331,9 @@ AvbSlotVerifyResult avb_append_options( verity_mode = "logging"; dm_verity_mode = "ignore_corruption"; break; + default: + ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT; + goto out; } new_ret = avb_replace( slot_data->cmdline, "$(ANDROID_VERITY_MODE)", dm_verity_mode); -- 2.18.0

3 23

[U-Boot] [PATCH] usb: ohci: Add OHCI PCI driver
by Marek Vasut 24 Aug '18

24 Aug '18

Add small OHCI PCI driver for USB 1.1 OHCI controllers on PCI bus. This driver matches only on PCI class (serial-ohci) and requires DM-USB ; any sort of deprecated legacy usage is not supported. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> --- drivers/usb/host/Kconfig | 6 +++++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ohci-pci.c | 55 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 62 insertions(+) create mode 100644 drivers/usb/host/ohci-pci.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index b4dd005651..99ecf5bdd7 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -225,6 +225,12 @@ config USB_OHCI_GENERIC ---help--- Enables support for generic OHCI controller. +config USB_OHCI_PCI + bool "Support for PCI-based OHCI USB controller" + depends on DM_USB + help + Enables support for the PCI-based OHCI controller. + endif # USB_OHCI_HCD config USB_UHCI_HCD diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index cb8c315a15..b7c94cadcb 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o obj-$(CONFIG_USB_OHCI_SUNXI) += ohci-sunxi.o obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o +obj-$(CONFIG_USB_OHCI_PCI) += ohci-pci.o # echi obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c new file mode 100644 index 0000000000..dd078f008e --- /dev/null +++ b/drivers/usb/host/ohci-pci.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marek Vasut <marek.vasut(a)gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <pci.h> +#include <usb.h> +#include <asm/io.h> + +#include "ohci.h" + +/* Information about the USB port */ +struct ohci_pci_priv { + ohci_t ohci; +}; + +static int ohci_pci_probe(struct udevice *dev) +{ + struct ohci_regs *regs; + u32 cmd; + + regs = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + if (!regs) + return -ENOMEM; + + /* Enable busmaster */ + dm_pci_read_config32(dev, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER; + dm_pci_write_config32(dev, PCI_COMMAND, cmd); + + debug("OHCI-PCI init regs %p\n", regs); + + return ohci_register(dev, regs); +} + +U_BOOT_DRIVER(ohci_pci) = { + .name = "ohci_pci", + .id = UCLASS_USB, + .probe = ohci_pci_probe, + .remove = ohci_deregister, + .ops = &ohci_usb_ops, + .platdata_auto_alloc_size = sizeof(struct usb_platdata), + .priv_auto_alloc_size = sizeof(struct ohci_pci_priv), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; + +static struct pci_device_id ohci_pci_supported[] = { + { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0) }, + {}, +}; + +U_BOOT_PCI_DEVICE(ohci_pci, ohci_pci_supported); -- 2.16.2

1 0

[U-Boot] [PATCH] pci: rmobile: Filter out device 1 and 2
by Marek Vasut 24 Aug '18

24 Aug '18

Only PCI device 1 and 2 is populated on the R-Car Gen2 internal PCIe controller. Ignore all other devices. This fix prevents a duplication of OHCI controller response on slot 0 and 1. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> --- drivers/pci/pci-rcar-gen2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci-rcar-gen2.c b/drivers/pci/pci-rcar-gen2.c index cbaba1986a..d913d53f3c 100644 --- a/drivers/pci/pci-rcar-gen2.c +++ b/drivers/pci/pci-rcar-gen2.c @@ -97,7 +97,7 @@ static int rcar_gen2_pci_addr_valid(pci_dev_t d, uint offset) /* Only one EHCI/OHCI device built-in */ slot = PCI_DEV(d); - if (slot > 2) + if (slot != 1 && slot != 2) return -EINVAL; /* bridge logic only has registers to 0x40 */ -- 2.16.2

1 0

[U-Boot] [PATCH v1] arm: at91: wdt: Convert watchdog driver to dm
by Prasanthi Chellakumar 24 Aug '18

24 Aug '18

Convert the Watchdog driver for AT91SAM9x processors to support the driver model and device tree Signed-off-by: Prasanthi Chellakumar <prasanthi.chellakumar(a)microchip.com> --- arch/arm/mach-at91/include/mach/at91_wdt.h | 12 +++- drivers/watchdog/Kconfig | 7 ++ drivers/watchdog/Makefile | 2 +- drivers/watchdog/at91sam9_wdt.c | 105 +++++++++++++++++++++-------- 4 files changed, 95 insertions(+), 31 deletions(-) diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h index 99b0cc8..df9f131 100644 --- a/arch/arm/mach-at91/include/mach/at91_wdt.h +++ b/arch/arm/mach-at91/include/mach/at91_wdt.h @@ -4,7 +4,7 @@ * * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> * Copyright (C) 2007 Andrew Victor - * Copyright (C) 2007 Atmel Corporation. + * Copyright (C) 2018 Microchip Technology Inc. * * Watchdog Timer (WDT) - System peripherals regsters. * Based on AT91SAM9261 datasheet revision D. @@ -27,15 +27,21 @@ typedef struct at91_wdt { #endif +/* Watchdog Control Register */ +#define AT91_WDT_CR 0x00 #define AT91_WDT_CR_WDRSTT 1 #define AT91_WDT_CR_KEY 0xa5000000 /* KEY Password */ -#define AT91_WDT_MR_WDV(x) (x & 0xfff) +/* Watchdog Mode Register*/ +#define AT91_WDT_MR 0X04 +#define AT91_WDT_MR_WDV (0xfff << 0) +#define AT91_WDT_MR_SET_WDV(x) ((x) & AT91_WDT_MR_WDV) #define AT91_WDT_MR_WDFIEN 0x00001000 #define AT91_WDT_MR_WDRSTEN 0x00002000 #define AT91_WDT_MR_WDRPROC 0x00004000 #define AT91_WDT_MR_WDDIS 0x00008000 -#define AT91_WDT_MR_WDD(x) ((x & 0xfff) << 16) +#define AT91_WDT_MR_WDD (0xfff << 16) +#define AT91_WDT_MR_SET_WDD(x) (((x) << 16) & AT91_WDT_MR_WDD) #define AT91_WDT_MR_WDDBGHLT 0x10000000 #define AT91_WDT_MR_WDIDLEHLT 0x20000000 diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index d545b3e..001a8d0 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -111,4 +111,11 @@ config XILINX_TB_WATCHDOG Select this to enable Xilinx Axi watchdog timer, which can be found on some Xilinx Microblaze Platforms. +config WDT_AT91 + bool "AT91 watchdog timer support" + depends on WDT + help + Select this to enable Microchip watchdog timer, which can be found on + some AT91 devices. + endmenu diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index f405f51..3f4fd59 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -3,7 +3,7 @@ # (C) Copyright 2008 # Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. -obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o +obj-$(CONFIG_WDT_AT91) += at91sam9_wdt.o obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610)) obj-y += imx_watchdog.o diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index fca2849..d3f8fa6 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -2,7 +2,7 @@ /* * [origin: Linux kernel drivers/watchdog/at91sam9_wdt.c] * - * Watchdog driver for Atmel AT91SAM9x processors. + * Watchdog driver for AT91SAM9x processors. * * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> * Copyright (C) 2008 Renaud CERRATO r.cerrato(a)til-technologies.fr @@ -14,38 +14,47 @@ * write to this register. Inform Linux to it too */ -#include <common.h> -#include <watchdog.h> -#include <asm/arch/hardware.h> #include <asm/io.h> #include <asm/arch/at91_wdt.h> +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <wdt.h> + +DECLARE_GLOBAL_DATA_PTR; /* * AT91SAM9 watchdog runs a 12bit counter @ 256Hz, * use this to convert a watchdog - * value from/to milliseconds. + * value from seconds. */ -#define ms_to_ticks(t) (((t << 8) / 1000) - 1) -#define ticks_to_ms(t) (((t + 1) * 1000) >> 8) +#define WDT_SEC2TICKS(s) (((s) << 8) - 1) /* Hardware timeout in seconds */ -#if !defined(CONFIG_AT91_HW_WDT_TIMEOUT) -#define WDT_HW_TIMEOUT 2 -#else -#define WDT_HW_TIMEOUT CONFIG_AT91_HW_WDT_TIMEOUT -#endif +#define WDT_MAX_TIMEOUT 16 +#define WDT_MIN_TIMEOUT 0 + +struct at91_wdt_priv { + void __iomem *regs; + u32 regval; +}; /* * Set the watchdog time interval in 1/256Hz (write-once) * Counter is 12 bit. */ -static int at91_wdt_settimeout(unsigned int timeout) +static int at91_wdt_start(struct udevice *dev, u64 timeout_s, ulong flags) { - unsigned int reg; - at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT; + struct at91_wdt_priv *priv = dev_get_priv(dev); + u32 timeout = WDT_SEC2TICKS(timeout_s); + + if (timeout_s > WDT_MAX_TIMEOUT || timeout_s < WDT_MIN_TIMEOUT) { + printf("Invalid watchdog counter value\n"); + return -1; + } /* Check if disabled */ - if (readl(&wd->mr) & AT91_WDT_MR_WDDIS) { + if (readl(priv->regs + AT91_WDT_MR) & AT91_WDT_MR_WDDIS) { printf("sorry, watchdog is disabled\n"); return -1; } @@ -56,25 +65,67 @@ static int at91_wdt_settimeout(unsigned int timeout) * Since WDV is a 12-bit counter, the maximum period is * 4096 / 256 = 16 seconds. */ + priv->regval &= ~AT91_WDT_MR_WDV; + priv->regval &= ~AT91_WDT_MR_WDD; + priv->regval |= AT91_WDT_MR_SET_WDV(timeout); + priv->regval |= AT91_WDT_MR_SET_WDD(timeout); + priv->regval |= AT91_WDT_MR_WDDBGHLT; + priv->regval |= AT91_WDT_MR_WDIDLEHLT; + priv->regval |= AT91_WDT_MR_WDRSTEN; - reg = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */ - | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */ - | AT91_WDT_MR_WDD(0xfff) /* restart at any time */ - | AT91_WDT_MR_WDV(timeout); /* timer value */ + writel(priv->regval, priv->regs + AT91_WDT_MR); - writel(reg, &wd->mr); + return 0; +} + +static int at91_wdt_stop(struct udevice *dev) +{ + struct at91_wdt_priv *priv = dev_get_priv(dev); + + /* Disable Watchdog Timer */ + priv->regval |= AT91_WDT_MR_WDDIS; + writel(priv->regval, priv->regs + AT91_WDT_MR); return 0; } -void hw_watchdog_reset(void) +static int at91_wdt_reset(struct udevice *dev) { - at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT; - writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, &wd->cr); + struct at91_wdt_priv *priv = dev_get_priv(dev); + + writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, priv->regs + AT91_WDT_CR); + + return 0; } -void hw_watchdog_init(void) +static const struct wdt_ops at91_wdt_ops = { + .start = at91_wdt_start, + .stop = at91_wdt_stop, + .reset = at91_wdt_reset, +}; + +static const struct udevice_id at91_wdt_ids[] = { + { .compatible = "atmel,at91sam9260-wdt" }, + {} +}; + +static int at91_wdt_probe(struct udevice *dev) { - /* 16 seconds timer, resets enabled */ - at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000)); + struct at91_wdt_priv *priv = dev_get_priv(dev); + + priv->regs = dev_remap_addr(dev); + if (!priv->regs) + return -EINVAL; + debug("%s: Probing wdt%u\n", __func__, dev->seq); + + return 0; } + +U_BOOT_DRIVER(at91_wdt) = { + .name = "at91_wdt", + .id = UCLASS_WDT, + .of_match = at91_wdt_ids, + .priv_auto_alloc_size = sizeof(struct at91_wdt_priv), + .ops = &at91_wdt_ops, + .probe = at91_wdt_probe, +}; -- 2.7.4

3 2

[U-Boot] [PATCH] MMC: davinici_mmc: Enable CD and WP with DM and OF_CONTROL
by Adam Ford 24 Aug '18

24 Aug '18

When used with a device tree, this will extract the card detect and write protect pins from the device tree and configure them accordingly. This assumes the GPIO_ACTIVE_LOW/HIGH is supported byt da8xx_gpio. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c index db950ea5ec..01d60f394f 100644 --- a/drivers/mmc/davinci_mmc.c +++ b/drivers/mmc/davinci_mmc.c @@ -15,6 +15,7 @@ #include <malloc.h> #include <asm/io.h> #include <asm/arch/sdmmc_defs.h> +#include <asm-generic/gpio.h> #define DAVINCI_MAX_BLOCKS (32) #define WATCHDOG_COUNT (100000) @@ -35,6 +36,8 @@ struct davinci_mmc_priv { struct davinci_mmc_regs *reg_base; /* Register base address */ uint input_clk; /* Input clock to MMC controller */ uint version; /* MMC Controller version */ + struct gpio_desc cd_gpio; /* Card Detect GPIO */ + struct gpio_desc wp_gpio; /* Write Protect GPIO */ }; struct davinci_mmc_plat @@ -425,9 +428,38 @@ static const struct mmc_ops dmmc_ops = { .init = dmmc_init, }; #else + +static int davinci_mmc_getcd(struct udevice *dev) +{ + struct davinci_mmc_priv *priv = dev_get_priv(dev); + int value; + + value = dm_gpio_get_value(&priv->cd_gpio); + /* if no CD return as 1 */ + if (value < 0) + return 1; + + return value; +} + +static int davinci_mmc_getwp(struct udevice *dev) +{ + struct davinci_mmc_priv *priv = dev_get_priv(dev); + int value; + + value = dm_gpio_get_value(&priv->wp_gpio); + /* if no WP return as 0 */ + if (value < 0) + return 0; + + return value; +} + static const struct dm_mmc_ops davinci_mmc_ops = { .send_cmd = davinci_mmc_send_cmd, .set_ios = davinci_mmc_set_ios, + .get_cd = davinci_mmc_getcd, + .get_wp = davinci_mmc_getwp, }; #endif @@ -475,6 +507,12 @@ static int davinci_mmc_probe(struct udevice *dev) priv->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev); priv->input_clk = clk_get(DAVINCI_MMCSD_CLKID); +#if CONFIG_IS_ENABLED(DM_GPIO) + /* These GPIOs are optional */ + gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); + gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); +#endif + upriv->mmc = &plat->mmc; return davinci_dm_mmc_init(dev); -- 2.17.1

2 2

[U-Boot] [PATCH v3.3 14/58] musb-new: sunxi: Use CLK and RESET support
by Jagan Teki 24 Aug '18

24 Aug '18

Now clock and reset drivers are available for respective SoC's so use clk and reset ops on musb driver. Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- Changes for v3.3: - drop flags, use has_reset Changes for v3.2: - add has_reset bool in existing driver data Changes for v3.1: - droped unused variables - add flags for checking reset require or not - handle clk and reset errors properly drivers/usb/musb-new/sunxi.c | 94 ++++++++++++++++++++++++------------ 1 file changed, 62 insertions(+), 32 deletions(-) diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index 9f71b84fd1..7126152a21 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -16,9 +16,11 @@ * This file is part of the Inventra Controller Driver for Linux. */ #include <common.h> +#include <clk.h> #include <dm.h> #include <generic-phy.h> #include <phy-sun4i-usb.h> +#include <reset.h> #include <asm/arch/cpu.h> #include <asm/arch/clock.h> #include <asm/arch/gpio.h> @@ -78,16 +80,16 @@ struct sunxi_musb_config { struct musb_hdrc_config *config; - u8 rst_bit; - u8 clkgate_bit; + bool has_reset; }; struct sunxi_glue { struct musb_host_data mdata; - struct sunxi_ccm_reg *ccm; struct sunxi_musb_config *cfg; struct device dev; struct phy phy; + struct clk clk; + struct reset_ctl rst; }; #define to_sunxi_glue(d) container_of(d, struct sunxi_glue, dev) @@ -291,25 +293,28 @@ static int sunxi_musb_init(struct musb *musb) pr_debug("%s():\n", __func__); + ret = clk_enable(&glue->clk); + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + + if (glue->cfg->has_reset) { + ret = reset_deassert(&glue->rst); + if (ret) { + dev_err(dev, "failed to deassert reset\n"); + goto err_clk; + } + } + ret = generic_phy_init(&glue->phy); if (ret) { pr_err("failed to init USB PHY\n"); - return ret; + goto err_rst; } musb->isr = sunxi_musb_interrupt; - setbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0)); - if (glue->cfg->clkgate_bit) - setbits_le32(&glue->ccm->ahb_gate0, - BIT(glue->cfg->clkgate_bit)); -#ifdef CONFIG_SUNXI_GEN_SUN6I - setbits_le32(&glue->ccm->ahb_reset0_cfg, BIT(AHB_GATE_OFFSET_USB0)); - if (glue->cfg->rst_bit) - setbits_le32(&glue->ccm->ahb_reset0_cfg, - BIT(glue->cfg->rst_bit)); -#endif - USBC_ConfigFIFO_Base(); USBC_EnableDpDmPullUp(musb->mregs); USBC_EnableIdPullUp(musb->mregs); @@ -324,6 +329,13 @@ static int sunxi_musb_init(struct musb *musb) USBC_ForceVbusValidToHigh(musb->mregs); return 0; + +err_rst: + if (glue->cfg->has_reset) + reset_assert(&glue->rst); +err_clk: + clk_disable(&glue->clk); + return ret; } static int sunxi_musb_exit(struct musb *musb) @@ -339,16 +351,19 @@ static int sunxi_musb_exit(struct musb *musb) } } -#ifdef CONFIG_SUNXI_GEN_SUN6I - clrbits_le32(&glue->ccm->ahb_reset0_cfg, BIT(AHB_GATE_OFFSET_USB0)); - if (glue->cfg->rst_bit) - clrbits_le32(&glue->ccm->ahb_reset0_cfg, - BIT(glue->cfg->rst_bit)); -#endif - clrbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0)); - if (glue->cfg->clkgate_bit) - clrbits_le32(&glue->ccm->ahb_gate0, - BIT(glue->cfg->clkgate_bit)); + if (glue->cfg->has_reset) { + ret = reset_assert(&glue->rst); + if (ret) { + dev_err(dev, "failed to deassert reset\n"); + return ret; + } + } + + ret = clk_disable(&glue->clk); + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } return 0; } @@ -442,9 +457,19 @@ static int musb_usb_probe(struct udevice *dev) if (!glue->cfg) return -EINVAL; - glue->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - if (IS_ERR(glue->ccm)) - return PTR_ERR(glue->ccm); + ret = clk_get_by_index(dev, 0, &glue->clk); + if (ret) { + dev_err(dev, "failed to get clock\n"); + return ret; + } + + if (glue->cfg->has_reset) { + ret = reset_get_by_index(dev, 0, &glue->rst); + if (ret) { + dev_err(dev, "failed to get reset\n"); + return ret; + } + } ret = generic_phy_get_by_name(dev, "usb", &glue->phy); if (ret) { @@ -495,21 +520,26 @@ static int musb_usb_remove(struct udevice *dev) static const struct sunxi_musb_config sun4i_a10_cfg = { .config = &musb_config, + .has_reset = false, +}; + +static const struct sunxi_musb_config sun6i_a31_cfg = { + .config = &musb_config, + .has_reset = true, }; static const struct sunxi_musb_config sun8i_h3_cfg = { .config = &musb_config_h3, - .rst_bit = 23, - .clkgate_bit = 23, + .has_reset = true, }; static const struct udevice_id sunxi_musb_ids[] = { { .compatible = "allwinner,sun4i-a10-musb", .data = (ulong)&sun4i_a10_cfg }, { .compatible = "allwinner,sun6i-a31-musb", - .data = (ulong)&sun4i_a10_cfg }, + .data = (ulong)&sun6i_a31_cfg }, { .compatible = "allwinner,sun8i-a33-musb", - .data = (ulong)&sun4i_a10_cfg }, + .data = (ulong)&sun6i_a31_cfg }, { .compatible = "allwinner,sun8i-h3-musb", .data = (ulong)&sun8i_h3_cfg }, { } -- 2.18.0.321.gffc6fa0e3

2 1

[U-Boot] Unaligned memory accesses exception
by Fernando AE 24 Aug '18

24 Aug '18

Hello all, I'm bringing up U-Boot for an iMX6UL board, and I've encountered unaligned memory accesses exceptions while I was trying to test the ETH commands (e.g., 'ping'). After investigation, I found out that the iMX6UL processor traps unaligned memory accesses by default. As a workaround, I disabled theses checks, hoping for negligible performance loss. I'm wondering if it is a bad idea to disable unaligned memory accesses during the U-Boot execution, regarding performance issues or other drawbacks at the kernel level. Thanks for your suggestions. Best regards, Fernando A. E.

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[U-Boot] [PATCH 0/6] [3/3] Initial support Texas Instrument's AM654 Platform
by Lokesh Vutla 24 Aug '18

24 Aug '18

Continue from PART 2/3... This series adds arm64 support for AM654 EVM. Patch 2/6 describes the boot flow in detail. I would recommend to go through the patch in order to understand the entire boot flow. Right now only arm64 support is added. r5 support will be posted later once loading of system firmware is ported to generic filesystem loader. Andreas Dannenberg (1): include: am654_evm: Establish initial environment for SD card boot Lokesh Vutla (5): board: ti: am654: a53: Add initial support for am654 board: ti: am65x: Add README arm64: dts: k3: Add Support for AM654 SoC arm64: dts: k3: Add u-boot specific nodes configs: am65x_evm_a53: Add initial support arch/arm/dts/Makefile | 2 + arch/arm/dts/k3-am65-main.dtsi | 31 +++ arch/arm/dts/k3-am65.dtsi | 87 ++++++++ arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 203 +++++++++++++++++++ arch/arm/dts/k3-am654-base-board.dts | 36 ++++ arch/arm/dts/k3-am654.dtsi | 115 +++++++++++ arch/arm/mach-k3/Kconfig | 1 + board/ti/am65x/Kconfig | 30 +++ board/ti/am65x/MAINTAINERS | 6 + board/ti/am65x/Makefile | 8 + board/ti/am65x/README | 134 ++++++++++++ board/ti/am65x/evm.c | 68 +++++++ configs/am65x_evm_a53_defconfig | 71 +++++++ include/configs/am65x_evm.h | 71 +++++++ include/dt-bindings/pinctrl/k3-am65.h | 49 +++++ 15 files changed, 912 insertions(+) create mode 100644 arch/arm/dts/k3-am65-main.dtsi create mode 100644 arch/arm/dts/k3-am65.dtsi create mode 100644 arch/arm/dts/k3-am654-base-board-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am654-base-board.dts create mode 100644 arch/arm/dts/k3-am654.dtsi create mode 100644 board/ti/am65x/Kconfig create mode 100644 board/ti/am65x/MAINTAINERS create mode 100644 board/ti/am65x/Makefile create mode 100644 board/ti/am65x/README create mode 100644 board/ti/am65x/evm.c create mode 100644 configs/am65x_evm_a53_defconfig create mode 100644 include/configs/am65x_evm.h create mode 100644 include/dt-bindings/pinctrl/k3-am65.h -- 2.18.0

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[U-Boot] Please pull u-boot-fsl-qoriq master
by York Sun 24 Aug '18

24 Aug '18

Tom, The following changes since commit b71d9e8b3805305ea4116733f515061710ad7081: Merge branch 'master' of git://git.denx.de/u-boot-sunxi (2018-08-20 13:41:56 -0400) are available in the git repository at: git://git.denx.de/u-boot-fsl-qoriq.git for you to fetch changes up to 4b5892c4808ec162253b4b8173b6995e5dac4246: armv8: layerscape: Build u-boot-with-spl.bin for selected boards (2018-08-23 08:17:35 -0700) Travis build log https://travis-ci.org/yorksun/u-boot/builds/419707822 ---------------------------------------------------------------- Jagdish Gediya (1): armv8: layerscape: Build u-boot-with-spl.bin for selected boards York Sun (1): armv8: fsl-layerscape: Update README.falcon for compression arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon | 2 +- include/configs/ls1088a_common.h | 1 + include/configs/ls2080a_common.h | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) Thanks. York

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