August 2018 - U-Boot

[U-Boot] [PATCH v2] drivers: esdhc: add support for ColdFire mcf5441x family
by Angelo Dureghello 26 Aug '18

26 Aug '18

This patch has been tested on the mcf54415-based stmark2 board. The eSDHC driver works reliably using DMA mode. Signed-off-by: Angelo Dureghello <angelo(a)sysam.it> --- Changes in v2: - add be to le 32-bit byte swap for ColdFire, - remove HS from host capabilities for ColdFire. --- drivers/mmc/fsl_esdhc.c | 43 ++++++++++++++++++++++++++++++++++++++++- include/fsl_esdhc.h | 1 + 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 4528345c67..315c24527d 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -382,6 +382,25 @@ static void check_and_invalidate_dcache_range invalidate_dcache_range(start, end); } +#ifdef CONFIG_MCF5441x +/* + * Swaps 32-bit words to little-endian byte order. + */ +static inline void sd_swap_dma_buff(struct mmc_data *data) +{ + int i, size = data->blocksize >> 2; + u32 *buffer = (u32 *)data->dest; + u32 sw; + + while (data->blocks--) { + for (i = 0; i < size; i++) { + sw = __sw32(*buffer); + *buffer++ = sw; + } + } +} +#endif + /* * Sends a command out on the bus. Takes the mmc pointer, * a command pointer, and an optional data pointer. @@ -538,8 +557,12 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, * cache-fill during the DMA operations such as the * speculative pre-fetching etc. */ - if (data->flags & MMC_DATA_READ) + if (data->flags & MMC_DATA_READ) { check_and_invalidate_dcache_range(cmd, data); +#ifdef CONFIG_MCF5441x + sd_swap_dma_buff(data); +#endif + } #endif } @@ -987,8 +1010,12 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) /* Disable the BRR and BWR bits in IRQSTAT */ esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); +#ifdef CONFIG_MCF5441x + esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD); +#else /* Put the PROCTL reg back to the default */ esdhc_write32(&regs->proctl, PROCTL_INIT); +#endif /* Set timout to the maximum value */ esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); @@ -1096,6 +1123,11 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, if (ret) return ret; +#ifdef CONFIG_MCF5441x + /* ColdFire, using SDHC_DATA[3] for card detection */ + esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD); +#endif + #ifndef CONFIG_FSL_USDHC esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN | SYSCTL_IPGEN | SYSCTL_CKEN); @@ -1120,6 +1152,15 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, voltage_caps = 0; caps = esdhc_read32(&regs->hostcapblt); +#ifdef CONFIG_MCF5441x + /* + * MCF5441x RM declares in more points that sdhc clock speed must + * never exceed 25 Mhz. From this, the HS bit needs to be disabled + * from host capabilities. + */ + caps &= ~ESDHC_HOSTCAPBLT_HSS; +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS | ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30); diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index acd8dd06f8..8dbd5249a7 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -106,6 +106,7 @@ #define PROCTL_INIT 0x00000020 #define PROCTL_DTW_4 0x00000002 #define PROCTL_DTW_8 0x00000004 +#define PROCTL_D3CD 0x00000008 #define CMDARG 0x0002e008 -- 2.18.0

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[U-Boot] [PATCH 1/1] efi_selftest: memory leak testing manage protocols
by Heinrich Schuchardt 26 Aug '18

26 Aug '18

Remove memory leak in efi_selftest_manageprotocols.c. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- .../efi_selftest_manageprotocols.c | 21 +++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/lib/efi_selftest/efi_selftest_manageprotocols.c b/lib/efi_selftest/efi_selftest_manageprotocols.c index 44b8da3ba5..b09e4cdcfa 100644 --- a/lib/efi_selftest/efi_selftest_manageprotocols.c +++ b/lib/efi_selftest/efi_selftest_manageprotocols.c @@ -179,7 +179,12 @@ static int execute(void) efi_st_error("LocateHandleBuffer failed to locate new handle\n"); return EFI_ST_FAILURE; } - boottime->set_mem(buffer, sizeof(efi_handle_t) * buffer_size, 0); + /* Release buffer */ + ret = boottime->free_pool(buffer); + if (ret != EFI_SUCCESS) { + efi_st_error("FreePool failed\n"); + return EFI_ST_FAILURE; + } /* * Test error handling in UninstallMultipleProtocols @@ -221,6 +226,7 @@ static int execute(void) efi_st_error("LocateHandleBuffer failed to locate new handle\n"); return EFI_ST_FAILURE; } + /* Clear the buffer, we are reusing it it the next step. */ boottime->set_mem(buffer, sizeof(efi_handle_t) * buffer_size, 0); /* @@ -248,7 +254,12 @@ static int execute(void) efi_st_error("LocateHandle failed to locate new handles\n"); return EFI_ST_FAILURE; } - boottime->set_mem(buffer, sizeof(efi_handle_t) * buffer_size, 0); + /* Release buffer */ + ret = boottime->free_pool(buffer); + if (ret != EFI_SUCCESS) { + efi_st_error("FreePool failed\n"); + return EFI_ST_FAILURE; + } /* * Test LocateProtocol @@ -319,6 +330,12 @@ static int execute(void) efi_st_error("Failed to get protocols per handle\n"); return EFI_ST_FAILURE; } + /* Release buffer */ + ret = boottime->free_pool(prot_buffer); + if (ret != EFI_SUCCESS) { + efi_st_error("FreePool failed\n"); + return EFI_ST_FAILURE; + } /* * Uninstall remaining protocols -- 2.18.0

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[U-Boot] [PATCH] drivers: esdhc: add support for coldfire mcf5441x family
by Angelo Dureghello 26 Aug '18

26 Aug '18

Signed-off-by: Angelo Dureghello <angelo(a)sysam.it> --- drivers/mmc/fsl_esdhc.c | 21 ++++++++++++++++----- include/fsl_esdhc.h | 1 + 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 4528345c67..e376926c53 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -26,6 +26,12 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_MCF5441x +#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO +#define CONFIG_SYS_FSL_ESDHC_USE_PIO +#endif +#endif + #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ IRQSTATEN_CINT | \ IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ @@ -399,7 +405,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) return 0; #endif - esdhc_write32(&regs->irqstat, -1); sync(); @@ -987,8 +992,12 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) /* Disable the BRR and BWR bits in IRQSTAT */ esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); +#ifdef CONFIG_MCF5441x + esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD); +#else /* Put the PROCTL reg back to the default */ esdhc_write32(&regs->proctl, PROCTL_INIT); +#endif /* Set timout to the maximum value */ esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); @@ -1014,7 +1023,6 @@ static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) return dm_gpio_get_value(&priv->cd_gpio); #endif #endif - while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout) udelay(1000); @@ -1112,11 +1120,16 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT); writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten); + +#ifdef CONFIG_MCF5441x + /* ColdFire, using SDHC_DATA[3] for card detection */ + esdhc_write32(&regs->proctl, esdhc_read32(&regs->proctl) | PROCTL_D3CD); +#endif + cfg = &plat->cfg; #ifndef CONFIG_DM_MMC memset(cfg, '\0', sizeof(*cfg)); #endif - voltage_caps = 0; caps = esdhc_read32(&regs->hostcapblt); @@ -1129,7 +1142,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 caps = caps | ESDHC_HOSTCAPBLT_VS33; #endif - if (caps & ESDHC_HOSTCAPBLT_VS18) voltage_caps |= MMC_VDD_165_195; if (caps & ESDHC_HOSTCAPBLT_VS30) @@ -1150,7 +1162,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, printf("voltage not supported by controller\n"); return -1; } - if (priv->bus_width == 8) cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; else if (priv->bus_width == 4) diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index acd8dd06f8..8dbd5249a7 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -106,6 +106,7 @@ #define PROCTL_INIT 0x00000020 #define PROCTL_DTW_4 0x00000002 #define PROCTL_DTW_8 0x00000004 +#define PROCTL_D3CD 0x00000008 #define CMDARG 0x0002e008 -- 2.18.0

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[U-Boot] [PATCH v2 0/7] ARM: dts: sunxi: Update dts(i) files from Linux-v4.18-rc3
by Jagan Teki 26 Aug '18

26 Aug '18

This series is trying to update SoC dtsi and board dts files for Allwinner sun4i, 5i, 6i, 8i-a23/a33/a83t, r40 SoC's from Linux-4.18-rc3 These update is useful for supporting features CLK, RESET, DM_MMC etc Since H3/H5/A64 is already updated with Linux-4.18-rc3, this series use same version to maintain proper compatibility for all SoC platforms syncs. Changes for v2: - Update commit subject line with Linux-v4.18-rc3 thanks, Jagan. Jagan Teki (7): ARM: dts: sun4i: Update A10 dts(i) files from Linux-v4.18-rc3 ARM: dts: sun5i: Update A10s/A13/gr8/r8 dts(i) files from Linux-v4.18-rc3 ARM: dts: sun6i: Update A31/A31s dts(i) files from Linux-v4.18-rc3 ARM: dts: sun7i: Update A20 dts(i) files from Linux-v4.18-rc3 ARM: dts: sun8i: Update A23/A33/r16 dts(i) files from Linux-v4.18-rc3 ARM: dts: sun8i: Update A83T dts(i) files from Linux-v4.18-rc3 ARM: dts: sun8i: Update R40/V40 dts(i) files from Linux-v4.18-rc3 arch/arm/dts/axp209.dtsi | 17 +- arch/arm/dts/axp81x.dtsi | 169 ++ arch/arm/dts/sun4i-a10-a1000.dts | 61 +- arch/arm/dts/sun4i-a10-ba10-tvbox.dts | 23 +- arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts | 37 +- arch/arm/dts/sun4i-a10-cubieboard.dts | 67 +- arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts | 76 +- arch/arm/dts/sun4i-a10-gemei-g9.dts | 28 +- arch/arm/dts/sun4i-a10-hackberry.dts | 32 +- arch/arm/dts/sun4i-a10-hyundai-a7hd.dts | 31 +- arch/arm/dts/sun4i-a10-inet-3f.dts | 2 +- arch/arm/dts/sun4i-a10-inet-3w.dts | 2 +- arch/arm/dts/sun4i-a10-inet1.dts | 58 +- arch/arm/dts/sun4i-a10-inet97fv2.dts | 41 +- arch/arm/dts/sun4i-a10-inet9f-rev03.dts | 101 +- .../dts/sun4i-a10-itead-iteaduino-plus.dts | 24 +- arch/arm/dts/sun4i-a10-jesurun-q5.dts | 34 +- arch/arm/dts/sun4i-a10-marsboard.dts | 38 +- arch/arm/dts/sun4i-a10-mini-xplus.dts | 16 +- arch/arm/dts/sun4i-a10-mk802.dts | 59 +- arch/arm/dts/sun4i-a10-mk802ii.dts | 9 +- arch/arm/dts/sun4i-a10-olinuxino-lime.dts | 75 +- arch/arm/dts/sun4i-a10-pcduino.dts | 47 +- arch/arm/dts/sun4i-a10-pcduino2.dts | 11 - arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts | 89 +- arch/arm/dts/sun4i-a10.dtsi | 1349 +++++++-------- arch/arm/dts/sun5i-a10s-auxtek-t003.dts | 26 +- arch/arm/dts/sun5i-a10s-auxtek-t004.dts | 42 +- arch/arm/dts/sun5i-a10s-mk802.dts | 24 +- arch/arm/dts/sun5i-a10s-olinuxino-micro.dts | 82 +- arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts | 24 +- arch/arm/dts/sun5i-a10s-wobo-i5.dts | 29 +- arch/arm/dts/sun5i-a10s.dtsi | 224 +-- .../dts/sun5i-a13-empire-electronix-d709.dts | 29 +- arch/arm/dts/sun5i-a13-hsg-h702.dts | 29 +- arch/arm/dts/sun5i-a13-inet-98v-rev2.dts | 164 +- arch/arm/dts/sun5i-a13-olinuxino-micro.dts | 44 +- arch/arm/dts/sun5i-a13-olinuxino.dts | 100 +- arch/arm/dts/sun5i-a13-utoo-p66.dts | 49 +- arch/arm/dts/sun5i-a13.dtsi | 268 +-- arch/arm/dts/sun5i-gr8-chip-pro.dts | 16 +- arch/arm/dts/sun5i-gr8.dtsi | 1082 +----------- arch/arm/dts/sun5i-r8-chip.dts | 91 +- arch/arm/dts/sun5i-r8.dtsi | 40 - .../dts/sun5i-reference-design-tablet.dtsi | 69 +- arch/arm/dts/sun5i.dtsi | 792 ++++----- arch/arm/dts/sun6i-a31-app4-evb1.dts | 7 +- arch/arm/dts/sun6i-a31-colombus.dts | 26 +- arch/arm/dts/sun6i-a31-hummingbird.dts | 153 +- arch/arm/dts/sun6i-a31-i7.dts | 82 +- arch/arm/dts/sun6i-a31-m9.dts | 23 +- arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts | 23 +- arch/arm/dts/sun6i-a31.dtsi | 1151 ++++++++----- arch/arm/dts/sun6i-a31s-cs908.dts | 2 - arch/arm/dts/sun6i-a31s-primo81.dts | 69 +- arch/arm/dts/sun6i-a31s-sina31s-core.dtsi | 1 - arch/arm/dts/sun6i-a31s-sina31s.dts | 77 +- arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 154 +- .../sun6i-a31s-yones-toptech-bs1078-v2.dts | 13 +- arch/arm/dts/sun6i-a31s.dtsi | 8 + .../dts/sun6i-reference-design-tablet.dtsi | 18 +- arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts | 32 +- arch/arm/dts/sun7i-a20-bananapi.dts | 106 +- arch/arm/dts/sun7i-a20-bananapro.dts | 73 +- arch/arm/dts/sun7i-a20-cubieboard2.dts | 56 +- arch/arm/dts/sun7i-a20-cubietruck.dts | 84 +- arch/arm/dts/sun7i-a20-hummingbird.dts | 30 +- arch/arm/dts/sun7i-a20-i12-tvbox.dts | 34 +- arch/arm/dts/sun7i-a20-icnova-swac.dts | 6 +- arch/arm/dts/sun7i-a20-itead-ibox.dts | 12 +- arch/arm/dts/sun7i-a20-lamobo-r1.dts | 73 +- arch/arm/dts/sun7i-a20-m3.dts | 12 +- arch/arm/dts/sun7i-a20-mk808c.dts | 43 +- arch/arm/dts/sun7i-a20-olimex-som-evb.dts | 108 +- arch/arm/dts/sun7i-a20-olimex-som204-evb.dts | 42 +- arch/arm/dts/sun7i-a20-olinuxino-lime.dts | 58 +- .../dts/sun7i-a20-olinuxino-lime2-emmc.dts | 6 +- arch/arm/dts/sun7i-a20-olinuxino-lime2.dts | 154 +- arch/arm/dts/sun7i-a20-olinuxino-micro.dts | 116 +- arch/arm/dts/sun7i-a20-orangepi-mini.dts | 77 +- arch/arm/dts/sun7i-a20-orangepi.dts | 42 +- arch/arm/dts/sun7i-a20-pcduino3-nano.dts | 55 +- arch/arm/dts/sun7i-a20-pcduino3.dts | 26 +- arch/arm/dts/sun7i-a20-primo73.dts | 58 +- arch/arm/dts/sun7i-a20-wexler-tab7200.dts | 30 +- arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts | 20 +- arch/arm/dts/sun7i-a20.dtsi | 1505 +++++++---------- arch/arm/dts/sun8i-a23-a33.dtsi | 112 +- arch/arm/dts/sun8i-a23-evb.dts | 11 +- arch/arm/dts/sun8i-a23-gt90h-v4.dts | 5 +- arch/arm/dts/sun8i-a23-inet86dz.dts | 6 +- .../dts/sun8i-a23-polaroid-mid2407pxe03.dts | 34 +- .../dts/sun8i-a23-polaroid-mid2809pxe04.dts | 25 +- arch/arm/dts/sun8i-a23-q8-tablet.dts | 13 + arch/arm/dts/sun8i-a23.dtsi | 4 +- arch/arm/dts/sun8i-a33-ga10h-v1.1.dts | 5 +- arch/arm/dts/sun8i-a33-inet-d978-rev2.dts | 29 +- arch/arm/dts/sun8i-a33-olinuxino.dts | 66 +- arch/arm/dts/sun8i-a33-sinlinx-sina33.dts | 53 +- arch/arm/dts/sun8i-a33.dtsi | 63 +- .../dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 195 ++- arch/arm/dts/sun8i-a83t-bananapi-m3.dts | 298 +++- arch/arm/dts/sun8i-a83t-cubietruck-plus.dts | 322 +++- arch/arm/dts/sun8i-a83t-tbs-a711.dts | 355 +++- arch/arm/dts/sun8i-a83t.dtsi | 885 +++++++++- arch/arm/dts/sun8i-q8-common.dtsi | 30 +- arch/arm/dts/sun8i-r16-bananapi-m2m.dts | 3 +- ...sun8i-r16-nintendo-nes-classic-edition.dts | 2 - arch/arm/dts/sun8i-r16-parrot.dts | 50 +- arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts | 168 +- arch/arm/dts/sun8i-r40.dtsi | 303 +++- .../dts/sun8i-reference-design-tablet.dtsi | 59 +- arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts | 50 + include/dt-bindings/clock/sun4i-a10-ccu.h | 202 +++ include/dt-bindings/clock/sun5i-ccu.h | 106 ++ include/dt-bindings/clock/sun6i-a31-ccu.h | 191 +++ include/dt-bindings/clock/sun7i-a20-ccu.h | 53 + include/dt-bindings/clock/sun8i-a83t-ccu.h | 140 ++ include/dt-bindings/reset/sun4i-a10-ccu.h | 69 + include/dt-bindings/reset/sun5i-ccu.h | 32 + include/dt-bindings/reset/sun6i-a31-ccu.h | 106 ++ include/dt-bindings/reset/sun8i-a83t-ccu.h | 98 ++ 122 files changed, 8374 insertions(+), 6154 deletions(-) create mode 100644 arch/arm/dts/axp81x.dtsi create mode 100644 include/dt-bindings/clock/sun4i-a10-ccu.h create mode 100644 include/dt-bindings/clock/sun5i-ccu.h create mode 100644 include/dt-bindings/clock/sun6i-a31-ccu.h create mode 100644 include/dt-bindings/clock/sun7i-a20-ccu.h create mode 100644 include/dt-bindings/clock/sun8i-a83t-ccu.h create mode 100644 include/dt-bindings/reset/sun4i-a10-ccu.h create mode 100644 include/dt-bindings/reset/sun5i-ccu.h create mode 100644 include/dt-bindings/reset/sun6i-a31-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-a83t-ccu.h -- 2.18.0.321.gffc6fa0e3

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[U-Boot] Regression on ESPRESSObin / status of upstreaming
by Jan Kiszka 26 Aug '18

26 Aug '18

Hi all, I was playing with upstream u-boot on the ESPRESSObin - what an entertaining build process... Anyway, I noticed that, when using latest version of Marvell's ATF, a3700-utils and mv-ddr-marvell (all on 18.06), I can make u-boot 2018.05 at least boot. However, anything >= 2018.07 will crash like this: TIM-1.0 WTMI-devel-18.05.0-06b6160 WTMI: system early-init CPU VDD voltage default value: 1.155V Fill memory before self refresh...done Fill memory before self refresh...done Now in Self-refresh Mode Restore termination values to original values Exited self-refresh ... Self refresh Pass. DDR self test mode test done!! Self refresh Pass. DDR self test mode test done!! QS GATING ============= Calibration done: cycle = 0x00 tap =0x61 CH0_PHY_RL_Control_CS0_B0[0xC0001180]: 0x00000061 CH0_PHY_RL_Control_CS0_B1[0xC0001184]: 0x00000061 QS GATING ============= Calibration done: cycle = 0x00 tap =0x5D CH0_PHY_RL_Control_CS1_B0[0xC00011A4]: 0x0000005D CH0_PHY_RL_Control_CS1_B1[0xC00011A8]: 0x0000005D DLL TUNING ============== DLL 0xc0001050[21:16]: [0,28,14] DLL 0xc0001050[29:24]: [4,33,1b] DLL 0xc0001054[21:16]: [0,2b,15] DLL 0xc0001054[29:24]: [8,32,1d] DLL 0xc0001074[21:16]: [0,3f,1f] DLL 0xc0001074[29:24]: [0,3f,1f] DLL: pass NOTICE: Booting Trusted Firmware NOTICE: BL1: v1.4(release):armada-18.05.2:v1.4-454-g80bbf686 NOTICE: BL1: Built : 11:31:27, Aug 25 2018 NOTICE: BL1: Booting BL2 NOTICE: BL2: v1.4(release):armada-18.05.2:v1.4-454-g80bbf686 NOTICE: BL2: Built : 11:31:28, Aug 25 2018 NOTICE: BL1: Booting BL31 NOTICE: BL31: v1.4(release):armada-18.05.2:v1.4-454-g80bbf686 NOTICE: BL31: Built : 11:3 U-Boot 2018.09-rc2-00093-g2418734ed4 (Aug 25 2018 - 13:33:43 +0200) DRAM: 512 MiB Comphy-0: UNCONNECTED 2.5 Gbps Comphy-1: UNCONNECTED 5 Gbps Comphy-2: SATA0 5 Gbps SATA link 0 timeout. AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode flags: ncq led only pmp fbss pio slum part sxs "Synchronous Abort" handler, esr 0x96000210 elr: 0000000000035c98 lr : 0000000000035c6c (reloc) elr: 000000001ff75c98 lr : 000000001ff75c6c x0 : 00000000d0074000 x1 : 0000000000000000 x2 : 00000000d0088000 x3 : 0000000000000008 x4 : 0000000000000000 x5 : 000000001ffbf678 x6 : 000000000000000a x7 : 000000001ffbf718 x8 : 0000000000000020 x9 : 0000000000000008 x10: 00000000000013d4 x11: 000000001fb2d3bc x12: 00000000000013e6 x13: 0000000000000a20 x14: 0000000000000000 x15: 000000001fb2d648 x16: 000000001ffbcb2a x17: 000000001ffbcb2a x18: 000000001fb2fde8 x19: 000000001fb31ae0 x20: 000000001fb318c0 x21: 0000000000000000 x22: 0000000000000000 x23: 0000000000000000 x24: 0000000000000000 x25: 0000000000000000 x26: 0000000000000000 x27: 0000000000000000 x28: 0000000000000000 x29: 000000001fb2d4d0 Resetting CPU ... Known issue? I was always using the related defconfig. Moreover, there still seems to be some feature gaps: - Only 512M of RAM is detected, although ATF was configured for the 1G I have on my ESPRESSObin, and downstream Marvell u-boot detect that. - MMC is not detected, at least in the working version (but I found no suspicious commits since then to change that). So even without the crash, those two issues would be blockers of moving to upstream. Are they related to any misconfiguration on my side, or are they known limitations? Then what are the plans to resolve them? Thanks, Jan

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[U-Boot] [PATCH] arm: omap: configs: various: Remove references to OMAP34XX_UARTx
by Adam Ford 25 Aug '18

25 Aug '18

Two boards include a reference to ti_omap3_common.h which points the UART driver to OMAP34XX_UARTx so the extra define should be unnecessary. Signed-off-by: Adam Ford <aford173(a)gmail.com> --- include/configs/omap3_evm.h | 1 - include/configs/omap3_pandora.h | 1 - 2 files changed, 2 deletions(-) diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 34418309cb..779087a949 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -34,7 +34,6 @@ #define CONFIG_REVISION_TAG /* Override OMAP3 serial console configuration */ -#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 /* NAND */ #if defined(CONFIG_NAND) diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 68e1d6f82d..1fc40e05ff 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -36,7 +36,6 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 /* commands to include */ -- 2.17.1

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[U-Boot] u-boot 2018.07/2018.09 'data abort' kernel start failure with GCC 8.2.0 on sun8i (H3)
by Auston Stewart 25 Aug '18

25 Aug '18

Greetings, As others have reported ( https://lists.denx.de/pipermail/u-boot/2018-July/334126.html), a 'data abort' occurs when attempting to load the kernel with recent u-boot compiled with recent GCC on Allwinner (Sunxi) H3 boards. I ran into this issue when performing a bootstrap of Shedbuilt GNU/Linux with upstream GCC 8.20, glibc 2.28 and binutils 2.31.1 on a Nano Pi Neo 512M board. I brought up this issue in IRC and did some debugging with xypron, who asked that I message the list. Configurations I've personally tested: u-boot 2018.07 nanopi_neo_defconfig / GCC 8.2.0 + Kernel 4.17.14 / GCC 8.2.0 = broken u-boot 2018.09-rc2 nanopi_neo_defconfig / GCC 8.2.0 + Kernel 4.17.14 / GCC 8.2.0 = broken u-boot 2018.05 nanopi_neo_defconfig / GCC 7.3.0 + Kernel 4.17.14 / GCC 8.2.0 = works u-boot 2018.03 nanopi_neo_defconfig / GCC 7.2.0 + Kernel 4.17.14 / GCC 8.2.0 = works u-boot 2018.09-rc2 ARMv7 unaligned access patch ( https://lists.denx.de/pipermail/u-boot/2018-March/324202.html) / nanopi_neo_defconfig / GCC 8.2.0 + Kernel 4.17.14 / GCC 8.2.0 = broken Error (captured on Nano Pi Neo 512M with 2018.09-rc2): (for complete log, see https://gist.github.com/austons/222c6f1fd304d0832bec9964a4f569f0) Starting kernel ... data abort pc : [<5ff9f16c>] lr : [<5ff76ed7>] reloc pc : [<4a02916c>] lr : [<4a000ed7>] sp : 5bf50588 ip : 5bf568da fp : 40008000 r10: 5bf50698 r9 : 5bf55ee0 r8 : 00000400 r7 : 00000000 r6 : 40008000 r5 : 49ff8000 r4 : 00000000 r3 : 49ff8000 r2 : 49ff8000 r1 : 00000000 r0 : 00000000 Flags: nZCv IRQs off FIQs off Mode UK6_32 Code: e12fff1e e52de008 fa000001 e3a00000 (e49df008) Resetting CPU ... I have access to a number of H3/sun8i test devices to assist in diagnosis. There is some speculation in the earlier thread that USB changes post-2018.07rc1 could be a cause, but the only confirmed workaround is reverting to earlier GCC. Thank you for your time. Please let me know if there are other details I can provide. Auston Stewart Shedbuilt GNU/Linux http://shedbuilt.net

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[U-Boot] Pull request: u-boot-sunxi/master
by Jagan Teki 25 Aug '18

25 Aug '18

Hi Tom, Please pull this PR. thanks, Jagan. The following changes since commit b71d9e8b3805305ea4116733f515061710ad7081: Merge branch 'master' of git://git.denx.de/u-boot-sunxi (2018-08-20 13:41:56 -0400) are available in the Git repository at: git://git.denx.de/u-boot-sunxi.git master for you to fetch changes up to 12069bd0466a87015dd40bb25c6b2571ee5f0851: usb: musb-new: Call musb_platform_exit from musb_stop (2018-08-23 17:31:24 +0530) ---------------------------------------------------------------- Jagan Teki (5): usb: musb-new: Fix improper musb host pointer usb: musb-new: sunxi: Allocate struct phy in private musb-new: sunxi: Access ahb_reset0_cfg via ccm offset usb: musb-new: sunxi: Add proper musb exit support usb: musb-new: Call musb_platform_exit from musb_stop board/compulab/cm_t3517/cm_t3517.c | 4 +- drivers/usb/musb-new/musb_core.c | 1 + drivers/usb/musb-new/musb_uboot.c | 12 ++--- drivers/usb/musb-new/pic32.c | 6 ++- drivers/usb/musb-new/sunxi.c | 107 ++++++++++++++++++++++--------------- include/linux/usb/musb.h | 4 +- 6 files changed, 80 insertions(+), 54 deletions(-)

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[U-Boot] [PULL] u-boot-socfpga/master
by Marek Vasut 25 Aug '18

25 Aug '18

The following changes since commit 2418734ed429058b396d2aeb6b91f875cdc8e4ce: Merge branch 'master' of git://git.denx.de/u-boot-tegra (2018-08-22 22:36:08 -0400) are available in the Git repository at: git://git.denx.de/u-boot-socfpga.git master for you to fetch changes up to a029f540c54c39847c329fc70b1b2e0ab6dedbcd: ARM: dts: socfpga: Add missing NAND reset (2018-08-24 12:05:21 +0200) ---------------------------------------------------------------- Ley Foon Tan (2): arm: socfpga: stratix10: Enable EMAC to FPGA bridge based on handoff arm: socfpga: stratix10: Fix mailbox urgent command with urgent register Marek Vasut (6): ARM: socfpga: Reorder Arria10 SPL timer: dw-apb: Add Designware APB timer driver ARM: dts: socfpga: Flag timer clock as pre-reloc ARM: socfpga: Convert Arria10 to timer framework ARM: dts: socfpga: Drop ad-hoc UART clock frequency encoding from DT ARM: dts: socfpga: Add missing NAND reset arch/arm/dts/socfpga_arria10.dtsi | 11 +++++++++++ arch/arm/dts/socfpga_arria10_socdk.dtsi | 13 ------------- arch/arm/mach-socfpga/Makefile | 1 - arch/arm/mach-socfpga/board.c | 8 -------- arch/arm/mach-socfpga/clock_manager_arria10.c | 11 ++++++++--- arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h | 3 ++- arch/arm/mach-socfpga/include/mach/misc.h | 5 +++++ arch/arm/mach-socfpga/mailbox_s10.c | 15 +++++++-------- arch/arm/mach-socfpga/misc_arria10.c | 25 +++++++++---------------- arch/arm/mach-socfpga/spl_a10.c | 28 ++++++++++++---------------- arch/arm/mach-socfpga/spl_s10.c | 2 +- configs/socfpga_arria10_defconfig | 3 +++ drivers/timer/Kconfig | 7 +++++++ drivers/timer/Makefile | 1 + drivers/timer/dw-apb-timer.c | 90 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/configs/socfpga_common.h | 2 ++ 16 files changed, 158 insertions(+), 67 deletions(-) create mode 100644 drivers/timer/dw-apb-timer.c

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[U-Boot] [PULL] u-boot-usb/master
by Marek Vasut 25 Aug '18

25 Aug '18

The following changes since commit 9f8cf76be256a83643ee05de6cffaeb452ed0931: Convert CONFIG_SYS_I2C_DAVINCI to Kconfig (2018-08-17 15:43:38 -0400) are available in the Git repository at: git://git.denx.de/u-boot-usb.git master for you to fetch changes up to 49c752c93a785b9bad9d3fbbd52a76bec003eac5: cmd: Add bind/unbind commands to bind a device to a driver from the command line (2018-08-21 16:21:37 +0200) ---------------------------------------------------------------- Adam Ford (2): usb: musb-new: omap2430: Remove dead code usb: musb-new: omap2430: Enable DM_USB and OF support Jean-Jacques Hiblot (7): usb: gadget: Add bcdDevice for the DWC3 USB Gadget Controller net: eth-uclass: Fix for DM USB ethernet support uclass: Add dev_get_uclass_index() to get the uclass/index of a device dm: print the index of the device when dumping the dm tree dm: convert device_get_global_by_of_offset() to device_get_global_by_ofnode() device: expose the functions used to remove and unbind children of a device cmd: Add bind/unbind commands to bind a device to a driver from the command line Sam Protsenko (1): cmd: fastboot: Validate user input arch/arm/mach-rockchip/rk3188-board-spl.c | 2 +- arch/arm/mach-rockchip/rk3288-board-spl.c | 2 +- arch/sandbox/dts/test.dts | 11 +++ cmd/Kconfig | 9 +++ cmd/Makefile | 1 + cmd/bind.c | 255 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ cmd/fastboot.c | 13 +++- configs/sandbox_defconfig | 1 + drivers/core/device-remove.c | 30 +++----- drivers/core/device.c | 19 +++-- drivers/core/dump.c | 16 ++-- drivers/core/uclass.c | 21 ++++++ drivers/usb/gadget/gadget_chips.h | 2 + drivers/usb/musb-new/omap2430.c | 596 +++++++++++++++++++++++++++++-------------------------------------------------------------------------------------------------------------------- include/dm/device-internal.h | 38 ++++++++++ include/dm/device.h | 23 +++++- include/dm/uclass-internal.h | 11 +++ net/eth-uclass.c | 3 +- test/py/tests/test_bind.py | 178 ++++++++++++++++++++++++++++++++++++++++++++ 19 files changed, 712 insertions(+), 519 deletions(-) create mode 100644 cmd/bind.c create mode 100644 test/py/tests/test_bind.py

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