June 2018 - U-Boot

[U-Boot] [PATCH] board: freescale: ls1012ardb: Add command to switch QSPI bank
by Jagdish Gediya 13 Aug '18

13 Aug '18

Add command "boot_bank X" to switch the boot bank to either 1 or 2. Signed-off-by: Jagdish Gediya <jagdish.gediya(a)nxp.com> --- board/freescale/ls1012ardb/ls1012ardb.c | 85 +++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index ed5a8e6..4d4f6fb 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -26,6 +26,9 @@ DECLARE_GLOBAL_DATA_PTR; +#define BOOT_FROM_UPPER_BANK 0x2 +#define BOOT_FROM_LOWER_BANK 0x1 + int checkboard(void) { #ifdef CONFIG_TARGET_LS1012ARDB @@ -212,3 +215,85 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } + +static int switch_to_bank1(void) +{ + u8 data; + int ret; + + i2c_set_bus_num(0); + + data = 0xf4; + ret = i2c_write(0x24, 0x3, 1, &data, 1); + if (ret) { + printf("i2c write error to chip : %u, addr : %u, data : %u\n", + 0x24, 0x3, data); + } + + return ret; +} + +static int switch_to_bank2(void) +{ + u8 data; + int ret; + + i2c_set_bus_num(0); + + data = 0xfc; + ret = i2c_write(0x24, 0x7, 1, &data, 1); + if (ret) { + printf("i2c write error to chip : %u, addr : %u, data : %u\n", + 0x24, 0x7, data); + goto err; + } + + data = 0xf5; + ret = i2c_write(0x24, 0x3, 1, &data, 1); + if (ret) { + printf("i2c write error to chip : %u, addr : %u, data : %u\n", + 0x24, 0x3, data); + } +err: + return ret; +} + +static int convert_flash_bank(int bank) +{ + int ret = 0; + + switch (bank) { + case BOOT_FROM_UPPER_BANK: + ret = switch_to_bank2(); + break; + case BOOT_FROM_LOWER_BANK: + ret = switch_to_bank1(); + break; + default: + ret = CMD_RET_USAGE; + break; + }; + + return ret; +} + +static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + if (strcmp(argv[1], "1") == 0) + convert_flash_bank(BOOT_FROM_LOWER_BANK); + else if (strcmp(argv[1], "2") == 0) + convert_flash_bank(BOOT_FROM_UPPER_BANK); + else + return CMD_RET_USAGE; + + return 0; +} + +U_BOOT_CMD( + boot_bank, 2, 0, flash_bank_cmd, + "Flash bank Selection Control", + "bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)" +); -- 1.9.1

6 10

[U-Boot] [PATCH v2] cmd: fastboot: Validate user input
by Sam Protsenko 13 Aug '18

13 Aug '18

In case when user provides '-' as USB controller index, like this: => fastboot - data abort occurs in strcmp() function in do_fastboot(), here: if (!strcmp(argv[1], "udp")) (tested on BeagleBone Black). That's because argv[1] is NULL when user types in the '-', and null pointer dereference occurs in strcmp() (which is ok according to C standard specification). So we must validate user input to prevent such behavior. While at it, check also the result of strtoul() function and handle error cases properly. Signed-off-by: Sam Protsenko <semen.protsenko(a)linaro.org> --- Changes for v2: - replace argv check with argc check - add mentioning of testing platform in commit message cmd/fastboot.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/cmd/fastboot.c b/cmd/fastboot.c index e6ae0570d5..ae3a5f627f 100644 --- a/cmd/fastboot.c +++ b/cmd/fastboot.c @@ -38,13 +38,18 @@ static int do_fastboot_usb(int argc, char *const argv[], #if CONFIG_IS_ENABLED(USB_FUNCTION_FASTBOOT) int controller_index; char *usb_controller; + char *endp; int ret; if (argc < 2) return CMD_RET_USAGE; usb_controller = argv[1]; - controller_index = simple_strtoul(usb_controller, NULL, 0); + controller_index = simple_strtoul(usb_controller, &endp, 0); + if (*endp != '\0') { + pr_err("Error: Wrong USB controller index format\n"); + return CMD_RET_FAILURE; + } ret = board_usb_init(controller_index, USB_INIT_DEVICE); if (ret) { @@ -120,6 +125,12 @@ NXTARG: ; } + /* Handle case when USB controller param is just '-' */ + if (argc == 1) { + pr_err("Error: Incorrect USB controller index\n"); + return CMD_RET_USAGE; + } + fastboot_init((void *)buf_addr, buf_size); if (!strcmp(argv[1], "udp")) -- 2.17.1

3 5

[U-Boot] [PATCH V3 1/2] mmc: add HS400 support
by Peng Fan 10 Aug '18

10 Aug '18

Add HS400 support. Selecting HS400 needs first select HS199 according to spec, so use a dedicated function for HS400. Add HS400 related macros. Remove the restriction of only using the low 6 bits of EXT_CSD_CARD_TYPE, using all the 8 bits. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Jean-Jacques Hiblot <jjhiblot(a)ti.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Kishon Vijay Abraham I <kishon(a)ti.com> Cc: Bin Meng <bmeng.cn(a)gmail.com> --- V3: Simplify code add error msg V2: remove 4bits support from HS400, as HS400 does not support 4bits per spec. drivers/mmc/Kconfig | 7 +++ drivers/mmc/mmc.c | 137 +++++++++++++++++++++++++++++++++++++++++----------- include/mmc.h | 11 +++++ 3 files changed, 128 insertions(+), 27 deletions(-) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 3f15f85efd..a535a87a8e 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -104,6 +104,13 @@ config SPL_MMC_UHS_SUPPORT cards. The IO voltage must be switchable from 3.3v to 1.8v. The bus frequency can go up to 208MHz (SDR104) +config MMC_HS400_SUPPORT + bool "enable HS400 support" + select MMC_HS200_SUPPORT + help + The HS400 mode is support by some eMMC. The bus frequency is up to + 200MHz. This mode requires tuning the IO. + config MMC_HS200_SUPPORT bool "enable HS200 support" help diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index f7827f527a..3bb6a68513 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -147,6 +147,7 @@ const char *mmc_mode_name(enum bus_mode mode) [MMC_HS_52] = "MMC High Speed (52MHz)", [MMC_DDR_52] = "MMC DDR52 (52MHz)", [MMC_HS_200] = "HS200 (200MHz)", + [MMC_HS_400] = "HS400 (200MHz)", }; if (mode >= MMC_MODES_END) @@ -171,6 +172,7 @@ static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode) [UHS_DDR50] = 50000000, [UHS_SDR104] = 208000000, [MMC_HS_200] = 200000000, + [MMC_HS_400] = 200000000, }; if (mode == MMC_LEGACY) @@ -769,6 +771,11 @@ static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode) case MMC_HS_200: speed_bits = EXT_CSD_TIMING_HS200; break; +#endif +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + case MMC_HS_400: + speed_bits = EXT_CSD_TIMING_HS400; + break; #endif case MMC_LEGACY: speed_bits = EXT_CSD_TIMING_LEGACY; @@ -816,7 +823,7 @@ static int mmc_get_capabilities(struct mmc *mmc) mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; - cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f; + cardtype = ext_csd[EXT_CSD_CARD_TYPE]; mmc->cardtype = cardtype; #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) @@ -824,6 +831,12 @@ static int mmc_get_capabilities(struct mmc *mmc) EXT_CSD_CARD_TYPE_HS200_1_8V)) { mmc->card_caps |= MMC_MODE_HS200; } +#endif +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V | + EXT_CSD_CARD_TYPE_HS400_1_8V)) { + mmc->card_caps |= MMC_MODE_HS400; + } #endif if (cardtype & EXT_CSD_CARD_TYPE_52) { if (cardtype & EXT_CSD_CARD_TYPE_DDR_52) @@ -1734,10 +1747,13 @@ static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode, u32 card_mask = 0; switch (mode) { + case MMC_HS_400: case MMC_HS_200: - if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_8V) + if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V | + EXT_CSD_CARD_TYPE_HS400_1_8V)) card_mask |= MMC_SIGNAL_VOLTAGE_180; - if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_2V) + if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V | + EXT_CSD_CARD_TYPE_HS400_1_2V)) card_mask |= MMC_SIGNAL_VOLTAGE_120; break; case MMC_DDR_52: @@ -1773,6 +1789,13 @@ static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode, #endif static const struct mode_width_tuning mmc_modes_by_pref[] = { +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + { + .mode = MMC_HS_400, + .widths = MMC_MODE_8BIT, + .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200 + }, +#endif #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) { .mode = MMC_HS_200, @@ -1816,6 +1839,54 @@ static const struct ext_csd_bus_width { {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1}, }; +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) +static int mmc_select_hs400(struct mmc *mmc) +{ + int err; + + /* Set timing to HS200 for tuning */ + err = mmc_set_card_speed(mmc, MMC_HS_200); + if (err) + return err; + + /* configure the bus mode (host) */ + mmc_select_mode(mmc, MMC_HS_200); + mmc_set_clock(mmc, mmc->tran_speed, false); + + /* execute tuning if needed */ + err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200); + if (err) { + debug("tuning failed\n"); + return err; + } + + /* Set back to HS */ + mmc_set_card_speed(mmc, MMC_HS); + mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false); + + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, + EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG); + if (err) + return err; + + err = mmc_set_card_speed(mmc, MMC_HS_400); + if (err) + return err; + + mmc_select_mode(mmc, MMC_HS_400); + err = mmc_set_clock(mmc, mmc->tran_speed, false); + if (err) + return err; + + return 0; +} +#else +static int mmc_select_hs400(struct mmc *mmc) +{ + return -ENOTSUPP; +} +#endif + #define for_each_supported_width(caps, ddr, ecbv) \ for (ecbv = ext_csd_bus_width;\ ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\ @@ -1869,37 +1940,49 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps) goto error; mmc_set_bus_width(mmc, bus_width(ecbw->cap)); - /* configure the bus speed (card) */ - err = mmc_set_card_speed(mmc, mwt->mode); - if (err) - goto error; - - /* - * configure the bus width AND the ddr mode (card) - * The host side will be taken care of in the next step - */ - if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) { - err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, - EXT_CSD_BUS_WIDTH, - ecbw->ext_csd_bits); + if (mwt->mode == MMC_HS_400) { + err = mmc_select_hs400(mmc); + if (err) { + printf("Select HS400 failed %d\n", err); + goto error; + } + } else { + /* configure the bus speed (card) */ + err = mmc_set_card_speed(mmc, mwt->mode); if (err) goto error; - } - /* configure the bus mode (host) */ - mmc_select_mode(mmc, mwt->mode); - mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE); + /* + * configure the bus width AND the ddr mode + * (card). The host side will be taken care + * of in the next step + */ + if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) { + err = mmc_switch(mmc, + EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BUS_WIDTH, + ecbw->ext_csd_bits); + if (err) + goto error; + } + + /* configure the bus mode (host) */ + mmc_select_mode(mmc, mwt->mode); + mmc_set_clock(mmc, mmc->tran_speed, + MMC_CLK_ENABLE); #ifdef MMC_SUPPORTS_TUNING - /* execute tuning if needed */ - if (mwt->tuning) { - err = mmc_execute_tuning(mmc, mwt->tuning); - if (err) { - pr_debug("tuning failed\n"); - goto error; + /* execute tuning if needed */ + if (mwt->tuning) { + err = mmc_execute_tuning(mmc, + mwt->tuning); + if (err) { + pr_debug("tuning failed\n"); + goto error; + } } - } #endif + } /* do a transfer to check the configuration */ err = mmc_read_and_compare_ext_csd(mmc); diff --git a/include/mmc.h b/include/mmc.h index 534c317b43..e12323b7cf 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -64,6 +64,7 @@ #define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52) #define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52) #define MMC_MODE_HS200 MMC_CAP(MMC_HS_200) +#define MMC_MODE_HS400 MMC_CAP(MMC_HS_400) #define MMC_MODE_8BIT BIT(30) #define MMC_MODE_4BIT BIT(29) @@ -248,6 +249,10 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) /* SDR mode @1.2V I/O */ #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ EXT_CSD_CARD_TYPE_HS200_1_2V) +#define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6) +#define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7) +#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ + EXT_CSD_CARD_TYPE_HS400_1_2V) #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ @@ -259,6 +264,7 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) #define EXT_CSD_TIMING_LEGACY 0 /* no high speed */ #define EXT_CSD_TIMING_HS 1 /* HS */ #define EXT_CSD_TIMING_HS200 2 /* HS200 */ +#define EXT_CSD_TIMING_HS400 3 /* HS400 */ #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) @@ -519,6 +525,7 @@ enum bus_mode { UHS_DDR50, UHS_SDR104, MMC_HS_200, + MMC_HS_400, MMC_MODES_END }; @@ -532,6 +539,10 @@ static inline bool mmc_is_mode_ddr(enum bus_mode mode) #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) else if (mode == UHS_DDR50) return true; +#endif +#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + else if (mode == MMC_HS_400) + return true; #endif else return false; -- 2.14.1

4 13

[U-Boot] [PATCH v3 0/7] Fixes/Addition to use the USB Ethernet gadget with the DWC3 gadget controller
by Jean-Jacques Hiblot 09 Aug '18

09 Aug '18

This series implements 2 fixes to be able to use USB Ethernet gadget with the dwc3 driver. It also adds new commands to bind/unbind a device to/from a driver and update the 'dm tree' command to make it easier to use those new commands. The bind/unbind commands can be used to bind the DWC3 USB gadget to the usb_ether driver from the command line instead of relying on platform code. Changes in v3: - update some commit logs - factorize code based on comments from ML - remove the devices before unbinding them - use device_find_global_by_ofnode() to get a device by its node. Changes in v2: - Make the bind/unbind command generic, not specific to usb device. - Update the API to be able to bind/unbind based on DTS node path - Add a Kconfig option to select the bind/unbind commands Jean-Jacques Hiblot (7): usb: gadget: Add bcdDevice for the DWC3 USB Gadget Controller net: eth-uclass: Fix for DM USB ethernet support uclass: Add dev_get_uclass_index() to get the uclass/index of a device dm: print the index of the device when dumping the dm tree dm: convert device_get_global_by_of_offset() to device_get_global_by_ofnode() device: expose the functions used to remove and unbind children of a device cmd: Add bind/unbind commands to bind a device to a driver from the command line arch/arm/mach-rockchip/rk3188-board-spl.c | 2 +- arch/arm/mach-rockchip/rk3288-board-spl.c | 2 +- arch/sandbox/dts/test.dts | 11 ++ cmd/Kconfig | 9 ++ cmd/Makefile | 1 + cmd/bind.c | 255 ++++++++++++++++++++++++++++++ configs/sandbox_defconfig | 1 + drivers/core/device-remove.c | 30 ++-- drivers/core/device.c | 19 ++- drivers/core/dump.c | 16 +- drivers/core/uclass.c | 21 +++ drivers/usb/gadget/gadget_chips.h | 2 + include/dm/device-internal.h | 38 +++++ include/dm/device.h | 23 ++- include/dm/uclass-internal.h | 11 ++ net/eth-uclass.c | 3 +- test/py/tests/test_bind.py | 178 +++++++++++++++++++++ 17 files changed, 584 insertions(+), 38 deletions(-) create mode 100644 cmd/bind.c create mode 100644 test/py/tests/test_bind.py -- 2.7.4

8 38

[U-Boot] [PATCHv2 1/2] dra7xx: Always enable UART1 and UART3 in early_padconf
by Tom Rini 07 Aug '18

07 Aug '18

It is safe to always setup the pinmux for UART1 and UART3 to be used in early_padconf and then if these pins are needed later on, they will be re-muxed. This allows us to drop the usage of CONFIG_CONS_INDEX here. Cc: Lokesh Vutla <lokeshvutla(a)ti.com> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- board/ti/dra7xx/mux_data.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index b5dcaa584a24..32c9ecacce2a 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -372,13 +372,10 @@ const struct pad_conf_entry dra71x_core_padconf_array[] = { }; const struct pad_conf_entry early_padconf[] = { -#if (CONFIG_CONS_INDEX == 1) {UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */ {UART1_TXD, (PIN_INPUT_SLEW | M0)}, /* UART1_TXD */ -#elif (CONFIG_CONS_INDEX == 3) {UART3_RXD, (PIN_INPUT_SLEW | M0)}, /* UART3_RXD */ {UART3_TXD, (PIN_INPUT_SLEW | M0)}, /* UART3_TXD */ -#endif {I2C1_SDA, (PIN_INPUT | M0)}, /* I2C1_SDA */ {I2C1_SCL, (PIN_INPUT | M0)}, /* I2C1_SCL */ }; -- 2.7.4

3 6

[U-Boot] [PATCH v2 1/3] configs: kirkwood: ds109: switch to DM_I2C
by Chris Packham 06 Aug '18

06 Aug '18

Enable DM_I2C and I2C_MVTSWI for the ds109 board. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- Changes in v2: - new configs/ds109_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index c9207433b374..fd10e6e3c36e 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -18,6 +18,8 @@ CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_MVSATA_IDE=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y -- 2.18.0

2 4

[U-Boot] [PATCH 0/6] mvebu: allow selection of boot device
by Baruch Siach 06 Aug '18

06 Aug '18

Currently the boot device that the generated .kwb image supports is statically set in two places. The BOOT_FROM directive in the per board kwbimage.cfg file, and the CONFIG_SPL_BOOT_DEVICE macro in the board config header file. The gdsys Controlcenter DC supports build time generation of the kwbimage.cfg file which allows build time selection of the boot device. This series extends the idea of kwbimage.cfg generation to all 32bit mvebu SoCs. In addition, this series makes Clearfog use the kconfig symbols alone for boot selection, so that no code modification is needed. The first three patches are cleanup patches that should not change existing behavior. The fourth patch extends the kwbimage.cfg build time generation support to all mvebu platforms. The fifth patch adds support for boot from UART. The last patch removes the static CONFIG_SPL_BOOT_DEVICE definition for Clearfog. I tested this series on Clearfog Base, booting from SD card, SPI flash, and UART. I ran a number of build tests for other platforms. I would appreciate reports of run tests on affected platforms. Baruch Siach (6): mvebu: turris_omnia: use u-boot-spl-dtb.bin mvebu: a38x: drop duplicate platform id symbols mvebu: consolidate SPL boot device config symbols mvebu: select boot device at SoC level mvebu: support UART boot image mvebu: clearfog: use kconfig symbols to select boot device arch/arm/Kconfig | 1 - .../a38x => arch/arm/mach-mvebu}/.gitignore | 0 arch/arm/mach-mvebu/Kconfig | 17 +++++---- arch/arm/mach-mvebu/Makefile | 33 +++++++++++++++++ arch/arm/mach-mvebu/include/mach/config.h | 4 +-- .../arm/mach-mvebu}/kwbimage.cfg.in | 0 board/CZ.NIC/turris_omnia/kwbimage.cfg | 12 ------- board/Marvell/db-88f6720/kwbimage.cfg | 12 ------- board/Marvell/db-88f6820-amc/kwbimage.cfg | 12 ------- board/Marvell/db-88f6820-gp/kwbimage.cfg | 12 ------- board/Marvell/db-mv784mp-gp/kwbimage.cfg | 12 ------- board/Synology/ds414/kwbimage.cfg | 12 ------- board/gdsys/a38x/Kconfig | 36 ------------------- board/gdsys/a38x/Makefile | 31 ---------------- board/kobol/helios4/kwbimage.cfg | 13 ------- board/maxbcm/kwbimage.cfg | 12 ------- board/solidrun/clearfog/kwbimage.cfg | 12 ------- board/theadorable/kwbimage.cfg | 12 ------- configs/clearfog_defconfig | 2 +- configs/helios4_defconfig | 2 +- include/configs/clearfog.h | 16 ++------- include/configs/turris_omnia.h | 4 +-- 22 files changed, 51 insertions(+), 216 deletions(-) rename {board/gdsys/a38x => arch/arm/mach-mvebu}/.gitignore (100%) rename {board/gdsys/a38x => arch/arm/mach-mvebu}/kwbimage.cfg.in (100%) delete mode 100644 board/CZ.NIC/turris_omnia/kwbimage.cfg delete mode 100644 board/Marvell/db-88f6720/kwbimage.cfg delete mode 100644 board/Marvell/db-88f6820-amc/kwbimage.cfg delete mode 100644 board/Marvell/db-88f6820-gp/kwbimage.cfg delete mode 100644 board/Marvell/db-mv784mp-gp/kwbimage.cfg delete mode 100644 board/Synology/ds414/kwbimage.cfg delete mode 100644 board/gdsys/a38x/Kconfig delete mode 100644 board/kobol/helios4/kwbimage.cfg delete mode 100644 board/maxbcm/kwbimage.cfg delete mode 100644 board/solidrun/clearfog/kwbimage.cfg delete mode 100644 board/theadorable/kwbimage.cfg -- 2.17.1

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[U-Boot] [PATCH] spi: Zap fsl_espi driver
by Jagan Teki 06 Aug '18

06 Aug '18

Dropped becuase - No proper changes related to since from 2015 - no dm conversion. Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- Note: Right now only drived removed, if there is no further update on this will remove respective code which is using this driver. drivers/spi/Kconfig | 7 - drivers/spi/Makefile | 1 - drivers/spi/fsl_espi.c | 389 ------------------------------------------------- 3 files changed, 397 deletions(-) delete mode 100644 drivers/spi/fsl_espi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 6667f7321f..aa6b3acdab 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -236,13 +236,6 @@ config CF_SPI Enable the ColdFire SPI driver. This driver can be used on some m68k SoCs. -config FSL_ESPI - bool "Freescale eSPI driver" - help - Enable the Freescale eSPI driver. This driver can be used to - access the SPI interface and SPI NOR flash on platforms embedding - this Freescale eSPI IP core. - config FSL_QSPI bool "Freescale QSPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 176bfa05cf..de75b32d44 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -26,7 +26,6 @@ obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o -obj-$(CONFIG_FSL_ESPI) += fsl_espi.o obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c deleted file mode 100644 index b1586d1291..0000000000 --- a/drivers/spi/fsl_espi.c +++ /dev/null @@ -1,389 +0,0 @@ -/* - * eSPI controller driver. - * - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * Author: Mingkai Hu (Mingkai.hu(a)freescale.com) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#include <malloc.h> -#include <spi.h> -#include <asm/immap_85xx.h> - -struct fsl_spi_slave { - struct spi_slave slave; - ccsr_espi_t *espi; - unsigned int div16; - unsigned int pm; - int tx_timeout; - unsigned int mode; - size_t cmd_len; - u8 cmd_buf[16]; - size_t data_len; - unsigned int max_transfer_length; -}; - -#define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave) -#define US_PER_SECOND 1000000UL - -#define ESPI_MAX_CS_NUM 4 -#define ESPI_FIFO_WIDTH_BIT 32 - -#define ESPI_EV_RNE BIT(9) -#define ESPI_EV_TNF BIT(8) -#define ESPI_EV_DON BIT(14) -#define ESPI_EV_TXE BIT(15) -#define ESPI_EV_RFCNT_SHIFT 24 -#define ESPI_EV_RFCNT_MASK (0x3f << ESPI_EV_RFCNT_SHIFT) - -#define ESPI_MODE_EN BIT(31) /* Enable interface */ -#define ESPI_MODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold */ -#define ESPI_MODE_RXTHR(x) ((x) << 0) /* Rx FIFO threshold */ - -#define ESPI_COM_CS(x) ((x) << 30) -#define ESPI_COM_TRANLEN(x) ((x) << 0) - -#define ESPI_CSMODE_CI_INACTIVEHIGH BIT(31) -#define ESPI_CSMODE_CP_BEGIN_EDGCLK BIT(30) -#define ESPI_CSMODE_REV_MSB_FIRST BIT(29) -#define ESPI_CSMODE_DIV16 BIT(28) -#define ESPI_CSMODE_PM(x) ((x) << 24) -#define ESPI_CSMODE_POL_ASSERTED_LOW BIT(20) -#define ESPI_CSMODE_LEN(x) ((x) << 16) -#define ESPI_CSMODE_CSBEF(x) ((x) << 12) -#define ESPI_CSMODE_CSAFT(x) ((x) << 8) -#define ESPI_CSMODE_CSCG(x) ((x) << 3) - -#define ESPI_CSMODE_INIT_VAL (ESPI_CSMODE_POL_ASSERTED_LOW | \ - ESPI_CSMODE_CSBEF(0) | ESPI_CSMODE_CSAFT(0) | \ - ESPI_CSMODE_CSCG(1)) - -#define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0 - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct fsl_spi_slave *fsl; - sys_info_t sysinfo; - unsigned long spibrg = 0; - unsigned long spi_freq = 0; - unsigned char pm = 0; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs); - if (!fsl) - return NULL; - - fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); - fsl->mode = mode; - fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; - - /* Set eSPI BRG clock source */ - get_sys_info(&sysinfo); - spibrg = sysinfo.freq_systembus / 2; - fsl->div16 = 0; - if ((spibrg / max_hz) > 32) { - fsl->div16 = ESPI_CSMODE_DIV16; - pm = spibrg / (max_hz * 16 * 2); - if (pm > 16) { - pm = 16; - debug("Requested speed is too low: %d Hz, %ld Hz " - "is used.\n", max_hz, spibrg / (32 * 16)); - } - } else - pm = spibrg / (max_hz * 2); - if (pm) - pm--; - fsl->pm = pm; - - if (fsl->div16) - spi_freq = spibrg / ((pm + 1) * 2 * 16); - else - spi_freq = spibrg / ((pm + 1) * 2); - - /* set tx_timeout to 10 times of one espi FIFO entry go out */ - fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT - * 10), spi_freq); - - return &fsl->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - free(fsl); -} - -void spi_init(void) -{ - -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = fsl->espi; - unsigned char pm = fsl->pm; - unsigned int cs = slave->cs; - unsigned int mode = fsl->mode; - unsigned int div16 = fsl->div16; - int i; - - debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs); - - /* Enable eSPI interface */ - out_be32(&espi->mode, ESPI_MODE_RXTHR(3) - | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN); - - out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */ - out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */ - - /* Init CS mode interface */ - for (i = 0; i < ESPI_MAX_CS_NUM; i++) - out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL); - - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & - ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16 - | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK - | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF))); - - /* Set eSPI BRG clock source */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_PM(pm) | div16); - - /* Set eSPI mode */ - if (mode & SPI_CPHA) - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_CP_BEGIN_EDGCLK); - if (mode & SPI_CPOL) - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_CI_INACTIVEHIGH); - - /* Character bit order: msb first */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_REV_MSB_FIRST); - - /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_LEN(7)); - - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ - -} - -static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout) -{ - ccsr_espi_t *espi = fsl->espi; - unsigned int tmpdout, event; - int tmp_tx_timeout; - - if (dout) - tmpdout = *(u32 *)dout; - else - tmpdout = 0; - - out_be32(&espi->tx, tmpdout); - out_be32(&espi->event, ESPI_EV_TNF); - debug("***spi_xfer:...%08x written\n", tmpdout); - - tmp_tx_timeout = fsl->tx_timeout; - /* Wait for eSPI transmit to go out */ - while (tmp_tx_timeout--) { - event = in_be32(&espi->event); - if (event & ESPI_EV_DON || event & ESPI_EV_TXE) { - out_be32(&espi->event, ESPI_EV_TXE); - break; - } - udelay(1); - } - - if (tmp_tx_timeout < 0) - debug("***spi_xfer:...Tx timeout! event = %08x\n", event); -} - -static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes) -{ - ccsr_espi_t *espi = fsl->espi; - unsigned int tmpdin, rx_times; - unsigned char *buf, *p_cursor; - - if (bytes <= 0) - return 0; - - rx_times = DIV_ROUND_UP(bytes, 4); - buf = (unsigned char *)malloc(4 * rx_times); - if (!buf) { - debug("SF: Failed to malloc memory.\n"); - return -1; - } - p_cursor = buf; - while (rx_times--) { - tmpdin = in_be32(&espi->rx); - debug("***spi_xfer:...%08x readed\n", tmpdin); - *(u32 *)p_cursor = tmpdin; - p_cursor += 4; - } - - if (din) - memcpy(din, buf, bytes); - - free(buf); - out_be32(&espi->event, ESPI_EV_RNE); - - return bytes; -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, - void *data_in, unsigned long flags) -{ - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = fsl->espi; - unsigned int event, rx_bytes; - const void *dout = NULL; - void *din = NULL; - int len = 0; - int num_blks, num_chunks, max_tran_len, tran_len; - int num_bytes; - unsigned char *buffer = NULL; - size_t buf_len; - u8 *cmd_buf = fsl->cmd_buf; - size_t cmd_len = fsl->cmd_len; - size_t data_len = bitlen / 8; - size_t rx_offset = 0; - int rf_cnt; - - max_tran_len = fsl->max_transfer_length; - switch (flags) { - case SPI_XFER_BEGIN: - cmd_len = fsl->cmd_len = data_len; - memcpy(cmd_buf, data_out, cmd_len); - return 0; - case 0: - case SPI_XFER_END: - if (bitlen == 0) { - spi_cs_deactivate(slave); - return 0; - } - buf_len = 2 * cmd_len + min(data_len, (size_t)max_tran_len); - len = cmd_len + data_len; - rx_offset = cmd_len; - buffer = (unsigned char *)malloc(buf_len); - if (!buffer) { - debug("SF: Failed to malloc memory.\n"); - return 1; - } - memcpy(buffer, cmd_buf, cmd_len); - if (data_in == NULL) - memcpy(buffer + cmd_len, data_out, data_len); - break; - case SPI_XFER_BEGIN | SPI_XFER_END: - len = data_len; - buffer = (unsigned char *)malloc(len * 2); - if (!buffer) { - debug("SF: Failed to malloc memory.\n"); - return 1; - } - memcpy(buffer, data_out, len); - rx_offset = len; - cmd_len = 0; - break; - } - - debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) len %u\n", - *(uint *)data_out, data_out, *(uint *)data_in, data_in, len); - - num_chunks = DIV_ROUND_UP(data_len, max_tran_len); - while (num_chunks--) { - if (data_in) - din = buffer + rx_offset; - dout = buffer; - tran_len = min(data_len, (size_t)max_tran_len); - num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4); - num_bytes = (tran_len + cmd_len) % 4; - fsl->data_len = tran_len + cmd_len; - spi_cs_activate(slave); - - /* Clear all eSPI events */ - out_be32(&espi->event , 0xffffffff); - /* handle data in 32-bit chunks */ - while (num_blks) { - event = in_be32(&espi->event); - if (event & ESPI_EV_TNF) { - fsl_espi_tx(fsl, dout); - /* Set up the next iteration */ - if (len > 4) { - len -= 4; - dout += 4; - } - } - - event = in_be32(&espi->event); - if (event & ESPI_EV_RNE) { - rf_cnt = ((event & ESPI_EV_RFCNT_MASK) - >> ESPI_EV_RFCNT_SHIFT); - if (rf_cnt >= 4) - rx_bytes = 4; - else if (num_blks == 1 && rf_cnt == num_bytes) - rx_bytes = num_bytes; - else - continue; - if (fsl_espi_rx(fsl, din, rx_bytes) - == rx_bytes) { - num_blks--; - if (din) - din = (unsigned char *)din - + rx_bytes; - } - } - } - if (data_in) { - memcpy(data_in, buffer + 2 * cmd_len, tran_len); - if (*buffer == 0x0b) { - data_in += tran_len; - data_len -= tran_len; - *(int *)buffer += tran_len; - } - } - spi_cs_deactivate(slave); - } - - free(buffer); - return 0; -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs < ESPI_MAX_CS_NUM; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = fsl->espi; - unsigned int com = 0; - size_t data_len = fsl->data_len; - - com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF)); - com |= ESPI_COM_CS(slave->cs); - com |= ESPI_COM_TRANLEN(data_len - 1); - out_be32(&espi->com, com); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = fsl->espi; - - /* clear the RXCNT and TXCNT */ - out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN)); - out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN); -} -- 2.14.3

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[U-Boot] armv5 and OMAP3 Question
by Adam Ford 04 Aug '18

04 Aug '18

The readme file for OMAP indicates that we compile using armv5 to "to allow more compilers to work" We have our arch/arm/mach-omap2/omap3/lowlevel_init.S file also noting some special assembly insturctions becuse we use armv5. The barriers defined also indicate we're using CP15 instead of the separate barrier instructions for armv7 because we're using armv5 instead. I just wonder in this day and age when we're noting a GCC version and generating warnings based on the GCC warning, do we still need to compile as armv5 any more? It seems like "to allow more compilers to work" would not really apply any more we're trying to push newer versions of GCC. (please don't flame me, I am honestly curious). adam

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[U-Boot] [PATCH] ARM: socfpga: Convert to DM serial
by Marek Vasut 04 Aug '18

04 Aug '18

Pull the serial port configuration from DT and use DM serial instead of having the serial configuration in two places, DT and board config. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <chin.liang.see(a)intel.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> --- arch/arm/Kconfig | 3 +++ arch/arm/dts/socfpga.dtsi | 2 ++ arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 1 + include/configs/socfpga_common.h | 8 -------- 4 files changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 532aa41a87..2012ac6410 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -737,6 +737,7 @@ config ARCH_SOCFPGA select ARCH_MISC_INIT select CPU_V7A select DM + select DM_SERIAL select ENABLE_ARM_SOC_BOOT0_HOOK select OF_CONTROL select SPL_LIBCOMMON_SUPPORT @@ -746,11 +747,13 @@ config ARCH_SOCFPGA select SPL_NAND_SUPPORT if SPL_NAND_DENALI select SPL_OF_CONTROL select SPL_SERIAL_SUPPORT + select SPL_DM_SERIAL select SPL_SPI_FLASH_SUPPORT if SPL_SPI_SUPPORT select SPL_SPI_SUPPORT if DM_SPI select SPL_WATCHDOG_SUPPORT select SUPPORT_SPL select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE + select SYS_NS16550 select SYS_THUMB_BUILD imply CMD_MTDPARTS imply CRC32_VERIFY diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index e64127fcb2..314449478d 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -737,6 +737,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&l4_sp_clk>; + clock-frequency = <100000000>; }; uart1: serial1@ffc03000 { @@ -746,6 +747,7 @@ reg-shift = <2>; reg-io-width = <4>; clocks = <&l4_sp_clk>; + clock-frequency = <100000000>; }; rst: rstmgr@ffd05000 { diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts index b573d0e658..06b61cb0af 100644 --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts @@ -24,6 +24,7 @@ }; &uart1 { + clock-frequency = <50000000>; u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 54b9edc97c..a60da85499 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -173,14 +173,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * Serial Driver */ #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) -#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS -#define CONFIG_SYS_NS16550_CLK 100000000 -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) -#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS -#define CONFIG_SYS_NS16550_CLK 50000000 -#endif /* * USB -- 2.16.2

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