June 2018 - U-Boot

[U-Boot] [PATCH] MIPS: add MIPS Release 6 build coverage for Boston boards
by Daniel Schwierzeck 29 Jun '18

29 Jun '18

Now that Travis CI is building with gcc-7.3.0, we can add build coverage for all combinations of MIPS Release 6 instruction sets (MIPS32, MIPS64, Big Endian, Little Endian). Add mew default configs for Boston board for all MIPS Release 6 variants. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> --- configs/boston32r6_defconfig | 41 +++++++++++++++++++++++++++++++++ configs/boston32r6el_defconfig | 42 ++++++++++++++++++++++++++++++++++ configs/boston64r6_defconfig | 41 +++++++++++++++++++++++++++++++++ configs/boston64r6el_defconfig | 42 ++++++++++++++++++++++++++++++++++ 4 files changed, 166 insertions(+) create mode 100644 configs/boston32r6_defconfig create mode 100644 configs/boston32r6el_defconfig create mode 100644 configs/boston64r6_defconfig create mode 100644 configs/boston64r6el_defconfig diff --git a/configs/boston32r6_defconfig b/configs/boston32r6_defconfig new file mode 100644 index 0000000000..1cd5667ce5 --- /dev/null +++ b/configs/boston32r6_defconfig @@ -0,0 +1,41 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x9FC00000 +CONFIG_TARGET_BOSTON=y +CONFIG_CPU_MIPS32_R6=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_BEST_MATCH=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_PROMPT="boston # " +# CONFIG_CMD_ELF is not set +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_PCI=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CFI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_PCH_GBE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_XILINX=y +CONFIG_SYS_NS16550=y +CONFIG_LZ4=y diff --git a/configs/boston32r6el_defconfig b/configs/boston32r6el_defconfig new file mode 100644 index 0000000000..c7f641c7d4 --- /dev/null +++ b/configs/boston32r6el_defconfig @@ -0,0 +1,42 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x9FC00000 +CONFIG_TARGET_BOSTON=y +CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32_R6=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_BEST_MATCH=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_PROMPT="boston # " +# CONFIG_CMD_ELF is not set +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_PCI=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CFI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_PCH_GBE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_XILINX=y +CONFIG_SYS_NS16550=y +CONFIG_LZ4=y diff --git a/configs/boston64r6_defconfig b/configs/boston64r6_defconfig new file mode 100644 index 0000000000..b4bb8a6d00 --- /dev/null +++ b/configs/boston64r6_defconfig @@ -0,0 +1,41 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0xFFFFFFFF9FC00000 +CONFIG_TARGET_BOSTON=y +CONFIG_CPU_MIPS64_R6=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_BEST_MATCH=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_PROMPT="boston # " +# CONFIG_CMD_ELF is not set +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_PCI=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CFI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_PCH_GBE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_XILINX=y +CONFIG_SYS_NS16550=y +CONFIG_LZ4=y diff --git a/configs/boston64r6el_defconfig b/configs/boston64r6el_defconfig new file mode 100644 index 0000000000..1cd4836b58 --- /dev/null +++ b/configs/boston64r6el_defconfig @@ -0,0 +1,42 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0xFFFFFFFF9FC00000 +CONFIG_TARGET_BOSTON=y +CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS64_R6=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_BEST_MATCH=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_PROMPT="boston # " +# CONFIG_CMD_ELF is not set +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_PCI=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CFI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_PCH_GBE=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PCI_XILINX=y +CONFIG_SYS_NS16550=y +CONFIG_LZ4=y -- 2.17.1

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[U-Boot] [PATCH] cpu: bmips: fix probe to get the address
by Philippe Reynes 29 Jun '18

29 Jun '18

In the device tree, the address for cpu is located in the node "cpus", not in the cpu node (for exemple cpu@0). So when probing cpu, the cpu address must be read in the cpu parent. The commit "cpu: bmips: convert to use live dt" (sha1: c444afbbefa103d567f197393d39ec0fcca21a0c) change this behaviour and read the address in the cpu node when probing cpu. We fix this by reading the address in the cpu parent. Signed-off-by: Philippe Reynes <philippe.reynes(a)softathome.com> --- drivers/cpu/bmips_cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c index f5bacd2..78560b0 100644 --- a/drivers/cpu/bmips_cpu.c +++ b/drivers/cpu/bmips_cpu.c @@ -407,7 +407,7 @@ int bmips_cpu_probe(struct udevice *dev) const struct bmips_cpu_hw *hw = (const struct bmips_cpu_hw *)dev_get_driver_data(dev); - priv->regs = dev_remap_addr(dev); + priv->regs = dev_remap_addr(dev_get_parent(dev)); if (!priv->regs) return -EINVAL; -- 2.7.4

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[U-Boot] [PATCH] led: bcm6328: read base address in the parent node
by Philippe Reynes 29 Jun '18

29 Jun '18

In the device tree, the address for the led is located in the parent node (for exemple leds), not in the led node (for exemple led@0). The commit "led: bcm6328: convert to use live dt" (sha1: 899455176058d673887a762aa38853188a030af4) change this behaviour and read the address in the led node. We fix this by reading the base address for led in the parent node. Signed-off-by: Philippe Reynes <philippe.reynes(a)softathome.com> --- drivers/led/led_bcm6328.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/led/led_bcm6328.c b/drivers/led/led_bcm6328.c index a29e5a0..7be4bad 100644 --- a/drivers/led/led_bcm6328.c +++ b/drivers/led/led_bcm6328.c @@ -173,7 +173,7 @@ static int bcm6328_led_probe(struct udevice *dev) struct bcm6328_led_priv *priv = dev_get_priv(dev); unsigned int pin; - priv->regs = dev_remap_addr(dev); + priv->regs = dev_remap_addr(dev_get_parent(dev)); if (!priv->regs) return -EINVAL; -- 2.7.4

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[U-Boot] Writes to FAT broken by bcm2835 sdhost driver
by Anton Gerasimov 29 Jun '18

29 Jun '18

[resending, forgot to subscribe from this address] Hi, For some reasons I need to save environment on RaspberryPi 3 and it worked well for me in older versions of u-boot, but stopped working in newer ones. Using bisect I figured out that the commits responsible for that were c8a73a26d6dd9b7d489e66529fe1412425d8f2d1 and caf2233b281c03e3e359061a3dfa537d8a25c273, introducing sdhost and pinctrl drivers respectively. Versions before these two work well wrt. writing to FAT/saving the environment. After these patches when compiled with rpi_3_32b_defconfig, reading works well, but fatwrite gives wait_transfer_complete - still waiting after 10001 retries and saveenv fsm 1, hsts 00000001 When I try to compile with CONFIG_MMC_BCM2835=n (CONFIG_MMC_SDHCI_BCM2835 is still enabled), neither read nor write works: Saving Environment to FAT... Card did not respond to voltage select! ** Bad device mmc 0 ** Failed (1) Finally with CONFIG_PINCTRL=n u-boot doesn't compile at all (not sure if it was intended behavior): serial_bcm283x_mu.c:162: undefined reference to `pinctrl_get_gpio_mux' serial_bcm283x_pl011.c:30: undefined reference to `pinctrl_get_gpio_mux' Would be grateful for any help with these issues. Best regargs, Anton Gerasimov

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[U-Boot] [PATCH] sf: Enable FSR polling on N25Q256(A)
by Marek Vasut 29 Jun '18

29 Jun '18

The N25Q256(A) datasheet clearly states that this device does have a Flag Status Register and does update FSR PEC bit 7 during Program and Erase cycles to indicate the cycle is in progress. Enable the FSR PEC bit polling on this device to prevent data corruption. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Jagan Teki <jagan(a)openedev.com> Cc: Tom Rini <trini(a)konsulko.com> --- drivers/mtd/spi/spi_flash_ids.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index 3b8f254ca2..fbc1bb6a5e 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -130,8 +130,8 @@ const struct spi_flash_info spi_flash_ids[] = { {"n25q64a", INFO(0x20bb17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, {"n25q128", INFO(0x20ba18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, {"n25q128a", INFO(0x20bb18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, - {"n25q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, - {"n25q256a", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, + {"n25q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {"n25q256a", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, {"n25q512", INFO(0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, {"n25q512a", INFO(0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, {"n25q1024", INFO(0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, -- 2.16.2

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[U-Boot] [for v2018.07 1/2] sunxi: Fix USB PHY index for H3 (missed chage)
by Jagan Teki 29 Jun '18

29 Jun '18

This patch update the USB PHY index for Allwinner H3. Same change[1] initially sent, by 'Chen-Yu Tai' but missed to apply due to recursive version changes on the same series. [1] https://lists.denx.de/pipermail/u-boot/2018-January/318817.html Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 8afeaf872e..3a59016955 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -275,9 +275,13 @@ struct sunxi_ccm_reg { * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call * them 0 - 2 like they were called on older SoCs. */ +#define AHB_GATE_OFFSET_USB_OHCI3 31 +#define AHB_GATE_OFFSET_USB_OHCI2 30 +#define AHB_GATE_OFFSET_USB_OHCI1 29 #define AHB_GATE_OFFSET_USB_OHCI0 28 -#define AHB_GATE_OFFSET_USB_EHCI2 27 -#define AHB_GATE_OFFSET_USB_EHCI1 26 +#define AHB_GATE_OFFSET_USB_EHCI3 27 +#define AHB_GATE_OFFSET_USB_EHCI2 26 +#define AHB_GATE_OFFSET_USB_EHCI1 25 #define AHB_GATE_OFFSET_USB_EHCI0 24 #elif defined(CONFIG_MACH_SUN50I) #define AHB_GATE_OFFSET_USB_OHCI0 28 @@ -290,7 +294,7 @@ struct sunxi_ccm_reg { #define AHB_GATE_OFFSET_USB_EHCI1 27 #define AHB_GATE_OFFSET_USB_EHCI0 26 #endif -#ifdef CONFIG_MACH_SUN50I +#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNXI_H3_H5) #define AHB_GATE_OFFSET_USB0 23 #elif !defined(CONFIG_MACH_SUN8I_R40) #define AHB_GATE_OFFSET_USB0 24 -- 2.17.1

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[U-Boot] [PATCH v3] x86: Use microcode update from device tree for all processors
by Bin Meng 29 Jun '18

29 Jun '18

From: Ivan Gorinov <ivan.gorinov(a)intel.com> Built without a ROM image with FSP (u-boot.rom), the U-Boot loader applies the microcode update data block encoded in Device Tree to the bootstrap processor but not passed to the other CPUs when multiprocessing is enabled. If the bootstrap processor successfully performs a microcode update from Device Tree, use the same data block for the other processors. Signed-off-by: Ivan Gorinov <ivan.gorinov(a)intel.com> Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> [bmeng: fixed build errors on edison and qemu-x86] Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v3: - don't change arch/x86/cpu/i386/cpu.c to fix build errors on edison and qemu-x86 arch/x86/cpu/intel_common/car.S | 2 ++ arch/x86/cpu/intel_common/microcode.c | 10 +++++++--- arch/x86/include/asm/microcode.h | 1 + arch/x86/lib/fsp/fsp_car.S | 4 +++- 4 files changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/x86/cpu/intel_common/car.S b/arch/x86/cpu/intel_common/car.S index fe8dfbc..52a77bb 100644 --- a/arch/x86/cpu/intel_common/car.S +++ b/arch/x86/cpu/intel_common/car.S @@ -239,4 +239,6 @@ _dt_ucode_base_size: .globl ucode_base ucode_base: /* Declared in microcode.h */ .long 0 /* microcode base */ +.globl ucode_size +ucode_size: /* Declared in microcode.h */ .long 0 /* microcode size */ diff --git a/arch/x86/cpu/intel_common/microcode.c b/arch/x86/cpu/intel_common/microcode.c index 11b1ec8..c7a539d 100644 --- a/arch/x86/cpu/intel_common/microcode.c +++ b/arch/x86/cpu/intel_common/microcode.c @@ -43,8 +43,6 @@ static int microcode_decode_node(const void *blob, int node, update->data = fdt_getprop(blob, node, "data", &update->size); if (!update->data) return -ENOENT; - update->data += UCODE_HEADER_LEN; - update->size -= UCODE_HEADER_LEN; update->header_version = fdtdec_get_int(blob, node, "intel,header-version", 0); @@ -124,6 +122,7 @@ static void microcode_read_cpu(struct microcode_update *cpu) int microcode_update_intel(void) { struct microcode_update cpu, update; + ulong address; const void *blob = gd->fdt_blob; int skipped; int count; @@ -167,7 +166,8 @@ int microcode_update_intel(void) skipped++; continue; } - wrmsr(MSR_IA32_UCODE_WRITE, (ulong)update.data, 0); + address = (ulong)update.data + UCODE_HEADER_LEN; + wrmsr(MSR_IA32_UCODE_WRITE, address, 0); rev = microcode_read_rev(); debug("microcode: updated to revision 0x%x date=%04x-%02x-%02x\n", rev, update.date_code & 0xffff, @@ -178,5 +178,9 @@ int microcode_update_intel(void) return -EFAULT; } count++; + if (!ucode_base) { + ucode_base = (ulong)update.data; + ucode_size = update.size; + } } while (1); } diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index f7b32a5..4ab7504 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -10,6 +10,7 @@ /* This is a declaration for ucode_base in start.S */ extern u32 ucode_base; +extern u32 ucode_size; /** * microcode_update_intel() - Apply microcode updates diff --git a/arch/x86/lib/fsp/fsp_car.S b/arch/x86/lib/fsp/fsp_car.S index 549d863..48edc83 100644 --- a/arch/x86/lib/fsp/fsp_car.S +++ b/arch/x86/lib/fsp/fsp_car.S @@ -102,8 +102,10 @@ temp_ram_init_params: _dt_ucode_base_size: /* These next two fields are filled in by ifdtool */ .globl ucode_base -ucode_base: /* Declared in micrcode.h */ +ucode_base: /* Declared in microcode.h */ .long 0 /* microcode base */ +.globl ucode_size +ucode_size: /* Declared in microcode.h */ .long 0 /* microcode size */ .long CONFIG_SYS_MONITOR_BASE /* code region base */ .long CONFIG_SYS_MONITOR_LEN /* code region size */ -- 2.7.4

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[U-Boot] [PATCH v2] dm: sunxi: Use DM for MMC and SATA on all A20 boards
by Adam Sampson 29 Jun '18

29 Jun '18

Generalise the change in commit 3936514b82e8 ("dm: sunxi: Move Linksprite_pcDuino3 to use DM for MMC, SATA") so it applies to all A20 boards: use the driver model for MMC and SATA, in preparation for CONFIG_BLK defaulting to y. Tested on Linksprite pcDuino3 Nano. Signed-off-by: Adam Sampson <ats(a)offog.org> --- Changes for v2: - at Maxime's suggestion, enabled by default at the Kconfig level for all A20 boards (which means the one board Simon updated previously doesn't need to specify them any more) arch/arm/mach-sunxi/Kconfig | 2 ++ configs/Linksprite_pcDuino3_defconfig | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index a3f7723028..78f76f52d0 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -174,6 +174,8 @@ config MACH_SUN7I select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI + select DM_MMC + select DM_SCSI if SCSI select DRAM_SUN4I select PHY_SUN4I_USB select SUNXI_GEN_SUN4I diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index d7e9c26cbf..f987cef711 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -13,10 +13,8 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_SCSI_AHCI=y -CONFIG_DM_MMC=y CONFIG_ETH_DESIGNWARE=y CONFIG_SUN7I_GMAC=y CONFIG_SCSI=y -CONFIG_DM_SCSI=y CONFIG_USB_EHCI_HCD=y CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y -- 2.18.0

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[U-Boot] [UBOOT PATCH v4 0/4] spi:xilinx_spi: Modify xilinx spi driver
by Vipul Kumar 29 Jun '18

29 Jun '18

This series of patches do the following: - This patch added support to get reg base address from DTS file - Added rxfifo() and txfifo() functions to add the modularity - Added support to read JEDEC-id twice at the boot time - Added live-tree support Changes in v2: - Split single patch into the series of patches Changes in v3: - Read reg in probe function - Removed xilinx_spi_ofdata_to_platdata function - Added fifo_depth read support in 2/3 and removed from 1/3 Changes in v4: - Moved static startup variable to private structure - Added live-tree support Michal Simek (1): spi: xilinx: Read reg base address from DTS file Vipul Kumar (3): spi: xilinx_spi: Modify transfer logic xilinx_spi_xfer() function spi: xilinx_spi: Added support to read JEDEC-id twice at the boot time spi: xilinx_spi: convert to livetree drivers/spi/xilinx_spi.c | 152 ++++++++++++++++++++++++++++++++++------------- 1 file changed, 110 insertions(+), 42 deletions(-) -- 2.7.4

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[U-Boot] [PATCH] spi: omap3: fix claim/release bus within DM
by Hannes Schmelzer 28 Jun '18

28 Jun '18

The claim/release bus function must not reset the whole SPI core because settings regarding wordlen, clock-frequency and so on made by set_wordlen, set_mode, set_speed get lost with this action. Resulting in a non-functional SPI. Without DM the failure didn't came up since after the spi_reset within claim bus all the setup (wordlen, mode, ...) was called, in DM they are called by the spi uclass. We change now the things as following for having a working SPI instance in DM: - move the spi_reset(...) to the probe call in DM for having a known hardware state after probe. Without DM we don't have a probe call, so we issue the reset as before during the claim_bus call. - in release bus we just reset the modulctrl to the reset-value (spi- slave) Signed-off-by: Hannes Schmelzer <oe5hpm(a)oevsv.at> --- drivers/spi/omap3_spi.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 4169abd..41bdab7 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -443,9 +443,6 @@ static void spi_reset(struct mcspi *regs) static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv) { unsigned int conf; - - spi_reset(priv->regs); - /* * setup when switching from (reset default) slave mode * to single-channel master mode @@ -480,6 +477,8 @@ int spi_claim_bus(struct spi_slave *slave) { struct omap3_spi_priv *priv = to_omap3_spi(slave); + spi_reset(priv->regs); + _omap3_spi_claim_bus(priv); _omap3_spi_set_wordlen(priv); _omap3_spi_set_mode(priv); @@ -492,8 +491,7 @@ void spi_release_bus(struct spi_slave *slave) { struct omap3_spi_priv *priv = to_omap3_spi(slave); - /* Reset the SPI hardware */ - spi_reset(priv->regs); + writel(OMAP3_MCSPI_MODULCTRL_MS, &priv->regs->modulctrl); } struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, @@ -600,8 +598,7 @@ static int omap3_spi_release_bus(struct udevice *dev) struct udevice *bus = dev->parent; struct omap3_spi_priv *priv = dev_get_priv(bus); - /* Reset the SPI hardware */ - spi_reset(priv->regs); + writel(OMAP3_MCSPI_MODULCTRL_MS, &priv->regs->modulctrl); return 0; } @@ -634,6 +631,9 @@ static int omap3_spi_probe(struct udevice *dev) else priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT; priv->wordlen = SPI_DEFAULT_WORDLEN; + + spi_reset(priv->regs); + return 0; } -- 2.7.4

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