February 2018 - U-Boot

[U-Boot] [PATCH] host-tools: use python2 explicitly for shebang
by Masahiro Yamada 04 Feb '18

04 Feb '18

All of these host tools are apparently written for Python2, not Python3. Use 'python2' in the shebang line according to PEP 394 (https://www.python.org/dev/peps/pep-0394/). Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- I sent some time before figuring out why Patman does not work on my machine. If 'python' points to python3, Patman does not epit any error message, it just stays silent until it consumes all memory on the system. scripts/dtc/pylibfdt/setup.py | 2 +- scripts/mailmapper | 2 +- test/py/test.py | 2 +- tools/buildman/buildman.py | 2 +- tools/dtoc/dtoc.py | 2 +- tools/microcode-tool.py | 2 +- tools/patman/patman.py | 2 +- tools/rkmux.py | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/scripts/dtc/pylibfdt/setup.py b/scripts/dtc/pylibfdt/setup.py index daf1089..4f7cf04 100755 --- a/scripts/dtc/pylibfdt/setup.py +++ b/scripts/dtc/pylibfdt/setup.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python2 """ setup.py file for SWIG libfdt diff --git a/scripts/mailmapper b/scripts/mailmapper index 922ada6..78b23d1 100755 --- a/scripts/mailmapper +++ b/scripts/mailmapper @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python2 # # Copyright (C) 2014, Masahiro Yamada <yamada.m(a)jp.panasonic.com> # diff --git a/test/py/test.py b/test/py/test.py index 74e560a..4695079 100755 --- a/test/py/test.py +++ b/test/py/test.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python2 # Copyright (c) 2015 Stephen Warren # Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. diff --git a/tools/buildman/buildman.py b/tools/buildman/buildman.py index 11a4f16..473117c 100755 --- a/tools/buildman/buildman.py +++ b/tools/buildman/buildman.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python2 # # Copyright (c) 2012 The Chromium OS Authors. # diff --git a/tools/dtoc/dtoc.py b/tools/dtoc/dtoc.py index ce7bc05..6eacfc9 100755 --- a/tools/dtoc/dtoc.py +++ b/tools/dtoc/dtoc.py @@ -1,4 +1,4 @@ -#!/usr/bin/python +#!/usr/bin/env python2 # # Copyright (C) 2016 Google, Inc # Written by Simon Glass <sjg(a)chromium.org> diff --git a/tools/microcode-tool.py b/tools/microcode-tool.py index 790c27e..069d961 100755 --- a/tools/microcode-tool.py +++ b/tools/microcode-tool.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python2 # # Copyright (c) 2014 Google, Inc # diff --git a/tools/patman/patman.py b/tools/patman/patman.py index 4b3bc78..7647440 100755 --- a/tools/patman/patman.py +++ b/tools/patman/patman.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python2 # # Copyright (c) 2011 The Chromium OS Authors. # diff --git a/tools/rkmux.py b/tools/rkmux.py index 3917335..11c192a 100755 --- a/tools/rkmux.py +++ b/tools/rkmux.py @@ -1,4 +1,4 @@ -#!/usr/bin/python +#!/usr/bin/env python2 # Script to create enums from datasheet register tables # -- 2.7.4

3 6

[U-Boot] [PATCH 0/4] Add support for treating compiler warnings as errors
by Daniel Schwierzeck 04 Feb '18

04 Feb '18

To enforce a zero-warnings policy (e.g. in CI builds), all compiler warnings have to be treated as errors. Extend Kbuild and buildman with according options to achieve this. Enable these new options in all Travis CI builds. All builds with compiler warnings will now fail. Only DTC warnings are still being ignored. Example build which failed due to a compiler warning: https://travis-ci.org/danielschwierzeck/u-boot/jobs/333349371#L936 Daniel Schwierzeck (4): Kbuild: support W=[N,]err for passing '-Werror' to the compiler buildman: add option -E for treating compiler warnings as errors travis.yml: fix 'set +e' in build script travis.yml: run buildman with option -E .travis.yml | 5 ++--- scripts/Makefile.extrawarn | 3 +++ tools/buildman/builder.py | 5 ++++- tools/buildman/builderthread.py | 2 ++ tools/buildman/cmdline.py | 2 ++ tools/buildman/control.py | 3 ++- 6 files changed, 15 insertions(+), 5 deletions(-) -- 2.16.1

3 9

[U-Boot] [PATCH 00/16] efi_loader: implement driver management
by Heinrich Schuchardt 04 Feb '18

04 Feb '18

This series implements the OpenProtocolInformation, ConnectController, and DisconnectController boot services. The EFI application creating a new device will call ConnectController to request the installation of all necessary drivers. Before deleting the device it will call DisconectController to remove all child controllers and to detach the driver. E.g. iPXE may be used to connect an iSCSI target. It then creates a handle by installing the EFI_BLOCK_IO_PROTOCOL. It calls ConnectController and expects U-Boot to create the partition handles and to provide the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL. (The driver connecting to the EFI_BLOCK_IO_PROTOCOL is not yet implemented in U-Boot.) A self test is provided for the driver management. The bootefi selftest now creates colored output. Two bug fixes are included. To complete the implementation of the EFI boot services the following future work is needed: * manage events in a linked list (see Rob's proposal) * implement ReinstallProtocol and RegisterProtocolNotify Heinrich Schuchardt (16): efi_selftest: colored test output efi_loader: simplify efi_remove_all_protocols efi_selftest: do not try to close device path protocol efi_loader: list of open protocol infos efi_loader: open_info in OpenProtocol efi_loader: open_info in CloseProtocol efi_loader: implement OpenProtocolInformation efi_loader: debug output installed device path efi_loader: implement ConnectController efi_loader: fix signature of efi_disconnect_controller efi_loader: implement DisconnectController efi_loader: disconnect controllers in UninstallProtocol efi_selftest: remove todo in manage protocols efi_selftest: remove todo in device path test efi_selftest: test for (Dis)ConnectController efi_loader: consistently use efi_handle_t for handles cmd/bootefi.c | 10 +- include/efi_api.h | 48 +- include/efi_loader.h | 31 +- include/efi_selftest.h | 27 +- lib/efi_loader/efi_boottime.c | 757 +++++++++++++++++++++--- lib/efi_loader/efi_console.c | 6 +- lib/efi_selftest/Makefile | 1 + lib/efi_selftest/efi_selftest.c | 25 +- lib/efi_selftest/efi_selftest_console.c | 13 +- lib/efi_selftest/efi_selftest_controllers.c | 385 ++++++++++++ lib/efi_selftest/efi_selftest_devicepath.c | 48 +- lib/efi_selftest/efi_selftest_manageprotocols.c | 22 +- 12 files changed, 1209 insertions(+), 164 deletions(-) create mode 100644 lib/efi_selftest/efi_selftest_controllers.c -- 2.14.2

2 35

[U-Boot] [PATCH v2] sandbox: Add 64-bit sandbox
by Mario Six 04 Feb '18

04 Feb '18

From: Mario Six <six(a)gdsys.cc> To debug device tree issues involving 32- and 64-bit platforms, it is useful to have a generic 64-bit platform available. Add a version of the sandbox that uses 64-bit integers for its physical addresses as well as a modified device tree. Signed-off-by: Mario Six <mario.six(a)gdsys.cc> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- v1 -> v2: * Renamed CONFIG_SANDBOX_64BIT to CONFIG_HOST_64BIT to make semantics more easily understandable * Switched control of integer width to depend on CONFIG_PHYS_64BIT instead of CONFIG_SANDBOX64 * Extended the sandbox README with information about the 64-bit sandbox --- arch/sandbox/Kconfig | 16 +- arch/sandbox/cpu/cpu.c | 2 +- arch/sandbox/dts/Makefile | 4 + arch/sandbox/dts/sandbox64.dts | 317 +++++++++++++++++++++++++++++++++++++++ arch/sandbox/include/asm/io.h | 6 + arch/sandbox/include/asm/types.h | 17 ++- board/sandbox/README.sandbox | 7 +- cmd/demo.c | 6 +- configs/sandbox64_defconfig | 200 ++++++++++++++++++++++++ drivers/demo/demo-simple.c | 2 +- 10 files changed, 561 insertions(+), 16 deletions(-) create mode 100644 arch/sandbox/dts/sandbox64.dts create mode 100644 configs/sandbox64_defconfig diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index 87418e3986..2a08533c4b 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -10,6 +10,11 @@ config SYS_BOARD config SYS_CPU default "sandbox" +config SANDBOX64 + bool "Use 64-bit addresses" + select PHYS_64BIT + select HOST_64BIT + config SANDBOX_SPL bool "Enable SPL for sandbox" select SUPPORT_SPL @@ -20,24 +25,25 @@ config SYS_CONFIG_NAME choice prompt "Run sandbox on 32/64-bit host" - default SANDBOX_64BIT + default HOST_64BIT help Sandbox can be built on 32-bit and 64-bit hosts. The default is to build on a 64-bit host and run on a 64-bit host. If you want to run sandbox on a 32-bit host, change it here. -config SANDBOX_32BIT +config HOST_32BIT bool "32-bit host" + depends on !PHYS_64BIT -config SANDBOX_64BIT +config HOST_64BIT bool "64-bit host" endchoice config SANDBOX_BITS_PER_LONG int - default 32 if SANDBOX_32BIT - default 64 if SANDBOX_64BIT + default 32 if HOST_32BIT + default 64 if HOST_64BIT endmenu diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 66c3a6a88a..4a20fde787 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -76,7 +76,7 @@ void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) if (enable_pci_map && !pci_map_physmem(paddr, &len, &map_dev, &ptr)) { if (plen != len) { printf("%s: Warning: partial map at %x, wanted %lx, got %lx\n", - __func__, paddr, len, plen); + __func__, (uint)paddr, len, plen); } map_len = len; return ptr; diff --git a/arch/sandbox/dts/Makefile b/arch/sandbox/dts/Makefile index 0197569262..861b4dc2b1 100644 --- a/arch/sandbox/dts/Makefile +++ b/arch/sandbox/dts/Makefile @@ -2,7 +2,11 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SANDBOX64 +dtb-$(CONFIG_SANDBOX) += sandbox64.dtb +else dtb-$(CONFIG_SANDBOX) += sandbox.dtb +endif dtb-$(CONFIG_UT_DM) += test.dtb targets += $(dtb-y) diff --git a/arch/sandbox/dts/sandbox64.dts b/arch/sandbox/dts/sandbox64.dts new file mode 100644 index 0000000000..18be889db6 --- /dev/null +++ b/arch/sandbox/dts/sandbox64.dts @@ -0,0 +1,317 @@ +/dts-v1/; + +#define USB_CLASS_HUB 9 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "sandbox"; + + aliases { + eth5 = "/eth@90000000"; + i2c0 = &i2c_0; + pci0 = &pci; + rtc0 = &rtc_0; + }; + + chosen { + stdout-path = "/serial"; + }; + + cros_ec: cros-ec@0 { + reg = <0 0 0 0>; + compatible = "google,cros-ec-sandbox"; + + /* + * This describes the flash memory within the EC. Note + * that the STM32L flash erases to 0, not 0xff. + */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0>; + #address-cells = <1>; + #size-cells = <1>; + + /* Information for sandbox */ + ro { + reg = <0 0xf000>; + }; + wp-ro { + reg = <0xf000 0x1000>; + }; + rw { + reg = <0x10000 0x10000>; + }; + }; + }; + + eth@10002000 { + compatible = "sandbox,eth"; + reg = <0x0 0x10002000 0x0 0x1000>; + fake-host-hwaddr = [00 00 66 44 22 00]; + }; + + eth@80000000 { + compatible = "sandbox,eth-raw"; + reg = <0x0 0x80000000 0x0 0x1000>; + host-raw-interface = "eth0"; + }; + + eth@90000000 { + compatible = "sandbox,eth-raw"; + reg = <0x0 0x90000000 0x0 0x1000>; + host-raw-interface = "lo"; + }; + + gpio_a: gpios@0 { + gpio-controller; + compatible = "sandbox,gpio"; + #gpio-cells = <1>; + gpio-bank-name = "a"; + num-gpios = <20>; + }; + + gpio_b: gpios@1 { + gpio-controller; + compatible = "sandbox,gpio"; + #gpio-cells = <2>; + gpio-bank-name = "b"; + num-gpios = <10>; + }; + + hexagon { + compatible = "demo-simple"; + colour = "white"; + sides = <6>; + }; + + i2c_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0 0 0>; + compatible = "sandbox,i2c"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + eeprom@2c { + reg = <0x2c>; + compatible = "i2c-eeprom"; + emul { + compatible = "sandbox,i2c-eeprom"; + sandbox,filename = "i2c.bin"; + sandbox,size = <128>; + }; + }; + + rtc_0: rtc@43 { + reg = <0x43>; + compatible = "sandbox-rtc"; + emul { + compatible = "sandbox,i2c-rtc"; + }; + }; + sandbox_pmic: sandbox_pmic { + reg = <0x40>; + }; + }; + + lcd { + u-boot,dm-pre-reloc; + compatible = "sandbox,lcd-sdl"; + xres = <1366>; + yres = <768>; + }; + + leds { + compatible = "gpio-leds"; + + iracibble { + gpios = <&gpio_a 1 0>; + label = "sandbox:red"; + }; + + martinet { + gpios = <&gpio_a 2 0>; + label = "sandbox:green"; + }; + }; + + pci: pci-controller { + compatible = "sandbox,pci"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0 0x10000000 0 0x10000000 0 0x2000 + 0x01000000 0 0x20000000 0 0x20000000 0 0x2000>; + pci@1f,0 { + compatible = "pci-generic"; + reg = <0xf800 0 0 0 0>; + emul@1f,0 { + compatible = "sandbox,swap-case"; + }; + }; + }; + + pinctrl { + compatible = "sandbox,pinctrl"; + + pinctrl_i2c0: i2c0 { + groups = "i2c"; + function = "i2c"; + bias-pull-up; + }; + + pinctrl_serial0: uart0 { + groups = "serial_a"; + function = "serial"; + }; + }; + + reset@1 { + compatible = "sandbox,reset"; + }; + + spi@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0 0 0>; + compatible = "sandbox,spi"; + cs-gpios = <0>, <&gpio_a 0>; + firmware_storage_spi: flash@0 { + reg = <0>; + compatible = "spansion,m25p16", "sandbox,spi-flash"; + spi-max-frequency = <40000000>; + sandbox,filename = "spi.bin"; + }; + }; + + spl-test { + u-boot,dm-pre-reloc; + compatible = "sandbox,spl-test"; + boolval; + intval = <1>; + intarray = <2 3 4>; + byteval = [05]; + bytearray = [06]; + longbytearray = [09 0a 0b 0c 0d 0e 0f 10 11]; + stringval = "message"; + stringarray = "multi-word", "message"; + }; + + spl-test2 { + u-boot,dm-pre-reloc; + compatible = "sandbox,spl-test"; + intval = <3>; + intarray = <5>; + byteval = [08]; + bytearray = [01 23 34]; + longbytearray = [09 0a 0b 0c]; + stringval = "message2"; + stringarray = "another", "multi-word", "message"; + }; + + spl-test3 { + u-boot,dm-pre-reloc; + compatible = "sandbox,spl-test"; + stringarray = "one"; + }; + + spl-test4 { + u-boot,dm-pre-reloc; + compatible = "sandbox,spl-test.2"; + }; + + square { + compatible = "demo-shape"; + colour = "blue"; + sides = <4>; + }; + + timer { + compatible = "sandbox,timer"; + clock-frequency = <1000000>; + }; + + tpm { + compatible = "google,sandbox-tpm"; + }; + + triangle { + compatible = "demo-shape"; + colour = "cyan"; + sides = <3>; + character = <83>; + light-gpios = <&gpio_a 2>, <&gpio_b 6 0>; + }; + + /* Needs to be available prior to relocation */ + uart0: serial { + compatible = "sandbox,serial"; + sandbox,text-colour = "cyan"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_serial0>; + }; + + usb@0 { + compatible = "sandbox,usb"; + status = "disabled"; + hub { + compatible = "sandbox,usb-hub"; + #address-cells = <1>; + #size-cells = <0>; + flash-stick { + reg = <0>; + compatible = "sandbox,usb-flash"; + }; + }; + }; + + usb@1 { + compatible = "sandbox,usb"; + hub { + compatible = "usb-hub"; + usb,device-class = <USB_CLASS_HUB>; + hub-emul { + compatible = "sandbox,usb-hub"; + #address-cells = <1>; + #size-cells = <0>; + flash-stick { + reg = <0>; + compatible = "sandbox,usb-flash"; + sandbox,filepath = "flash.bin"; + }; + }; + }; + }; + + usb@2 { + compatible = "sandbox,usb"; + status = "disabled"; + }; + + spmi: spmi@0 { + compatible = "sandbox,spmi"; + #address-cells = <0x1>; + #size-cells = <0x1>; + pm8916@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 0x1>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + spmi_gpios: gpios@c000 { + compatible = "qcom,pm8916-gpio"; + reg = <0xc000 0x400>; + gpio-controller; + gpio-count = <4>; + #gpio-cells = <2>; + gpio-bank-name="spmi"; + }; + }; + }; +}; + +#include "cros-ec-keyboard.dtsi" +#include "sandbox_pmic.dtsi" diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h index 59729f5635..8aacbaa817 100644 --- a/arch/sandbox/include/asm/io.h +++ b/arch/sandbox/include/asm/io.h @@ -43,9 +43,15 @@ phys_addr_t map_to_sysmem(const void *ptr); #define readb(addr) ((void)addr, 0) #define readw(addr) ((void)addr, 0) #define readl(addr) ((void)addr, 0) +#ifdef CONFIG_SANDBOX64 +#define readq(addr) ((void)addr, 0) +#endif #define writeb(v, addr) ((void)addr) #define writew(v, addr) ((void)addr) #define writel(v, addr) ((void)addr) +#ifdef CONFIG_SANDBOX64 +#define writeq(v, addr) ((void)addr) +#endif /* * Clear and set bits in one shot. These macros can be used to clear and diff --git a/arch/sandbox/include/asm/types.h b/arch/sandbox/include/asm/types.h index 623cdafefa..6657f3a7b9 100644 --- a/arch/sandbox/include/asm/types.h +++ b/arch/sandbox/include/asm/types.h @@ -51,14 +51,23 @@ typedef __UINT64_TYPE__ u64; #endif /* - * Number of bits in a C 'long' on this architecture. Set this to 32 when - * building on a 32-bit machine. + * Number of bits in a C 'long' on this architecture. */ -#define BITS_PER_LONG 32 - +#ifdef CONFIG_PHYS64 +#define BITS_PER_LONG 64 +#else /* CONFIG_PHYS64 */ +#define BITS_PER_LONG 32 +#endif /* CONFIG_PHYS64 */ + +#ifdef CONFIG_PHYS64 +typedef unsigned long long dma_addr_t; +typedef u64 phys_addr_t; +typedef u64 phys_size_t; +#else /* CONFIG_PHYS64 */ typedef unsigned long dma_addr_t; typedef u32 phys_addr_t; typedef u32 phys_size_t; +#endif /* CONFIG_PHYS64 */ #endif /* __KERNEL__ */ diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox index 9bc13e142b..760866f1c3 100644 --- a/board/sandbox/README.sandbox +++ b/board/sandbox/README.sandbox @@ -24,8 +24,11 @@ single board in board/sandbox. CONFIG_SANDBOX_BIG_ENDIAN should be defined when running on big-endian machines. -By default sandbox builds and runs on 64-bit hosts. If you are going to build -and run sandbox on a 32-bit host, select CONFIG_SANDBOX_32BIT. +There are two versions of the sandbox: One using 32-bit-wide integers, and one +using 64-bit-wide integers. The 32-bit version can be build and run on either +32 or 64-bit hosts by either selecting or deselecting CONFIG_SANDBOX_32BIT; by +default, the sandbox it built for a 32-bit host. The sandbox using 64-bit-wide +integers can only be built on 64-bit hosts. Note that standalone/API support is not available at present. diff --git a/cmd/demo.c b/cmd/demo.c index 209dc4a57c..bf14f7b1c5 100644 --- a/cmd/demo.c +++ b/cmd/demo.c @@ -71,9 +71,9 @@ int do_demo_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) dev; ret = uclass_next_device(&dev)) { printf("entry %d - instance %08x, ops %08x, platdata %08x\n", - i++, map_to_sysmem(dev), - map_to_sysmem(dev->driver->ops), - map_to_sysmem(dev_get_platdata(dev))); + i++, (uint)map_to_sysmem(dev), + (uint)map_to_sysmem(dev->driver->ops), + (uint)map_to_sysmem(dev_get_platdata(dev))); } return cmd_process_error(cmdtp, ret); diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig new file mode 100644 index 0000000000..85b339936f --- /dev/null +++ b/configs/sandbox64_defconfig @@ -0,0 +1,200 @@ +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SANDBOX64=y +CONFIG_DEFAULT_DEVICE_TREE="sandbox64" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_BOOTSTAGE_FDT=y +CONFIG_BOOTSTAGE_STASH=y +CONFIG_BOOTSTAGE_STASH_ADDR=0x0 +CONFIG_BOOTSTAGE_STASH_SIZE=0x4096 +CONFIG_CONSOLE_RECORD=y +CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000 +CONFIG_SILENT_CONSOLE=y +CONFIG_PRE_CONSOLE_BUFFER=y +CONFIG_PRE_CON_BUF_ADDR=0x100000 +CONFIG_LOG=y +CONFIG_LOG_MAX_LEVEL=6 +CONFIG_CMD_CPU=y +CONFIG_CMD_LICENSE=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_ELF is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_ENV_CALLBACK=y +CONFIG_CMD_ENV_FLAGS=y +CONFIG_LOOPW=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MX_CYCLIC=y +CONFIG_CMD_DEMO=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_IDE=y +CONFIG_CMD_I2C=y +CONFIG_CMD_PCI=y +CONFIG_CMD_READ=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TFTPSRV=y +CONFIG_CMD_RARP=y +CONFIG_CMD_CDP=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_ETHSW=y +CONFIG_CMD_BMP=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_SOUND=y +CONFIG_CMD_QFW=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_TPM=y +CONFIG_CMD_TPM_TEST=y +CONFIG_CMD_BTRFS=y +CONFIG_CMD_CBFS=y +CONFIG_CMD_CRAMFS=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_LOG=y +CONFIG_MAC_PARTITION=y +CONFIG_AMIGA_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_HOSTFILE=y +CONFIG_NETCONSOLE=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DEVRES=y +CONFIG_DEBUG_DEVRES=y +CONFIG_ADC=y +CONFIG_ADC_SANDBOX=y +CONFIG_CLK=y +CONFIG_CPU=y +CONFIG_DM_DEMO=y +CONFIG_DM_DEMO_SIMPLE=y +CONFIG_DM_DEMO_SHAPE=y +CONFIG_PM8916_GPIO=y +CONFIG_SANDBOX_GPIO=y +CONFIG_DM_I2C_COMPAT=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_I2C_CROS_EC_LDO=y +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_SANDBOX=y +CONFIG_I2C_MUX=y +CONFIG_SPL_I2C_MUX=y +CONFIG_I2C_ARB_GPIO_CHALLENGE=y +CONFIG_CROS_EC_KEYB=y +CONFIG_I8042_KEYB=y +CONFIG_LED=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_SANDBOX_MBOX=y +CONFIG_MISC=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_I2C=y +CONFIG_CROS_EC_LPC=y +CONFIG_CROS_EC_SANDBOX=y +CONFIG_CROS_EC_SPI=y +CONFIG_PWRSEQ=y +CONFIG_SPL_PWRSEQ=y +CONFIG_I2C_EEPROM=y +CONFIG_MMC_SANDBOX=y +CONFIG_SPI_FLASH_SANDBOX=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_NVME=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_SANDBOX=y +CONFIG_PHY=y +CONFIG_PHY_SANDBOX=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_ROCKCHIP_RK3036=y +CONFIG_PINCTRL_ROCKCHIP_RK3288=y +CONFIG_PINCTRL_SANDBOX=y +CONFIG_POWER_DOMAIN=y +CONFIG_SANDBOX_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_ACT8846=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_PMIC_MAX77686=y +CONFIG_PMIC_PM8916=y +CONFIG_PMIC_RK8XX=y +CONFIG_PMIC_S2MPS11=y +CONFIG_DM_PMIC_SANDBOX=y +CONFIG_PMIC_S5M8767=y +CONFIG_PMIC_TPS65090=y +CONFIG_DM_REGULATOR=y +CONFIG_REGULATOR_ACT8846=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_MAX77686=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_REGULATOR_S5M8767=y +CONFIG_DM_REGULATOR_SANDBOX=y +CONFIG_REGULATOR_TPS65090=y +CONFIG_DM_PWM=y +CONFIG_PWM_SANDBOX=y +CONFIG_RAM=y +CONFIG_REMOTEPROC_SANDBOX=y +CONFIG_DM_RESET=y +CONFIG_SANDBOX_RESET=y +CONFIG_DM_RTC=y +CONFIG_SANDBOX_SERIAL=y +CONFIG_SOUND=y +CONFIG_SOUND_SANDBOX=y +CONFIG_SANDBOX_SPI=y +CONFIG_SPMI=y +CONFIG_SPMI_SANDBOX=y +CONFIG_SYSRESET=y +CONFIG_TIMER=y +CONFIG_TIMER_EARLY=y +CONFIG_SANDBOX_TIMER=y +CONFIG_TPM_TIS_SANDBOX=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EMUL=y +CONFIG_USB_STORAGE=y +CONFIG_USB_KEYBOARD=y +CONFIG_DM_VIDEO=y +CONFIG_CONSOLE_ROTATION=y +CONFIG_CONSOLE_TRUETYPE=y +CONFIG_CONSOLE_TRUETYPE_CANTORAONE=y +CONFIG_VIDEO_SANDBOX_SDL=y +CONFIG_WDT=y +CONFIG_WDT_SANDBOX=y +CONFIG_FS_CBFS=y +CONFIG_FS_CRAMFS=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_TPM=y +CONFIG_LZ4=y +CONFIG_ERRNO_STR=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_UNIT_TEST=y +CONFIG_UT_TIME=y +CONFIG_UT_DM=y +CONFIG_UT_ENV=y +CONFIG_UT_OVERLAY=y diff --git a/drivers/demo/demo-simple.c b/drivers/demo/demo-simple.c index f069748e05..d05b1dfd87 100644 --- a/drivers/demo/demo-simple.c +++ b/drivers/demo/demo-simple.c @@ -17,7 +17,7 @@ static int simple_hello(struct udevice *dev, int ch) { const struct dm_demo_pdata *pdata = dev_get_platdata(dev); - printf("Hello from %08x: %s %d\n", map_to_sysmem(dev), pdata->colour, + printf("Hello from %08x: %s %d\n", (uint)map_to_sysmem(dev), pdata->colour, pdata->sides); return 0; -- 2.11.0

2 2

[U-Boot] [PATCH] doc: mxc_hab: Improve the config option list
by Fabio Estevam 04 Feb '18

04 Feb '18

From: Fabio Estevam <fabio.estevam(a)nxp.com> The original text is from the time that the config options were not converted to Kconfig. After the conversion to Kconfig only CONFIG_SECURE_BOOT and CONFIG_CMD_DEKBLOB need to be selected by the user. The other config options are automatically selected by the Kconfig logic. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- doc/README.mxc_hab | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/doc/README.mxc_hab b/doc/README.mxc_hab index c1f8ded..4bd07d3 100644 --- a/doc/README.mxc_hab +++ b/doc/README.mxc_hab @@ -68,13 +68,10 @@ the CSF file. The DEK blob is generated by an authenticated U-Boot image with the dek_blob cmd enabled. The image used for DEK blob generation -needs to have the following configurations enabled: +needs to have the following configurations enabled in Kconfig: -CONFIG_SECURE_BOOT -CONFIG_SYS_FSL_SEC_COMPAT 4 /* HAB version */ -CONFIG_FSL_CAAM -CONFIG_CMD_DEKBLOB -CONFIG_SYS_FSL_SEC_LE +CONFIG_SECURE_BOOT=y +CONFIG_CMD_DEKBLOB=y Note: The encrypted boot feature is only supported by HABv4 or greater. -- 2.7.4

3 2

[U-Boot] [PATCH] arm: dts: imx6ull: move input include to base device tree
by Stefan Agner 04 Feb '18

04 Feb '18

From: Stefan Agner <stefan.agner(a)toradex.com> The input keycode KEY_POWER is used in the imx6ull.dtsi file, hence include the input header where used. Signed-off-by: Stefan Agner <stefan.agner(a)toradex.com> --- arch/arm/dts/imx6ull-14x14-evk.dts | 1 - arch/arm/dts/imx6ull.dtsi | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/imx6ull-14x14-evk.dts b/arch/arm/dts/imx6ull-14x14-evk.dts index 2a941bff1c..8a1b67d6bb 100644 --- a/arch/arm/dts/imx6ull-14x14-evk.dts +++ b/arch/arm/dts/imx6ull-14x14-evk.dts @@ -8,7 +8,6 @@ /dts-v1/; -#include <dt-bindings/input/input.h> #include "imx6ull.dtsi" / { diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi index ea882a7f14..28b8422f31 100644 --- a/arch/arm/dts/imx6ull.dtsi +++ b/arch/arm/dts/imx6ull.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/imx6ul-clock.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include "imx6ull-pinfunc.h" #include "imx6ull-pinfunc-snvs.h" -- 2.15.1

2 1

[U-Boot] [PATCH v2] mx6sabresd: Add fastboot support
by Fabio Estevam 04 Feb '18

04 Feb '18

From: Fabio Estevam <fabio.estevam(a)nxp.com> fastboot tool is a convenient way to flash the eMMC, so add support for it. Examples of usages: On the mx6sabresd: => fastboot 0 On the Linux PC connected via USB: $ sudo fastboot getvar bootloader-version -i 0x0525 bootloader-version: U-Boot 2018.01-00550-g7517cfe finished. total time: 0.000s Shawn Guo described the following method for flashing the eMMC via flashboot: "I booted the board into Debian via NFS, and then use gpart to create GPT partitions on the eMMC. With CONFIG_EFI_PARTITION enabled in U-Boot, I can list the partitions on eMMC as below. => mmc dev 2 switch to partitions #0, OK mmc2(part 0) is current device => mmc part Partition Map for MMC device 2 -- Partition Type: EFI Part Start LBA End LBA Name Attributes Type GUID Partition GUID 1 0x00000800 0x000407ff "boot" attrs: 0x0000000000000000 type: 21686148-6449-6e6f-744e-656564454649 guid: 6137f187-600c-4dc4-8a74-ee8f0250d455 2 0x00040800 0x002987ff "system" attrs: 0x0000000000000000 type: 0fc63daf-8483-4772-8e79-3d69d8477de4 guid: af78282f-21b5-4324-bf7a-f460d1ae0015 3 0x00298800 0x003187ff "vendor" attrs: 0x0000000000000000 type: 0fc63daf-8483-4772-8e79-3d69d8477de4 guid: 15830513-0195-4e86-9b2c-cd3af5e14570 4 0x00318800 0x003587ff "cache" attrs: 0x0000000000000000 type: 0fc63daf-8483-4772-8e79-3d69d8477de4 guid: 6e909a60-606b-4c43-bbd4-f780afd97302 5 0x00358800 0x00ecbfde "data" attrs: 0x0000000000000000 type: 0fc63daf-8483-4772-8e79-3d69d8477de4 guid: 9e79dc0b-35d9-40f0-b638-3e718362cb26 => fastboot 0 At this point, I can do 'fastboot flash system system.img -i 0x0525' from host PC." Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- Changes since v1: - Select CONFIG_EFI_PARTITION=y (Shawn) - Provide the eMMC flashing procedure (Michael) configs/mx6sabresd_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 3e4c13c..9a4184b 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -20,6 +20,12 @@ CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_USB_GADGET_SUPPORT=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_USB_DEV=0 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=2 CONFIG_CMD_BOOTZ=y CONFIG_CMD_SPL=y CONFIG_CMD_SPL_WRITE_SIZE=0x20000 @@ -41,6 +47,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_EFI_PARTITION=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y -- 2.7.4

2 1

[U-Boot] [PATCH 1/2] mx6sabre_common: Allow building CONFIG_USB_FUNCTION_MASS_STORAGE
by Fabio Estevam 04 Feb '18

04 Feb '18

From: Fabio Estevam <fabio.estevam(a)nxp.com> Selecting CONFIG_USB_FUNCTION_MASS_STORAGE=y in the defconfig leads to the following error: cmd/built-in.o: In function `do_usb_mass_storage': cmd/usb_mass_storage.c:217: undefined reference to `fsg_main_thread' cmd/usb_mass_storage.c:170: undefined reference to `fsg_init' CONFIG_USB_FUNCTION_MASS_STORAGE option is built only for the non-SPL case as per the logic in drivers/usb/gadget/Makefile, so remove the incorrect CONFIG_SPL ifdefery to fix the build failure. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- include/configs/mx6sabre_common.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index f083dc8..42e650a 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -208,10 +208,8 @@ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP -#ifndef CONFIG_SPL #define CONFIG_USBD_HS #define CONFIG_USB_FUNCTION_MASS_STORAGE -#endif #endif /* __MX6QSABRE_COMMON_CONFIG_H */ -- 2.7.4

3 4

[U-Boot] [PATCH] board: tbs2910: add private imx config
by Soeren Moch 04 Feb '18

04 Feb '18

Add board specific imx config file with recommended IPU Qos settings and adapted DDR configuration. Signed-off-by: Soeren Moch <smoch(a)web.de> --- Cc: Stefano Babic <sbabic(a)denx.de> Cc: u-boot(a)lists.denx.de --- board/tbs/tbs2910/Kconfig | 2 +- board/tbs/tbs2910/tbs2910.cfg | 115 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 116 insertions(+), 1 deletion(-) create mode 100644 board/tbs/tbs2910/tbs2910.cfg diff --git a/board/tbs/tbs2910/Kconfig b/board/tbs/tbs2910/Kconfig index 55c475c..2e5e1d4 100644 --- a/board/tbs/tbs2910/Kconfig +++ b/board/tbs/tbs2910/Kconfig @@ -13,6 +13,6 @@ config MX6Q default y config IMX_CONFIG - default "board/boundary/nitrogen6x/nitrogen6q2g.cfg" + default "board/tbs/tbs2910/tbs2910.cfg" endif diff --git a/board/tbs/tbs2910/tbs2910.cfg b/board/tbs/tbs2910/tbs2910.cfg new file mode 100644 index 0000000..37fd4ba --- /dev/null +++ b/board/tbs/tbs2910/tbs2910.cfg @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2017 Soeren Moch <smoch(a)web.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define __ASSEMBLY__ +#include "asm/arch/crm_regs.h" +#include "asm/arch/iomux.h" +#include "asm/arch/mx6-ddr.h" + +/* image version 2 for imx6 */ +IMAGE_VERSION 2 +BOOT_FROM sd + +/* set the default clock gates to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0x00FFF300 +DATA 4, CCM_CCGR5, 0x0F0000C3 +DATA 4, CCM_CCGR6, 0x000003FF +/* set CKO1 (used as AUDIO_MCLK) to ahb_clk_root/8 = 16.5 MHz */ +DATA 4, CCM_CCOSR, 0x000000fb + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF +/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ +DATA 4, MX6_IOMUXC_GPR6, 0x77177717 +DATA 4, MX6_IOMUXC_GPR7, 0x77177717 + + +/* + * DDR3/DDR3L settings + * use default 40 Ohm pad drive strength, no odt + * 4x256Mx16 DDR3L-1066 7-7-7 + */ + +/* disable dq pullup */ +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +/* disable dqs pullup */ +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 +/* set ddr input mode for dq signals */ +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +/* set ddr input mode for dqs signals */ +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +/* set pad calibration type to DDR3 */ +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +/* ZQ calibration */ +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +/* dqs write delay */ +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001f001f +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001f001f +DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f001f +DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001f001f +/* dqs read delay */ +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 +/* dqs read gating control */ +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43000300 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03000300 +DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43000300 +DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03000300 +/* start delay line calibration */ +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +/* tRFC=0x89+1,tXS=0x8e+1,tXP=3+1,tXPDLL=0xc+1,tFAW=0x17+1,tCL=0x4+3 */ +DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974 +/* tRCD=6+1,tRP=6+1,tRC=0x1a+1,tRAS=0x13+1,tRPA=tRP+1,tWR=7+1,tMRD=0xb+1,tCWL=4+2 */ +DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64 +/* tDLLK=0x1ff+1,tRTP=3+1,tWTR=3+1,tRRD=3+1 */ +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +/* RTW_SAME=2,WTR_DIFF=3,WTW_DIFF=3,RTW_DIFF=2,RTR_DIFF=2 */ +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +/* tXPR=0x8e+1,SDE2RST=0x10-2,RST2CKE=0x23-2 */ +DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023 +/* ODT timing */ +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +/* read odt settings, 120 Ohm */ +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 +DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 +/* cs0, 15-bit row, 10-bit column, BL 8, 64-bit bus */ +DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 +/* interleaved bank access (row/bank/col), 5 cycles additional read delay */ +DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 +/* 2GiByte RAM at cs0 */ +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 +/* load mode registers of external ddr chips */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +/* externel chip ZQ calibration */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +/* configure and start refreshes, 8 refresh commands at 32 kHz */ +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +/* tCKE=2+1,tCKSRX=6,tCKSE=6, active power down after 256 cycles (setting 5) */ +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +/* set automatic self refresh */ +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +/* controller configuration finished */ +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 -- 2.7.4

2 1

[U-Boot] [PATCH V3] imx: mx25: Remove SION bit in all pin-mux that are safe
by Michael Trimarchi 04 Feb '18

04 Feb '18

SION bit should be used in the situation that we need to read back the value of a pin and should not be set by default macro. We get some malfunction as raised by following thread https://www.spinics.net/lists/linux-usb/msg162574.html As reported by this application note: https://www.nxp.com/docs/en/application-note/AN5078.pdf The software input on (SION) bit is an option to force an input path to be active regardless of the value driven by the corresponding module. It is used when the nature direction of a pin depending on selected alternative function is an output, but it is needed to read the real logic value on a pin. The SION bit can be used in: • Loopback: the module of a selected alternative function drives the pad and also receives the pad value as an input • GPIO capture: the module of a selected alternative function drives the pin and the value is captured by the GPIO SION bit is not necessary when the pin is configured as a peripheral apart specific silicon bug. If an application needs to have this set, this should be done in board file or in dts file Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> --- Changes V2->V3: - SION pin -> SION bit - mulfuction to malfunction Changes V1->V2: - some english typo - avoid changes from 0x00 to 0 or 0x01 to 1 when are not needed - preserve one SION bit on sdcard for a bug in silicon and add linux comment on it --- arch/arm/include/asm/arch-mx25/iomux-mx25.h | 571 ++++++++++++++-------------- 1 file changed, 290 insertions(+), 281 deletions(-) diff --git a/arch/arm/include/asm/arch-mx25/iomux-mx25.h b/arch/arm/include/asm/arch-mx25/iomux-mx25.h index 5b2863e..437f122 100644 --- a/arch/arm/include/asm/arch-mx25/iomux-mx25.h +++ b/arch/arm/include/asm/arch-mx25/iomux-mx25.h @@ -36,59 +36,59 @@ enum { MX25_PAD_A13__A13 = IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL), MX25_PAD_A13__GPIO_4_1 = IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A14__A14 = IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A14__GPIO_2_0 = IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_A14__A14 = IOMUX_PAD(0x230, 0x010, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A14__GPIO_2_0 = IOMUX_PAD(0x230, 0x010, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A15__A15 = IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A15__GPIO_2_1 = IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_A15__A15 = IOMUX_PAD(0x234, 0x014, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A15__GPIO_2_1 = IOMUX_PAD(0x234, 0x014, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A16__A16 = IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A16__GPIO_2_2 = IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_A16__A16 = IOMUX_PAD(0x000, 0x018, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A16__GPIO_2_2 = IOMUX_PAD(0x000, 0x018, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A17__A17 = IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A17__GPIO_2_3 = IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_A17__A17 = IOMUX_PAD(0x238, 0x01c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A17__GPIO_2_3 = IOMUX_PAD(0x238, 0x01c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A18__A18 = IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A18__GPIO_2_4 = IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_A18__FEC_COL = IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL), + MX25_PAD_A18__A18 = IOMUX_PAD(0x23c, 0x020, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A18__GPIO_2_4 = IOMUX_PAD(0x23c, 0x020, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_A18__FEC_COL = IOMUX_PAD(0x23c, 0x020, 0x07, 0x504, 0, NO_PAD_CTRL), - MX25_PAD_A19__A19 = IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A19__FEC_RX_ER = IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL), - MX25_PAD_A19__GPIO_2_5 = IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_A19__A19 = IOMUX_PAD(0x240, 0x024, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A19__FEC_RX_ER = IOMUX_PAD(0x240, 0x024, 0x07, 0x518, 0, NO_PAD_CTRL), + MX25_PAD_A19__GPIO_2_5 = IOMUX_PAD(0x240, 0x024, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A20__A20 = IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A20__GPIO_2_6 = IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_A20__FEC_RDATA2 = IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL), + MX25_PAD_A20__A20 = IOMUX_PAD(0x244, 0x028, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A20__GPIO_2_6 = IOMUX_PAD(0x244, 0x028, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_A20__FEC_RDATA2 = IOMUX_PAD(0x244, 0x028, 0x07, 0x50c, 0, NO_PAD_CTRL), - MX25_PAD_A21__A21 = IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A21__GPIO_2_7 = IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_A21__FEC_RDATA3 = IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL), + MX25_PAD_A21__A21 = IOMUX_PAD(0x248, 0x02c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A21__GPIO_2_7 = IOMUX_PAD(0x248, 0x02c, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_A21__FEC_RDATA3 = IOMUX_PAD(0x248, 0x02c, 0x07, 0x510, 0, NO_PAD_CTRL), - MX25_PAD_A22__A22 = IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A22__GPIO_2_8 = IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_A22__A22 = IOMUX_PAD(0x000, 0x030, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A22__GPIO_2_8 = IOMUX_PAD(0x000, 0x030, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A23__A23 = IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A23__GPIO_2_9 = IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_A23__A23 = IOMUX_PAD(0x24c, 0x034, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A23__GPIO_2_9 = IOMUX_PAD(0x24c, 0x034, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_A24__A24 = IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A24__GPIO_2_10 = IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_A24__FEC_RX_CLK = IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL), + MX25_PAD_A24__A24 = IOMUX_PAD(0x250, 0x038, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A24__GPIO_2_10 = IOMUX_PAD(0x250, 0x038, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_A24__FEC_RX_CLK = IOMUX_PAD(0x250, 0x038, 0x07, 0x514, 0, NO_PAD_CTRL), - MX25_PAD_A25__A25 = IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_A25__GPIO_2_11 = IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_A25__FEC_CRS = IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL), + MX25_PAD_A25__A25 = IOMUX_PAD(0x254, 0x03c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_A25__GPIO_2_11 = IOMUX_PAD(0x254, 0x03c, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_A25__FEC_CRS = IOMUX_PAD(0x254, 0x03c, 0x07, 0x508, 0, NO_PAD_CTRL), - MX25_PAD_EB0__EB0 = IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_EB0__AUD4_TXD = IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL), - MX25_PAD_EB0__GPIO_2_12 = IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_EB0__EB0 = IOMUX_PAD(0x258, 0x040, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_EB0__AUD4_TXD = IOMUX_PAD(0x258, 0x040, 0x04, 0x464, 0, NO_PAD_CTRL), + MX25_PAD_EB0__GPIO_2_12 = IOMUX_PAD(0x258, 0x040, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_EB1__EB1 = IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_EB1__AUD4_RXD = IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL), - MX25_PAD_EB1__GPIO_2_13 = IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_EB1__EB1 = IOMUX_PAD(0x25c, 0x044, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_EB1__AUD4_RXD = IOMUX_PAD(0x25c, 0x044, 0x04, 0x460, 0, NO_PAD_CTRL), + MX25_PAD_EB1__GPIO_2_13 = IOMUX_PAD(0x25c, 0x044, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_OE__OE = IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_OE__AUD4_TXC = IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL), - MX25_PAD_OE__GPIO_2_14 = IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_OE__OE = IOMUX_PAD(0x260, 0x048, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_OE__AUD4_TXC = IOMUX_PAD(0x260, 0x048, 0x04, 0, 0, NO_PAD_CTRL), + MX25_PAD_OE__GPIO_2_14 = IOMUX_PAD(0x260, 0x048, 0x05, 0, 0, NO_PAD_CTRL), MX25_PAD_CS0__CS0 = IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL), MX25_PAD_CS0__GPIO_4_2 = IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL), @@ -97,51 +97,51 @@ enum { MX25_PAD_CS1__NF_CE3 = IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL), MX25_PAD_CS1__GPIO_4_3 = IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS4__CS4 = IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL), + MX25_PAD_CS4__CS4 = IOMUX_PAD(0x264, 0x054, 0x00, 0, 0, NO_PAD_CTRL), MX25_PAD_CS4__NF_CE1 = IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS4__UART5_CTS = IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS4__GPIO_3_20 = IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CS4__UART5_CTS = IOMUX_PAD(0x264, 0x054, 0x03, 0, 0, NO_PAD_CTRL), + MX25_PAD_CS4__GPIO_3_20 = IOMUX_PAD(0x264, 0x054, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS5__CS5 = IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL), + MX25_PAD_CS5__CS5 = IOMUX_PAD(0x268, 0x058, 0x00, 0, 0, NO_PAD_CTRL), MX25_PAD_CS5__NF_CE2 = IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL), - MX25_PAD_CS5__UART5_RTS = IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL), - MX25_PAD_CS5__GPIO_3_21 = IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CS5__UART5_RTS = IOMUX_PAD(0x268, 0x058, 0x03, 0x574, 0, NO_PAD_CTRL), + MX25_PAD_CS5__GPIO_3_21 = IOMUX_PAD(0x268, 0x058, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_NF_CE0__NF_CE0 = IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_NF_CE0__GPIO_3_22 = IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_NF_CE0__NF_CE0 = IOMUX_PAD(0x26c, 0x05c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_NF_CE0__GPIO_3_22 = IOMUX_PAD(0x26c, 0x05c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_ECB__ECB = IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_ECB__UART5_TXD_MUX = IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL), - MX25_PAD_ECB__GPIO_3_23 = IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_ECB__ECB = IOMUX_PAD(0x270, 0x060, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_ECB__UART5_TXD_MUX = IOMUX_PAD(0x270, 0x060, 0x03, 0, 0, NO_PAD_CTRL), + MX25_PAD_ECB__GPIO_3_23 = IOMUX_PAD(0x270, 0x060, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_LBA__LBA = IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_LBA__UART5_RXD_MUX = IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL), - MX25_PAD_LBA__GPIO_3_24 = IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_LBA__LBA = IOMUX_PAD(0x274, 0x064, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_LBA__UART5_RXD_MUX = IOMUX_PAD(0x274, 0x064, 0x03, 0x578, 0, NO_PAD_CTRL), + MX25_PAD_LBA__GPIO_3_24 = IOMUX_PAD(0x274, 0x064, 0x05, 0, 0, NO_PAD_CTRL), MX25_PAD_BCLK__BCLK = IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL), MX25_PAD_BCLK__GPIO_4_4 = IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_RW__RW = IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_RW__AUD4_TXFS = IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL), - MX25_PAD_RW__GPIO_3_25 = IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_RW__RW = IOMUX_PAD(0x278, 0x06c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_RW__AUD4_TXFS = IOMUX_PAD(0x278, 0x06c, 0x04, 0x474, 0, NO_PAD_CTRL), + MX25_PAD_RW__GPIO_3_25 = IOMUX_PAD(0x278, 0x06c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFWE_B__NFWE_B = IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFWE_B__GPIO_3_26 = IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_NFWE_B__NFWE_B = IOMUX_PAD(0x000, 0x070, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_NFWE_B__GPIO_3_26 = IOMUX_PAD(0x000, 0x070, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFRE_B__NFRE_B = IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFRE_B__GPIO_3_27 = IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_NFRE_B__NFRE_B = IOMUX_PAD(0x000, 0x074, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_NFRE_B__GPIO_3_27 = IOMUX_PAD(0x000, 0x074, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFALE__NFALE = IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFALE__GPIO_3_28 = IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_NFALE__NFALE = IOMUX_PAD(0x000, 0x078, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_NFALE__GPIO_3_28 = IOMUX_PAD(0x000, 0x078, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFCLE__NFCLE = IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFCLE__GPIO_3_29 = IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_NFCLE__NFCLE = IOMUX_PAD(0x000, 0x07c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_NFCLE__GPIO_3_29 = IOMUX_PAD(0x000, 0x07c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFWP_B__NFWP_B = IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFWP_B__GPIO_3_30 = IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_NFWP_B__NFWP_B = IOMUX_PAD(0x000, 0x080, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_NFWP_B__GPIO_3_30 = IOMUX_PAD(0x000, 0x080, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_NFRB__NFRB = IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE), - MX25_PAD_NFRB__GPIO_3_31 = IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_NFRB__NFRB = IOMUX_PAD(0x27c, 0x084, 0x00, 0, 0, PAD_CTL_PKE), + MX25_PAD_NFRB__GPIO_3_31 = IOMUX_PAD(0x27c, 0x084, 0x05, 0, 0, NO_PAD_CTRL), MX25_PAD_D15__D15 = IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL), MX25_PAD_D15__LD16 = IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST), @@ -197,309 +197,318 @@ enum { MX25_PAD_D0__D0 = IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL), MX25_PAD_D0__GPIO_4_20 = IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_LD0__LD0 = IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD0__CSI_D0 = IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL), - MX25_PAD_LD0__GPIO_2_15 = IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_LD0__LD0 = IOMUX_PAD(0x2c0, 0x0c8, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD0__CSI_D0 = IOMUX_PAD(0x2c0, 0x0c8, 0x02, 0x488, 0, NO_PAD_CTRL), + MX25_PAD_LD0__GPIO_2_15 = IOMUX_PAD(0x2c0, 0x0c8, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_LD1__LD1 = IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD1__CSI_D1 = IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL), - MX25_PAD_LD1__GPIO_2_16 = IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_LD1__LD1 = IOMUX_PAD(0x2c4, 0x0cc, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD1__CSI_D1 = IOMUX_PAD(0x2c4, 0x0cc, 0x02, 0x48c, 0, NO_PAD_CTRL), + MX25_PAD_LD1__GPIO_2_16 = IOMUX_PAD(0x2c4, 0x0cc, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_LD2__LD2 = IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD2__GPIO_2_17 = IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_LD2__LD2 = IOMUX_PAD(0x2c8, 0x0d0, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD2__GPIO_2_17 = IOMUX_PAD(0x2c8, 0x0d0, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_LD3__LD3 = IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD3__GPIO_2_18 = IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_LD3__LD3 = IOMUX_PAD(0x2cc, 0x0d4, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD3__GPIO_2_18 = IOMUX_PAD(0x2cc, 0x0d4, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_LD4__LD4 = IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD4__GPIO_2_19 = IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_LD4__LD4 = IOMUX_PAD(0x2d0, 0x0d8, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD4__GPIO_2_19 = IOMUX_PAD(0x2d0, 0x0d8, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_LD5__LD5 = IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD5__GPIO_1_19 = IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_LD5__LD5 = IOMUX_PAD(0x2d4, 0x0dc, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD5__GPIO_1_19 = IOMUX_PAD(0x2d4, 0x0dc, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_LD6__LD6 = IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD6__GPIO_1_20 = IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_LD6__LD6 = IOMUX_PAD(0x2d8, 0x0e0, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD6__GPIO_1_20 = IOMUX_PAD(0x2d8, 0x0e0, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_LD7__LD7 = IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD7__GPIO_1_21 = IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_LD7__LD7 = IOMUX_PAD(0x2dc, 0x0e4, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD7__GPIO_1_21 = IOMUX_PAD(0x2dc, 0x0e4, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_LD8__LD8 = IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD8__FEC_TX_ERR = IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_LD8__LD8 = IOMUX_PAD(0x2e0, 0x0e8, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD8__FEC_TX_ERR = IOMUX_PAD(0x2e0, 0x0e8, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_LD9__LD9 = IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD9__FEC_COL = IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL), + MX25_PAD_LD9__LD9 = IOMUX_PAD(0x2e4, 0x0ec, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD9__FEC_COL = IOMUX_PAD(0x2e4, 0x0ec, 0x05, 0x504, 1, NO_PAD_CTRL), - MX25_PAD_LD10__LD10 = IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD10__FEC_RX_ER = IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL), + MX25_PAD_LD10__LD10 = IOMUX_PAD(0x2e8, 0x0f0, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD10__FEC_RX_ER = IOMUX_PAD(0x2e8, 0x0f0, 0x05, 0x518, 1, NO_PAD_CTRL), - MX25_PAD_LD11__LD11 = IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD11__FEC_RDATA2 = IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL), + MX25_PAD_LD11__LD11 = IOMUX_PAD(0x2ec, 0x0f4, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD11__FEC_RDATA2 = IOMUX_PAD(0x2ec, 0x0f4, 0x05, 0x50c, 1, NO_PAD_CTRL), - MX25_PAD_LD12__LD12 = IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD12__FEC_RDATA3 = IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL), + MX25_PAD_LD12__LD12 = IOMUX_PAD(0x2f0, 0x0f8, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD12__FEC_RDATA3 = IOMUX_PAD(0x2f0, 0x0f8, 0x05, 0x510, 1, NO_PAD_CTRL), - MX25_PAD_LD13__LD13 = IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD13__FEC_TDATA2 = IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_LD13__LD13 = IOMUX_PAD(0x2f4, 0x0fc, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD13__FEC_TDATA2 = IOMUX_PAD(0x2f4, 0x0fc, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_LD14__LD14 = IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD14__FEC_TDATA3 = IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_LD14__LD14 = IOMUX_PAD(0x2f8, 0x100, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD14__FEC_TDATA3 = IOMUX_PAD(0x2f8, 0x100, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_LD15__LD15 = IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_LD15__FEC_RX_CLK = IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL), + MX25_PAD_LD15__LD15 = IOMUX_PAD(0x2fc, 0x104, 0x00, 0, 0, PAD_CTL_SRE_FAST), + MX25_PAD_LD15__FEC_RX_CLK = IOMUX_PAD(0x2fc, 0x104, 0x05, 0x514, 1, NO_PAD_CTRL), - MX25_PAD_HSYNC__HSYNC = IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_HSYNC__GPIO_1_22 = IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_HSYNC__HSYNC = IOMUX_PAD(0x300, 0x108, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_HSYNC__GPIO_1_22 = IOMUX_PAD(0x300, 0x108, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSYNC__VSYNC = IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSYNC__GPIO_1_23 = IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_VSYNC__VSYNC = IOMUX_PAD(0x304, 0x10c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_VSYNC__GPIO_1_23 = IOMUX_PAD(0x304, 0x10c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_LSCLK__LSCLK = IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_LSCLK__GPIO_1_24 = IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_LSCLK__LSCLK = IOMUX_PAD(0x308, 0x110, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_LSCLK__GPIO_1_24 = IOMUX_PAD(0x308, 0x110, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_OE_ACD__OE_ACD = IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_OE_ACD__GPIO_1_25 = IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_OE_ACD__OE_ACD = IOMUX_PAD(0x30c, 0x114, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_OE_ACD__GPIO_1_25 = IOMUX_PAD(0x30c, 0x114, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CONTRAST__CONTRAST = IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CONTRAST__PWM4_PWMO = IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL), - MX25_PAD_CONTRAST__FEC_CRS = IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL), + MX25_PAD_CONTRAST__CONTRAST = IOMUX_PAD(0x310, 0x118, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CONTRAST__PWM4_PWMO = IOMUX_PAD(0x310, 0x118, 0x04, 0, 0, NO_PAD_CTRL), + MX25_PAD_CONTRAST__FEC_CRS = IOMUX_PAD(0x310, 0x118, 0x05, 0x508, 1, NO_PAD_CTRL), - MX25_PAD_PWM__PWM = IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_PWM__GPIO_1_26 = IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_PWM__USBH2_OC = IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP), + MX25_PAD_PWM__PWM = IOMUX_PAD(0x314, 0x11c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_PWM__GPIO_1_26 = IOMUX_PAD(0x314, 0x11c, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_PWM__USBH2_OC = IOMUX_PAD(0x314, 0x11c, 0x06, 0x580, 1, PAD_CTL_PUS_100K_UP), - MX25_PAD_CSI_D2__CSI_D2 = IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D2__UART5_RXD_MUX = IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL), - MX25_PAD_CSI_D2__GPIO_1_27 = IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D2__CSPI3_MOSI = IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D2__CSI_D2 = IOMUX_PAD(0x318, 0x120, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D2__UART5_RXD_MUX = IOMUX_PAD(0x318, 0x120, 0x01, 0x578, 1, NO_PAD_CTRL), + MX25_PAD_CSI_D2__GPIO_1_27 = IOMUX_PAD(0x318, 0x120, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D2__CSPI3_MOSI = IOMUX_PAD(0x318, 0x120, 0x07, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D3__CSI_D3 = IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D3__GPIO_1_28 = IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D3__CSPI3_MISO = IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL), + MX25_PAD_CSI_D3__CSI_D3 = IOMUX_PAD(0x31c, 0x124, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D3__GPIO_1_28 = IOMUX_PAD(0x31c, 0x124, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D3__CSPI3_MISO = IOMUX_PAD(0x31c, 0x124, 0x07, 0x4b4, 1, NO_PAD_CTRL), - MX25_PAD_CSI_D4__CSI_D4 = IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D4__UART5_RTS = IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL), - MX25_PAD_CSI_D4__GPIO_1_29 = IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D4__CSPI3_SCLK = IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D4__CSI_D4 = IOMUX_PAD(0x320, 0x128, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D4__UART5_RTS = IOMUX_PAD(0x320, 0x128, 0x01, 0x574, 1, NO_PAD_CTRL), + MX25_PAD_CSI_D4__GPIO_1_29 = IOMUX_PAD(0x320, 0x128, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D4__CSPI3_SCLK = IOMUX_PAD(0x320, 0x128, 0x07, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D5__CSI_D5 = IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D5__GPIO_1_30 = IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D5__CSPI3_RDY = IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D5__CSI_D5 = IOMUX_PAD(0x324, 0x12c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D5__GPIO_1_30 = IOMUX_PAD(0x324, 0x12c, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D5__CSPI3_RDY = IOMUX_PAD(0x324, 0x12c, 0x07, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D6__CSI_D6 = IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D6__GPIO_1_31 = IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D6__CSI_D6 = IOMUX_PAD(0x328, 0x130, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D6__GPIO_1_31 = IOMUX_PAD(0x328, 0x130, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D7__CSI_D7 = IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D7__GPIO_1_6 = IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D7__CSI_D7 = IOMUX_PAD(0x32c, 0x134, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D7__GPIO_1_6 = IOMUX_PAD(0x32c, 0x134, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D8__CSI_D8 = IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D8__GPIO_1_7 = IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D8__CSI_D8 = IOMUX_PAD(0x330, 0x138, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D8__GPIO_1_7 = IOMUX_PAD(0x330, 0x138, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D9__CSI_D9 = IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_D9__GPIO_4_21 = IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D9__CSI_D9 = IOMUX_PAD(0x334, 0x13c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_D9__GPIO_4_21 = IOMUX_PAD(0x334, 0x13c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_MCLK__GPIO_1_8 = IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x338, 0x140, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_MCLK__GPIO_1_8 = IOMUX_PAD(0x338, 0x140, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_VSYNC__GPIO_1_9 = IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x33c, 0x144, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_VSYNC__GPIO_1_9 = IOMUX_PAD(0x33c, 0x144, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_HSYNC__GPIO_1_10 = IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x340, 0x148, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_HSYNC__GPIO_1_10 = IOMUX_PAD(0x340, 0x148, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSI_PIXCLK__GPIO_1_11 = IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x344, 0x14c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSI_PIXCLK__GPIO_1_11 = IOMUX_PAD(0x344, 0x14c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_I2C1_CLK__GPIO_1_12 = IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x348, 0x150, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_I2C1_CLK__GPIO_1_12 = IOMUX_PAD(0x348, 0x150, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_I2C1_DAT__GPIO_1_13 = IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x34c, 0x154, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_I2C1_DAT__GPIO_1_13 = IOMUX_PAD(0x34c, 0x154, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_MOSI__GPIO_1_14 = IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_MOSI__GPIO_1_14 = IOMUX_PAD(0x350, 0x158, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_MISO__GPIO_1_15 = IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x354, 0x15c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_MISO__GPIO_1_15 = IOMUX_PAD(0x354, 0x15c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_SS0__GPIO_1_16 = IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x358, 0x160, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_SS0__GPIO_1_16 = IOMUX_PAD(0x358, 0x160, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_SS1__I2C3_DAT = IOMUX_PAD(0x35c, 0x164, 0x11, 0x528, 1, NO_PAD_CTRL), - MX25_PAD_CSPI1_SS1__GPIO_1_17 = IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_SS1__I2C3_DAT = IOMUX_PAD(0x35c, 0x164, 0x01, 0x528, 1, NO_PAD_CTRL), + MX25_PAD_CSPI1_SS1__GPIO_1_17 = IOMUX_PAD(0x35c, 0x164, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_SCLK__GPIO_1_18 = IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x360, 0x168, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_SCLK__GPIO_1_18 = IOMUX_PAD(0x360, 0x168, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CSPI1_RDY__CSPI1_RDY = IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE), - MX25_PAD_CSPI1_RDY__GPIO_2_22 = IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CSPI1_RDY__CSPI1_RDY = IOMUX_PAD(0x364, 0x16c, 0x00, 0, 0, PAD_CTL_PKE), + MX25_PAD_CSPI1_RDY__GPIO_2_22 = IOMUX_PAD(0x364, 0x16c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN), - MX25_PAD_UART1_RXD__GPIO_4_22 = IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x368, 0x170, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN), + MX25_PAD_UART1_RXD__GPIO_4_22 = IOMUX_PAD(0x368, 0x170, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART1_TXD__GPIO_4_23 = IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x36c, 0x174, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_UART1_TXD__GPIO_4_23 = IOMUX_PAD(0x36c, 0x174, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_UART1_RTS__CSI_D0 = IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL), - MX25_PAD_UART1_RTS__GPIO_4_24 = IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x00, 0, 0, PAD_CTL_PUS_100K_UP), + MX25_PAD_UART1_RTS__CSI_D0 = IOMUX_PAD(0x370, 0x178, 0x01, 0x488, 1, NO_PAD_CTRL), + MX25_PAD_UART1_RTS__GPIO_4_24 = IOMUX_PAD(0x370, 0x178, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_UART1_CTS__CSI_D1 = IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL), - MX25_PAD_UART1_CTS__GPIO_4_25 = IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x374, 0x17c, 0x00, 0, 0, PAD_CTL_PUS_100K_UP), + MX25_PAD_UART1_CTS__CSI_D1 = IOMUX_PAD(0x374, 0x17c, 0x01, 0x48c, 1, NO_PAD_CTRL), + MX25_PAD_UART1_CTS__GPIO_4_25 = IOMUX_PAD(0x374, 0x17c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_RXD__GPIO_4_26 = IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x378, 0x180, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_UART2_RXD__GPIO_4_26 = IOMUX_PAD(0x378, 0x180, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_TXD__GPIO_4_27 = IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x37c, 0x184, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_UART2_TXD__GPIO_4_27 = IOMUX_PAD(0x37c, 0x184, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_RTS__UART2_RTS = IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_RTS__FEC_COL = IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL), - MX25_PAD_UART2_RTS__GPIO_4_28 = IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_UART2_RTS__UART2_RTS = IOMUX_PAD(0x380, 0x188, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_UART2_RTS__FEC_COL = IOMUX_PAD(0x380, 0x188, 0x02, 0x504, 2, NO_PAD_CTRL), + MX25_PAD_UART2_RTS__GPIO_4_28 = IOMUX_PAD(0x380, 0x188, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_CTS__FEC_RX_ER = IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL), - MX25_PAD_UART2_CTS__UART2_CTS = IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_UART2_CTS__GPIO_4_29 = IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_UART2_CTS__FEC_RX_ER = IOMUX_PAD(0x384, 0x18c, 0x02, 0x518, 2, NO_PAD_CTRL), + MX25_PAD_UART2_CTS__UART2_CTS = IOMUX_PAD(0x384, 0x18c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_UART2_CTS__GPIO_4_29 = IOMUX_PAD(0x384, 0x18c, 0x05, 0, 0, NO_PAD_CTRL), + /* + * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD + * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM + * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon + * bug that configuring the SD1_CMD function doesn't enable the input path for + * this pin. + * This might have side effects for other hardware units that are connected to + * that pin and use the respective function as input. + */ MX25_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_CMD__FEC_RDATA2 = IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL), - MX25_PAD_SD1_CMD__GPIO_2_23 = IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_SD1_CMD__FEC_RDATA2 = IOMUX_PAD(0x388, 0x190, 0x02, 0x50c, 2, NO_PAD_CTRL), + MX25_PAD_SD1_CMD__GPIO_2_23 = IOMUX_PAD(0x388, 0x190, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_CLK__FEC_RDATA3 = IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL), - MX25_PAD_SD1_CLK__GPIO_2_24 = IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x38c, 0x194, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), + MX25_PAD_SD1_CLK__FEC_RDATA3 = IOMUX_PAD(0x38c, 0x194, 0x02, 0x510, 2, NO_PAD_CTRL), + MX25_PAD_SD1_CLK__GPIO_2_24 = IOMUX_PAD(0x38c, 0x194, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA0__GPIO_2_25 = IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x390, 0x198, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), + MX25_PAD_SD1_DATA0__GPIO_2_25 = IOMUX_PAD(0x390, 0x198, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA1__AUD7_RXD = IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL), - MX25_PAD_SD1_DATA1__GPIO_2_26 = IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x394, 0x19c, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), + MX25_PAD_SD1_DATA1__AUD7_RXD = IOMUX_PAD(0x394, 0x19c, 0x03, 0x478, 0, NO_PAD_CTRL), + MX25_PAD_SD1_DATA1__GPIO_2_26 = IOMUX_PAD(0x394, 0x19c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA2__FEC_RX_CLK = IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL), - MX25_PAD_SD1_DATA2__GPIO_2_27 = IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x398, 0x1a0, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), + MX25_PAD_SD1_DATA2__FEC_RX_CLK = IOMUX_PAD(0x398, 0x1a0, 0x05, 0x514, 2, NO_PAD_CTRL), + MX25_PAD_SD1_DATA2__GPIO_2_27 = IOMUX_PAD(0x398, 0x1a0, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP), - MX25_PAD_SD1_DATA3__FEC_CRS = IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL), - MX25_PAD_SD1_DATA3__GPIO_2_28 = IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0, 0, PAD_CTL_PUS_47K_UP), + MX25_PAD_SD1_DATA3__FEC_CRS = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0x508, 2, NO_PAD_CTRL), + MX25_PAD_SD1_DATA3__GPIO_2_28 = IOMUX_PAD(0x39c, 0x1a4, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_ROW0__KPP_ROW0 = IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW0__GPIO_2_29 = IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_KPP_ROW0__KPP_ROW0 = IOMUX_PAD(0x3a0, 0x1a8, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), + MX25_PAD_KPP_ROW0__GPIO_2_29 = IOMUX_PAD(0x3a0, 0x1a8, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_ROW1__KPP_ROW1 = IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW1__GPIO_2_30 = IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_KPP_ROW1__KPP_ROW1 = IOMUX_PAD(0x3a4, 0x1ac, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), + MX25_PAD_KPP_ROW1__GPIO_2_30 = IOMUX_PAD(0x3a4, 0x1ac, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_ROW2__KPP_ROW2 = IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW2__CSI_D0 = IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL), - MX25_PAD_KPP_ROW2__GPIO_2_31 = IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_KPP_ROW2__KPP_ROW2 = IOMUX_PAD(0x3a8, 0x1b0, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), + MX25_PAD_KPP_ROW2__CSI_D0 = IOMUX_PAD(0x3a8, 0x1b0, 0x03, 0x488, 2, NO_PAD_CTRL), + MX25_PAD_KPP_ROW2__GPIO_2_31 = IOMUX_PAD(0x3a8, 0x1b0, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_ROW3__KPP_ROW3 = IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL), - MX25_PAD_KPP_ROW3__CSI_LD1 = IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL), - MX25_PAD_KPP_ROW3__GPIO_3_0 = IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_KPP_ROW3__KPP_ROW3 = IOMUX_PAD(0x3ac, 0x1b4, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL), + MX25_PAD_KPP_ROW3__CSI_LD1 = IOMUX_PAD(0x3ac, 0x1b4, 0x03, 0x48c, 2, NO_PAD_CTRL), + MX25_PAD_KPP_ROW3__GPIO_3_0 = IOMUX_PAD(0x3ac, 0x1b4, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_COL0__KPP_COL0 = IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL0__UART4_RXD_MUX = IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL), - MX25_PAD_KPP_COL0__AUD5_TXD = IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL0__GPIO_3_1 = IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_KPP_COL0__KPP_COL0 = IOMUX_PAD(0x3b0, 0x1b8, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), + MX25_PAD_KPP_COL0__UART4_RXD_MUX = IOMUX_PAD(0x3b0, 0x1b8, 0x01, 0x570, 1, NO_PAD_CTRL), + MX25_PAD_KPP_COL0__AUD5_TXD = IOMUX_PAD(0x3b0, 0x1b8, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), + MX25_PAD_KPP_COL0__GPIO_3_1 = IOMUX_PAD(0x3b0, 0x1b8, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_COL1__KPP_COL1 = IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL1__UART4_TXD_MUX = IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_COL1__AUD5_RXD = IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL1__GPIO_3_2 = IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_KPP_COL1__KPP_COL1 = IOMUX_PAD(0x3b4, 0x1bc, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), + MX25_PAD_KPP_COL1__UART4_TXD_MUX = IOMUX_PAD(0x3b4, 0x1bc, 0x01, 0, 0, NO_PAD_CTRL), + MX25_PAD_KPP_COL1__AUD5_RXD = IOMUX_PAD(0x3b4, 0x1bc, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), + MX25_PAD_KPP_COL1__GPIO_3_2 = IOMUX_PAD(0x3b4, 0x1bc, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_COL2__KPP_COL2 = IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL2__UART4_RTS = IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_COL2__AUD5_TXC = IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL2__GPIO_3_3 = IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_KPP_COL2__KPP_COL2 = IOMUX_PAD(0x3b8, 0x1c0, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), + MX25_PAD_KPP_COL2__UART4_RTS = IOMUX_PAD(0x3b8, 0x1c0, 0x01, 0, 0, NO_PAD_CTRL), + MX25_PAD_KPP_COL2__AUD5_TXC = IOMUX_PAD(0x3b8, 0x1c0, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), + MX25_PAD_KPP_COL2__GPIO_3_3 = IOMUX_PAD(0x3b8, 0x1c0, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_COL3__KPP_COL3 = IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL), - MX25_PAD_KPP_COL3__UART4_CTS = IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL), - MX25_PAD_KPP_COL3__AUD5_TXFS = IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PUS_100K_UP), - MX25_PAD_KPP_COL3__GPIO_3_4 = IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_KPP_COL3__KPP_COL3 = IOMUX_PAD(0x3bc, 0x1c4, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL), + MX25_PAD_KPP_COL3__UART4_CTS = IOMUX_PAD(0x3bc, 0x1c4, 0x01, 0, 0, NO_PAD_CTRL), + MX25_PAD_KPP_COL3__AUD5_TXFS = IOMUX_PAD(0x3bc, 0x1c4, 0x02, 0, 0, PAD_CTL_PUS_100K_UP), + MX25_PAD_KPP_COL3__GPIO_3_4 = IOMUX_PAD(0x3bc, 0x1c4, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_MDC__AUD4_TXD = IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL), - MX25_PAD_FEC_MDC__GPIO_3_5 = IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x3c0, 0x1c8, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_FEC_MDC__AUD4_TXD = IOMUX_PAD(0x3c0, 0x1c8, 0x02, 0x464, 1, NO_PAD_CTRL), + MX25_PAD_FEC_MDC__GPIO_3_5 = IOMUX_PAD(0x3c0, 0x1c8, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP), - MX25_PAD_FEC_MDIO__AUD4_RXD = IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL), - MX25_PAD_FEC_MDIO__GPIO_3_6 = IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x3c4, 0x1cc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP), + MX25_PAD_FEC_MDIO__AUD4_RXD = IOMUX_PAD(0x3c4, 0x1cc, 0x02, 0x460, 1, NO_PAD_CTRL), + MX25_PAD_FEC_MDIO__GPIO_3_6 = IOMUX_PAD(0x3c4, 0x1cc, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_TDATA0__FEC_TDATA0 = IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_TDATA0__GPIO_3_7 = IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_FEC_TDATA0__FEC_TDATA0 = IOMUX_PAD(0x3c8, 0x1d0, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_FEC_TDATA0__GPIO_3_7 = IOMUX_PAD(0x3c8, 0x1d0, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_TDATA1__FEC_TDATA1 = IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_TDATA1__AUD4_TXFS = IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL), - MX25_PAD_FEC_TDATA1__GPIO_3_8 = IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_FEC_TDATA1__FEC_TDATA1 = IOMUX_PAD(0x3cc, 0x1d4, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_FEC_TDATA1__AUD4_TXFS = IOMUX_PAD(0x3cc, 0x1d4, 0x02, 0x474, 1, NO_PAD_CTRL), + MX25_PAD_FEC_TDATA1__GPIO_3_8 = IOMUX_PAD(0x3cc, 0x1d4, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_TX_EN__GPIO_3_9 = IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x3d0, 0x1d8, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_FEC_TX_EN__GPIO_3_9 = IOMUX_PAD(0x3d0, 0x1d8, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_RDATA0__FEC_RDATA0 = IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_RDATA0__GPIO_3_10 = IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_FEC_RDATA0__FEC_RDATA0 = IOMUX_PAD(0x3d4, 0x1dc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), + MX25_PAD_FEC_RDATA0__GPIO_3_10 = IOMUX_PAD(0x3d4, 0x1dc, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_RDATA1__FEC_RDATA1 = IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_RDATA1__GPIO_3_11 = IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_FEC_RDATA1__FEC_RDATA1 = IOMUX_PAD(0x3d8, 0x1e0, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), + MX25_PAD_FEC_RDATA1__GPIO_3_11 = IOMUX_PAD(0x3d8, 0x1e0, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_RX_DV__CAN2_RX = IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP), - MX25_PAD_FEC_RX_DV__GPIO_3_12 = IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x3dc, 0x1e4, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), + MX25_PAD_FEC_RX_DV__CAN2_RX = IOMUX_PAD(0x3dc, 0x1e4, 0x04, 0x484, 0, PAD_CTL_PUS_22K_UP), + MX25_PAD_FEC_RX_DV__GPIO_3_12 = IOMUX_PAD(0x3dc, 0x1e4, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), - MX25_PAD_FEC_TX_CLK__GPIO_3_13 = IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x3e0, 0x1e8, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN), + MX25_PAD_FEC_TX_CLK__GPIO_3_13 = IOMUX_PAD(0x3e0, 0x1e8, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_RTCK__RTCK = IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_RTCK__OWIRE = IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL), - MX25_PAD_RTCK__GPIO_3_14 = IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_RTCK__RTCK = IOMUX_PAD(0x3e4, 0x1ec, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_RTCK__OWIRE = IOMUX_PAD(0x3e4, 0x1ec, 0x01, 0, 0, NO_PAD_CTRL), + MX25_PAD_RTCK__GPIO_3_14 = IOMUX_PAD(0x3e4, 0x1ec, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_DE_B__DE_B = IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_DE_B__GPIO_2_20 = IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_DE_B__DE_B = IOMUX_PAD(0x3ec, 0x1f0, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_DE_B__GPIO_2_20 = IOMUX_PAD(0x3ec, 0x1f0, 0x05, 0, 0, NO_PAD_CTRL), MX25_PAD_TDO__TDO = IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_A__GPIO_A = IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_A__CAN1_TX = IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP), - MX25_PAD_GPIO_A__USBOTG_PWR = IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE), + MX25_PAD_GPIO_A__GPIO_A = IOMUX_PAD(0x3f0, 0x1f4, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_GPIO_A__CAN1_TX = IOMUX_PAD(0x3f0, 0x1f4, 0x06, 0, 0, PAD_CTL_PUS_22K_UP), + MX25_PAD_GPIO_A__USBOTG_PWR = IOMUX_PAD(0x3f0, 0x1f4, 0x02, 0, 0, PAD_CTL_PKE), - MX25_PAD_GPIO_B__GPIO_B = IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_B__CAN1_RX = IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K_UP), - MX25_PAD_GPIO_B__USBOTG_OC = IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP), + MX25_PAD_GPIO_B__GPIO_B = IOMUX_PAD(0x3f4, 0x1f8, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_GPIO_B__CAN1_RX = IOMUX_PAD(0x3f4, 0x1f8, 0x06, 0x480, 1, PAD_CTL_PUS_22K_UP), + MX25_PAD_GPIO_B__USBOTG_OC = IOMUX_PAD(0x3f4, 0x1f8, 0x02, 0x57c, 1, PAD_CTL_PUS_100K_UP), - MX25_PAD_GPIO_C__GPIO_C = IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_C__CAN2_TX = IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP), + MX25_PAD_GPIO_C__GPIO_C = IOMUX_PAD(0x3f8, 0x1fc, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_GPIO_C__CAN2_TX = IOMUX_PAD(0x3f8, 0x1fc, 0x06, 0, 0, PAD_CTL_PUS_22K_UP), - MX25_PAD_GPIO_D__GPIO_D = IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL), + MX25_PAD_GPIO_D__GPIO_D = IOMUX_PAD(0x3fc, 0x200, 0x00, 0, 0, NO_PAD_CTRL), MX25_PAD_GPIO_E__LD16 = IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_GPIO_D__CAN2_RX = IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP), + MX25_PAD_GPIO_D__CAN2_RX = IOMUX_PAD(0x3fc, 0x200, 0x06, 0x484, 1, PAD_CTL_PUS_22K_UP), - MX25_PAD_GPIO_E__GPIO_E = IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL), + MX25_PAD_GPIO_E__GPIO_E = IOMUX_PAD(0x400, 0x204, 0x00, 0, 0, NO_PAD_CTRL), MX25_PAD_GPIO_F__LD17 = IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST), - MX25_PAD_GPIO_E__I2C3_CLK = IOMUX_PAD(0x400, 0x204, 0x11, 0x524, 2, NO_PAD_CTRL), - MX25_PAD_GPIO_E__AUD7_TXD = IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL), + MX25_PAD_GPIO_E__I2C3_CLK = IOMUX_PAD(0x400, 0x204, 0x01, 0x524, 2, NO_PAD_CTRL), + MX25_PAD_GPIO_E__AUD7_TXD = IOMUX_PAD(0x400, 0x204, 0x04, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_F__GPIO_F = IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_GPIO_F__AUD7_TXC = IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL), + MX25_PAD_GPIO_F__GPIO_F = IOMUX_PAD(0x404, 0x208, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_GPIO_F__AUD7_TXC = IOMUX_PAD(0x404, 0x208, 0x04, 0, 0, NO_PAD_CTRL), - MX25_PAD_EXT_ARMCLK__EXT_ARMCLK = IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_EXT_ARMCLK__GPIO_3_15 = IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_EXT_ARMCLK__EXT_ARMCLK = IOMUX_PAD(0x000, 0x20c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_EXT_ARMCLK__GPIO_3_15 = IOMUX_PAD(0x000, 0x20c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK = IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_UPLL_BYPCLK__GPIO_3_16 = IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK = IOMUX_PAD(0x000, 0x210, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_UPLL_BYPCLK__GPIO_3_16 = IOMUX_PAD(0x000, 0x210, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_REQ__VSTBY_REQ = IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_REQ__AUD7_TXFS = IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_REQ__GPIO_3_17 = IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_ACK__VSTBY_ACK = IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_VSTBY_ACK__GPIO_3_18 = IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_VSTBY_REQ__VSTBY_REQ = IOMUX_PAD(0x408, 0x214, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_VSTBY_REQ__AUD7_TXFS = IOMUX_PAD(0x408, 0x214, 0x04, 0, 0, NO_PAD_CTRL), + MX25_PAD_VSTBY_REQ__GPIO_3_17 = IOMUX_PAD(0x408, 0x214, 0x05, 0, 0, NO_PAD_CTRL), + MX25_PAD_VSTBY_ACK__VSTBY_ACK = IOMUX_PAD(0x40c, 0x218, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_VSTBY_ACK__GPIO_3_18 = IOMUX_PAD(0x40c, 0x218, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_POWER_FAIL__POWER_FAIL = IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_POWER_FAIL__AUD7_RXD = IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL), - MX25_PAD_POWER_FAIL__GPIO_3_19 = IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_POWER_FAIL__POWER_FAIL = IOMUX_PAD(0x410, 0x21c, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_POWER_FAIL__AUD7_RXD = IOMUX_PAD(0x410, 0x21c, 0x04, 0x478, 1, NO_PAD_CTRL), + MX25_PAD_POWER_FAIL__GPIO_3_19 = IOMUX_PAD(0x410, 0x21c, 0x05, 0, 0, NO_PAD_CTRL), - MX25_PAD_CLKO__CLKO = IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL), - MX25_PAD_CLKO__GPIO_2_21 = IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL), + MX25_PAD_CLKO__CLKO = IOMUX_PAD(0x414, 0x220, 0x00, 0, 0, NO_PAD_CTRL), + MX25_PAD_CLKO__GPIO_2_21 = IOMUX_PAD(0x414, 0x220, 0x05, 0, 0, NO_PAD_CTRL), MX25_PAD_BOOT_MODE0__BOOT_MODE0 = IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL), MX25_PAD_BOOT_MODE0__GPIO_4_30 = IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL), -- 2.7.4

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