February 2018 - U-Boot

[U-Boot] [PATCH 1/1] i2c: mvtwsi.c: Avoid NULL dereference
by Heinrich Schuchardt 06 Feb '18

06 Feb '18

For '#ifndef CONFIG_DM_I2C' twsi_i2c_init() passes NULL as 4th parameter to __twsi_i2c_init(). Identified with cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- drivers/i2c/mvtwsi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index dfbc4e053f..30bee0d52e 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -490,7 +490,8 @@ static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed, /* Reset controller */ twsi_reset(twsi); /* Set speed */ - *actual_speed = __twsi_i2c_set_bus_speed(twsi, speed); + if (actual_speed) + *actual_speed = __twsi_i2c_set_bus_speed(twsi, speed); /* Set slave address; even though we don't use it */ writel(slaveadd, &twsi->slave_address); writel(0, &twsi->xtnd_slave_addr); -- 2.15.1

2 1

[U-Boot] [RESEND PATCH v2 1/6] i2c: fsl_i2c: Fix style violations
by Mario Six 06 Feb '18

06 Feb '18

Fix some style violations in the fsl_i2c I2C driver, and use shorter type names for variables in some cases. Reviewed-by: Heiko Schocher <hs(a)denx.de> Signed-off-by: Mario Six <mario.six(a)gdsys.cc> --- v1 -> v2: None --- drivers/i2c/fsl_i2c.c | 111 +++++++++++++++++++++++++------------------------- 1 file changed, 56 insertions(+), 55 deletions(-) diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index ff3dc25927..d957cf6286 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -116,10 +116,10 @@ static const struct { * * The return value is the actual bus speed that is set. */ -static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base, - unsigned int i2c_clk, unsigned int speed) +static uint set_i2c_bus_speed(const struct fsl_i2c_base *base, + uint i2c_clk, uint speed) { - unsigned short divider = min(i2c_clk / speed, (unsigned int)USHRT_MAX); + ushort divider = min(i2c_clk / speed, (uint)USHRT_MAX); /* * We want to choose an FDR/DFSR that generates an I2C bus speed that @@ -130,8 +130,8 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base, #ifdef __PPC__ u8 dfsr, fdr = 0x31; /* Default if no FDR found */ /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */ - unsigned short a, b, ga, gb; - unsigned long c_div, est_div; + ushort a, b, ga, gb; + ulong c_div, est_div; #ifdef CONFIG_FSL_I2C_CUSTOM_DFSR dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR; @@ -151,18 +151,21 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base, for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) { for (gb = 0; gb < 8; gb++) { b = 16 << gb; - c_div = b * (a + ((3*dfsr)/b)*2); - if ((c_div > divider) && (c_div < est_div)) { - unsigned short bin_gb, bin_ga; + c_div = b * (a + ((3 * dfsr) / b) * 2); + if (c_div > divider && c_div < est_div) { + ushort bin_gb, bin_ga; est_div = c_div; bin_gb = gb << 2; bin_ga = (ga & 0x3) | ((ga & 0x4) << 3); fdr = bin_gb | bin_ga; speed = i2c_clk / est_div; - debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, " - "a:%d, b:%d, speed:%d\n", - fdr, est_div, ga, gb, a, b, speed); + + debug("FDR: 0x%.2x, ", fdr); + debug("div: %ld, ", est_div); + debug("ga: 0x%x, gb: 0x%x, ", ga, gb); + debug("a: %d, b: %d, speed: %d\n", a, b, speed); + /* Condition 2 not accounted for */ debug("Tr <= %d ns\n", (b - 3 * dfsr) * 1000000 / @@ -174,13 +177,13 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base, if (a == 24) a += 4; } - debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr); - debug("FDR:0x%.2x, speed:%d\n", fdr, speed); + debug("divider: %d, est_div: %ld, DFSR: %d\n", divider, est_div, dfsr); + debug("FDR: 0x%.2x, speed: %d\n", fdr, speed); #endif writeb(dfsr, &base->dfsrr); /* set default filter */ writeb(fdr, &base->fdr); /* set bus speed */ #else - unsigned int i; + uint i; for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) if (fsl_i2c_speed_map[i].divider >= divider) { @@ -197,7 +200,7 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base, } #ifndef CONFIG_DM_I2C -static unsigned int get_i2c_clock(int bus) +static uint get_i2c_clock(int bus) { if (bus) return gd->arch.i2c2_clk; /* I2C2 clock */ @@ -211,10 +214,11 @@ static int fsl_i2c_fixup(const struct fsl_i2c_base *base) const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); unsigned long long timeval = 0; int ret = -1; - unsigned int flags = 0; + uint flags = 0; #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 - unsigned int svr = get_svr(); + uint svr = get_svr(); + if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) flags = I2C_CR_BIT6; @@ -263,7 +267,7 @@ static void __i2c_init(const struct fsl_i2c_base *base, int speed, int /* Call board specific i2c bus reset routine before accessing the * environment, which might be in a chip on that bus. For details * about this problem see doc/I2C_Edge_Conditions. - */ + */ i2c_init_board(); #endif writeb(0, &base->cr); /* stop I2C controller */ @@ -286,8 +290,7 @@ static void __i2c_init(const struct fsl_i2c_base *base, int speed, int } } -static int -i2c_wait4bus(const struct fsl_i2c_base *base) +static int i2c_wait4bus(const struct fsl_i2c_base *base) { unsigned long long timeval = get_ticks(); const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); @@ -300,8 +303,7 @@ i2c_wait4bus(const struct fsl_i2c_base *base) return 0; } -static inline int -i2c_wait(const struct fsl_i2c_base *base, int write) +static inline int i2c_wait(const struct fsl_i2c_base *base, int write) { u32 csr; unsigned long long timeval = get_ticks(); @@ -317,29 +319,29 @@ i2c_wait(const struct fsl_i2c_base *base, int write) writeb(0x0, &base->sr); if (csr & I2C_SR_MAL) { - debug("i2c_wait: MAL\n"); + debug("%s: MAL\n", __func__); return -1; } if (!(csr & I2C_SR_MCF)) { - debug("i2c_wait: unfinished\n"); + debug("%s: unfinished\n", __func__); return -1; } if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) { - debug("i2c_wait: No RXACK\n"); + debug("%s: No RXACK\n", __func__); return -1; } return 0; } while ((get_ticks() - timeval) < timeout); - debug("i2c_wait: timed out\n"); + debug("%s: timed out\n", __func__); return -1; } -static inline int -i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, u8 dir, int rsta) +static inline int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, + u8 dir, int rsta) { writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX | (rsta ? I2C_CR_RSTA : 0), @@ -353,8 +355,8 @@ i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, u8 dir, int rsta) return 1; } -static inline int -__i2c_write_data(const struct fsl_i2c_base *base, u8 *data, int length) +static inline int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data, + int length) { int i; @@ -368,8 +370,8 @@ __i2c_write_data(const struct fsl_i2c_base *base, u8 *data, int length) return i; } -static inline int -__i2c_read_data(const struct fsl_i2c_base *base, u8 *data, int length) +static inline int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data, + int length) { int i; @@ -399,9 +401,8 @@ __i2c_read_data(const struct fsl_i2c_base *base, u8 *data, int length) return i; } -static int -__i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen, - u8 *data, int dlen) +static int __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, + int olen, u8 *data, int dlen) { int ret = -1; /* signal error */ @@ -447,9 +448,8 @@ __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen, return -1; } -static int -__i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen, - u8 *data, int dlen) +static int __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, + u8 *offset, int olen, u8 *data, int dlen) { int ret = -1; /* signal error */ @@ -471,10 +471,9 @@ __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen, return -1; } -static int -__i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip) +static int __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip) { - /* For unknow reason the controller will ACK when + /* For unknown reason the controller will ACK when * probing for a slave with the same address, so skip * it. */ @@ -484,8 +483,8 @@ __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip) return __i2c_read(base, chip, 0, 0, NULL, 0); } -static unsigned int __i2c_set_bus_speed(const struct fsl_i2c_base *base, - unsigned int speed, int i2c_clk) +static uint __i2c_set_bus_speed(const struct fsl_i2c_base *base, + uint speed, int i2c_clk) { writeb(0, &base->cr); /* stop controller */ set_i2c_bus_speed(base, i2c_clk, speed); @@ -501,32 +500,30 @@ static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) get_i2c_clock(adap->hwadapnr), adap->hwadapnr); } -static int -fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip) +static int fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip) { return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip); } -static int -fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen, - u8 *data, int dlen) +static int fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, + int olen, u8 *data, int dlen) { u8 *o = (u8 *)&offset; + return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen], olen, data, dlen); } -static int -fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen, - u8 *data, int dlen) +static int fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, + int olen, u8 *data, int dlen) { u8 *o = (u8 *)&offset; + return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen], olen, data, dlen); } -static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap, - unsigned int speed) +static uint fsl_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) { return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed, get_i2c_clock(adap->hwadapnr)); @@ -562,12 +559,14 @@ static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr, u32 chip_flags) { struct fsl_i2c_dev *dev = dev_get_priv(bus); + return __i2c_probe_chip(dev->base, chip_addr); } -static int fsl_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +static int fsl_i2c_set_bus_speed(struct udevice *bus, uint speed) { struct fsl_i2c_dev *dev = dev_get_priv(bus); + return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk); } @@ -600,6 +599,7 @@ static int fsl_i2c_ofdata_to_platdata(struct udevice *bus) static int fsl_i2c_probe(struct udevice *bus) { struct fsl_i2c_dev *dev = dev_get_priv(bus); + __i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk, dev->index); return 0; @@ -613,7 +613,8 @@ static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) memset(&dummy, 0, sizeof(struct i2c_msg)); /* We expect either two messages (one with an offset and one with the - * actucal data) or one message (just data) */ + * actual data) or one message (just data) + */ if (nmsgs > 2 || nmsgs == 0) { debug("%s: Only one or two messages are supported.", __func__); return -1; -- 2.11.0

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[U-Boot] [PATCH] arm64: zynqmp: Sync mini defconfigs with latest fpga changes
by Michal Simek 06 Feb '18

06 Feb '18

The patch "cmd: Make CONFIG_CMD_FPGA depend on CONFIG_FPGA" (sha1: a4fa8114632a008735142b12a29de1771a115209) added dependency on FPGA which is not reflected in mini defconfigs. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- configs/xilinx_zynqmp_mini_emmc_defconfig | 1 - configs/xilinx_zynqmp_mini_nand_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/xilinx_zynqmp_mini_emmc_defconfig b/configs/xilinx_zynqmp_mini_emmc_defconfig index 5d854d9b8bc1..f77abf2f8cd3 100644 --- a/configs/xilinx_zynqmp_mini_emmc_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc_defconfig @@ -24,7 +24,6 @@ CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_CRC32 is not set # CONFIG_CMD_DM is not set # CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig index d6e2eb8a16e8..8a5de92ec9c8 100644 --- a/configs/xilinx_zynqmp_mini_nand_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_defconfig @@ -24,7 +24,6 @@ CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_CRC32 is not set # CONFIG_CMD_DM is not set # CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_ECHO is not set -- 1.9.1

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[U-Boot] [PATCH] Kconfig: Use imply for network commands in distro default
by Michal Simek 06 Feb '18

06 Feb '18

There is no reason to unconditially select network commands as distro defaults. Systems without ethernet but with sd, sata, usb should also be able to use distro defaults. Use imply instead of select. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Kconfig b/Kconfig index 9b8a8077993a..55bb00936cf7 100644 --- a/Kconfig +++ b/Kconfig @@ -69,14 +69,14 @@ config DISTRO_DEFAULTS imply USE_BOOTCOMMAND select CMD_BOOTZ if ARM && !ARM64 select CMD_BOOTI if ARM64 - select CMD_DHCP - select CMD_PXE + imply CMD_DHCP + imply CMD_PXE select CMD_EXT2 select CMD_EXT4 select CMD_FAT select CMD_FS_GENERIC - select CMD_MII - select CMD_PING + imply CMD_MII + imply CMD_PING select CMD_PART select HUSH_PARSER help -- 1.9.1

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Re: [U-Boot] [PATCH v3 12/15] env: Allow to build multiple environments in Kconfig
by Goldschmidt Simon 06 Feb '18

06 Feb '18

On 01.02.2018 20:47, Maxime Ripard wrote: > On Thu, Feb 01, 2018 at 11:06:14AM +0100, Simon Goldschmidt wrote: >> On 23.01.2018 21:17, Maxime Ripard wrote: >> > Now that we have everything in place in the code, let's allow to build >> > multiple environments backend through Kconfig. >> > >> > Reviewed-by: Andre Przywara <andre.przywara(a)arm.com> >> > Reviewed-by: Lukasz Majewski <lukma(a)denx.de> >> > Reviewed-by: Simon Glass <sjg(a)chromium.org> >> > Signed-off-by: Maxime Ripard <maxime.ripard(a)free-electrons.com> >> >> I get a build error when enabling CONFIG_ENV_IS_IN_SPI_FLASH and >> CONFIG_ENV_IS_IN_MMC at the same time. > > Is that happening in any of the current defconfig right now? Or is it > only when you add more environments? No, this is with my own config. I'm trying out the new feature :-) > >> The build error is in host tools, not in U-Boot or SPL itself. In fact, this >> is not specific to CONFIG_ENV_IS_IN_SPI_FLASH but to the combination of >> CONFIG_ENV_IS_IN_MMC and any of the environments marked as ENVCRC- in >> tools/Makefile. >> >> The actual error is that the compiler does not know standard types in efi.h >> and mmc.h, e.g.: >> In file included from include/blk.h:11:0, >> from include/part.h:10, >> from include/mmc.h:16, >> from include/environment.h:168, >> from ./tools/../env/embedded.c:16, >> from tools/env/embedded.c:2: >> include/efi.h:32:2: error: unknown type name ‘u8’ >> u8 b[16]; >> ^~ >> >> I can't think of a correct fix right now... > > I'm not sure what it could be either, that file looks like it would > need a quite big rework, in order to be able to operate properly. > > Do you actually need those? Maybe we can just disable those in Kconfig > to forbid such a combination? I planned to have the environment in both SPI flash and eMMC to be able to use a common U-Boot binary accross multiple boards. I don't need 'tools/envcrc' though. And this is where the build error is. Maybe we could disable the combination for 'tools/envcrc' only? Simon

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[U-Boot] [PATCH 0/4] arm: imx: convert MX23/28 and MXS NAND to Kconfig
by Stefan Agner 06 Feb '18

06 Feb '18

From: Stefan Agner <stefan.agner(a)toradex.com> This converts i.MX23/28 to Kconfig. This helps to properly add dependencies for GPMI NAND (NAND_MXS) configs. Patch 4 is from a previous patchset "mtd: nand: mxs_nand: improve ECC support". -- Stefan Stefan Agner (4): arm: imx: mx23: Move MX23 selection to Kconfig arm: imx: mx28: Move MX28 selection to Kconfig spl: use ARCH_MX23/28 to specify SPL_LDSCRIPT Convert CONFIG_NAND_MXS to Kconfig arch/arm/Kconfig | 87 +++++---------------------------- arch/arm/mach-imx/mx2/Kconfig | 79 ++++++++++++++++++++++++++++++ configs/apx4devkit_defconfig | 6 ++- configs/aristainetos2_defconfig | 3 +- configs/aristainetos2b_defconfig | 3 +- configs/aristainetos_defconfig | 3 +- configs/bg0900_defconfig | 6 ++- configs/cm_fx6_defconfig | 11 +---- configs/colibri_imx7_defconfig | 3 +- configs/gwventana_nand_defconfig | 3 +- configs/m28evk_defconfig | 6 ++- configs/mx23_olinuxino_defconfig | 3 +- configs/mx23evk_defconfig | 3 +- configs/mx28evk_auart_console_defconfig | 6 ++- configs/mx28evk_defconfig | 6 ++- configs/mx28evk_nand_defconfig | 6 ++- configs/mx28evk_spi_defconfig | 6 ++- configs/mx6sabreauto_defconfig | 3 +- configs/mx6sxsabreauto_defconfig | 3 +- configs/pcm058_defconfig | 3 +- configs/pfla02_defconfig | 3 ++ configs/platinum_picon_defconfig | 3 +- configs/platinum_titanium_defconfig | 3 +- configs/sansa_fuze_plus_defconfig | 1 + configs/sc_sps_1_defconfig | 3 +- configs/titanium_defconfig | 3 +- configs/ts4600_defconfig | 3 +- configs/xfi3_defconfig | 3 +- drivers/mtd/nand/Kconfig | 2 +- include/configs/apx4devkit.h | 1 - include/configs/aristainetos-common.h | 1 - include/configs/bg0900.h | 3 -- include/configs/cm_fx6.h | 1 - include/configs/colibri_imx7.h | 2 - include/configs/gw_ventana.h | 1 - include/configs/m28evk.h | 1 - include/configs/mx23_olinuxino.h | 1 - include/configs/mx23evk.h | 1 - include/configs/mx28evk.h | 1 - include/configs/mx6sabreauto.h | 1 - include/configs/mx6sxsabreauto.h | 1 - include/configs/mxs.h | 1 - include/configs/pcm058.h | 1 - include/configs/pfla02.h | 1 - include/configs/platinum.h | 1 - include/configs/sansa_fuze_plus.h | 3 -- include/configs/sc_sps_1.h | 1 - include/configs/titanium.h | 1 - include/configs/ts4600.h | 3 -- include/configs/xfi3.h | 3 -- scripts/config_whitelist.txt | 2 - 51 files changed, 159 insertions(+), 146 deletions(-) -- 2.16.1

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[U-Boot] [PATCH v3 1/2] arm: sunxi: Allwinner A10 SPI driver
by Stefan Mavrodiev 06 Feb '18

06 Feb '18

Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is adapted from mailine kernel. Signed-off-by: Stefan Mavrodiev <stefan(a)olimex.com> --- Changes for v3: - Add required changes in dts and defeconfig file for testing Changes for v2: - Updated copyright including original owners - Remove write/read register function. They are replaced with direct opts - Some coding style changes drivers/spi/Kconfig | 5 + drivers/spi/Makefile | 1 + drivers/spi/sun4i_spi.c | 456 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 462 insertions(+) create mode 100644 drivers/spi/sun4i_spi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 494639f..9001182 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -132,6 +132,11 @@ config STM32_QSPI used to access the SPI NOR flash chips on platforms embedding this ST IP core. +config SUN4I_SPI + bool "Allwinner A10 SoCs SPI controller" + help + SPI driver for Allwinner sun4i, sun5i and sun7i SoCs + config TEGRA114_SPI bool "nVidia Tegra114 SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index e3184db..aa7645a 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o obj-$(CONFIG_SH_SPI) += sh_spi.o obj-$(CONFIG_SH_QSPI) += sh_qspi.o obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o +obj-$(CONFIG_SUN4I_SPI) += sun4i_spi.o obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o diff --git a/drivers/spi/sun4i_spi.c b/drivers/spi/sun4i_spi.c new file mode 100644 index 0000000..4f4cca6 --- /dev/null +++ b/drivers/spi/sun4i_spi.c @@ -0,0 +1,456 @@ +/* + * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V. + * S.J.R. van Schaik <stephan(a)whiteboxsystems.nl> + * M.B.W. Wajer <merlijn(a)whiteboxsystems.nl> + * + * (C) Copyright 2017 Olimex Ltd.. + * Stefan Mavrodiev <stefan(a)olimex.com> + * + * + * Based on linux spi driver. Original copyright follows: + * linux/drivers/spi/spi-sun4i.c + * + * Copyright (C) 2012 - 2014 Allwinner Tech + * Pan Nan <pannan(a)allwinnertech.com> + * + * Copyright (C) 2014 Maxime Ripard + * Maxime Ripard <maxime.ripard(a)free-electrons.com> + * + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <spi.h> +#include <errno.h> +#include <fdt_support.h> +#include <wait_bit.h> + +#include <asm/bitops.h> +#include <asm/gpio.h> +#include <asm/io.h> + +#include <asm/arch/clock.h> + +#define SUN4I_FIFO_DEPTH 64 + +#define SUN4I_RXDATA_REG 0x00 + +#define SUN4I_TXDATA_REG 0x04 + +#define SUN4I_CTL_REG 0x08 +#define SUN4I_CTL_ENABLE BIT(0) +#define SUN4I_CTL_MASTER BIT(1) +#define SUN4I_CTL_CPHA BIT(2) +#define SUN4I_CTL_CPOL BIT(3) +#define SUN4I_CTL_CS_ACTIVE_LOW BIT(4) +#define SUN4I_CTL_LMTF BIT(6) +#define SUN4I_CTL_TF_RST BIT(8) +#define SUN4I_CTL_RF_RST BIT(9) +#define SUN4I_CTL_XCH_MASK 0x0400 +#define SUN4I_CTL_XCH BIT(10) +#define SUN4I_CTL_CS_MASK 0x3000 +#define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK) +#define SUN4I_CTL_DHB BIT(15) +#define SUN4I_CTL_CS_MANUAL BIT(16) +#define SUN4I_CTL_CS_LEVEL BIT(17) +#define SUN4I_CTL_TP BIT(18) + +#define SUN4I_INT_CTL_REG 0x0c +#define SUN4I_INT_CTL_RF_F34 BIT(4) +#define SUN4I_INT_CTL_TF_E34 BIT(12) +#define SUN4I_INT_CTL_TC BIT(16) + +#define SUN4I_INT_STA_REG 0x10 + +#define SUN4I_DMA_CTL_REG 0x14 + +#define SUN4I_WAIT_REG 0x18 + +#define SUN4I_CLK_CTL_REG 0x1c +#define SUN4I_CLK_CTL_CDR2_MASK 0xff +#define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK) +#define SUN4I_CLK_CTL_CDR1_MASK 0xf +#define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8) +#define SUN4I_CLK_CTL_DRS BIT(12) + +#define SUN4I_MAX_XFER_SIZE 0xffffff + +#define SUN4I_BURST_CNT_REG 0x20 +#define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE) + +#define SUN4I_XMIT_CNT_REG 0x24 +#define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE) + +#define SUN4I_FIFO_STA_REG 0x28 +#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f +#define SUN4I_FIFO_STA_RF_CNT_BITS 0 +#define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f +#define SUN4I_FIFO_STA_TF_CNT_BITS 16 + +#define SUN4I_SPI_MAX_RATE 24000000 +#define SUN4I_SPI_MIN_RATE 3000 +#define SUN4I_SPI_DEFAULT_RATE 1000000 +#define SUN4I_SPI_TIMEOUT_US 1000000 + +/* sun4i spi register set */ +struct sun4i_spi_regs { + u32 rxdata; + u32 txdata; + u32 ctl; + u32 intctl; + u32 st; + u32 dmactl; + u32 wait; + u32 cctl; + u32 bc; + u32 tc; + u32 fifo_sta; +}; + +struct sun4i_spi_platdata { + u32 base_addr; + u32 max_hz; +}; + +struct sun4i_spi_priv { + struct sun4i_spi_regs *regs; + u32 freq; + u32 mode; + + const u8 *tx_buf; + u8 *rx_buf; +}; + +DECLARE_GLOBAL_DATA_PTR; + +static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len) +{ + u8 byte; + + while (len--) { + byte = readb(&priv->regs->rxdata); + *priv->rx_buf++ = byte; + } +} + +static inline void sun4i_spi_fill_fifo(struct sun4i_spi_priv *priv, int len) +{ + u8 byte; + + while (len--) { + byte = priv->tx_buf ? *priv->tx_buf++ : 0; + writeb(byte, &priv->regs->txdata); + } +} + +static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable) +{ + struct sun4i_spi_priv *priv = dev_get_priv(bus); + u32 reg; + + reg = readl(&priv->regs->ctl); + + reg &= ~SUN4I_CTL_CS_MASK; + reg |= SUN4I_CTL_CS(cs); + + if (enable) + reg &= ~SUN4I_CTL_CS_LEVEL; + else + reg |= SUN4I_CTL_CS_LEVEL; + + writel(reg, &priv->regs->ctl); +} + +static int sun4i_spi_parse_pins(struct udevice *dev) +{ + const void *fdt = gd->fdt_blob; + const char *pin_name; + const fdt32_t *list; + u32 phandle; + int drive, pull = 0, pin, i; + int offset; + int size; + + list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size); + if (!list) { + printf("WARNING: sun4i_spi: cannot find pinctrl-0 node\n"); + return -EINVAL; + } + + while (size) { + phandle = fdt32_to_cpu(*list++); + size -= sizeof(*list); + + offset = fdt_node_offset_by_phandle(fdt, phandle); + if (offset < 0) + return offset; + + drive = fdt_getprop_u32_default_node(fdt, offset, 0, + "drive-strength", 0); + if (drive) { + if (drive <= 10) + drive = 0; + else if (drive <= 20) + drive = 1; + else if (drive <= 30) + drive = 2; + else + drive = 3; + } else { + drive = fdt_getprop_u32_default_node(fdt, offset, 0, + "allwinner,drive", + 0); + drive = min(drive, 3); + } + + if (fdt_get_property(fdt, offset, "bias-disable", NULL)) + pull = 0; + else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL)) + pull = 1; + else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL)) + pull = 2; + else + pull = fdt_getprop_u32_default_node(fdt, offset, 0, + "allwinner,pull", + 0); + pull = min(pull, 2); + + for (i = 0; ; i++) { + pin_name = fdt_stringlist_get(fdt, offset, + "pins", i, NULL); + if (!pin_name) { + pin_name = fdt_stringlist_get(fdt, offset, + "allwinner,pins", + i, NULL); + if (!pin_name) + break; + } + + pin = name_to_gpio(pin_name); + if (pin < 0) + break; + + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0); + sunxi_gpio_set_drv(pin, drive); + sunxi_gpio_set_pull(pin, pull); + } + } + return 0; +} + +static inline void sun4i_spi_enable_clock(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *const)SUNXI_CCM_BASE; + + setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_SPI0)); + writel((1 << 31), &ccm->spi0_clk_cfg); +} + +static int sun4i_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct sun4i_spi_platdata *plat = dev_get_platdata(bus); + int node = dev_of_offset(bus); + + plat->base_addr = devfdt_get_addr(bus); + plat->max_hz = fdtdec_get_int(gd->fdt_blob, node, + "spi-max-frequency", + SUN4I_SPI_DEFAULT_RATE); + + if (plat->max_hz > SUN4I_SPI_MAX_RATE) + plat->max_hz = SUN4I_SPI_MAX_RATE; + + return 0; +} + +static int sun4i_spi_probe(struct udevice *bus) +{ + struct sun4i_spi_platdata *plat = dev_get_platdata(bus); + struct sun4i_spi_priv *priv = dev_get_priv(bus); + + sun4i_spi_enable_clock(); + sun4i_spi_parse_pins(bus); + + priv->regs = (struct sun4i_spi_regs *)(uintptr_t)plat->base_addr; + priv->freq = plat->max_hz; + + return 0; +} + +static int sun4i_spi_claim_bus(struct udevice *dev) +{ + struct sun4i_spi_priv *priv = dev_get_priv(dev->parent); + + writel(SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP | + SUN4I_CTL_CS_MANUAL | SUN4I_CTL_CS_ACTIVE_LOW, + &priv->regs->ctl); + return 0; +} + +static int sun4i_spi_release_bus(struct udevice *dev) +{ + struct sun4i_spi_priv *priv = dev_get_priv(dev->parent); + u32 reg; + + reg = readl(&priv->regs->ctl); + reg &= ~SUN4I_CTL_ENABLE; + writel(reg, &priv->regs->ctl); + + return 0; +} + +static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct sun4i_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + + u32 len = bitlen / 8; + u32 reg; + u8 nbytes; + int ret; + + priv->tx_buf = dout; + priv->rx_buf = din; + + if (bitlen % 8) { + debug("%s: non byte-aligned SPI transfer.\n", __func__); + return -ENAVAIL; + } + + if (flags & SPI_XFER_BEGIN) + sun4i_spi_set_cs(bus, slave_plat->cs, true); + + reg = readl(&priv->regs->ctl); + + /* Reset FIFOs */ + writel(reg | SUN4I_CTL_RF_RST | SUN4I_CTL_TF_RST, &priv->regs->ctl); + + while (len) { + /* Setup the transfer now... */ + nbytes = min(len, (u32)(SUN4I_FIFO_DEPTH - 1)); + + /* Setup the counters */ + writel(SUN4I_BURST_CNT(nbytes), &priv->regs->bc); + writel(SUN4I_XMIT_CNT(nbytes), &priv->regs->tc); + + /* Fill the TX FIFO */ + sun4i_spi_fill_fifo(priv, nbytes); + + /* Start the transfer */ + reg = readl(&priv->regs->ctl); + writel(reg | SUN4I_CTL_XCH, &priv->regs->ctl); + + /* Wait transfer to complete */ + ret = wait_for_bit(__func__, &priv->regs->ctl, + SUN4I_CTL_XCH_MASK, false, + SUN4I_SPI_TIMEOUT_US, false); + if (ret) { + printf("ERROR: sun4i_spi: Timeout transferring data\n"); + sun4i_spi_set_cs(bus, slave_plat->cs, false); + return ret; + } + + /* Drain the RX FIFO */ + sun4i_spi_drain_fifo(priv, nbytes); + + len -= nbytes; + } + + if (flags & SPI_XFER_END) + sun4i_spi_set_cs(bus, slave_plat->cs, false); + + return 0; +} + +static int sun4i_spi_set_speed(struct udevice *dev, uint speed) +{ + struct sun4i_spi_platdata *plat = dev_get_platdata(dev); + struct sun4i_spi_priv *priv = dev_get_priv(dev); + unsigned int div; + u32 reg; + + if (speed > plat->max_hz) + speed = plat->max_hz; + + if (speed < SUN4I_SPI_MIN_RATE) + speed = SUN4I_SPI_MIN_RATE; + /* + * Setup clock divider. + * + * We have two choices there. Either we can use the clock + * divide rate 1, which is calculated thanks to this formula: + * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1)) + * Or we can use CDR2, which is calculated with the formula: + * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) + * Whether we use the former or the latter is set through the + * DRS bit. + * + * First try CDR2, and if we can't reach the expected + * frequency, fall back to CDR1. + */ + + div = SUN4I_SPI_MAX_RATE / (2 * speed); + + if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) { + if (div > 0) + div--; + + reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS; + } else { + div = __ilog2(SUN4I_SPI_MAX_RATE) - __ilog2(speed); + reg = SUN4I_CLK_CTL_CDR1(div); + } + + priv->freq = speed; + writel(reg, &priv->regs->cctl); + + return 0; +} + +static int sun4i_spi_set_mode(struct udevice *dev, uint mode) +{ + struct sun4i_spi_priv *priv = dev_get_priv(dev); + u32 reg; + + reg = readl(&priv->regs->ctl); + reg &= ~(SUN4I_CTL_CPOL | SUN4I_CTL_CPHA); + + if (mode & SPI_CPOL) + reg |= SUN4I_CTL_CPOL; + + if (mode & SPI_CPHA) + reg |= SUN4I_CTL_CPHA; + + priv->mode = mode; + writel(reg, &priv->regs->ctl); + + return 0; +} + +static const struct dm_spi_ops sun4i_spi_ops = { + .claim_bus = sun4i_spi_claim_bus, + .release_bus = sun4i_spi_release_bus, + .xfer = sun4i_spi_xfer, + .set_speed = sun4i_spi_set_speed, + .set_mode = sun4i_spi_set_mode, +}; + +static const struct udevice_id sun4i_spi_ids[] = { + { .compatible = "allwinner,sun4i-a10-spi" }, + { } +}; + +U_BOOT_DRIVER(sun4i_spi) = { + .name = "sun4i_spi", + .id = UCLASS_SPI, + .of_match = sun4i_spi_ids, + .ops = &sun4i_spi_ops, + .ofdata_to_platdata = sun4i_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct sun4i_spi_platdata), + .priv_auto_alloc_size = sizeof(struct sun4i_spi_priv), + .probe = sun4i_spi_probe, +}; -- 2.7.4

3 11

[U-Boot] UDP packet sender
by Gaëtan Carlier 06 Feb '18

06 Feb '18

Hi, I would like to implement a new command and submit it to the mailing list. The command will have the following format: udpsend <destination/broadcast ip> <destination port> <source port> <text to send> udpsend 255.255.255.255 4040 0 hello world If source port is 0, a random port will be used (11000 + (get_timer(0) % 4096)) Where do I have to place my code : cmd or net directory ? For me cmd will be the better directory to keep it away from all more complex stuff like DHCP, TFTP, ... Thank you for these informations. Regards, Gaëtan.

3 8

[U-Boot] [PATCH] arm64 :show_regs: show the address before relocation
by Peng Fan 06 Feb '18

06 Feb '18

After relocation, when error happends, it is hard to track ELR and LR with asm file objdumped from elf file. So subtract the gd->reloc_off the reflect the compliation address. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- arch/arm/lib/interrupts_64.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c index 7c9cfce69f..cbcfeec2b0 100644 --- a/arch/arm/lib/interrupts_64.c +++ b/arch/arm/lib/interrupts_64.c @@ -9,6 +9,7 @@ #include <linux/compiler.h> #include <efi_loader.h> +DECLARE_GLOBAL_DATA_PTR; int interrupt_init(void) { @@ -29,8 +30,13 @@ void show_regs(struct pt_regs *regs) { int i; - printf("ELR: %lx\n", regs->elr); - printf("LR: %lx\n", regs->regs[30]); + if (gd->flags & GD_FLG_RELOC) { + printf("ELR: %lx\n", regs->elr - gd->reloc_off); + printf("LR: %lx\n", regs->regs[30] - gd->reloc_off); + } else { + printf("ELR: %lx\n", regs->elr); + printf("LR: %lx\n", regs->regs[30]); + } for (i = 0; i < 29; i += 2) printf("x%-2d: %016lx x%-2d: %016lx\n", i, regs->regs[i], i+1, regs->regs[i+1]); -- 2.14.1

4 6

[U-Boot] [PATCH] usb: ulpi: kconfig: Remove meaningless choice default
by Ulf Magnusson 06 Feb '18

06 Feb '18

'default' on a choice refers to the symbol selected by default, not to the choice mode, so 'default n' is meaningless. No functional changes. Optional choices implicitly default to n mode (and there is no way to make them default to another mode). Discovered in Kconfiglib (https://github.com/ulfalizer/Kconfiglib), which prints the following warning: warning: the default selection n (undefined) of <choice> (defined at drivers/usb/ulpi/Kconfig:3) is not contained in the choice I've added a corresponding warning to the C tools too, which is currently in linux-next: https://patchwork.kernel.org/patch/9983667/ Signed-off-by: Ulf Magnusson <ulfalizer(a)gmail.com> --- drivers/usb/ulpi/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/usb/ulpi/Kconfig b/drivers/usb/ulpi/Kconfig index 329d2df3ed..001564d40c 100644 --- a/drivers/usb/ulpi/Kconfig +++ b/drivers/usb/ulpi/Kconfig @@ -3,7 +3,6 @@ comment "ULPI drivers" choice prompt "ULPI Viewport type" optional - default n help Select ULPI viewport (SoC-side interface to ULPI) implementation appropriate for the device if you want to communicate with -- 2.14.1

2 1