February 2018 - U-Boot

[U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series
by Calvin Johnson 01 Mar '18

01 Mar '18

Hi, This patch series introduces U-Boot support for NXP's LS1012A Packet Forwarding Engine (pfe_eth). LS1012A uses hardware packet forwarding engine to provide high performance Ethernet interfaces. The device includes two Ethernet ports. Changes in v2 series: 1. PFE patches submitted on top of this base patch are now merged to this patch. 2. Platform changes are segregated into different patches. 3. Network enabled on 2g5rdb platform 4. Moved from legacy to new driver model. Calvin Johnson (12): drivers: net: phy: Fix aquantia compilation with DM drivers: net: pfe_eth: LS1012A PFE driver introduction drivers: net: pfe_eth: provide pfe commands drivers: net: pfe_eth: LS1012A PFE headers board: freescale: ls1012aqds: enable network support on ls1012aqds board: freescale: ls1012afrdm: enable network support on ls1012afrdm board: freescale: ls1012ardb: enable network support on ls1012ardb board: freescale: ls1012a2g5rdb: enable network support on ls1012a2g5rdb armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC armv8: layerscape: csu: enable ns access to PFE registers configs: ls1012a: add pfe configuration for LS1012A Prabhakar Kushwaha (1): armv8: fsl-layerscape: Add support of GPIO structure arch/arm/cpu/armv8/fsl-layerscape/soc.c | 23 + .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 63 +- .../include/asm/arch-fsl-layerscape/ns_access.h | 2 + arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 + board/freescale/ls1012afrdm/Kconfig | 14 + board/freescale/ls1012afrdm/Makefile | 1 + board/freescale/ls1012afrdm/eth.c | 122 +++ board/freescale/ls1012afrdm/ls1012afrdm.c | 5 - board/freescale/ls1012aqds/Kconfig | 14 + board/freescale/ls1012aqds/Makefile | 1 + board/freescale/ls1012aqds/eth.c | 304 +++++++ board/freescale/ls1012aqds/ls1012aqds.c | 97 +- board/freescale/ls1012aqds/ls1012aqds_pfe.h | 48 + board/freescale/ls1012aqds/ls1012aqds_qixis.h | 2 +- board/freescale/ls1012ardb/Kconfig | 28 + board/freescale/ls1012ardb/Makefile | 1 + board/freescale/ls1012ardb/eth.c | 131 +++ board/freescale/ls1012ardb/ls1012ardb.c | 4 - configs/ls1012a2g5rdb_qspi_defconfig | 2 + configs/ls1012afrdm_qspi_defconfig | 2 + configs/ls1012aqds_qspi_defconfig | 2 + configs/ls1012ardb_qspi_defconfig | 2 + drivers/net/Kconfig | 1 + drivers/net/Makefile | 1 + drivers/net/pfe_eth/Kconfig | 17 + drivers/net/pfe_eth/Makefile | 12 + drivers/net/pfe_eth/pfe_cmd.c | 497 ++++++++++ drivers/net/pfe_eth/pfe_driver.c | 643 +++++++++++++ drivers/net/pfe_eth/pfe_eth.c | 297 ++++++ drivers/net/pfe_eth/pfe_firmware.c | 230 +++++ drivers/net/pfe_eth/pfe_hw.c | 999 +++++++++++++++++++++ drivers/net/pfe_eth/pfe_mdio.c | 291 ++++++ drivers/net/phy/aquantia.c | 1 + include/configs/ls1012a2g5rdb.h | 2 +- include/configs/ls1012a_common.h | 6 +- include/configs/ls1012afrdm.h | 9 +- include/configs/ls1012aqds.h | 14 + include/configs/ls1012ardb.h | 14 +- include/dm/platform_data/pfe_dm_eth.h | 21 + include/pfe_eth/pfe/cbus.h | 77 ++ include/pfe_eth/pfe/cbus/bmu.h | 40 + include/pfe_eth/pfe/cbus/class_csr.h | 180 ++++ include/pfe_eth/pfe/cbus/emac.h | 140 +++ include/pfe_eth/pfe/cbus/gpi.h | 62 ++ include/pfe_eth/pfe/cbus/hif.h | 68 ++ include/pfe_eth/pfe/cbus/hif_nocpy.h | 40 + include/pfe_eth/pfe/cbus/tmu_csr.h | 148 +++ include/pfe_eth/pfe/cbus/util_csr.h | 47 + include/pfe_eth/pfe/pfe_hw.h | 163 ++++ include/pfe_eth/pfe_driver.h | 59 ++ include/pfe_eth/pfe_eth.h | 104 +++ include/pfe_eth/pfe_firmware.h | 17 + include/pfe_eth/pfe_mdio.h | 13 + 53 files changed, 5060 insertions(+), 24 deletions(-) create mode 100644 board/freescale/ls1012afrdm/eth.c create mode 100644 board/freescale/ls1012aqds/eth.c create mode 100644 board/freescale/ls1012aqds/ls1012aqds_pfe.h create mode 100644 board/freescale/ls1012ardb/eth.c create mode 100644 drivers/net/pfe_eth/Kconfig create mode 100644 drivers/net/pfe_eth/Makefile create mode 100644 drivers/net/pfe_eth/pfe_cmd.c create mode 100644 drivers/net/pfe_eth/pfe_driver.c create mode 100644 drivers/net/pfe_eth/pfe_eth.c create mode 100644 drivers/net/pfe_eth/pfe_firmware.c create mode 100644 drivers/net/pfe_eth/pfe_hw.c create mode 100644 drivers/net/pfe_eth/pfe_mdio.c create mode 100644 include/dm/platform_data/pfe_dm_eth.h create mode 100644 include/pfe_eth/pfe/cbus.h create mode 100644 include/pfe_eth/pfe/cbus/bmu.h create mode 100644 include/pfe_eth/pfe/cbus/class_csr.h create mode 100644 include/pfe_eth/pfe/cbus/emac.h create mode 100644 include/pfe_eth/pfe/cbus/gpi.h create mode 100644 include/pfe_eth/pfe/cbus/hif.h create mode 100644 include/pfe_eth/pfe/cbus/hif_nocpy.h create mode 100644 include/pfe_eth/pfe/cbus/tmu_csr.h create mode 100644 include/pfe_eth/pfe/cbus/util_csr.h create mode 100644 include/pfe_eth/pfe/pfe_hw.h create mode 100644 include/pfe_eth/pfe_driver.h create mode 100644 include/pfe_eth/pfe_eth.h create mode 100644 include/pfe_eth/pfe_firmware.h create mode 100644 include/pfe_eth/pfe_mdio.h -- 2.7.4

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[U-Boot] [PATCH] This patch is the Interfaces changes for, net.h, net.c, ping.c files for introducing TCP and wget into u-boot.
by DH＠synoia.com 01 Mar '18

01 Mar '18

From: Duncan Hare <DuncanCHare(a)yahoo.com> All the code is new, and not copied from any source. >>>>> <<<< Commit-notes Why netboot: Central management, including logs and change control, coupled with with enhanced security and unauthorized change detection and remediation by exposing a small attack surface. Why TCP: Currently file transfer are done using tftp or NFS both over udp. This requires a request to be sent from client (u-boot) to the boot server. For a 4 Mbyte kernel, with a 1k block size this requires 4,000 request for a block. Using a large block size, one greater than the Ethernet maximum frame size limitation, would require fragmentation, which u-boot supports. However missing fragment recovery requires timeout detection and re-transmission requests for missing fragments. UDP is ideally suited to fast single packet exchanges, inquiry/response, for example dns, becuse of the lack of connection overhead. UDP as a file transport mechanism is slow, even in low latency networks, because file transfer with udp requires poll/response mechanism to provide transfer integrity. In networks with large latency, for example: the internet, UDP is even slower. What is a 30 second transfer on a local boot server and LAN increase to over 3 minutes, because of all the requests/response traffic. This was anticipated in the evolution of the IP protocols and TCP was developed and then enhanced for high latency high bandwidth networks. The current standard is TCP with selective acknowledgment. In our testing we have reduce kernel transmission time to around 0.4 seconds for a 4Mbyte kernel, with a 100 Mbps downlink. Why http and wget: HTTP is the most efficient file retrieval protocol in common use. The client send a single request, after TCP connection, to receive a file of any length. WGET is the application which implements http file transfer outside browsers as a file transfer protocol. Versions of wget exists on many operating systems. END Signed-off-by: Duncan Hare <DuncanCHare(a)yahoo.com> --- Changes in v7: Revised to meet patch review Patch 1 Interfaces patch 2 TCP Patch 3 wget include/net.h | 25 +++++++++++++++++++------ net/net.c | 10 +++++++--- net/ping.c | 9 ++------- 3 files changed, 28 insertions(+), 16 deletions(-) diff --git a/include/net.h b/include/net.h index 455b48f6c7..7e5f5a6a5b 100644 --- a/include/net.h +++ b/include/net.h @@ -15,17 +15,26 @@ #include <asm/cache.h> #include <asm/byteorder.h> /* for nton* / ntoh* stuff */ -#define DEBUG_LL_STATE 0 /* Link local state machine changes */ -#define DEBUG_DEV_PKT 0 /* Packets or info directed to the device */ -#define DEBUG_NET_PKT 0 /* Packets on info on the network at large */ +#define DEBUG_LL_STATE 0 /* Link local state machine changes */ +#define DEBUG_DEV_PKT 0 /* Packets or info directed to the device */ +#define DEBUG_NET_PKT 0 /* Packets on info on the network at large */ #define DEBUG_INT_STATE 0 /* Internal network state changes */ /* * The number of receive packet buffers, and the required packet buffer * alignment in memory. * + * The number of buffers for TCP is used to calculate a static TCP window + * size, becuse TCP window size is a promise to the sending TCP to be able + * to buffer up to the window size of data. + * When the sending TCP has a window size of outstanding unacknowledged + * data, the sending TCP will stop sending. */ +#if defined(CONFIG_TCP) +#define CONFIG_SYS_RX_ETH_BUFFER 12 /* For TCP */ +#endif + #ifdef CONFIG_SYS_RX_ETH_BUFFER # define PKTBUFSRX CONFIG_SYS_RX_ETH_BUFFER #else @@ -354,6 +363,7 @@ struct vlan_ethernet_hdr { #define IPPROTO_ICMP 1 /* Internet Control Message Protocol */ #define IPPROTO_UDP 17 /* User Datagram Protocol */ +#define IPPROTO_TCP 6 /* Transmission Control Protocol */ /* * Internet Protocol (IP) header. @@ -596,10 +606,10 @@ int net_set_ether(uchar *xet, const uchar *dest_ethaddr, uint prot); int net_update_ether(struct ethernet_hdr *et, uchar *addr, uint prot); /* Set IP header */ -void net_set_ip_header(uchar *pkt, struct in_addr dest, struct in_addr source); +void net_set_ip_header(uchar *pkt, struct in_addr dest, struct in_addr source, + u16 pkt_len, u8 prot); void net_set_udp_header(uchar *pkt, struct in_addr dest, int dport, - int sport, int len); - + int sport, int len); /** * compute_ip_checksum() - Compute IP checksum * @@ -670,6 +680,9 @@ static inline void net_send_packet(uchar *pkt, int len) * @param sport Source UDP port * @param payload_len Length of data after the UDP header */ +int net_send_ip_packet(uchar *ether, struct in_addr dest, int dport, int sport, + int payload_len, int proto); + int net_send_udp_packet(uchar *ether, struct in_addr dest, int dport, int sport, int payload_len); diff --git a/net/net.c b/net/net.c index 4259c9e321..26aab1f30f 100644 --- a/net/net.c +++ b/net/net.c @@ -1426,7 +1426,9 @@ int net_update_ether(struct ethernet_hdr *et, uchar *addr, uint prot) } } -void net_set_ip_header(uchar *pkt, struct in_addr dest, struct in_addr source) +void net_set_ip_header(uchar *pkt, struct in_addr dest, struct in_addr source, + u16 pkt_len, u8 prot) + { struct ip_udp_hdr *ip = (struct ip_udp_hdr *)pkt; @@ -1436,10 +1438,11 @@ void net_set_ip_header(uchar *pkt, struct in_addr dest, struct in_addr source) /* IP_HDR_SIZE / 4 (not including UDP) */ ip->ip_hl_v = 0x45; ip->ip_tos = 0; - ip->ip_len = htons(IP_HDR_SIZE); + ip->ip_len = htons(pkt_len); ip->ip_id = htons(net_ip_id++); ip->ip_off = htons(IP_FLAGS_DFRAG); /* Don't fragment */ ip->ip_ttl = 255; + ip->ip_p = prot; ip->ip_sum = 0; /* already in network byte order */ net_copy_ip((void *)&ip->ip_src, &source); @@ -1460,7 +1463,8 @@ void net_set_udp_header(uchar *pkt, struct in_addr dest, int dport, int sport, if (len & 1) pkt[IP_UDP_HDR_SIZE + len] = 0; - net_set_ip_header(pkt, dest, net_ip); + net_set_ip_header(pkt, dest, net_ip, IP_UDP_HDR_SIZE + len, + IPPROTO_UDP); ip->ip_len = htons(IP_UDP_HDR_SIZE + len); ip->ip_p = IPPROTO_UDP; ip->ip_sum = compute_ip_checksum(ip, IP_HDR_SIZE); diff --git a/net/ping.c b/net/ping.c index 9508cf1160..254b646193 100644 --- a/net/ping.c +++ b/net/ping.c @@ -20,16 +20,11 @@ struct in_addr net_ping_ip; static void set_icmp_header(uchar *pkt, struct in_addr dest) { /* - * Construct an IP and ICMP header. + * Construct an ICMP header. */ - struct ip_hdr *ip = (struct ip_hdr *)pkt; struct icmp_hdr *icmp = (struct icmp_hdr *)(pkt + IP_HDR_SIZE); - net_set_ip_header(pkt, dest, net_ip); - - ip->ip_len = htons(IP_ICMP_HDR_SIZE); - ip->ip_p = IPPROTO_ICMP; - ip->ip_sum = compute_ip_checksum(ip, IP_HDR_SIZE); + net_set_ip_header(pkt, dest, net_ip, IP_ICMP_HDR_SIZE, IPPROTO_ICMP); icmp->type = ICMP_ECHO_REQUEST; icmp->code = 0; -- 2.11.0

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[U-Boot] [PATCH v2 1/3] watchdog: Add Cadence watchdog driver
by Michal Simek 28 Feb '18

28 Feb '18

From: Shreenidhi Shedi <imshedi(a)gmail.com> This IP can be found on Zynq and ZynqMP devices. The driver was tested with reset-on-timeout; feature. Also adding WATCHDOG symbol to Kconfig because it is required. Signed-off-by: Shreenidhi Shedi <imshedi(a)gmail.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Changes in v2: - s/int32/int/g - Extend CONFIG_WATCHDOG option to have option to disable it. drivers/watchdog/Kconfig | 16 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/cdns_wdt.c | 276 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 293 insertions(+) create mode 100644 drivers/watchdog/cdns_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index fc46b6774d57..8a66e479ab84 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -1,5 +1,13 @@ menu "Watchdog Timer Support" +config WATCHDOG + bool "Enable U-Boot watchdog reset" + help + This option enables U-Boot watchdog support where U-Boot is using + watchdog_reset function to service watchdog device in U-Boot. Enable + this option if you want to service enabled watchdog by U-Boot. Disable + this option if you want U-Boot to start watchdog but never service it. + config HW_WATCHDOG bool @@ -78,4 +86,12 @@ config WDT_ORION Select this to enable Orion watchdog timer, which can be found on some Marvell Armada chips. +config WDT_CDNS + bool "Cadence watchdog timer support" + depends on WDT + imply WATCHDOG + help + Select this to enable Cadence watchdog timer, which can be found on some + Xilinx Microzed Platform. + endmenu diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index ab6a6b79e1d7..4b97df3ab67b 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -22,3 +22,4 @@ obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o +obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o diff --git a/drivers/watchdog/cdns_wdt.c b/drivers/watchdog/cdns_wdt.c new file mode 100644 index 000000000000..71733cf8ba1f --- /dev/null +++ b/drivers/watchdog/cdns_wdt.c @@ -0,0 +1,276 @@ +/* + * Cadence WDT driver - Used by Xilinx Zynq + * Reference: Linux kernel Cadence watchdog driver. + * + * Author(s): Shreenidhi Shedi <yesshedi(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <wdt.h> +#include <clk.h> +#include <linux/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct cdns_regs { + u32 zmr; /* WD Zero mode register, offset - 0x0 */ + u32 ccr; /* Counter Control Register offset - 0x4 */ + u32 restart; /* Restart key register, offset - 0x8 */ + u32 status; /* Status Register, offset - 0xC */ +}; + +struct cdns_wdt_priv { + bool rst; + u32 timeout; + void __iomem *reg; + struct cdns_regs *regs; +}; + +#define CDNS_WDT_DEFAULT_TIMEOUT 10 + +/* Supports 1 - 516 sec */ +#define CDNS_WDT_MIN_TIMEOUT 1 +#define CDNS_WDT_MAX_TIMEOUT 516 + +/* Restart key */ +#define CDNS_WDT_RESTART_KEY 0x00001999 + +/* Counter register access key */ +#define CDNS_WDT_REGISTER_ACCESS_KEY 0x00920000 + +/* Counter value divisor */ +#define CDNS_WDT_COUNTER_VALUE_DIVISOR 0x1000 + +/* Clock prescaler value and selection */ +#define CDNS_WDT_PRESCALE_64 64 +#define CDNS_WDT_PRESCALE_512 512 +#define CDNS_WDT_PRESCALE_4096 4096 +#define CDNS_WDT_PRESCALE_SELECT_64 1 +#define CDNS_WDT_PRESCALE_SELECT_512 2 +#define CDNS_WDT_PRESCALE_SELECT_4096 3 + +/* Input clock frequency */ +#define CDNS_WDT_CLK_75MHZ 75000000 + +/* Counter maximum value */ +#define CDNS_WDT_COUNTER_MAX 0xFFF + +/********************* Register Map **********************************/ + +/* + * Zero Mode Register - This register controls how the time out is indicated + * and also contains the access code to allow writes to the register (0xABC). + */ +#define CDNS_WDT_ZMR_WDEN_MASK 0x00000001 /* Enable the WDT */ +#define CDNS_WDT_ZMR_RSTEN_MASK 0x00000002 /* Enable the reset output */ +#define CDNS_WDT_ZMR_IRQEN_MASK 0x00000004 /* Enable IRQ output */ +#define CDNS_WDT_ZMR_RSTLEN_16 0x00000030 /* Reset pulse of 16 pclk cycles */ +#define CDNS_WDT_ZMR_ZKEY_VAL 0x00ABC000 /* Access key, 0xABC << 12 */ + +/* + * Counter Control register - This register controls how fast the timer runs + * and the reset value and also contains the access code to allow writes to + * the register. + */ +#define CDNS_WDT_CCR_CRV_MASK 0x00003FFC /* Counter reset value */ + +/* Write access to Registers */ +static inline void cdns_wdt_writereg(u32 *addr, u32 val) +{ + writel(val, addr); +} + +/** + * cdns_wdt_reset - Reload the watchdog timer (i.e. pat the watchdog). + * + * @dev: Watchdog device + * + * Write the restart key value (0x00001999) to the restart register. + * + * Return: Always 0 + */ +static int cdns_wdt_reset(struct udevice *dev) +{ + struct cdns_wdt_priv *priv = dev_get_priv(dev); + + debug("%s\n", __func__); + + cdns_wdt_writereg(&priv->regs->restart, CDNS_WDT_RESTART_KEY); + + return 0; +} + +/** + * cdns_wdt_start - Enable and start the watchdog. + * + * @dev: Watchdog device + * @timeout: Timeout value + * @flags: Driver flags + * + * The counter value is calculated according to the formula: + * count = (timeout * clock) / prescaler + 1. + * + * The calculated count is divided by 0x1000 to obtain the field value + * to write to counter control register. + * + * Clears the contents of prescaler and counter reset value. Sets the + * prescaler to 4096 and the calculated count and access key + * to write to CCR Register. + * + * Sets the WDT (WDEN bit) and either the Reset signal(RSTEN bit) + * or Interrupt signal(IRQEN) with a specified cycles and the access + * key to write to ZMR Register. + * + * Return: Upon success 0, failure -1. + */ +static int cdns_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + ulong clk_f; + u32 count, prescaler, ctrl_clksel, data = 0; + struct clk clock; + struct cdns_wdt_priv *priv = dev_get_priv(dev); + + if (clk_get_by_index(dev, 0, &clock) < 0) { + dev_err(dev, "failed to get clock\n"); + return -1; + } + + clk_f = clk_get_rate(&clock); + if (IS_ERR_VALUE(clk_f)) { + dev_err(dev, "failed to get rate\n"); + return -1; + } + + debug("%s: CLK_FREQ %ld, timeout %lld\n", __func__, clk_f, timeout); + + if ((timeout < CDNS_WDT_MIN_TIMEOUT) || + (timeout > CDNS_WDT_MAX_TIMEOUT)) { + timeout = priv->timeout; + } + + if (clk_f <= CDNS_WDT_CLK_75MHZ) { + prescaler = CDNS_WDT_PRESCALE_512; + ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_512; + } else { + prescaler = CDNS_WDT_PRESCALE_4096; + ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_4096; + } + + /* + * Counter value divisor to obtain the value of + * counter reset to be written to control register. + */ + count = (timeout * (clk_f / prescaler)) / + CDNS_WDT_COUNTER_VALUE_DIVISOR + 1; + + if (count > CDNS_WDT_COUNTER_MAX) + count = CDNS_WDT_COUNTER_MAX; + + cdns_wdt_writereg(&priv->regs->zmr, CDNS_WDT_ZMR_ZKEY_VAL); + + count = (count << 2) & CDNS_WDT_CCR_CRV_MASK; + + /* Write counter access key first to be able write to register */ + data = count | CDNS_WDT_REGISTER_ACCESS_KEY | ctrl_clksel; + cdns_wdt_writereg(&priv->regs->ccr, data); + + data = CDNS_WDT_ZMR_WDEN_MASK | CDNS_WDT_ZMR_RSTLEN_16 | + CDNS_WDT_ZMR_ZKEY_VAL; + + /* Reset on timeout if specified in device tree. */ + if (priv->rst) { + data |= CDNS_WDT_ZMR_RSTEN_MASK; + data &= ~CDNS_WDT_ZMR_IRQEN_MASK; + } else { + data &= ~CDNS_WDT_ZMR_RSTEN_MASK; + data |= CDNS_WDT_ZMR_IRQEN_MASK; + } + + cdns_wdt_writereg(&priv->regs->zmr, data); + cdns_wdt_writereg(&priv->regs->restart, CDNS_WDT_RESTART_KEY); + + return 0; +} + +/** + * cdns_wdt_stop - Stop the watchdog. + * + * @dev: Watchdog device + * + * Read the contents of the ZMR register, clear the WDEN bit in the register + * and set the access key for successful write. + * + * Return: Always 0 + */ +static int cdns_wdt_stop(struct udevice *dev) +{ + struct cdns_wdt_priv *priv = dev_get_priv(dev); + + cdns_wdt_writereg(&priv->regs->zmr, + CDNS_WDT_ZMR_ZKEY_VAL & (~CDNS_WDT_ZMR_WDEN_MASK)); + + return 0; +} + +/** + * cdns_wdt_probe - Probe call for the device. + * + * @dev: Handle to the udevice structure. + * + * Return: Always 0. + */ +static int cdns_wdt_probe(struct udevice *dev) +{ + struct cdns_wdt_priv *priv = dev_get_priv(dev); + + debug("%s: Probing wdt%u\n", __func__, dev->seq); + + priv->reg = ioremap((u32)priv->regs, sizeof(struct cdns_regs)); + + cdns_wdt_stop(dev); + + return 0; +} + +static int cdns_wdt_ofdata_to_platdata(struct udevice *dev) +{ + int node = dev_of_offset(dev); + struct cdns_wdt_priv *priv = dev_get_priv(dev); + + priv->regs = devfdt_get_addr_ptr(dev); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); + + priv->timeout = fdtdec_get_int(gd->fdt_blob, node, "timeout-sec", + CDNS_WDT_DEFAULT_TIMEOUT); + + priv->rst = fdtdec_get_bool(gd->fdt_blob, node, "reset-on-timeout"); + + debug("%s: timeout %d, reset %d\n", __func__, priv->timeout, priv->rst); + + return 0; +} + +static const struct wdt_ops cdns_wdt_ops = { + .start = cdns_wdt_start, + .reset = cdns_wdt_reset, + .stop = cdns_wdt_stop, +}; + +static const struct udevice_id cdns_wdt_ids[] = { + { .compatible = "cdns,wdt-r1p2" }, + {} +}; + +U_BOOT_DRIVER(cdns_wdt) = { + .name = "cdns_wdt", + .id = UCLASS_WDT, + .of_match = cdns_wdt_ids, + .probe = cdns_wdt_probe, + .priv_auto_alloc_size = sizeof(struct cdns_wdt_priv), + .ofdata_to_platdata = cdns_wdt_ofdata_to_platdata, + .ops = &cdns_wdt_ops, +}; -- 1.9.1

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Re: [U-Boot] [PATCH v10 00/27] dm: Generic MTD Subsystem, with SPI-NOR interface
by Prabhakar Kushwaha 28 Feb '18

28 Feb '18

Dear Jagan, > -----Original Message----- > From: U-Boot [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Jagan > Teki > Sent: Thursday, December 28, 2017 11:42 AM > To: u-boot(a)lists.denx.de > Cc: Tom Rini <trini(a)konsulko.com> > Subject: [U-Boot] [PATCH v10 00/27] dm: Generic MTD Subsystem, with SPI- > NOR interface > > Compared to previous series’s [1], [2], [3] and [4] this patch set redefined > most of the implementation suitable to fit into existing driver-model. > > MTD is generic subsystem for underlying flash devices like nand, parallel nor, > spinor, dataflash etc. So to drive this theory with driver model(with an > example of block layer) mtd is common device interaction for most of > memory technology flashes like nand, parallel nor, spinor, dataflash etc, > these are treated as interface types wrt u-boot driver model. > > Once the respective interface driver bind happen, the uclass driver will pass > an 'interface type' to mtd layer to create device for it, for example once > spinor ULASS_SPI_NOR driver bind happen, the uclass driver of spinor will > pass MTD_IF_TYPE_SPI_NOR interface type to create mtd device for spinor > devices. > > SPI-NOR: > ======= > Some of the SPI device drivers at drivers/spi not a real spi controllers, Unlike > normal/generic SPI controllers they operates only with SPI-NOR flash > devices. these were technically termed as SPI-NOR controllers, Ex: > drivers/spi/fsl_qspi.c > > The problem with these were resides at drivers/spi is entire SPI layer > becomes SPI-NOR flash oriented which is absolutely a wrong indication > where SPI layer getting effected more with flash operations - So this SPI-NOR > core will resolve this issue by separating all SPI-NOR flash operations from spi > layer and creats a generic layer called SPI-NOR core which can be used to > interact SPI-NOR to SPI driver interface layer and the SPI-NOR controller > driver. > > ======================================= > cmd/spinor.c > ======================================= > mtd-uclass.c > ======================================= > spi-nor-uclass.c > ======================================= > spi-nor.c > ======================================= > m25p80.c zynq_qspinor.c > ======================================= > spi-uclass.c > ======================================= > zynq_qspi.c > ======================================= > #####SPI NOR chip###### > ======================================= > As per this patch-set, fsl_qspi is looks to be getting proposed in driver/mtd/spi-nor/ folder. fsl_qspi is supporting both flash and fpga. We are not sure about its location. There is an on-going effort for similar type of requirement in Linux by Boris Brezillon . It is dealing with controllers supporting NORs, NANDs, SRAMs etc. http://patchwork.ozlabs.org/project/linux-mtd/list/?series=27088 Borris has also ported fsl_qspi in driver/spi to use this new framework. It is still not completely tested. https://github.com/bbrezillon/linux/commit/43cc45764b975bfbb191de3f6a37e073… Will you also follow similar approach as being done in http://patchwork.ozlabs.org/project/linux-mtd/list/?series=27088 for longer term? For Now, We are planning to update fsl_qspi driver to support dynamic LUT. Similar patch is in progress in Linux http://patchwork.ozlabs.org/project/linux-mtd/list/?series=26084 Now we are confused, should be port fsl_qspi in driver/mtd/spi-nor and then update driver Or We update driver/spi/fsl_qspi for dynamic LUTs. We may need to modify existing framework to get all required info for dynamic LUT. Also we want some change in framework like support of - 4 byte address and SFDP : http://patchwork.ozlabs.org/project/uboot/list/?series=19621&state=* - SMPT : in discussion in Linux http://patchwork.ozlabs.org/patch/869718/ Which code base should we use? u-boot-spi.git branch mtd-spinor-working or u-boot.git master branch --pk

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[U-Boot] [PATCH v9 0/4] Generic firmware loader
by tien.fong.chee＠intel.com 28 Feb '18

28 Feb '18

From: Tien Fong Chee <tien.fong.chee(a)intel.com> This patchset contains generic firmware loader which is very close to Linux firmware loader but for U-Boot framework. Generic firmware loader can be used load whatever into target location, and then consumer driver would use it to program whatever, ie. the FPGA. This version mainly resolved comments from Marek Vasut in [v8]. This series is working on top of u-boot.git - http://git.denx.de/u-boot.git . [v8]: https://www.mail-archive.com/u-boot@lists.denx.de/msg278735.html v8 -> v9 changes: ----------------- - Swap these two -- mount first and umount seconds. - Removed #ifdef CONFIG_SPL. - Adding depends on SPL to config GENERIC_FIRMWARE_LOADER at Kconfig. - Set mode=0 to usb_stor_scan. - Sata device number be pulled from devpart in default_locations table. - Removed debug for CONFIG_SPL. - Adding UBI to default_location table. Patchset history ---------------- [v1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg271905.html [v2]: https://www.mail-archive.com/u-boot@lists.denx.de/msg271979.html [v3]: https://www.mail-archive.com/u-boot@lists.denx.de/msg272039.html [v4]: https://www.mail-archive.com/u-boot@lists.denx.de/msg272432.html [v5]: https://www.mail-archive.com/u-boot@lists.denx.de/msg272771.html [v6]: https://www.mail-archive.com/u-boot@lists.denx.de/msg273961.html [v7]: https://www.mail-archive.com/u-boot@lists.denx.de/msg276775.html Tien Fong Chee (4): spl: Remove static declaration on spl_mmc_find_device function cmd: ubifs: Move ubifs_initialized checking into cmd_ubifs_umount() cmd: ubifs: Factor out some checking codes into cmd_ubifs_mount() common: Generic firmware loader for file system cmd/ubifs.c | 40 ++--- common/Kconfig | 10 ++ common/Makefile | 1 + common/fs_loader.c | 365 +++++++++++++++++++++++++++++++++++++++++++++ common/spl/spl_mmc.c | 2 +- doc/README.firmware_loader | 83 +++++++++++ include/fs_loader.h | 28 ++++ include/spl.h | 2 + include/ubi_uboot.h | 2 + 9 files changed, 515 insertions(+), 18 deletions(-) create mode 100644 common/fs_loader.c create mode 100644 doc/README.firmware_loader create mode 100644 include/fs_loader.h -- 2.2.0

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[U-Boot] Pull request: u-boot-net.git master
by Joe Hershberger 28 Feb '18

28 Feb '18

Hi Tom, The following changes since commit 4bafceff0e9e5a36908031e41c69a6b37e82da58: Merge git://git.denx.de/u-boot-mmc (2018-02-25 22:28:59 -0500) are available in the git repository at: git://git.denx.de/u-boot-net.git master for you to fetch changes up to a0fd381fc60460a23d85c71ea06af0daa2427b2c: net: phy: smsc: Add SMSC LAN8741 support (2018-02-26 15:51:37 -0600) ---------------------------------------------------------------- Arno Steffens (1): net: phy: smsc: Add SMSC LAN8741 support Bernhard Messerklinger (1): net: e1000: Fix e1000_igb semaphore handling Eugeniy Paltsev (1): NET: designware: fix clock enable Mario Six (7): net: tsec: Fix style violations net: tsec: Fix memory leak in error path net: tsec: Make live-tree compatible net: phy: marvell: Fix style violations net: phy: marvell 88e151x: Fix handling of bare RGMII interface type cmd: mdio: Fix style violations phy: Fix style violations cmd/mdio.c | 7 ++- drivers/net/designware.c | 2 +- drivers/net/e1000.c | 2 +- drivers/net/phy/marvell.c | 47 ++++++++++--------- drivers/net/phy/phy.c | 94 ++++++++++++++++++++++--------------- drivers/net/phy/smsc.c | 11 +++++ drivers/net/tsec.c | 116 +++++++++++++++++++++++----------------------- 7 files changed, 155 insertions(+), 124 deletions(-) Thanks! -Joe

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[U-Boot] [U-Boot PATCH 0/2] Adds support for secure boot on TCI6630K2L HS devices
by Madan Srinivas 28 Feb '18

28 Feb '18

This series adds support for the secure Lammar (K2L) SoC. It defines a new defconfig file for K2L HS, based on the GP K2L defconfig and updates the u-boot default env variables to install the secure boot-monitor on startup. Madan Srinivas (2): configs: k2l: Updates u-boot env to install secure boot monitor defconfig: k2l_hs_evm: Add k2l_hs_evm_defconfig configs/k2l_hs_evm_defconfig | 43 +++++++++++++++++++++++++++++++++++++++++++ include/configs/k2l_evm.h | 9 +++++++++ 2 files changed, 52 insertions(+) create mode 100644 configs/k2l_hs_evm_defconfig -- 1.9.1

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[U-Boot] [PATCH] board: am335x: Set serial# variable
by Sam Protsenko 27 Feb '18

27 Feb '18

serial# variable is needed to show device correctly in "fastboot devices" output. It's useful when we have several devices (in fastboot mode) connected to single host and want to choose which one to flash. Reuse board_serial variable (obtained from EEPROM in set_board_info_env() function) to set serial#. We can't use omap_die_id_serial(), because AM335x lacks DIE_ID, as can be seen from AM335x TRM. The other available option would be to reuse ethaddr variable, but using board_serial seems more reasonable for this purpose. Signed-off-by: Sam Protsenko <semen.protsenko(a)linaro.org> --- board/ti/am335x/board.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 1a52bffc00..4d421697bf 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -732,6 +732,10 @@ int board_late_init(void) */ if (get_device_type() == HS_DEVICE) env_set("boot_fit", "1"); + + /* Reuse serial number set by set_board_info_env() (from EEPROM) */ + if (!env_get("serial#")) + env_set("serial#", env_get("board_serial")); #endif #if !defined(CONFIG_SPL_BUILD) -- 2.16.1

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[U-Boot] [PATCH] armv8: sec_firmware: Remove JR3 from device tree node in all cases
by Ruchika Gupta 27 Feb '18

27 Feb '18

JR3 was getting removed from device tree only if random number generation was successful. However, if SEC firmware is present,JR3 should be removed from device tree node irrespective of the random seed generation as SEC firmware reserves it for it's use. Not removing it in case of random number generation failure causes the kernel to crash. Random number generation was being called twice. This is not required. If SEC firmware is running, SIP call can be made to the SEC firmware to get the random number. This call itself would return failure if function is not supported. Duplicate calling of random number generation function has been removed Signed-off-by: Ruchika Gupta <ruchika.gupta(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 4 ++-- arch/arm/cpu/armv8/sec_firmware.c | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 80af318..6a19f4d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -415,8 +415,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) ccsr_sec_t __iomem *sec; #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT - if (fdt_fixup_kaslr(blob)) - fdt_fixup_remove_jr(blob); + fdt_fixup_remove_jr(blob); + fdt_fixup_kaslr(blob); #endif sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index b56ea78..ebf41b5 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -320,7 +320,6 @@ bool sec_firmware_support_hwrng(void) { uint8_t rand[8]; if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) { - if (!sec_firmware_get_random(rand, 8)) return true; } @@ -429,8 +428,10 @@ int fdt_fixup_kaslr(void *fdt) #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) /* Check if random seed generation is supported */ - if (sec_firmware_support_hwrng() == false) + if (sec_firmware_support_hwrng() == false) { + printf("WARNING: SEC firmware not running, no kaslr-seed\n"); return 0; + } ret = sec_firmware_get_random(rand, 8); if (ret < 0) { -- 2.7.4

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[U-Boot] [PATCH v2] arm: socfpga: cyclone5: Enable Macronix flash support
by chin.liang.see＠intel.com 27 Feb '18

27 Feb '18

From: Chin Liang See <chin.liang.see(a)intel.com> Enable Macronix flash support for Cyclone5 SoC Signed-off-by: Chin Liang See <chin.liang.see(a)intel.com> --- Changes for v2 - Undo change for is1, sr1500 and vining --- configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 522b6d2..5202f47 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -45,6 +45,7 @@ CONFIG_DM_MMC=y CONFIG_MMC_DW=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 8448913..f421740 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -45,6 +45,7 @@ CONFIG_DM_MMC=y CONFIG_MMC_DW=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index f49ee96..3873c2b 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -46,6 +46,7 @@ CONFIG_DM_MMC=y CONFIG_MMC_DW=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_MICREL=y -- 2.2.2

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