December 2018 - U-Boot

[U-Boot] [PATCH] evb_rk3399: revert CONFIG_SYS_MMC_ENV_DEV to 0
by Max Kellermann 14 Dec '18

14 Dec '18

This was changed to 1 in commit 0717dde057e, but a few months later, commit 5f9411af37b swapped the order of eMMC and SD card by assigning indexed aliases to `&sdhci` and `&sdmmc`. --- include/configs/evb_rk3399.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h index a99eeab484..b9c4d683f4 100644 --- a/include/configs/evb_rk3399.h +++ b/include/configs/evb_rk3399.h @@ -8,7 +8,7 @@ #include <configs/rk3399_common.h> -#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 #define SDRAM_BANK_SIZE (2UL << 30) -- 2.19.2

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[U-Boot] [PATCH v2 0/2] SiFive UART support
by Anup Patel 14 Dec '18

14 Dec '18

This patchset adds SiFive UART driver for SiFive UART found on SiFive boards. The driver is tested on QEMU sifive_u machine. In fact, with this patchset same U-Boot binary boots on QEMU virt machine and QEMU sifive_u machine in both M-mode and S-mode. The patches are based upon latest RISC-V UBoot tree (git://git.denx.de/u-boot-riscv.git) at commit id 48cbf6246052de10d35b616b5efb2f783904a49d Changes since v1: - Fixed copyright header in SiFive UART driver - Imply SIFIVE_SERIAL for QEMU emulation instead of enabling it in defconfigs. Anup Patel (2): drivers: serial: Add SiFive UART driver riscv: qemu: Imply SIFIVE_SERIAL for emulation board/emulation/qemu-riscv/Kconfig | 1 + drivers/serial/Kconfig | 13 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_sifive.c | 191 +++++++++++++++++++++++++++++ 4 files changed, 206 insertions(+) create mode 100644 drivers/serial/serial_sifive.c -- 2.17.1

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Re: [U-Boot] [PATCH v5 00/25] riscv: Adding RISC-V CPU and timer driver
by Rick Chen 14 Dec '18

14 Dec '18

Hi Bin > > From: Bin Meng [mailto:bmeng.cn@gmail.com] > > Sent: Friday, December 14, 2018 9:22 AM > > To: Rick Jian-Zhi Chen(陳建志); Simon Glass; Lukas Auer; Anup Patel; U-Boot > > Mailing List > > Subject: Re: [PATCH v5 00/25] riscv: Adding RISC-V CPU and timer driver > > > > Hi Rick, > > > > On Wed, Dec 12, 2018 at 10:08 PM Bin Meng <bmeng.cn(a)gmail.com> wrote: > > > > > > This adds DM drivers to support RISC-V CPU and timer, plus some bug fixes. > > > > > > This series is available at u-boot-x86/riscv-working for testing. > > > > > > Changes in v5: > > > - Introduced another Kconfig option for the cache ops on AX25 CPU, > > > so that it remains selectable in Kconfig menu, but only visible > > > to AX25 platform. > > > - check if dev is valid, otherwise print a warning > > > > > > > If no other comments, would you please apply this series? I hope we can get this > > series in v2019.01. OK. I need to do some verification on it. After that I will send a PR ASAP. B.R Rick > > > > Regards, > > Bin

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[U-Boot] [PATCH 0/9] Add support for loading FPGA bitstream
by tien.fong.chee＠intel.com 14 Dec '18

14 Dec '18

From: Tien Fong Chee <tien.fong.chee(a)intel.com> These series of patches enable peripheral bitstream being programmed into FPGA to get the DDR up running. This's also called early IO release, because the peripheral bitstream is only initializing FPGA IOs, PLL, IO48 and DDR. Once DDR is up running, core bitstream from FIT image which contains user FPGA design would be loaded into DDR location, where it's defined as 0x1000 by default in fit_spl_fpga.its. fpga load would be called to program core bitstream into FPGA and entering user mode. Lastly, U-Boot from FIT image would be loaded to DDR, and up running from there. For the whole mechanism to work, the SDMMC flash layout would be designed as shown in below: RAW partition: 1. spl_w_dtb-mkpimage.bin mkpimage -hv 1 -o spl/spl_w_dtb-mkpimage.bin spl/u-boot-spl-dtb.bin spl/u-boot-spl-dtb.bin spl/u-boot-spl-dtb.bin spl/u-boot-spl-dtb.bin FAT partition: 1. u-boot.itb(default build) - uboot - fdt - fpga 2. ghrd_10as066n2.periph.rbf.mkimage mkimage -A arm -T firmware -C none -O u-boot -a 0 -e 0 -n \"RBF\" -d ghrd_10as066n2.periph.rbf ghrd_10as066n2.periph.rbf.mkimage This series is working on top of u-boot.git - http://git.denx.de/u-boot.git . Tien Fong Chee (9): ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading spl : socfpga: Implement fpga bitstream loading with socfpga loadfs ARM: socfpga: Bundle U-Boot fitImage into SFP on Arria10 ARM: socfpga: Add SPL fitImage config match ARM: socfpga: Set default DTB address on A10 ARM: socfpga: Use custom header target buffer in SPL ARM: socfpga: Add default fitImage for Arria10 SoCDK ARM: socfpga: Synchronize the configuration for A10 SoCDK Makefile | 9 +- arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 18 + arch/arm/mach-socfpga/board.c | 8 + .../include/mach/fpga_manager_arria10.h | 30 ++- arch/arm/mach-socfpga/spl_a10.c | 70 ++++- board/altera/arria10-socdk/fit_spl_fpga.its | 54 +++ common/spl/spl_mmc.c | 2 +- configs/socfpga_arria10_defconfig | 51 +++- .../fpga/altera-socfpga-a10-fpga-mgr.txt | 6 + drivers/fpga/Kconfig | 9 + drivers/fpga/socfpga_arria10.c | 417 +++++++++++++++++++- include/configs/socfpga_common.h | 4 + include/mmc.h | 1 + 13 files changed, 657 insertions(+), 22 deletions(-) create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its -- 1.7.7.4

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Re: [U-Boot] [PATCH] zynq-gem: Flush cache before handing RX packet to receive handler
by Bin Meng 14 Dec '18

14 Dec '18

On Thu, Dec 13, 2018 at 10:02 PM Stefan Theil <Stefan.Theil(a)mixed-mode.de> wrote: > > > > > -----Ursprüngliche Nachricht----- > > Von: Bin Meng [mailto:bmeng.cn@gmail.com] > > Gesendet: Donnerstag, 13. Dezember 2018 14:59 > > An: Stefan Theil > > Cc: Michal Simek; U-Boot Mailing List > > Betreff: Re: [U-Boot] [PATCH] zynq-gem: Flush cache before handing RX > > packet to receive handler > > > > Hi Stefan, > > > > On Thu, Dec 13, 2018 at 9:51 PM Stefan Theil <Stefan.Theil@mixed- > > mode.de> wrote: > > > > > > > -----Ursprüngliche Nachricht----- > > > > Von: Michal Simek [mailto:monstr@monstr.eu] > > > > Gesendet: Donnerstag, 13. Dezember 2018 14:48 > > > > An: Stefan Theil; Bin Meng > > > > Cc: U-Boot Mailing List > > > > Betreff: Re: [U-Boot] [PATCH] zynq-gem: Flush cache before handing > > > > RX packet to receive handler > > > > > > > > On 13. 12. 18 14:41, Stefan Theil wrote: > > > > > > > > > > > > > > >> -----Ursprüngliche Nachricht----- > > > > >> Von: Bin Meng [mailto:bmeng.cn@gmail.com] > > > > >> Gesendet: Donnerstag, 13. Dezember 2018 14:37 > > > > >> An: Stefan Theil > > > > >> Cc: U-Boot Mailing List > > > > >> Betreff: Re: Re: [U-Boot] [PATCH] zynq-gem: Flush cache before > > > > >> handing RX packet to receive handler > > > > >> > > > > >> Hi Stefan, > > > > >> > > > > >> On Thu, Dec 13, 2018 at 9:26 PM Stefan Theil <Stefan.Theil@mixed- > > > > >> mode.de> wrote: > > > > >>> > > > > >>> Hmm good question. I went with flush because that's what's done > > > > >>> in the > > > > >> transmit function: > > > > >>> > > > > >>> addr = (ulong) ptr; > > > > >>> addr &= ~(ARCH_DMA_MINALIGN - 1); size = roundup(len, > > > > >>> ARCH_DMA_MINALIGN); flush_dcache_range(addr, > > > > >> addr > > > > >>> + size); > > > > >>> > > > > >>> addr = (ulong)priv->rxbuffers; > > > > >>> addr &= ~(ARCH_DMA_MINALIGN - 1); size = roundup((RX_BUF * > > > > >>> PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); > > flush_dcache_range(addr, > > > > >>> addr + size); barrier(); > > > > >>> > > > > >>> But since we actually want the uncached data invalidation seems > > > > >>> logical. I > > > > >> have to admit though, I don't have much experience with caches. > > > > >> This patch completely fixed my problem... Maybe somebody with a > > > > >> bit more expertise can add their opinion? > > > > >> > > > > >> It should be 'invalidate' primitive when it comes to the RX path. > > > > >> For TX path, it should be 'flush'. > > > > >> > > > > >> Regards, > > > > >> Bin > > > > > > > > > > Then why are all receive buffers flushed before sending a packet? > > > > > In any > > > > case, I'll try it with invalidate and submit an updated version. > > > > > > > > When you creating packet, cpu is used and caches are filled with > > > > data which you are asking by DMA to send. That's why you need to > > > > flush them to DDR for dma to take it. If you don't do that DMA can work > > with incorrect data. > > > > > > I know, but you don't create *receive* packets when you're sending a > > packet, are you? Why would you need to flush those before sending a > > packet? That's what I'm wondering about. > > > > > > > Why did you mention *receive* packets and sending a packet? The receive > > packets and send packets are two different buffers. > > Take a look at "zynq_gem_send" in "drivers/net/zynq_gem.c" then, where it says: > I just took a look at the driver, and (see below) > addr = (ulong)priv->rxbuffers; > addr &= ~(ARCH_DMA_MINALIGN - 1); > size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); > flush_dcache_range(addr, addr + size); > barrier(); > > I'm fairly certain that "priv->rxbuffers" has nothing to do with sending a packet. > I strongly suspect the above codes are some leftovers of copy & paste. Could you please remove these codes and have a test? > > > > > > On RX path if cpu touches that memory space before DMA receive data > > > > to the memory, cpu can work with incorrect data. > > > > That's why you need to invalidate that range to ensure that data > > > > which you will read is that one got from DMA. > > > > > > > > It is kind of interesting that we didn't observe this issue. > > > > > > Probably because most people don't receive enough packets between > > sending packets, so the receive buffers are flushed often enough. Regards, Bin

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[U-Boot] [PATCH v5 00/25] riscv: Adding RISC-V CPU and timer driver
by Bin Meng 14 Dec '18

14 Dec '18

This adds DM drivers to support RISC-V CPU and timer, plus some bug fixes. This series is available at u-boot-x86/riscv-working for testing. Changes in v5: - Introduced another Kconfig option for the cache ops on AX25 CPU, so that it remains selectable in Kconfig menu, but only visible to AX25 platform. - check if dev is valid, otherwise print a warning Changes in v4: - print warnings for S-mode without CONFIG_CPU Changes in v3: - remove 'select RISCV_CLINT' in Kconfig - do not mention the spec version number v1.10 - adjust riscv_get_time() API signature to have a return value - check return value of syscon_get_first_range() - probe cpus in the pre-relocation stage too - new patch to remove non-DM version of print_cpuinfo() - add sedeleg (0x102) and sideleg (0x103) CSRs - new patch to update supports_extension() to use desc from cpu driver - only initialize mcounteren CSR for S-mode - only touch satp in M-mode U-Boot - move the implementation to arch_cpu_init_dm() - new patch to save boot hart id to the global data - new patch to change to use boot_hart from global data - new patch to remove ae350.dts Changes in v2: - Use 'Hz' instead of 'HZ' - add DM_FLAG_PRE_RELOC flag to the simple-bus driver - pass NULL as the timer device to device_bind_with_driver_data() - remove the probe to syscon driver in the timer probe, to make the driver generic, and rely on platform codes to provide the API riscv_get_time(). - incorporated and reworked Anup's S-mode timer patch @ http://patchwork.ozlabs.org/patch/1006663/ - rename the driver name to sifive_clint - save the clint base address to arch specific global data to support pre-relocation stage - remove the probe routine - add riscv_clear_ipi() API - incorporated and reworked Anup's S-mode timer patch @ http://patchwork.ozlabs.org/patch/1006663/ - add CMD_CPU as well - move to arch/riscv/cpu/cpu.c - new patch to add indirect stringification to csr_xxx ops - use csr_set() to set MSTATUS_FS - only enabling the cycle, time, and instret counters - change to use satp - rebase on u-boot/master - drop the patch "riscv: Pass correct exception code to _exit_trap()" - drop the patch "riscv: Refactor handle_trap() a little for future extension" - drop the patch "riscv: Allow U-Boot to run on hart 0 only", and leave the SMP support to Lukas's future patch series Anup Patel (2): riscv: Introduce a Kconfig option for machine mode riscv: Implement riscv_get_time() API using rdtime instruction Bin Meng (22): dm: cpu: Add timebase frequency to the platdata riscv: qemu: Create a simple-bus driver for the soc node cpu: Add a RISC-V CPU driver timer: Add generic driver for RISC-V privileged architecture defined timer riscv: ax25: Hide the ax25-specific Kconfig option riscv: Add a SYSCON driver for SiFive's Core Local Interruptor riscv: qemu: Add platform-specific Kconfig options riscv: Enlarge the default SYS_MALLOC_F_LEN riscv: Probe cpus during boot riscv: Remove non-DM version of print_cpuinfo() riscv: Add CSR numbers riscv: Add exception codes for xcause register riscv: Update supports_extension() to use desc from cpu driver riscv: Add indirect stringification to csr_xxx ops riscv: Do some basic architecture level cpu initialization riscv: Move trap handler codes to mtrap.S riscv: Fix context restore before returning from trap handler riscv: Return to previous privilege level after trap handling riscv: Adjust the _exit_trap() position to come before handle_trap() riscv: Save boot hart id to the global data riscv: bootm: Change to use boot_hart from global data riscv: Remove ae350.dts Lukas Auer (1): riscv: add Kconfig entries for the code model arch/riscv/Kconfig | 60 ++++++++- arch/riscv/Makefile | 9 +- arch/riscv/cpu/Makefile | 2 +- arch/riscv/cpu/ax25/Kconfig | 17 ++- arch/riscv/cpu/ax25/cache.c | 12 +- arch/riscv/cpu/cpu.c | 98 ++++++++++----- arch/riscv/cpu/mtrap.S | 103 +++++++++++++++ arch/riscv/cpu/qemu/Kconfig | 12 ++ arch/riscv/cpu/qemu/cpu.c | 14 +++ arch/riscv/cpu/start.S | 93 +------------- arch/riscv/dts/ae350.dts | 229 --------------------------------- arch/riscv/include/asm/csr.h | 16 +-- arch/riscv/include/asm/encoding.h | 236 +++++++++++++++++++++++++++++++++++ arch/riscv/include/asm/global_data.h | 4 + arch/riscv/include/asm/syscon.h | 19 +++ arch/riscv/lib/Makefile | 2 + arch/riscv/lib/asm-offsets.c | 19 +++ arch/riscv/lib/bootm.c | 2 +- arch/riscv/lib/interrupts.c | 62 +++++---- arch/riscv/lib/rdtime.c | 38 ++++++ arch/riscv/lib/sifive_clint.c | 84 +++++++++++++ board/AndesTech/ax25-ae350/Kconfig | 4 + board/emulation/qemu-riscv/Kconfig | 1 + drivers/cpu/Kconfig | 6 + drivers/cpu/Makefile | 1 + drivers/cpu/riscv_cpu.c | 116 +++++++++++++++++ drivers/timer/Kconfig | 7 ++ drivers/timer/Makefile | 1 + drivers/timer/riscv_timer.c | 56 +++++++++ include/cpu.h | 3 + 30 files changed, 921 insertions(+), 405 deletions(-) create mode 100644 arch/riscv/cpu/mtrap.S create mode 100644 arch/riscv/cpu/qemu/Kconfig delete mode 100644 arch/riscv/dts/ae350.dts create mode 100644 arch/riscv/include/asm/syscon.h create mode 100644 arch/riscv/lib/asm-offsets.c create mode 100644 arch/riscv/lib/rdtime.c create mode 100644 arch/riscv/lib/sifive_clint.c create mode 100644 drivers/cpu/riscv_cpu.c create mode 100644 drivers/timer/riscv_timer.c -- 2.7.4

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[U-Boot] sunxi: regression in dram init for h3 board
by Karl Palsson 13 Dec '18

13 Dec '18

Hi, The commit: a8011eb84dfac5187cebf00ed8bc981bdb5c1fa1 Author: Olliver Schinagl <oliver(a)schinagl.nl> Date: Wed Nov 21 20:05:25 2018 +0200 sunxi: board: Print error after power initialization fails causes a regression in DRAM init/detection on (at least) the sunxi H3 nanopi board I have. (The exact board isn't actually upstream yet, but it's compatible with the nanopi-neo or neo-air) >>> Good behaviour: U-Boot SPL 2019.01-rc1-00293-g0c5b0ff71a (Dec 13 2018 - 16:46:41 +0000) DRAM: 512 MiB Trying to boot from FEL <snipped normal FEL boot output> >>> Bad behaviour: U-Boot spl 2019.01-rc1-00101-ga8011eb84d (Dec 13 2018 - 16:44:48 +0000) DRAM: 0 MiB ### ERROR ### Please RESET the board ### Confirmed the bisection by reverting this patch on current master. I'm not expert in this area to know enough about the cause. The description of the commit sounds perfectly reasonable :) Cheers, Karl P

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[U-Boot] [PATCH] Add support for initializing MMC
by tien.fong.chee＠intel.com 13 Dec '18

13 Dec '18

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Firmware loader would encounter problem if the MMC is accessed before initializing it. This patch would adding the support of initializing MMC before the MMC is accessed by firmware loader. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> --- drivers/misc/fs_loader.c | 33 ++++++++++++++++++++++++++++++++- 1 files changed, 32 insertions(+), 1 deletions(-) diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c index 57a14a3..675f625 100644 --- a/drivers/misc/fs_loader.c +++ b/drivers/misc/fs_loader.c @@ -12,6 +12,7 @@ #include <linux/string.h> #include <mapmem.h> #include <malloc.h> +#include <mmc.h> #include <spl.h> DECLARE_GLOBAL_DATA_PTR; @@ -221,6 +222,7 @@ static int fs_loader_ofdata_to_platdata(struct udevice *dev) { const char *fs_loader_path; u32 phandlepart[2]; + struct device_platdata *plat = NULL; fs_loader_path = ofnode_get_chosen_prop("firmware-loader"); @@ -229,7 +231,6 @@ static int fs_loader_ofdata_to_platdata(struct udevice *dev) fs_loader_node = ofnode_path(fs_loader_path); if (ofnode_valid(fs_loader_node)) { - struct device_platdata *plat; plat = dev->platdata; if (!ofnode_read_u32_array(fs_loader_node, @@ -247,6 +248,36 @@ static int fs_loader_ofdata_to_platdata(struct udevice *dev) } } +#ifdef CONFIG_MMC + int ret; + + ret = mmc_initialize(NULL); + if (ret) { + debug("MMC: could not initialize mmc. error: %d\n", ret); + + return ret; + } + + if (plat->phandlepart.phandle) { + ofnode node = ofnode_get_by_phandle(plat->phandlepart.phandle); + + struct udevice *mmc_dev = NULL; + + ret = device_get_global_by_ofnode(node, &mmc_dev); + if (!ret) { + struct mmc *mmc = mmc_get_mmc_dev(mmc_dev); + + ret = mmc_init(mmc); + if (ret) { + debug("MMC: mmc init failed with error: %d\n", + ret); + + return ret; + } + } + } +#endif + return 0; } -- 1.7.7.4

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[U-Boot] [PATCH v2 0/2] Read default speed and mode values from DT
by Patrick Delaunay 13 Dec '18

13 Dec '18

This serie generalize the commit 96907c0fe50a ("dm: spi: Read default speed and mode values from DT") In case of DT boot, don't read default speed and mode for SPI from CONFIG_*, instead read from DT node. This will make sure that boards with multiple SPI/QSPI controllers can be probed at different bus frequencies and SPI modes. Today it is only done in the command sf; this patch do the same for the other user of the spi_flash_probe(): spl and splash to avoid probe issue. Changes in v2: - use variables to avoid duplicated code - use variables to avoid duplicated code Patrick Delaunay (2): spl_spi: Read default speed and mode values from DT splash: sf: Read default speed and mode values from DT common/spl/spl_spi.c | 10 ++++++++-- common/splash_source.c | 12 ++++++++++-- 2 files changed, 18 insertions(+), 4 deletions(-) -- 2.7.4

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[U-Boot] [PATCH v3] zynq-gem: Use appropriate cache flush/invalidate for RX and TX
by Stefan Theil 13 Dec '18

13 Dec '18

The cache was only flushed before *transmitting* packets, but not when receiving them, leading to an issue where new packets were handed to the receive handler with old contents in cache. This only happens when a lot of packets are received without sending packages every now and then. Also flushing the receive buffers in the transmit function makes no sense and can be removed. Signed-off-by: Stefan Theil <stefan.theil(a)mixed-mode.de> --- Changes for v2: - Use invalidate_dcache_range instead of flush_dcache_range Changes for v3: - Remove unnecessary flushing of all RX buffers in zynq_gem_send --- drivers/net/zynq_gem.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 9bd79b198a..4f7d945562 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -570,11 +570,6 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len) addr &= ~(ARCH_DMA_MINALIGN - 1); size = roundup(len, ARCH_DMA_MINALIGN); flush_dcache_range(addr, addr + size); - - addr = (ulong)priv->rxbuffers; - addr &= ~(ARCH_DMA_MINALIGN - 1); - size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); - flush_dcache_range(addr, addr + size); barrier(); /* Start transmit */ @@ -621,6 +616,9 @@ static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) *packetp = (uchar *)(uintptr_t)addr; + invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); + barrier(); + return frame_len; } -- 2.17.1

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