December 2018 - U-Boot

[U-Boot] [PATCH u-boot] arm: dts: s400: Fix status for eMMC and SDIO ports
by Neil Armstrong 19 Dec '18

19 Dec '18

Under U-boot, the WiFi SDIO Module should be disabled and the eMMC modules should be enabled, so this patch adds an s400-u-boot.dtsi include file specific for U-Boot that will be included by the build system. Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> --- arch/arm/dts/meson-axg-s400-u-boot.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 arch/arm/dts/meson-axg-s400-u-boot.dtsi diff --git a/arch/arm/dts/meson-axg-s400-u-boot.dtsi b/arch/arm/dts/meson-axg-s400-u-boot.dtsi new file mode 100644 index 0000000000..c46eb3f38d --- /dev/null +++ b/arch/arm/dts/meson-axg-s400-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Amlogic, Inc. All rights reserved. + */ + +/* wifi module */ +&sd_emmc_b { + status = "disabled"; +}; + +/* emmc storage */ +&sd_emmc_c { + status = "okay"; +}; -- 2.19.2

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[U-Boot] [PATCH] MIPS: remove local_irq_[save|restore] from CP0 macros
by Daniel Schwierzeck 19 Dec '18

19 Dec '18

With moving write_on_tlb() to arch/mips/include/asm/mipsregs.h there are now compiler warnings when some generic code includes asm/io.h. This happens for example when enabling OF live tree. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> --- arch/mips/include/asm/mipsregs.h | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 930562ebb2..f80311e64e 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1013,9 +1013,7 @@ do { \ #define __read_64bit_c0_split(source, sel) \ ({ \ unsigned long long __val; \ - unsigned long __flags; \ \ - local_irq_save(__flags); \ if (sel == 0) \ __asm__ __volatile__( \ ".set\tmips64\n\t" \ @@ -1034,16 +1032,12 @@ do { \ "dsra\t%L0, %L0, 32\n\t" \ ".set\tmips0" \ : "=r" (__val)); \ - local_irq_restore(__flags); \ \ __val; \ }) #define __write_64bit_c0_split(source, sel, val) \ do { \ - unsigned long __flags; \ - \ - local_irq_save(__flags); \ if (sel == 0) \ __asm__ __volatile__( \ ".set\tmips64\n\t" \ @@ -1064,7 +1058,6 @@ do { \ "dmtc0\t%L0, " #source ", " #sel "\n\t" \ ".set\tmips0" \ : : "r" (val)); \ - local_irq_restore(__flags); \ } while (0) #define __readx_32bit_c0_register(source) \ -- 2.20.1

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[U-Boot] getting usb working
by Frank Wunderlich 19 Dec '18

19 Dec '18

Hi, i'm trying to get USB working in uboot. first thing i've noticed: usb3 and usb2 cannot be used together (multiple definition of "submit_control_msg" and other functions). next i try to enable usb-command (which seems to be needed), then i get this: common/usb_storage.c: In function ‘usb_stor_probe_device’: common/usb_storage.c:206:32: error: ‘struct usb_device’ has no member named ‘dev’; did you mean ‘devnum’? data = dev_get_platdata(udev->dev); ^~~ devnum common/usb_storage.c:216:34: error: ‘struct usb_device’ has no member named ‘dev’; did you mean ‘devnum’? ret = blk_create_devicef(udev->dev, "usb_storage_blk", str, ^~~ devnum is there a vendor-specific driver (bpi-r2) missing or do i make anything wrong? how about sata...is there anything needed from vendor? regards Frank

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[U-Boot] [PATCH 00/10] i.MX8QXP: MEK: support SPL
by Peng Fan 19 Dec '18

19 Dec '18

This is to support SPL for i.MX8QXP MEK board and default support SPL. In this patchset, use SPL FIT, but actually we could not use SPL FIT for secure boot, in NXP vendor tree, there is another format called container, NXP use SPL + container for secure boot. The container support is on my TODO list. But to make SPL work in upstream, use SPL FIT here. Peng Fan (10): imx8qxp: add SUPPORT_SPL option imx8: scu: use dedicated MU for SPL arm: imx: build mach-imx for i.MX8 gpio: introduce CONFIG_SPL_DM_PCA953X spl: imx8: add spl boot device dts: imx8qxp-mek: introduce u-boot dtsi imx: mkimage_fit_atf: introduce BL33_BASE_ADDR imx: build flash.bin for i.MX8 imx8qxp: mek: default enable SPL imx8qxp: mek: update README Makefile | 2 +- arch/arm/Makefile | 2 +- arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 112 +++++++++++++++++++++++++++++++ arch/arm/dts/fsl-imx8qxp-mek.dts | 1 + arch/arm/mach-imx/Makefile | 15 ++++- arch/arm/mach-imx/imx8/Kconfig | 8 +++ arch/arm/mach-imx/mkimage_fit_atf.sh | 3 +- arch/arm/mach-imx/spl.c | 14 +++- board/freescale/imx8qxp_mek/Makefile | 1 + board/freescale/imx8qxp_mek/README | 8 ++- board/freescale/imx8qxp_mek/imximage.cfg | 4 +- board/freescale/imx8qxp_mek/spl.c | 75 +++++++++++++++++++++ configs/imx8qxp_mek_defconfig | 24 +++++++ drivers/gpio/Kconfig | 23 +++++++ drivers/gpio/Makefile | 2 +- drivers/misc/imx8/scu.c | 4 ++ include/configs/imx8qxp_mek.h | 26 +++++++ 17 files changed, 311 insertions(+), 13 deletions(-) create mode 100644 arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi create mode 100644 board/freescale/imx8qxp_mek/spl.c -- 2.14.1

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[U-Boot] [PATCH v2 0/2] Read SFDP parameters and access flash above 16MB
by Rajat Srivastava 19 Dec '18

19 Dec '18

Add functionality to read and parse SFDP parameters to auto-detect flash size, page size and address width of flash. This enables flash access above 16MB using 4-byte addressing mode. Add driver support to get SFDP information of flash and use it to access flash above 16MB. --- Changes in v2: - Make SFDP parsing the default way to read flash parameters. - Change SPI_FLASH_USE_SFDP flag to SPI_FLASH_SKIP_SFDP to provide an option to skip SFDP parsing for a particular flash. - Convert patch-set of 3 patches to 2 patches. --- Rajat Srivastava (2): mtd/spi: Add JEDEC SFDP support in SPI framework fsl_qspi: Access flash above 16MB using SFDP drivers/mtd/spi/sf_internal.h | 4 + drivers/mtd/spi/spi_flash.c | 301 +++++++++++++++++++++++++++++++++++++++--- drivers/spi/fsl_qspi.c | 103 ++++++++++++++- include/spi.h | 2 + include/spi_flash.h | 120 +++++++++++++++++ 5 files changed, 502 insertions(+), 28 deletions(-) -- 2.14.1

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[U-Boot] [PATCH] i2c: xiic: Add Xilinx AXI I2C driver
by Marek Vasut 19 Dec '18

19 Dec '18

Add Xilinx AXI I2C controller driver based on the Linux i2c-xiic driver. This driver is stripped of all the IRQ handling and uses pure polling, yet tries to retain most of the structure of the Linux driver to make backporting of fixes easy. Note that the IP has a known limitation on 255 bytes read and write, according to xilinx this is still being worked on [1]. [1] https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI-IIC-V2-0-… Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Michal Simek <monstr(a)monstr.eu> Cc: Michal Simek <michal.simek(a)xilinx.com> Cc: Heiko Schocher <hs(a)denx.de> --- drivers/i2c/Kconfig | 6 + drivers/i2c/Makefile | 1 + drivers/i2c/xilinx_xiic.c | 340 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 347 insertions(+) create mode 100644 drivers/i2c/xilinx_xiic.c diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 5eceab9ea8..810d861f32 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -437,6 +437,12 @@ config SYS_I2C_BUS_MAX help Define the maximum number of available I2C buses. +config SYS_I2C_XILINX_XIIC + bool "Xilinx AXI I2C driver" + depends on DM_I2C + help + Support for Xilinx AXI I2C controller. + config SYS_I2C_ZYNQ bool "Xilinx I2C driver" depends on ARCH_ZYNQMP || ARCH_ZYNQ diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index da368cc02a..94c68c8ba1 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o +obj-$(CONFIG_SYS_I2C_XILINX_XIIC) += xilinx_xiic.o obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o obj-$(CONFIG_I2C_MUX) += muxes/ diff --git a/drivers/i2c/xilinx_xiic.c b/drivers/i2c/xilinx_xiic.c new file mode 100644 index 0000000000..180cd14fec --- /dev/null +++ b/drivers/i2c/xilinx_xiic.c @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx AXI I2C driver + * + * Copyright (C) 2018 Marek Vasut <marex(a)denx.de> + * + * Based on Linux 4.14.y i2c-xiic.c + * Copyright (c) 2002-2007 Xilinx Inc. + * Copyright (c) 2009-2010 Intel Corporation + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <i2c.h> +#include <wait_bit.h> +#include <asm/io.h> + +struct xilinx_xiic_priv { + void __iomem *base; + struct clk clk; +}; + +#define XIIC_MSB_OFFSET 0 +#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET) + +/* + * Register offsets in bytes from RegisterBase. Three is added to the + * base offset to access LSB (IBM style) of the word + */ +#define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ +#define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */ +#define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ +#define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ +#define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */ +#define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ +#define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ +#define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ +#define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ +#define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */ + +/* Control Register masks */ +#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ +#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ +#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ +#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ +#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ +#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ +#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ + +/* Status Register masks */ +#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ +#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ +#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ +#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ +#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ +#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ +#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ +#define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ + +/* Interrupt Status Register masks Interrupt occurs when... */ +#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ +#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ +#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ +#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ +#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ +#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ +#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ +#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ + +/* The following constants specify the depth of the FIFOs */ +#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ +#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ + +/* + * Tx Fifo upper bit masks. + */ +#define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ +#define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ + +/* + * The following constants define the register offsets for the Interrupt + * registers. There are some holes in the memory map for reserved addresses + * to allow other registers to be added and still match the memory map of the + * interrupt controller registers + */ +#define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ +#define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ +#define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ +#define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ + +#define XIIC_RESET_MASK 0xAUL + +static u8 i2c_8bit_addr_from_flags(uint addr, u16 flags) +{ + return (addr << 1) | (flags & I2C_M_RD ? 1 : 0); +} + +static void xiic_irq_clr(struct xilinx_xiic_priv *priv, u32 mask) +{ + u32 isr = readl(priv->base + XIIC_IISR_OFFSET); + + writel(isr & mask, priv->base + XIIC_IISR_OFFSET); +} + +static int xiic_read_rx(struct xilinx_xiic_priv *priv, + struct i2c_msg *msg, int nmsgs) +{ + u8 bytes_in_fifo; + u32 pos = 0; + int i, ret; + + while (pos < msg->len) { + ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET, + XIIC_SR_RX_FIFO_EMPTY_MASK, false, + 1000, true); + if (ret) + return ret; + + bytes_in_fifo = readb(priv->base + XIIC_RFO_REG_OFFSET) + 1; + + if (bytes_in_fifo > msg->len) + bytes_in_fifo = msg->len; + + for (i = 0; i < bytes_in_fifo; i++) { + msg->buf[pos++] = readb(priv->base + + XIIC_DRR_REG_OFFSET); + } + } + + return 0; +} + +static int xiic_tx_fifo_space(struct xilinx_xiic_priv *priv) +{ + /* return the actual space left in the FIFO */ + return IIC_TX_FIFO_DEPTH - readb(priv->base + XIIC_TFO_REG_OFFSET) - 1; +} + +static void xiic_fill_tx_fifo(struct xilinx_xiic_priv *priv, + struct i2c_msg *msg, int nmsgs) +{ + u8 fifo_space = xiic_tx_fifo_space(priv); + int len = msg->len; + u32 pos = 0; + + len = (len > fifo_space) ? fifo_space : len; + + while (len--) { + u16 data = msg->buf[pos++]; + + if (pos == len && nmsgs == 1) { + /* last message in transfer -> STOP */ + data |= XIIC_TX_DYN_STOP_MASK; + } + writew(data, priv->base + XIIC_DTR_REG_OFFSET); + } +} + +static void xilinx_xiic_set_addr(struct udevice *dev, u8 addr, + u16 flags, u32 len, u32 nmsgs) +{ + struct xilinx_xiic_priv *priv = dev_get_priv(dev); + + xiic_irq_clr(priv, XIIC_INTR_TX_ERROR_MASK); + + if (!(flags & I2C_M_NOSTART)) { + /* write the address */ + u16 data = i2c_8bit_addr_from_flags(addr, flags) | + XIIC_TX_DYN_START_MASK; + if (nmsgs == 1 && len == 0) + /* no data and last message -> add STOP */ + data |= XIIC_TX_DYN_STOP_MASK; + + writew(data, priv->base + XIIC_DTR_REG_OFFSET); + } +} + +static int xilinx_xiic_read_common(struct udevice *dev, struct i2c_msg *msg, + u32 nmsgs) +{ + struct xilinx_xiic_priv *priv = dev_get_priv(dev); + u8 rx_watermark; + + /* Clear and enable Rx full interrupt. */ + xiic_irq_clr(priv, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); + + /* we want to get all but last byte, because the TX_ERROR IRQ is used + * to inidicate error ACK on the address, and negative ack on the last + * received byte, so to not mix them receive all but last. + * In the case where there is only one byte to receive + * we can check if ERROR and RX full is set at the same time + */ + rx_watermark = msg->len; + if (rx_watermark > IIC_RX_FIFO_DEPTH) + rx_watermark = IIC_RX_FIFO_DEPTH; + + writeb(rx_watermark - 1, priv->base + XIIC_RFD_REG_OFFSET); + + xilinx_xiic_set_addr(dev, msg->addr, msg->flags, msg->len, nmsgs); + + xiic_irq_clr(priv, XIIC_INTR_BNB_MASK); + + writew((msg->len & 0xff) | ((nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0), + priv->base + XIIC_DTR_REG_OFFSET); + + if (nmsgs == 1) + /* very last, enable bus not busy as well */ + xiic_irq_clr(priv, XIIC_INTR_BNB_MASK); + + return xiic_read_rx(priv, msg, nmsgs); +} + +static int xilinx_xiic_write_common(struct udevice *dev, struct i2c_msg *msg, + int nmsgs) +{ + struct xilinx_xiic_priv *priv = dev_get_priv(dev); + int ret; + + xilinx_xiic_set_addr(dev, msg->addr, msg->flags, msg->len, nmsgs); + xiic_fill_tx_fifo(priv, msg, nmsgs); + + ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET, + XIIC_SR_TX_FIFO_EMPTY_MASK, false, 1000, true); + if (ret) + return ret; + + /* Clear any pending Tx empty, Tx Error and then enable them. */ + xiic_irq_clr(priv, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | + XIIC_INTR_BNB_MASK); + + return 0; +} + +static void xiic_clear_rx_fifo(struct xilinx_xiic_priv *priv) +{ + u8 sr; + + for (sr = readb(priv->base + XIIC_SR_REG_OFFSET); + !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); + sr = readb(priv->base + XIIC_SR_REG_OFFSET)) + readb(priv->base + XIIC_DRR_REG_OFFSET); +} + +static void xiic_reinit(struct xilinx_xiic_priv *priv) +{ + writel(XIIC_RESET_MASK, priv->base + XIIC_RESETR_OFFSET); + + /* Set receive Fifo depth to maximum (zero based). */ + writeb(IIC_RX_FIFO_DEPTH - 1, priv->base + XIIC_RFD_REG_OFFSET); + + /* Reset Tx Fifo. */ + writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); + + /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ + writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); + + /* make sure RX fifo is empty */ + xiic_clear_rx_fifo(priv); + + /* Disable interrupts */ + writel(0, priv->base + XIIC_DGIER_OFFSET); + + xiic_irq_clr(priv, XIIC_INTR_ARB_LOST_MASK); +} + +static int xilinx_xiic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) +{ + int ret; + + for (; nmsgs > 0; nmsgs--, msg++) { + if (msg->flags & I2C_M_RD) + ret = xilinx_xiic_read_common(dev, msg, nmsgs); + else + ret = xilinx_xiic_write_common(dev, msg, nmsgs); + + if (ret) + return -EREMOTEIO; + } + + return ret; +} + +static int xilinx_xiic_probe_chip(struct udevice *dev, uint addr, uint flags) +{ + struct xilinx_xiic_priv *priv = dev_get_priv(dev); + u32 reg; + int ret; + + xiic_reinit(priv); + + xilinx_xiic_set_addr(dev, addr, 0, 0, 1); + ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET, + XIIC_SR_BUS_BUSY_MASK, false, 1000, true); + if (ret) + return ret; + + reg = readl(priv->base + XIIC_IISR_OFFSET); + if (reg & XIIC_INTR_TX_ERROR_MASK) + return -ENODEV; + + return 0; +} + +static int xilinx_xiic_set_speed(struct udevice *dev, uint speed) +{ + return 0; +} + +static int xilinx_xiic_probe(struct udevice *dev) +{ + struct xilinx_xiic_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); + xiic_reinit(priv); + + return 0; +} + +static const struct dm_i2c_ops xilinx_xiic_ops = { + .xfer = xilinx_xiic_xfer, + .probe_chip = xilinx_xiic_probe_chip, + .set_bus_speed = xilinx_xiic_set_speed, +}; + +static const struct udevice_id xilinx_xiic_ids[] = { + { .compatible = "xlnx,xps-iic-2.00.a" }, + { } +}; + +U_BOOT_DRIVER(xilinx_xiic) = { + .name = "xilinx_axi_i2c", + .id = UCLASS_I2C, + .of_match = xilinx_xiic_ids, + .probe = xilinx_xiic_probe, + .priv_auto_alloc_size = sizeof(struct xilinx_xiic_priv), + .ops = &xilinx_xiic_ops, +}; -- 2.17.1

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[U-Boot] [PATCH 0/9] ARM: dts: uniphier: updates for v2019.01
by Masahiro Yamada 19 Dec '18

19 Dec '18

Masahiro Yamada (9): ARM: uniphier: do not modify bootcmd environment variable at run-time ARM: uniphier: allow to source boot script before distro-boot ARM: uniphier: add CONFIG_PREBOOT linux/kernel.h: import DIV_ROUND_CLOSEST_ULL from Linux mtd: rawnand: denali_dt: add more clocks based on IP datasheet mtd: rawnand: denali: optimize timing parameters for data interface mtd: rawnand: denali: fix a race condition when DMA is kicked clk: uniphier: add NAND 200MHz clock ARM: uniphier: dts: sync with Linux 4.20-rc7 arch/arm/dts/uniphier-ld11.dtsi | 52 +++++- arch/arm/dts/uniphier-ld20-global.dts | 4 + arch/arm/dts/uniphier-ld20-ref.dts | 4 + arch/arm/dts/uniphier-ld20.dtsi | 242 +++++++++++++++++++++++++++- arch/arm/dts/uniphier-ld4.dtsi | 14 +- arch/arm/dts/uniphier-pinctrl.dtsi | 20 +++ arch/arm/dts/uniphier-pro4-ace.dts | 8 +- arch/arm/dts/uniphier-pro4-sanji.dts | 8 +- arch/arm/dts/uniphier-pro4.dtsi | 143 ++++++++++++++++- arch/arm/dts/uniphier-pro5.dtsi | 25 ++- arch/arm/dts/uniphier-pxs2.dtsi | 207 +++++++++++++++++++++++- arch/arm/dts/uniphier-pxs3.dtsi | 267 ++++++++++++++++++++++++++++++- arch/arm/dts/uniphier-sld8.dtsi | 14 +- arch/arm/mach-uniphier/board_late_init.c | 8 +- configs/uniphier_ld4_sld8_defconfig | 1 + configs/uniphier_v7_defconfig | 1 + configs/uniphier_v8_defconfig | 1 + drivers/clk/uniphier/clk-uniphier-sys.c | 8 +- drivers/mtd/nand/raw/denali.c | 53 +++--- drivers/mtd/nand/raw/denali.h | 1 + drivers/mtd/nand/raw/denali_dt.c | 40 ++++- include/configs/uniphier.h | 26 +++ include/linux/kernel.h | 12 ++ 23 files changed, 1109 insertions(+), 50 deletions(-) -- 2.7.4

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[U-Boot] fighting with unreliable designware-based 1G debug port
by rpjday＠crashcourse.ca 19 Dec '18

19 Dec '18

i've just been handed an issue regarding a modified version of u-boot v2015.07 and an unreliable designware MAC i'm hoping someone can give me some guidance on while i continue to dig through the code and continue testing. ARM-based target board has, among other things, an ethernet debug port that is used for downloading and flashing firmware images while in u-boot. problem is that, after coming up in u-boot, the debug port is totally inoperative anywhere from 1/3 to 1/2 of the time (reportedly no packet traffic at all). if one resets a few times, eventually the port is operational. there is no apparent pattern, and no predictable number of retries until the port works. for the testers, i configured u-boot to include the mdio command to let them poke around, then went to the DW data sheet, where i found the following in the GMAC register map: reg 48: 0x00C0 AN Control Register reg 49: 0x00C4 AN Status Register further down in the data sheet, a couple useful bits from the status register: 5 ANC Auto-Negotiation Complete 2 LS Link Status one of the testers, armed with this information and an ability to poke around the registers, *assures* me that there is a direct correlation between the debug port working, and those two bits from the status register both being set to one. both one -- working. both zero -- dead. given my assumption that those two bits simply display the current situation (you can't just set them), this suggests that *something* related to the dwmac is not being initialized properly when u-boot comes up. i can also see register: reg 54: 0x00D8 SGMII/RGMII/SMII Control and Status Register but have yet to dig into that; that's today's project. there is, AFAICT, a single line change to the v2015.07 designware.c file for this target board, down around line 267 (clearly modifying settings in the AN control register): ... snip ... #ifdef CONFIG_DW_AXI_BURST_LEN writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); #endif * Enable Auto-Negotiation and External loopback (same way as * linux driver does it) to get this driver to work. */ ====> writel(readl((u32)mac_p + 0xc0) | (1<<12) | (1<<14), (u32)mac_p + 0xc0); /* Start up the PHY */ ret = phy_startup(priv->phydev); ... snip ... the line marked "====>" is the line added to the source file. from the data sheet, the two bits being set in the AN control register are: 14 ELE loopback enable 12 ANE auto-negotiation enable despite the comment that that line is necessary to get the driver to work, it is still unreliable as i've already described. finally, the configuration for this board does *not* include CONFIG_RESET_PHY_R, so there is no invocation of a board-specific reset_phy() routine in common/board_r.c: #ifdef CONFIG_CMD_NET static int initr_net(void) { puts("Net: "); eth_initialize(); #if defined(CONFIG_RESET_PHY_R) <=== NOT configured debug("Reset Ethernet PHY\n"); reset_phy(); #endif return 0; } #endif which makes me wonder if there *should* be a reset_phy() routine defined for this board (whatever it might need to do). bottom line: has anyone else had this sort of maddeningly unreliable behaviour with a designware MAC? have there been any bug fixes since v2015.07 that might be applicable here? (i'm about to dig into the git log to see what's happened since then.) does that single line change to designware.c to set ELE and ANE in the AN control register look familiar to anyone, as in, has anyone else needed to do something similar? totally open to advice here. rday

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[U-Boot] [PATCH v6 0/4] Stratix10 FPGA reconfiguration support
by chee.hong.ang＠intel.com 19 Dec '18

19 Dec '18

From: "Ang, Chee Hong" <chee.hong.ang(a)intel.com> Summary of v6 changes: - Patch 1/4 and 4/4 are unchanged - Patch 2/4: - fixed compilation warnings in drivers/fpga/stratix10.c - Patch 3/4: - socfpga_fpga_add() in misc.c - define fpga descriptor structure in misc_arria10.c, misc_gen5.c & misc_s10.c respectively - removed for-loop in socfpga_fpga_add() (only 1 FPGA device added) v5 patchsets: https://lists.denx.de/pipermail/u-boot/2018-November/349670.html Ang, Chee Hong (4): arm: socfpga: stratix10: Add macros for mailbox's arguments arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 6 + arch/arm/mach-socfpga/include/mach/misc.h | 4 +- arch/arm/mach-socfpga/misc.c | 26 +- arch/arm/mach-socfpga/misc_arria10.c | 22 +- arch/arm/mach-socfpga/misc_gen5.c | 22 +- arch/arm/mach-socfpga/misc_s10.c | 22 ++ configs/socfpga_stratix10_defconfig | 1 + drivers/fpga/Kconfig | 11 + drivers/fpga/Makefile | 1 + drivers/fpga/altera.c | 6 + drivers/fpga/stratix10.c | 288 +++++++++++++++++++++++ include/altera.h | 8 + 12 files changed, 389 insertions(+), 28 deletions(-) create mode 100644 drivers/fpga/stratix10.c -- 2.7.4

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[U-Boot] [PATCH] Revert "sunxi: board: Print error after power initialization fails"
by karlp＠tweak.net.au 19 Dec '18

19 Dec '18

From: Karl Palsson <karlp(a)tweak.net.au> This reverts commit a8011eb84dfac5187cebf00ed8bc981bdb5c1fa1 This causes DRAM init failures on (at least) * allwinner h3 nanopi-duo2 * allwinner h2+ orangepi zero v1.1 Signed-off-by: Karl Palsson <karlp(a)tweak.net.au> --- Ideally, this should get into 2019.01, so that this release is not broken on those targets. board/sunxi/board.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 917f5b18f6..f022f365e9 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -637,6 +637,13 @@ void sunxi_board_init(void) power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON)); #endif #endif + printf("DRAM:"); + gd->ram_size = sunxi_dram_init(); + printf(" %d MiB\n", (int)(gd->ram_size >> 20)); + if (!gd->ram_size) + hang(); + + sunxi_spl_store_dram_size(gd->ram_size); /* * Only clock up the CPU to full speed if we are reasonably @@ -645,16 +652,7 @@ void sunxi_board_init(void) if (!power_failed) clock_set_pll1(CONFIG_SYS_CLK_FREQ); else - printf("Error setting up the power controller.\n" - "CPU frequency not set.\n"); - - printf("DRAM:"); - gd->ram_size = sunxi_dram_init(); - printf(" %d MiB\n", (int)(gd->ram_size >> 20)); - if (!gd->ram_size) - hang(); - - sunxi_spl_store_dram_size(gd->ram_size); + printf("Failed to set core voltage! Can't set CPU frequency\n"); } #endif -- 2.14.5

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