December 2018 - U-Boot

[U-Boot] FEC and EFI Simple Network
by Patrick Wildt 24 Feb '19

24 Feb '19

Hi, I have been debugging network issues when running an EFI Application that uses the EFI Simple Network protocol on an i.MX6 machine (FEC). The symptom is that u-boot's (FEC) internal RX ring index is reset to 0, while the controller is still at idx 3 (or something else). This is caused by the following circumstances: The Simple Network protocol offers methods like Start(), Stop(), Initialize(), Shutdown(), Reset(). Also the protocol has a state. The states are Stopped, Started, Initialized. The transition is as follows: Stopped ---Start()---> Started ---Initialize()--> Initialized Start() does some initialization, Initialize() allocates the TX/RX descriptors and actually kicks off the network engine. So far, only Initialize() is implemented in our u-boot interface, and it calls eth_init() which in the end calls fec_init(). Our network state is _always_ Started. This means that EFI Applications see that that the state is Started and then call Initialize() to start the actual network traffic. There is no call to Stop()/Shutdown()/Reset() as it's supposed to be in a sane state. In my case the FEC is already initialized since I booted using network and the RX desc index is already non-zero. Now the EFI Application sees that the state is Started, calls Initialize() which makes u-boot call eth_init() which then calls fec_init(). fec_init() does not reset the controller so that the controller-internal RX desc index is not reset to zero. fec_init() calls fec_open() which then resets the driver-internal RX desc index to zero. Now they are out of sync, boom. This means that fec_init() without a previous fec_halt() breaks the whole network if it was already running. The Designware driver as used by some sunxi platforms does a reset of the controller in the init function. Maybe calling fec_halt() at the start of fec_init() could be a possible solution? Patrick diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index ff7ad91116..ba8bd9920d 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -522,6 +522,12 @@ static int fec_open(struct eth_device *edev) return 0; } +#ifdef CONFIG_DM_ETH +static void fecmxc_halt(struct udevice *dev); +#else +static void fec_halt(struct eth_device *dev); +#endif + #ifdef CONFIG_DM_ETH static int fecmxc_init(struct udevice *dev) #else @@ -537,6 +543,15 @@ static int fec_init(struct eth_device *dev, bd_t *bd) u8 *i; ulong addr; +#ifdef CONFIG_DM_ETH + fecmxc_halt(dev); +#else + fec_halt(dev); +#endif + + writel(~FEC_TCNTRL_GTS & readl(&fec->eth->x_cntrl), + &fec->eth->x_cntrl); + /* Initialize MAC address */ #ifdef CONFIG_DM_ETH fecmxc_set_hwaddr(dev); @@ -825,19 +840,12 @@ static int fec_recv(struct eth_device *dev) } if (ievent & FEC_IEVENT_HBERR) { /* Heartbeat error */ - writel(0x00000001 | readl(&fec->eth->x_cntrl), + writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), &fec->eth->x_cntrl); } if (ievent & FEC_IEVENT_GRA) { /* Graceful stop complete */ - if (readl(&fec->eth->x_cntrl) & 0x00000001) { -#ifdef CONFIG_DM_ETH - fecmxc_halt(dev); -#else - fec_halt(dev); -#endif - writel(~0x00000001 & readl(&fec->eth->x_cntrl), - &fec->eth->x_cntrl); + if (readl(&fec->eth->x_cntrl) & FEC_TCNTRL_GTS) { #ifdef CONFIG_DM_ETH fecmxc_init(dev); #else

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[U-Boot] [PATCH v2 0/4] ARM: atmel: boards: enable SPL support
by Bo Shen 22 Feb '19

22 Feb '19

This patch series enable SPL support for following boards: - at91sam9m10g45ek - NAND flash boot support - SD card boot support - at91sam9n12ek - NAND flash boot support - SPI flash boot support - at91sam9x5ek - NAND flash boot support - SPI flash boot support Changes in v2: - Remove the meaningless prefix "+S:" in configuration file. Bo Shen (4): ARM: atmel: arm926ejs: fix clock configuration ARM: atmel: at91sam9m10g45ek: enable spl support ARM: atmel: at91sam9x5ek: enable spl support ARM: atmel: at91sam9n12ek: enable spl support arch/arm/mach-at91/Kconfig | 3 + arch/arm/mach-at91/Makefile | 2 + arch/arm/mach-at91/arm926ejs/clock.c | 54 +++++++++-------- arch/arm/mach-at91/arm926ejs/u-boot-spl.lds | 48 +++++++++++++++ arch/arm/mach-at91/include/mach/at91_pmc.h | 6 +- arch/arm/mach-at91/include/mach/at91sam9x5.h | 10 ++++ arch/arm/mach-at91/mpddrc.c | 3 +- arch/arm/mach-at91/spl.c | 2 +- arch/arm/mach-at91/spl_at91.c | 11 +++- board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 80 +++++++++++++++++++++++++ board/atmel/at91sam9n12ek/at91sam9n12ek.c | 73 ++++++++++++++++++++++ board/atmel/at91sam9x5ek/at91sam9x5ek.c | 74 +++++++++++++++++++++++ configs/at91sam9m10g45ek_mmc_defconfig | 1 + configs/at91sam9m10g45ek_nandflash_defconfig | 1 + configs/at91sam9n12ek_nandflash_defconfig | 1 + configs/at91sam9n12ek_spiflash_defconfig | 1 + configs/at91sam9x5ek_nandflash_defconfig | 1 + configs/at91sam9x5ek_spiflash_defconfig | 1 + include/configs/at91sam9m10g45ek.h | 58 ++++++++++++++++++ include/configs/at91sam9n12ek.h | 58 +++++++++++++++++- include/configs/at91sam9x5ek.h | 57 ++++++++++++++++++ 21 files changed, 513 insertions(+), 32 deletions(-) create mode 100644 arch/arm/mach-at91/arm926ejs/u-boot-spl.lds -- 2.3.3.220.g9ab698f

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[U-Boot] [PATCH v3 0/2] core: ofnode: Fix ofnode_get_addr_index function
by Keerthy 21 Feb '19

21 Feb '19

The series adds a fix to ofnode_get_addr_index function and also adds a new ofnode_get_addr_size_index function. Changes in v3: Fixed compilation issues with sandbox_defconfig Keerthy (2): core: ofnode: Fix ofnode_get_addr_index function core: ofnode: Add ofnode_get_addr_size_index drivers/core/ofnode.c | 25 +++++++++++++++++-------- include/dm/ofnode.h | 14 ++++++++++++++ 2 files changed, 31 insertions(+), 8 deletions(-) -- 1.9.1

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[U-Boot] [PATCH] QE: ls1043a: modify CONFIG_SYS_QE_FW_ADDR to (512*4A00) in SD Card
by Zhao Qiang 20 Feb '19

20 Feb '19

Due to the new layout of Layerscape series, move the QE firmware to address (512*4A00) in SD Card. Signed-off-by: Zhao Qiang <qiang.zhao(a)nxp.com> --- include/configs/ls1043a_common.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 4279d53..62ac915 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -194,7 +194,7 @@ */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) -#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08) +#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4A00) #elif defined(CONFIG_QSPI_BOOT) #define CONFIG_SYS_QE_FW_IN_SPIFLASH #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 -- 1.7.1

2 1

[U-Boot] [PATCH v2] armv8:LX2160: Adds distro secure boot support.
by Udit Agarwal 20 Feb '19

20 Feb '19

Adds esbc validate command for verification of MC and DPC firmware. Adds secure boot defconfig. Signed-off-by: Udit Agarwal <udit.agarwal(a)nxp.com> --- Changes in v2: Correct flash offset for Kernel header for secure boot. configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 86 ++++++++++++++++++++ include/configs/lx2160a_common.h | 12 ++- 2 files changed, 97 insertions(+), 1 deletion(-) create mode 100644 configs/lx2160ardb_tfa_SECURE_BOOT_defconfig diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..b7e3967ad9 --- /dev/null +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,86 @@ +CONFIG_ARM=y +CONFIG_TARGET_LX2160ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_SECURE_BOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" +CONFIG_NR_DRAM_BANKS=3 +CONFIG_DM=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_TFABOOT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_SERIAL=y +CONFIG_SERIAL_PROBE_ALL=y +CONFIG_CONS_INDEX=0 +CONFIG_FSL_CAAM=y +CONFIG_FSL_ESDHC=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MICRON=y +CONFIG_SPI_FLASH_USE_4K_SECTORS=n +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_NXP_FSPI=y +CONFIG_FSPI_AHB_EN_4BYTE=y +CONFIG_SYS_FSPI_AHB_INIT=y +CONFIG_PHYLIB=y +CONFIG_NETDEVICES=y +CONFIG_PHY_GIGE=y +CONFIG_CMD_NET=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_FAT=y +CONFIG_CMD_EXT2=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LX=y +CONFIG_E1000=y +CONFIG_NET=y +CONFIG_DM_MMC=y +CONFIG_DM_MMC_OPS=n +CONFIG_BLK=n +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +# CONFIG_SYS_FSL_DDR_PHY is not set +CONFIG_SYS_GEN2_DDR_PHY=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_PHYLIB_10G=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_CORTINA=y +CONFIG_PHY_ATHEROS=y +CONFIG_PHY_INPHI=y +CONFIG_INPHI_25G=y +CONFIG_HUSH_PARSER=y +CONFIG_EMC2305=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index fa554bc2f5..3ff54a4dc9 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -198,11 +198,19 @@ unsigned long get_board_ddr_clk(void); /* Initial environment variables */ #define XSPI_MC_INIT_CMD \ + "env exists secureboot && " \ + "esbc_validate 0x20700000 && " \ + "esbc_validate 0x20740000 ;" \ "fsl_mc start mc 0x20a00000 0x20e00000\0" #define SD_MC_INIT_CMD \ "mmc read 0x80000000 0x5000 0x800;" \ "mmc read 0x80100000 0x7000 0x800;" \ + "env exists secureboot && " \ + "mmc read 0x80700000 0x3800 0x10 && " \ + "mmc read 0x80740000 0x3A00 0x10 && " \ + "esbc_validate 0x80700000 && " \ + "esbc_validate 0x80740000 ;" \ "fsl_mc start mc 0x80000000 0x80100000\0" #define EXTRA_ENV_SETTINGS \ @@ -213,7 +221,7 @@ unsigned long get_board_ddr_clk(void); "initrd_high=0xffffffffffffffff\0" \ "fdt_addr=0x64f00000\0" \ "kernel_start=0x1000000\0" \ - "kernelheader_start=0x800000\0" \ + "kernelheader_start=0x7C0000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ "fdtheader_addr_r=0x80100000\0" \ @@ -224,7 +232,9 @@ unsigned long get_board_ddr_clk(void); "load_addr=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "kernel_addr_sd=0x8000\0" \ + "kernelhdr_addr_sd=0x3E00\0" \ "kernel_size_sd=0x1d000\0" \ + "kernelhdr_size_sd=0x10\0" \ "console=ttyAMA0,38400n8\0" \ BOOTENV \ "mcmemsize=0x70000000\0" \ -- 2.17.1

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[U-Boot] [PATCH 1/2] armv8: emc2305: add support for fan controller
by Meenakshi Aggarwal 20 Feb '19

20 Feb '19

Add support for fan controller emc2305. Signed-off-by: Sriram Dash <sriram.dash(a)nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 +++++ board/freescale/common/Makefile | 2 ++ board/freescale/common/emc2305.c | 41 +++++++++++++++++++++++++++++++ board/freescale/common/emc2305.h | 23 +++++++++++++++++ 4 files changed, 72 insertions(+) create mode 100644 board/freescale/common/emc2305.c create mode 100644 board/freescale/common/emc2305.h diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 5dba2af..b0e779d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -346,6 +346,12 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. +config EMC2305 + bool "Fan controller" + help + Enable the EMC2305 fan controller for configuration of fan + speed. + config SECURE_BOOT bool "Secure Boot" help diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index e3c5eae..a9d61a8 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -64,6 +64,8 @@ obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o +obj-$(CONFIG_EMC2305) += emc2305.o + # deal with common files for P-series corenet based devices obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/ obj-$(CONFIG_TARGET_P3041DS) += p_corenet/ diff --git a/board/freescale/common/emc2305.c b/board/freescale/common/emc2305.c new file mode 100644 index 0000000..8523084 --- /dev/null +++ b/board/freescale/common/emc2305.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <i2c.h> +#include <asm/io.h> + +#include "emc2305.h" + +DECLARE_GLOBAL_DATA_PTR; + +void set_fan_speed(u8 data) +{ + u8 index; + u8 Fan[NUM_OF_FANS] = {I2C_EMC2305_FAN1, + I2C_EMC2305_FAN2, + I2C_EMC2305_FAN3, + I2C_EMC2305_FAN4, + I2C_EMC2305_FAN5}; + + for (index = 0; index < NUM_OF_FANS; index++) { + if (i2c_write(I2C_EMC2305_ADDR, Fan[index], 1, &data, 1) != 0) { + printf("Error: failed to change fan speed @%x\n", + Fan[index]); + } + } +} + +void emc2305_init(void) +{ + u8 data; + + data = I2C_EMC2305_CMD; + if (i2c_write(I2C_EMC2305_ADDR, I2C_EMC2305_CONF, 1, &data, 1) != 0) + printf("Error: failed to configure EMC2305\n"); +} diff --git a/board/freescale/common/emc2305.h b/board/freescale/common/emc2305.h new file mode 100644 index 0000000..eddf537 --- /dev/null +++ b/board/freescale/common/emc2305.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __EMC2305_H_ +#define __EMC2305_H_ + +#define I2C_EMC2305_CONF 0x20 +#define I2C_EMC2305_FAN1 0x30 +#define I2C_EMC2305_FAN2 0x40 +#define I2C_EMC2305_FAN3 0x50 +#define I2C_EMC2305_FAN4 0x60 +#define I2C_EMC2305_FAN5 0x70 + +#define NUM_OF_FANS 5 + +void emc2305_init(void); +void set_fan_speed(u8 data); + +#endif /* __EMC2305_H_ */ -- 1.9.1

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[U-Boot] [PATCH 1/2] armv8: dts: fsl-lx2160a: add sata node support
by Peng Ma 20 Feb '19

20 Feb '19

One lx2160A, there is one SATA 3.0 advanced host controller interface which is a high-performance SATA solution that delivers comprehensive and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA capabilities, in accordance with the serial ATA revision 3.0 of Serial ATA International Organization. Signed-off-by: Peng Ma <peng.ma(a)nxp.com> --- arch/arm/dts/fsl-lx2160a-rdb.dts | 16 ++++++++++++++++ arch/arm/dts/fsl-lx2160a.dtsi | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+), 0 deletions(-) diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts index c3b3a06..7c4f0e7 100644 --- a/arch/arm/dts/fsl-lx2160a-rdb.dts +++ b/arch/arm/dts/fsl-lx2160a-rdb.dts @@ -53,3 +53,19 @@ &esdhc1 { status = "okay"; }; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sata3 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index c268bd9..c8cab6a 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -238,4 +238,41 @@ bus-range = <0x0 0xff>; ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + + sata0: sata@3200000 { + compatible = "fsl,ls2080a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 133 4>; + clocks = <&clockgen 4 3>; + status = "disabled"; + + }; + + sata1: sata@3210000 { + compatible = "fsl,ls2080a-ahci"; + reg = <0x0 0x3210000 0x0 0x10000>; + interrupts = <0 136 4>; + clocks = <&clockgen 4 3>; + status = "disabled"; + + }; + + sata2: sata@3220000 { + compatible = "fsl,ls2080a-ahci"; + reg = <0x0 0x3220000 0x0 0x10000>; + interrupts = <0 97 4>; + clocks = <&clockgen 4 3>; + status = "disabled"; + + }; + + sata3: sata@3230000 { + compatible = "fsl,ls2080a-ahci"; + reg = <0x0 0x3230000 0x0 0x10000>; + interrupts = <0 100 4>; + clocks = <&clockgen 4 3>; + status = "disabled"; + + }; + }; -- 1.7.1

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[U-Boot] [v1 1/2] armv8: dts: fsl-lx2160a: add sata node support
by Peng Ma 20 Feb '19

20 Feb '19

One lx2160A, there is one SATA 3.0 advanced host controller interface which is a high-performance SATA solution that delivers comprehensive and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA capabilities, in accordance with the serial ATA revision 3.0 of Serial ATA International Organization. Signed-off-by: Peng Ma <peng.ma(a)nxp.com> --- Depends on: - https://patchwork.ozlabs.org/project/uboot/list/?series=72964 - https://patchwork.ozlabs.org/project/uboot/list/?series=78759 arch/arm/dts/fsl-lx2160a-rdb.dts | 16 ++++++++++++++++ arch/arm/dts/fsl-lx2160a.dtsi | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+), 0 deletions(-) diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts index c3b3a06..7c4f0e7 100644 --- a/arch/arm/dts/fsl-lx2160a-rdb.dts +++ b/arch/arm/dts/fsl-lx2160a-rdb.dts @@ -53,3 +53,19 @@ &esdhc1 { status = "okay"; }; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sata3 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index c268bd9..c8cab6a 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -238,4 +238,41 @@ bus-range = <0x0 0xff>; ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + + sata0: sata@3200000 { + compatible = "fsl,ls2080a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 133 4>; + clocks = <&clockgen 4 3>; + status = "disabled"; + + }; + + sata1: sata@3210000 { + compatible = "fsl,ls2080a-ahci"; + reg = <0x0 0x3210000 0x0 0x10000>; + interrupts = <0 136 4>; + clocks = <&clockgen 4 3>; + status = "disabled"; + + }; + + sata2: sata@3220000 { + compatible = "fsl,ls2080a-ahci"; + reg = <0x0 0x3220000 0x0 0x10000>; + interrupts = <0 97 4>; + clocks = <&clockgen 4 3>; + status = "disabled"; + + }; + + sata3: sata@3230000 { + compatible = "fsl,ls2080a-ahci"; + reg = <0x0 0x3230000 0x0 0x10000>; + interrupts = <0 100 4>; + clocks = <&clockgen 4 3>; + status = "disabled"; + + }; + }; -- 1.7.1

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[U-Boot] [PATCH] armv8: lx2160a: Modify dspi1 controller intrrupts property
by Chuanhua Han 20 Feb '19

20 Feb '19

This patch is to modify the dspi1 controller interrupt number for lx2160a, the original 240 interrupt is problematic and cannot be registered, so first change it to share an interrupt with dspi0. Signed-off-by: Chuanhua Han <chuanhua.han(a)nxp.com> --- depend on: - https://patchwork.ozlabs.org/patch/990093/ arch/arm/dts/fsl-lx2160a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index b407dc6e13..6f1a302548 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -89,7 +89,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2110000 0x0 0x10000>; - interrupts = <0 240 0x4>; /* Level high type */ + interrupts = <0 26 0x4>; /* Level high type */ num-cs = <6>; }; -- 2.17.1

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[U-Boot] [PATCH v1] armv8: lx2160a: add eSDHC nodes
by Yinbo Zhu 20 Feb '19

20 Feb '19

This patch is to add eSDHC nodes for lx2160a. Signed-off-by: Yinbo Zhu <yinbo.zhu(a)nxp.com> --- arch/arm/dts/fsl-lx2160a-rdb.dts | 8 ++++++++ arch/arm/dts/fsl-lx2160a.dtsi | 24 ++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 0 deletions(-) diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts index 162ec25..1d67ba6 100644 --- a/arch/arm/dts/fsl-lx2160a-rdb.dts +++ b/arch/arm/dts/fsl-lx2160a-rdb.dts @@ -38,3 +38,11 @@ reg = <0>; }; }; + +&esdhc0 { + status = "okay"; +}; + +&esdhc1 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 12655fc..ad9bfa2 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -76,6 +76,30 @@ status = "disabled"; }; + esdhc0: esdhc@2140000 { + status = "disabled"; + compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; /* Level high type */ + clocks = <&clockgen 4 1>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + little-endian; + bus-width = <4>; + }; + + esdhc1: esdhc@2150000 { + status = "disabled"; + compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; + reg = <0x0 0x2150000 0x0 0x10000>; + interrupts = <0 28 0x4>; /* Level high type */ + clocks = <&clockgen 4 1>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + little-endian; + bus-width = <4>; + }; + fspi: flexspi@20c0000 { compatible = "nxp,lx2160a-fspi"; #address-cells = <1>; -- 1.7.1

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