November 2018 - U-Boot

[U-Boot] [PATCH] QSPI flash driver compatibility fixes for mx6ull
by Neil Stainton 28 Jan '19

28 Jan '19

Avoid "SF: Timeout!" messages and generally speed up QSPI flash operations on mx6ull EVK by adding a QSPI sequence for reading "flag status register" as required for some (ST/Micron) NOR flash devices by the DM spi-flash driver. Enable QSPI clock in EVK specific board_init function, as per other Freescale EVKs. Tested on mcimx6ull EVK, U303 populated with a Micron MT25QL256ABA (ID reads as 'n25q256'). Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Jagan Teki <jagan(a)openedev.com> Signed-off-by: Neil Stainton <nstainton(a)asl-control.co.uk> --- arch/arm/dts/imx6ull-14x14-evk.dts | 2 +- board/freescale/mx6ullevk/mx6ullevk.c | 15 +++++++++++++++ drivers/mtd/spi/spi_flash.c | 4 ++-- drivers/spi/fsl_qspi.c | 24 +++++++++++++++++++----- 4 files changed, 37 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/imx6ull-14x14-evk.dts b/arch/arm/dts/imx6ull-14x14-evk.dts index 8a1b67d..7cb6d16 100644 --- a/arch/arm/dts/imx6ull-14x14-evk.dts +++ b/arch/arm/dts/imx6ull-14x14-evk.dts @@ -454,10 +454,10 @@ flash0: n25q256a@0 { #address-cells = <1>; #size-cells = <1>; - /* compatible = "micron,n25q256a"; */ compatible = "spi-flash"; spi-max-frequency = <29000000>; spi-nor,ddr-quad-read-dummy = <6>; + memory-map = <0x60000000 0x02000000>; reg = <0>; }; }; diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c index ad83f36..46d61bc 100644 --- a/board/freescale/mx6ullevk/mx6ullevk.c +++ b/board/freescale/mx6ullevk/mx6ullevk.c @@ -58,11 +58,26 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_FSL_QSPI +static int board_qspi_init(void) +{ + /* Set the clock */ + enable_qspi_clk(0); + + return 0; +} +#endif /* !defined(CONFIG_FSL_QSPI) */ + int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_FSL_QSPI + /* Set the clock */ + board_qspi_init(); +#endif + return 0; } diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index c159124..c817772 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -360,7 +360,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) } #ifdef CONFIG_SPI_FLASH_BAR - ret = clean_bar(flash); + clean_bar(flash); #endif return ret; @@ -422,7 +422,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, } #ifdef CONFIG_SPI_FLASH_BAR - ret = clean_bar(flash); + clean_bar(flash); #endif return ret; diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 1598c4f..07c3ade 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -47,10 +47,12 @@ DECLARE_GLOBAL_DATA_PTR; #endif #define SEQID_WRAR 13 #define SEQID_RDAR 14 +#define SEQID_RDFSR 15 /* QSPI CMD */ #define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */ #define QSPI_CMD_RDSR 0x05 /* Read status register */ +#define QSPI_CMD_RDFSR 0x70 /* Read flag status register */ #define QSPI_CMD_WREN 0x06 /* Write enable */ #define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */ #define QSPI_CMD_BE_4K 0x20 /* 4K erase */ @@ -230,6 +232,15 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv) qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0); qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0); + /* Read Flag Status */ + lut_base = SEQID_RDFSR * 4; + qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDFSR) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | + PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0); + /* Erase a sector */ lut_base = SEQID_SE * 4; #ifdef CONFIG_SPI_FLASH_BAR @@ -698,7 +709,7 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) qspi_write32(priv->flags, &regs->mcr, mcr_reg); } -static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len) +static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len, u8 seqid) { struct fsl_qspi_regs *regs = priv->regs; u32 mcr_reg, reg, data; @@ -712,7 +723,7 @@ static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len) qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base); qspi_write32(priv->flags, &regs->ipcr, - (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0); + (seqid << QSPI_IPCR_SEQID_SHIFT) | 0); while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK) ; @@ -815,10 +826,13 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen, #endif } else if (priv->cur_seqid == QSPI_CMD_RDAR) { qspi_op_read(priv, din, bytes); - } else if (priv->cur_seqid == QSPI_CMD_RDID) + } else if (priv->cur_seqid == QSPI_CMD_RDID) { qspi_op_rdid(priv, din, bytes); - else if (priv->cur_seqid == QSPI_CMD_RDSR) - qspi_op_rdsr(priv, din, bytes); + } else if (priv->cur_seqid == QSPI_CMD_RDSR) { + qspi_op_rdsr(priv, din, bytes, SEQID_RDSR); + } else if (priv->cur_seqid == QSPI_CMD_RDFSR) { + qspi_op_rdsr(priv, din, bytes, SEQID_RDFSR); + } #ifdef CONFIG_SPI_FLASH_BAR else if ((priv->cur_seqid == QSPI_CMD_BRRD) || (priv->cur_seqid == QSPI_CMD_RDEAR)) { -- 2.7.4

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[U-Boot] [PATCH 0/3] Support for the Aspeed ast2500 FMC/SPI controllers
by Cédric Le Goater 26 Jan '19

26 Jan '19

Hello, This series adds a driver for the Aspeed ast2500 FMC/SPI controllers as one can find on the POWER9 OpenPOWER platforms. It was tested on the AST2500 evb using a w25q256 flash device. Git tree available here: https://github.com/legoater/u-boot/commits/aspeed Thanks, C. Cédric Le Goater (3): aspeed: ast2500: Add AHB clock spi: Add support for the Aspeed ast2500 SPI controllers aspeed: Add SPI support to the ast2500 Eval Board .../arm/include/asm/arch-aspeed/scu_ast2500.h | 2 + arch/arm/include/asm/arch-aspeed/spi.h | 114 +++ include/dt-bindings/clock/ast2500-scu.h | 1 + drivers/clk/aspeed/clk_ast2500.c | 12 + drivers/spi/aspeed_spi.c | 788 ++++++++++++++++++ arch/arm/dts/ast2500-evb.dts | 17 + arch/arm/dts/ast2500-u-boot.dtsi | 12 + arch/arm/dts/ast2500.dtsi | 71 ++ configs/evb-ast2500_defconfig | 10 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + 11 files changed, 1036 insertions(+) create mode 100644 arch/arm/include/asm/arch-aspeed/spi.h create mode 100644 drivers/spi/aspeed_spi.c -- 2.17.1

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[U-Boot] [PATCH 1/2] net: phy: Move fixed link code to separate routine
by Siva Durga Prasad Paladugu 25 Jan '19

25 Jan '19

This patch moves fixed-link functionality code to a separate routine inorder to make it more modular and cleaner. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/net/phy/phy.c | 34 +++++++++++++++++++++++++++------- 1 file changed, 27 insertions(+), 7 deletions(-) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index e837eb7..3cb2785 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -875,18 +875,18 @@ void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev) debug("%s connected to %s\n", dev->name, phydev->drv->name); } +#ifdef CONFIG_PHY_FIXED #ifdef CONFIG_DM_ETH -struct phy_device *phy_connect(struct mii_dev *bus, int addr, - struct udevice *dev, - phy_interface_t interface) +static struct phy_device *phy_connect_fixed(struct mii_dev *bus, + struct udevice *dev, + phy_interface_t interface) #else -struct phy_device *phy_connect(struct mii_dev *bus, int addr, - struct eth_device *dev, - phy_interface_t interface) +static struct phy_device *phy_connect_fixed(struct mii_dev *bus, + struct eth_device *dev, + phy_interface_t interface) #endif { struct phy_device *phydev = NULL; -#ifdef CONFIG_PHY_FIXED int sn; const char *name; @@ -900,7 +900,27 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr, } sn = fdt_next_subnode(gd->fdt_blob, sn); } + + return phydev; +} #endif + +#ifdef CONFIG_DM_ETH +struct phy_device *phy_connect(struct mii_dev *bus, int addr, + struct udevice *dev, + phy_interface_t interface) +#else +struct phy_device *phy_connect(struct mii_dev *bus, int addr, + struct eth_device *dev, + phy_interface_t interface) +#endif +{ + struct phy_device *phydev = NULL; + +#ifdef CONFIG_PHY_FIXED + phydev = phy_connect_fixed(bus, dev, interface); +#endif + if (!phydev) phydev = phy_find_by_mask(bus, 1 << addr, interface); -- 2.7.4

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[U-Boot] [PATCH v2] Aquantia: Print information about system interface and firmware version
by Valentin-catalin Neacsu 24 Jan '19

24 Jan '19

Print information about Aquantia firmware loaded on the phy. Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu(a)nxp.com> --- V2: - Fix typo in title. (Clement Peron) drivers/net/phy/aquantia.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index 553069f3dc..2609664c69 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -22,6 +22,11 @@ #define AQUANTIA_SYSTEM_INTERFACE_SR 0xe812 #define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441 +#define AQUANTIA_FIRMWARE_ID 0x20 +#define AQUANTIA_RESERVED_STATUS 0xc885 +#define AQUANTIA_FIRMWARE_MAJOR_MASK 0xff00 +#define AQUANTIA_FIRMWARE_MINOR_MASK 0xff +#define AQUANTIA_FIRMWARE_BUILD_MASK 0xf0 #define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008 #define AQUANTIA_SI_IN_USE_MASK 0x0078 @@ -30,6 +35,7 @@ int aquantia_config(struct phy_device *phydev) { u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); + u32 reg_val1 = 0; if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { /* 1000BASE-T mode */ @@ -56,6 +62,11 @@ int aquantia_config(struct phy_device *phydev) phy_write(phydev, MDIO_MMD_PHYXS, AQUANTIA_VENDOR_PROVISIONING_REG, AQUANTIA_USX_AUTONEG_CONTROL_ENA); + printf("%s: system interface USXGMII\n", + phydev->dev->name); + } else { + printf("%s: system interface XFI\n", + phydev->dev->name); } } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500) { @@ -73,6 +84,16 @@ int aquantia_config(struct phy_device *phydev) val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK; phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); } + + val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS); + reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID); + + printf("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name, + phydev->drv->name, + (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8, + reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK, + (val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4); + return 0; } -- 2.17.1

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[U-Boot] [PATCH 1/2] AQUANTIA USXGMII autoneg enable
by Valentin-catalin Neacsu 24 Jan '19

24 Jan '19

If System interface protocol is USXGMII then enable USXGMII autoneg Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu(a)nxp.com> --- drivers/net/phy/aquantia.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index 6678147545..603abb5a7f 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ * * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP */ #include <config.h> #include <common.h> @@ -20,6 +21,13 @@ #define AQUNTIA_SPEED_LSB_MASK 0x2000 #define AQUNTIA_SPEED_MSB_MASK 0x40 +#define AQUANTIA_SYSTEM_INTERFACE_SR 0xe812 +#define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441 + +#define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008 +#define AQUANTIA_SI_IN_USE_MASK 0x0078 +#define AQUANTIA_SI_USXGMII 0x0018 + int aquantia_config(struct phy_device *phydev) { u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); @@ -41,6 +49,16 @@ int aquantia_config(struct phy_device *phydev) phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, AQUNTIA_SPEED_LSB_MASK | AQUNTIA_SPEED_MSB_MASK); + + val = phy_read(phydev, MDIO_MMD_PHYXS, + AQUANTIA_SYSTEM_INTERFACE_SR); + /* If SI is USXGMII then start USXGMII autoneg*/ + if ((val & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII) { + phy_write(phydev, MDIO_MMD_PHYXS, + AQUANTIA_VENDOR_PROVISIONING_REG, + AQUANTIA_USX_AUTONEG_CONTROL_ENA); + } + } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500) { /* 2.5GBASE-T mode */ phydev->advertising = SUPPORTED_1000baseT_Full; -- 2.17.1

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[U-Boot] [PATCH 1/2] net: move ether_crc to tsec driver
by Chris Packham 24 Jan '19

24 Jan '19

ether_crc was added to the core net code in commit 53a5c424bf86 ("multicast tftp: RFC2090") so that other drivers could use it. However the only current user of it is tsec.c so move it there. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- drivers/net/tsec.c | 25 +++++++++++++++++++++++++ include/net.h | 1 - net/eth_legacy.c | 24 ------------------------ 3 files changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 03a46da2f8a1..9a4fab85e928 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -80,6 +80,31 @@ static void tsec_configure_serdes(struct tsec_private *priv) #ifdef CONFIG_MCAST_TFTP +/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c + * and this is the ethernet-crc method needed for TSEC -- and perhaps + * some other adapter -- hash tables + */ +#define CRCPOLY_LE 0xedb88320 +static u32 ether_crc(size_t len, unsigned char const *p) +{ + int i; + u32 crc; + + crc = ~0; + while (len--) { + crc ^= *p++; + for (i = 0; i < 8; i++) + crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0); + } + /* an reverse the bits, cuz of way they arrive -- last-first */ + crc = (crc >> 16) | (crc << 16); + crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00); + crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0); + crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc); + crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa); + return crc; +} + /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ /* Set the appropriate hash bit for the given addr */ diff --git a/include/net.h b/include/net.h index 51c099dae2e5..359bfb5ef69f 100644 --- a/include/net.h +++ b/include/net.h @@ -289,7 +289,6 @@ const char *eth_get_name(void); /* get name of current device */ #ifdef CONFIG_MCAST_TFTP int eth_mcast_join(struct in_addr mcast_addr, int join); -u32 ether_crc(size_t len, unsigned char const *p); #endif diff --git a/net/eth_legacy.c b/net/eth_legacy.c index 2a9caa3509b0..d2e16b8fa3da 100644 --- a/net/eth_legacy.c +++ b/net/eth_legacy.c @@ -310,30 +310,6 @@ int eth_mcast_join(struct in_addr mcast_ip, int join) return eth_current->mcast(eth_current, mcast_mac, join); } -/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c - * and this is the ethernet-crc method needed for TSEC -- and perhaps - * some other adapter -- hash tables - */ -#define CRCPOLY_LE 0xedb88320 -u32 ether_crc(size_t len, unsigned char const *p) -{ - int i; - u32 crc; - crc = ~0; - while (len--) { - crc ^= *p++; - for (i = 0; i < 8; i++) - crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0); - } - /* an reverse the bits, cuz of way they arrive -- last-first */ - crc = (crc >> 16) | (crc << 16); - crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00); - crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0); - crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc); - crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa); - return crc; -} - #endif -- 2.19.2

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[U-Boot] [PATCH] net: phy: micrel: fix KSZ9031 clock skew for values greater 0ps
by Andreas Pretzsch 24 Jan '19

24 Jan '19

For KSZ9021, all skew register fields are 4-bit wide. For KSZ9031, the clock skew register fields are 5-bit wide. The common code in ksz90x1_of_config_group calculating the combined register value checks if the requested value is above the maximum and uses this maximum if so. The calculation of this maximum uses the register width, but the check itself does not. It uses a hardcoded value of 0xf, which is too low in case of the 5-bit clock (0x1f). This detail was probably lost during driver unification. Effect (only for KSZ9031 clock skews): For values greater 900 (== 0ps), this silently results in 1860 (== +960ps) instead of the requested one. Fix the check by using the bit width instead of hardcoded value(s). Signed-off-by: Andreas Pretzsch <apr(a)cn-eng.de> --- drivers/net/phy/micrel_ksz90x1.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c index 3951535bf1..63e7b0242b 100644 --- a/drivers/net/phy/micrel_ksz90x1.c +++ b/drivers/net/phy/micrel_ksz90x1.c @@ -123,8 +123,8 @@ static int ksz90x1_of_config_group(struct phy_device *phydev, } else { changed = 1; /* Value was changed in OF */ /* Calculate the register value and fix corner cases */ - if (val[i] > ps_to_regval * 0xf) { - max = (1 << ofcfg->grp[i].size) - 1; + max = (1 << ofcfg->grp[i].size) - 1; + if (val[i] > ps_to_regval * max) { regval |= max << offset; } else { regval |= (val[i] / ps_to_regval) << offset; -- 2.19.1

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[U-Boot] [PATCH] net: fix env flags for eth10addr and above
by Simon Goldschmidt 24 Jan '19

24 Jan '19

With CONFIG_REGEX enabled, ETHADDR_WILDCARD is set up for up to 10 interfaces (0..9) as the number can only have one digit. On boards with more than 10 interfaces, this leads to the protection and format checks being absent for eth10addr and above. Fix this by changing ETHADDR_WILDCARD from "\\d?" to "\\d*" to allow more than one digit. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- include/env_flags.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/env_flags.h b/include/env_flags.h index cc2c34f939..23744e395c 100644 --- a/include/env_flags.h +++ b/include/env_flags.h @@ -38,7 +38,7 @@ enum env_flags_varaccess { #ifdef CONFIG_CMD_NET #ifdef CONFIG_REGEX -#define ETHADDR_WILDCARD "\\d?" +#define ETHADDR_WILDCARD "\\d*" #else #define ETHADDR_WILDCARD #endif -- 2.17.1

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[U-Boot] [PATCH] net: remove duplicate definition of ETHADDR_WILDCARD
by Simon Goldschmidt 24 Jan '19

24 Jan '19

ETHADDR_WILDCARD is defined as the same value in both env_flags.h and env_callback.h As env_callback.h includes env_flags.h, remove the duplicate definition from env_callback.h Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- include/env_callback.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/env_callback.h b/include/env_callback.h index 3c44ff574b..507a52e13c 100644 --- a/include/env_callback.h +++ b/include/env_callback.h @@ -32,10 +32,8 @@ #ifdef CONFIG_REGEX #define ENV_DOT_ESCAPE "\\" -#define ETHADDR_WILDCARD "\\d?" #else #define ENV_DOT_ESCAPE -#define ETHADDR_WILDCARD #endif #ifdef CONFIG_CMD_DNS -- 2.17.1

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[U-Boot] [PATCH] net: explicitly assign errno to return code in case of network failure
by Thomas RIENOESSL 24 Jan '19

24 Jan '19

When dealing with two ethernet ports and having "netretry" set to "once", it could occur that the connection (e.g. an ARP request) failed, hence the status of the netloop was "NETLOOP_FAIL". Due to the setting of "netretry", the network logic would then switch to the other network interface, assigning "ret" with the return value of "net_start_again()". If this call succeeded we would return 0 (i.e. success) to the caller when in reality the network action failed. Change-Id: I58b935b0f6c7a300d1dd0058803f7d3c9455b0dc Signed-off-by: Thomas RIENOESSL <thomas.rienoessl(a)bachmann.info> --- net/net.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/net.c b/net/net.c index 31cf306ae7..568ba74f78 100644 --- a/net/net.c +++ b/net/net.c @@ -657,6 +657,7 @@ restart: /* Invalidate the last protocol */ eth_set_last_protocol(BOOTP); debug_cond(DEBUG_INT_STATE, "--- net_loop Fail!\n"); + ret = -ENONET; goto done; case NETLOOP_CONTINUE: -- 2.19.1

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