November 2018 - U-Boot

[U-Boot] [PATCH 1/2] spi: pl022: Get rid of platdata ifdef's
by Jagan Teki 14 Nov '18

14 Nov '18

pl022 spi driver support both OF_CONTROL and PLATDATA and it's using #ifdef check for differentiating platdata vs of_control. So this patch simplify the code and drop the ifdefs Cc: Quentin Schulz <quentin.schulz(a)bootlin.com> Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- drivers/spi/pl022_spi.c | 48 ++++++++++++---------------- include/dm/platform_data/pl022_spi.h | 9 ------ 2 files changed, 20 insertions(+), 37 deletions(-) diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c index 86b71d2e21..dd27444a43 100644 --- a/drivers/spi/pl022_spi.c +++ b/drivers/spi/pl022_spi.c @@ -72,11 +72,7 @@ struct pl022_spi_slave { void *base; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct clk clk; -#else unsigned int freq; -#endif }; /* @@ -96,30 +92,13 @@ static int pl022_is_supported(struct pl022_spi_slave *ps) return 0; } -#if !CONFIG_IS_ENABLED(OF_PLATDATA) -static int pl022_spi_ofdata_to_platdata(struct udevice *bus) -{ - struct pl022_spi_pdata *plat = bus->platdata; - const void *fdt = gd->fdt_blob; - int node = dev_of_offset(bus); - - plat->addr = fdtdec_get_addr_size(fdt, node, "reg", &plat->size); - - return clk_get_by_index(bus, 0, &plat->clk); -} -#endif - static int pl022_spi_probe(struct udevice *bus) { struct pl022_spi_pdata *plat = dev_get_platdata(bus); struct pl022_spi_slave *ps = dev_get_priv(bus); ps->base = ioremap(plat->addr, plat->size); -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - ps->clk = plat->clk; -#else ps->freq = plat->freq; -#endif /* Check the PL022 version */ if (!pl022_is_supported(ps)) @@ -240,11 +219,7 @@ static int pl022_spi_set_speed(struct udevice *bus, uint speed) u16 scr = SSP_SCR_MIN, cr0 = 0, cpsr = SSP_CPSR_MIN, best_scr = scr, best_cpsr = cpsr; u32 min, max, best_freq = 0, tmp; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - u32 rate = clk_get_rate(&ps->clk); -#else u32 rate = ps->freq; -#endif bool found = false; max = spi_rate(rate, SSP_CPSR_MIN, SSP_SCR_MIN); @@ -316,6 +291,25 @@ static const struct dm_spi_ops pl022_spi_ops = { }; #if !CONFIG_IS_ENABLED(OF_PLATDATA) +static int pl022_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct pl022_spi_pdata *plat = bus->platdata; + struct udevice *clkdev; + const void *fdt = gd->fdt_blob; + int node = dev_of_offset(bus); + int ret; + + plat->addr = fdtdec_get_addr_size(fdt, node, "reg", &plat->size); + + ret = clk_get_by_index(bus, 0, &clkdev); + if (ret) + return ret; + + plat->freq = clk_get_rate(clkdev); + + return 0; +} + static const struct udevice_id pl022_spi_ids[] = { { .compatible = "arm,pl022-spi" }, { } @@ -327,11 +321,9 @@ U_BOOT_DRIVER(pl022_spi) = { .id = UCLASS_SPI, #if !CONFIG_IS_ENABLED(OF_PLATDATA) .of_match = pl022_spi_ids, -#endif - .ops = &pl022_spi_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) .ofdata_to_platdata = pl022_spi_ofdata_to_platdata, #endif + .ops = &pl022_spi_ops, .platdata_auto_alloc_size = sizeof(struct pl022_spi_pdata), .priv_auto_alloc_size = sizeof(struct pl022_spi_slave), .probe = pl022_spi_probe, diff --git a/include/dm/platform_data/pl022_spi.h b/include/dm/platform_data/pl022_spi.h index 77fe6da3cb..57d12ac912 100644 --- a/include/dm/platform_data/pl022_spi.h +++ b/include/dm/platform_data/pl022_spi.h @@ -10,19 +10,10 @@ #ifndef __PL022_SPI_H__ #define __PL022_SPI_H__ -#if !CONFIG_IS_ENABLED(OF_PLATDATA) -#include <clk.h> -#endif -#include <fdtdec.h> - struct pl022_spi_pdata { fdt_addr_t addr; fdt_size_t size; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct clk clk; -#else unsigned int freq; -#endif }; #endif -- 2.18.0.321.gffc6fa0e3

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[U-Boot] [PATCH u-boot v2] spi: Add Amlogic Meson SPI Flash Controller driver
by Neil Armstrong 14 Nov '18

14 Nov '18

The Amlogic Meson SoCs embeds a Flash oriented SPI Controller name SPIFC. This driver, ported from the Linux meson-spi-spifc driver, add support for this controller on the Amlogic Meson GX SoCs in U-Boot. [ported from linux version commit 2f58ea64bd8931bd7709732fe0a96e0bfb44a00b] Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> --- Changes since v1 : - removed the meson_spifc_claim_bus/meson_spifc_release_bus enabling disabling the clock and making register access with the clock disabled drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/meson_spifc.c | 335 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 344 insertions(+) create mode 100644 drivers/spi/meson_spifc.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 516188ea88..6085788481 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -116,6 +116,14 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config MESON_SPIFC + bool "Amlogic Meson SPI Flash Controller driver" + depends on ARCH_MESON + help + Enable the Amlogic Meson SPI Flash Controller SPIFC) driver. + This driver can be used to access the SPI NOR flash chips on + Amlogic Meson SoCs. + config MT7621_SPI bool "MediaTek MT7621 SPI driver" depends on ARCH_MT7620 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 7242ea7e40..67b42daf4e 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o +obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o diff --git a/drivers/spi/meson_spifc.c b/drivers/spi/meson_spifc.c new file mode 100644 index 0000000000..df516d3e4c --- /dev/null +++ b/drivers/spi/meson_spifc.c @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014 Beniamino Galvani <b.galvani(a)gmail.com> + * Copyright (C) 2018 BayLibre, SAS + * Author: Neil Armstrong <narmstrong(a)baylibre.com> + * + * Amlogic Meson SPI Flash Controller driver + */ + +#include <common.h> +#include <spi.h> +#include <clk.h> +#include <dm.h> +#include <regmap.h> +#include <errno.h> +#include <asm/io.h> +#include <linux/bitfield.h> + +/* register map */ +#define REG_CMD 0x00 +#define REG_ADDR 0x04 +#define REG_CTRL 0x08 +#define REG_CTRL1 0x0c +#define REG_STATUS 0x10 +#define REG_CTRL2 0x14 +#define REG_CLOCK 0x18 +#define REG_USER 0x1c +#define REG_USER1 0x20 +#define REG_USER2 0x24 +#define REG_USER3 0x28 +#define REG_USER4 0x2c +#define REG_SLAVE 0x30 +#define REG_SLAVE1 0x34 +#define REG_SLAVE2 0x38 +#define REG_SLAVE3 0x3c +#define REG_C0 0x40 +#define REG_B8 0x60 +#define REG_MAX 0x7c + +/* register fields */ +#define CMD_USER BIT(18) +#define CTRL_ENABLE_AHB BIT(17) +#define CLOCK_SOURCE BIT(31) +#define CLOCK_DIV_SHIFT 12 +#define CLOCK_DIV_MASK (0x3f << CLOCK_DIV_SHIFT) +#define CLOCK_CNT_HIGH_SHIFT 6 +#define CLOCK_CNT_HIGH_MASK (0x3f << CLOCK_CNT_HIGH_SHIFT) +#define CLOCK_CNT_LOW_SHIFT 0 +#define CLOCK_CNT_LOW_MASK (0x3f << CLOCK_CNT_LOW_SHIFT) +#define USER_DIN_EN_MS BIT(0) +#define USER_CMP_MODE BIT(2) +#define USER_CLK_NOT_INV BIT(7) +#define USER_UC_DOUT_SEL BIT(27) +#define USER_UC_DIN_SEL BIT(28) +#define USER_UC_MASK ((BIT(5) - 1) << 27) +#define USER1_BN_UC_DOUT_SHIFT 17 +#define USER1_BN_UC_DOUT_MASK (0xff << 16) +#define USER1_BN_UC_DIN_SHIFT 8 +#define USER1_BN_UC_DIN_MASK (0xff << 8) +#define USER4_CS_POL_HIGH BIT(23) +#define USER4_IDLE_CLK_HIGH BIT(29) +#define USER4_CS_ACT BIT(30) +#define SLAVE_TRST_DONE BIT(4) +#define SLAVE_OP_MODE BIT(30) +#define SLAVE_SW_RST BIT(31) + +#define SPIFC_BUFFER_SIZE 64 + +struct meson_spifc_priv { + struct regmap *regmap; + struct clk clk; +}; + +/** + * meson_spifc_wait_ready() - wait for the current operation to terminate + * @spifc: the Meson SPI device + * Return: 0 on success, a negative value on error + */ +static int meson_spifc_wait_ready(struct meson_spifc_priv *spifc) +{ + u32 data; + ulong tbase = get_timer(0); + + do { + regmap_read(spifc->regmap, REG_SLAVE, &data); + if (data & SLAVE_TRST_DONE) + return 0; + } while (get_timer(tbase) < 5 * CONFIG_SYS_HZ); + + return -ETIMEDOUT; +} + +/** + * meson_spifc_drain_buffer() - copy data from device buffer to memory + * @spifc: the Meson SPI device + * @buf: the destination buffer + * @len: number of bytes to copy + */ +static void meson_spifc_drain_buffer(struct meson_spifc_priv *spifc, + u8 *buf, int len) +{ + u32 data; + int i = 0; + + while (i < len) { + regmap_read(spifc->regmap, REG_C0 + i, &data); + + if (len - i >= 4) { + *((u32 *)buf) = data; + buf += 4; + } else { + memcpy(buf, &data, len - i); + break; + } + i += 4; + } +} + +/** + * meson_spifc_fill_buffer() - copy data from memory to device buffer + * @spifc: the Meson SPI device + * @buf: the source buffer + * @len: number of bytes to copy + */ +static void meson_spifc_fill_buffer(struct meson_spifc_priv *spifc, + const u8 *buf, int len) +{ + u32 data = 0; + int i = 0; + + while (i < len) { + if (len - i >= 4) + data = *(u32 *)buf; + else + memcpy(&data, buf, len - i); + + regmap_write(spifc->regmap, REG_C0 + i, data); + + buf += 4; + i += 4; + } +} + +/** + * meson_spifc_txrx() - transfer a chunk of data + * @spifc: the Meson SPI device + * @dout: data buffer for TX + * @din: data buffer for RX + * @offset: offset of the data to transfer + * @len: length of the data to transfer + * @last_xfer: whether this is the last transfer of the message + * @last_chunk: whether this is the last chunk of the transfer + * Return: 0 on success, a negative value on error + */ +static int meson_spifc_txrx(struct meson_spifc_priv *spifc, + const u8 *dout, u8 *din, int offset, + int len, bool last_xfer, bool last_chunk) +{ + bool keep_cs = true; + int ret; + + if (dout) + meson_spifc_fill_buffer(spifc, dout + offset, len); + + /* enable DOUT stage */ + regmap_update_bits(spifc->regmap, REG_USER, USER_UC_MASK, + USER_UC_DOUT_SEL); + regmap_write(spifc->regmap, REG_USER1, + (8 * len - 1) << USER1_BN_UC_DOUT_SHIFT); + + /* enable data input during DOUT */ + regmap_update_bits(spifc->regmap, REG_USER, USER_DIN_EN_MS, + USER_DIN_EN_MS); + + if (last_chunk && last_xfer) + keep_cs = false; + + regmap_update_bits(spifc->regmap, REG_USER4, USER4_CS_ACT, + keep_cs ? USER4_CS_ACT : 0); + + /* clear transition done bit */ + regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_TRST_DONE, 0); + /* start transfer */ + regmap_update_bits(spifc->regmap, REG_CMD, CMD_USER, CMD_USER); + + ret = meson_spifc_wait_ready(spifc); + + if (!ret && din) + meson_spifc_drain_buffer(spifc, din + offset, len); + + return ret; +} + +/** + * meson_spifc_xfer() - perform a single transfer + * @dev: the SPI controller device + * @bitlen: length of the transfer + * @dout: data buffer for TX + * @din: data buffer for RX + * @flags: transfer flags + * Return: 0 on success, a negative value on error + */ +static int meson_spifc_xfer(struct udevice *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct meson_spifc_priv *spifc = dev_get_priv(slave->parent); + int blen = bitlen / 8; + int len, done = 0, ret = 0; + + if (bitlen % 8) + return -EINVAL; + + debug("xfer len %d (%d) dout %p din %p\n", bitlen, blen, dout, din); + + regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB, 0); + + while (done < blen && !ret) { + len = min_t(int, blen - done, SPIFC_BUFFER_SIZE); + ret = meson_spifc_txrx(spifc, dout, din, done, len, + flags & SPI_XFER_END, + done + len >= blen); + done += len; + } + + regmap_update_bits(spifc->regmap, REG_CTRL, CTRL_ENABLE_AHB, + CTRL_ENABLE_AHB); + + return ret; +} + +/** + * meson_spifc_set_speed() - program the clock divider + * @dev: the SPI controller device + * @speed: desired speed in Hz + */ +static int meson_spifc_set_speed(struct udevice *dev, uint speed) +{ + struct meson_spifc_priv *spifc = dev_get_priv(dev); + unsigned long parent, value; + int n; + + parent = clk_get_rate(&spifc->clk); + n = max_t(int, parent / speed - 1, 1); + + debug("parent %lu, speed %u, n %d\n", parent, speed, n); + + value = (n << CLOCK_DIV_SHIFT) & CLOCK_DIV_MASK; + value |= (n << CLOCK_CNT_LOW_SHIFT) & CLOCK_CNT_LOW_MASK; + value |= (((n + 1) / 2 - 1) << CLOCK_CNT_HIGH_SHIFT) & + CLOCK_CNT_HIGH_MASK; + + regmap_write(spifc->regmap, REG_CLOCK, value); + + return 0; +} + +/** + * meson_spifc_set_mode() - setups the SPI bus mode + * @dev: the SPI controller device + * @mode: desired mode bitfield + * Return: 0 on success, -ENODEV on error + */ +static int meson_spifc_set_mode(struct udevice *dev, uint mode) +{ + struct meson_spifc_priv *spifc = dev_get_priv(dev); + + if (mode & (SPI_CPHA | SPI_RX_QUAD | SPI_RX_DUAL | + SPI_TX_QUAD | SPI_TX_DUAL)) + return -ENODEV; + + regmap_update_bits(spifc->regmap, REG_USER, USER_CLK_NOT_INV, + mode & SPI_CPOL ? USER_CLK_NOT_INV : 0); + + regmap_update_bits(spifc->regmap, REG_USER4, USER4_CS_POL_HIGH, + mode & SPI_CS_HIGH ? USER4_CS_POL_HIGH : 0); + + return 0; +} + +/** + * meson_spifc_hw_init() - reset and initialize the SPI controller + * @spifc: the Meson SPI device + */ +static void meson_spifc_hw_init(struct meson_spifc_priv *spifc) +{ + /* reset device */ + regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_SW_RST, + SLAVE_SW_RST); + /* disable compatible mode */ + regmap_update_bits(spifc->regmap, REG_USER, USER_CMP_MODE, 0); + /* set master mode */ + regmap_update_bits(spifc->regmap, REG_SLAVE, SLAVE_OP_MODE, 0); +} + +static const struct dm_spi_ops meson_spifc_ops = { + .xfer = meson_spifc_xfer, + .set_speed = meson_spifc_set_speed, + .set_mode = meson_spifc_set_mode, +}; + +static int meson_spifc_probe(struct udevice *dev) +{ + struct meson_spifc_priv *priv = dev_get_priv(dev); + int ret; + + ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap); + if (ret) + return ret; + + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret) + return ret; + + ret = clk_enable(&priv->clk); + if (ret) + return ret; + + meson_spifc_hw_init(priv); + + return 0; +} + +static const struct udevice_id meson_spifc_ids[] = { + { .compatible = "amlogic,meson-gxbb-spifc", }, + { } +}; + +U_BOOT_DRIVER(meson_spifc) = { + .name = "meson_spifc", + .id = UCLASS_SPI, + .of_match = meson_spifc_ids, + .ops = &meson_spifc_ops, + .probe = meson_spifc_probe, + .priv_auto_alloc_size = sizeof(struct meson_spifc_priv), +}; -- 2.19.1

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[U-Boot] [PATCH] driver/mtd: Add MICRON manufacturer id in spi framework
by Ashish Kumar 14 Nov '18

14 Nov '18

Signed-off-by: Suresh Gupta <suresh.gupta(a)nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur(a)nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> --- drivers/mtd/spi/sf_internal.h | 1 + drivers/mtd/spi/spi_flash.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 4f63cacc64..26f5c7c995 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -32,6 +32,7 @@ enum spi_nor_option_flags { /* CFI Manufacture ID's */ #define SPI_FLASH_CFI_MFR_SPANSION 0x01 #define SPI_FLASH_CFI_MFR_STMICRO 0x20 +#define SPI_FLASH_CFI_MFR_MICRON 0x2C #define SPI_FLASH_CFI_MFR_MACRONIX 0xc2 #define SPI_FLASH_CFI_MFR_SST 0xbf #define SPI_FLASH_CFI_MFR_WINBOND 0xef diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index c159124259..c73011748e 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -1096,6 +1096,7 @@ static int set_quad_mode(struct spi_flash *flash, #endif #ifdef CONFIG_SPI_FLASH_STMICRO case SPI_FLASH_CFI_MFR_STMICRO: + case SPI_FLASH_CFI_MFR_MICRON: debug("SF: QEB is volatile for %02x flash\n", JEDEC_MFR(info)); return 0; #endif @@ -1183,6 +1184,7 @@ int spi_flash_scan(struct spi_flash *flash) #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) /* NOR protection support for STmicro/Micron chips and similar */ if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_STMICRO || + JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MICRON || JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) { flash->flash_lock = stm_lock; flash->flash_unlock = stm_unlock; -- 2.17.1

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[U-Boot] USB: ci_udc fails to link in SPL when DM is active
by Sven Schwermer 14 Nov '18

14 Nov '18

Hi, I’m trying to build an SPL image for an iMX7 platform with the following options active: CONFIG_SPL=y CONFIG_SPL_USB_GADGET_SUPPORT=y CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_CMD_USB=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_SDP=y This leads to the SPL failing to link: LD spl/u-boot-spl drivers/built-in.o: In function `usb_gadget_register_driver': /root/u-boot/drivers/usb/gadget/ci_udc.c:1019: undefined reference to `usb_setup_ehci_gadget' scripts/Makefile.spl:364: recipe for target 'spl/u-boot-spl' failed make[1]: *** [spl/u-boot-spl] Error 1 Makefile:1539: recipe for target 'spl/u-boot-spl' failed make: *** [spl/u-boot-spl] Error 2 Is DM_USB in SPL with this driver not supported or should I have configured something else? I’m using the current mainline master branch. Thanks, Sven

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Re: [U-Boot] [PATCH 05/19] riscv: Add a SYSCON driver for Core Local Interruptor
by Rick Chen 14 Nov '18

14 Nov '18

<rick(a)andestech.com> 於 2018年11月14日週三下午3:35寫道： > > > Hi Lukas, > > > > On Tue, Nov 13, 2018 at 10:45 PM Auer, Lukas <lukas.auer(a)aisec.fraunhofer.de> > > wrote: > > > > > > Hi Bin, > > > > > > On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote: > > > > This adds U-Boot syscon driver for RISC-V Core Local Interruptor > > > > (CLINT). The CLINT block holds memory-mapped control and status > > > > registers associated with software and timer interrupts. > > > > > > > > 3 APIs are provided for U-Boot to implement Supervisor Binary > > > > Interface (SBI) as defined by the RISC-V privileged architecture > > > > spec v1.10. > > > > > > > > Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> > > > > --- > > > > > > Would it make sense to also abstract the functions provided by the > > > CLINT more? The reason why I am asking is because the CLINT is > > > (unfortunately) not specified as part of RISC-V. It is developing into > > > a de facto standard since other platforms are following SiFive's > > > implementation, but there is nothing that would prevent them from > > > implementing something else. > > > > > > > I think your observation is correct about CLINT. Rick, does Andes's RISC-V > > processor also follow SiFive's CLINT model? > > Hi Ben As I know the mtime is the same as SiFive, but ipi is different. They all implemented via IP block instead of CSR. And the following base definition seem to be fixed as some kind of HW implement. Maybe it can be more flexible. /* MSIP registers */ #define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4) /* Timer compare register */ #define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8) /* Timer register */ #define MTIME_REG(base) ((ulong)(base) + 0xbff8) Andes's ipi memory map plic0: interrupt-controller@e4000000 { compatible = "riscv,plic0"; #address-cells = <2>; #interrupt-cells = <2>; interrupt-controller; reg = <0x0 0xe4000000 0x0 0x2000000>; riscv,ndev=<71>; interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; }; Andes's mt memory map plmt0@e6000000 { compatible = "riscv,plmt0"; interrupts-extended = <&CPU0_intc 7>; reg = <0x0 0xe6000000 0x0 0x100000>; }; }; It is obviously to be found that their base is different here. Rick > > > Two immediate examples I can think of would be mtime and the IPI > > > implementation. Many SoC vendors will likely already have a suitable > > > timer IP block for mtime. I can imagine that they would choose to re- > > > use their memory map instead of following that of the CLINT. > > > For the IPI implementation there is already an alternative, the SBI. > > > If U-Boot should be able to run in supervisor mode, it would be > > > helpful to support both the SBI and the CLINT interface. > > > > > > > I am not sure I followed you here. This driver provides 3 APIs: > > riscv_send_ipi() is for IPI, and the other 2 are for mtime/mtimecmp. > > > > > So what we would need is some kind of API for the functionality > > > provided by the CLINT. For the multi-core support (I will try to send > > > out a series soon) I am re-using the IRQ uclass ID (it is only used in > > > arch code) to define a irq-uclass for RISC-V, which handles everything > > > with IPIs. The CLINT0 and SBI are then just different driver > > > implementing the uclass. > > > > > > This is just an idea right now, what do you think? > > > > > > > Regards, > > Bin

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[U-Boot] [PATCH] efi_loader: correct a function prototype of QueryCapsuleCapabilities()
by AKASHI Takahiro 14 Nov '18

14 Nov '18

See UEFI specification v2.7, section 8.5.3. Signed-off-by: AKASHI Takahiro <takahiro.akashi(a)linaro.org> --- include/efi_api.h | 4 ++-- lib/efi_loader/efi_runtime.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/efi_api.h b/include/efi_api.h index f0c23a28e3d6..10917bad43a7 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -242,8 +242,8 @@ struct efi_runtime_services { efi_status_t (EFIAPI *query_capsule_caps)( struct efi_capsule_header **capsule_header_array, efi_uintn_t capsule_count, - u64 maximum_capsule_size, - u32 reset_type); + u64 *maximum_capsule_size, + u32 *reset_type); efi_status_t (EFIAPI *query_variable_info)( u32 attributes, u64 *maximum_variable_storage_size, diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c index 2c8bbb4eba4d..ae750f5371ff 100644 --- a/lib/efi_loader/efi_runtime.c +++ b/lib/efi_loader/efi_runtime.c @@ -625,8 +625,8 @@ efi_status_t __efi_runtime EFIAPI efi_update_capsule( efi_status_t __efi_runtime EFIAPI efi_query_capsule_caps( struct efi_capsule_header **capsule_header_array, efi_uintn_t capsule_count, - u64 maximum_capsule_size, - u32 reset_type) + u64 *maximum_capsule_size, + u32 *reset_type) { return EFI_UNSUPPORTED; } -- 2.19.0

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[U-Boot] [PATCH] efi_loader: SetVirtualAddressMap() should return EFI_UNSUPPORTED
by AKASHI Takahiro 14 Nov '18

14 Nov '18

See UEFI specification 2.7, section 8.4. Signed-off-by: AKASHI Takahiro <takahiro.akashi(a)linaro.org> --- lib/efi_loader/efi_runtime.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c index abcf03c5a42e..2c8bbb4eba4d 100644 --- a/lib/efi_loader/efi_runtime.c +++ b/lib/efi_loader/efi_runtime.c @@ -284,7 +284,7 @@ static const struct efi_runtime_detach_list_struct efi_runtime_detach_list[] = { }, { /* invalidate_*cache_all are gone */ .ptr = &efi_runtime_services.set_virtual_address_map, - .patchto = &efi_invalid_parameter, + .patchto = &efi_unimplemented, }, { /* RTC accessors are gone */ .ptr = &efi_runtime_services.get_time, -- 2.19.0

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[U-Boot] error: Invalid register name for 'gd'
by Manoj Tiwary 14 Nov '18

14 Nov '18

Hi all, I am trying to cross-compile the U-boot on my Ubuntu pc cloned from git clone git://git.denx.de/u-boot.git with gcc-linaro-6.2.1-2016.11-x86_64_arm-linux-gnueabi compiler. But while compiling I am getting following error: ./arch/arm/include/asm/global_data.h:110:58: error: invalid register name for 'gd' #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("x18") ^ cmd/bdinfo.c:14:1: note: in expansion of macro 'DECLARE_GLOBAL_DATA_PTR' DECLARE_GLOBAL_DATA_PTR; ^~~~~~~~~~~~~~~~~~~~~~~ scripts/Makefile.build:278: recipe for target 'cmd/bdinfo.o' failed make[1]: *** [cmd/bdinfo.o] Error 1 Makefile:1408: recipe for target 'cmd' failed make: *** [cmd] Error 2 Suggest me a way to resolve this error. Thanks & Regards, Manoj

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[U-Boot] [PATCH 1/5] ARM: dts: rmobile: Add eMMC DS pinmux
by Marek Vasut 14 Nov '18

14 Nov '18

Add pinmux entry for the eMMC DS line, as it is connected on these boards. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- arch/arm/dts/salvator-common.dtsi | 4 ++-- arch/arm/dts/ulcb.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/salvator-common.dtsi b/arch/arm/dts/salvator-common.dtsi index 514c57b2c8..826a02c333 100644 --- a/arch/arm/dts/salvator-common.dtsi +++ b/arch/arm/dts/salvator-common.dtsi @@ -480,13 +480,13 @@ }; sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; }; sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; }; diff --git a/arch/arm/dts/ulcb.dtsi b/arch/arm/dts/ulcb.dtsi index 4b00db8970..b61e2656d5 100644 --- a/arch/arm/dts/ulcb.dtsi +++ b/arch/arm/dts/ulcb.dtsi @@ -308,13 +308,13 @@ }; sdhi2_pins: sd2 { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; }; sdhi2_pins_uhs: sd2_uhs { - groups = "sdhi2_data8", "sdhi2_ctrl"; + groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; function = "sdhi2"; power-source = <1800>; }; -- 2.18.0

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[U-Boot] [PATCH] clk: renesas: Allow reconfiguring SDHI clock on Gen3
by Marek Vasut 14 Nov '18

14 Nov '18

The SDHI clock must be configured differently for HS200/HS400/SDR104 modes. Add support for reconfiguring the SDHI clock settings into the clock driver. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- drivers/clk/renesas/clk-rcar-gen3.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 99698b1f46..0529fc8763 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -107,7 +107,7 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk, return renesas_clk_get_parent(clk, info, parent); } -static int gen3_clk_setup_sdif_div(struct clk *clk) +static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate) { struct gen3_clk_priv *priv = dev_get_priv(clk->dev); struct cpg_mssr_info *info = priv->info; @@ -133,7 +133,7 @@ static int gen3_clk_setup_sdif_div(struct clk *clk) debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset); - writel(1, priv->base + core->offset); + writel((rate == 400000000) ? 0x4 : 0x1, priv->base + core->offset); return 0; } @@ -141,10 +141,6 @@ static int gen3_clk_setup_sdif_div(struct clk *clk) static int gen3_clk_enable(struct clk *clk) { struct gen3_clk_priv *priv = dev_get_priv(clk->dev); - int ret = gen3_clk_setup_sdif_div(clk); - - if (ret) - return ret; return renesas_clk_endisable(clk, priv->base, true); } @@ -328,7 +324,7 @@ static ulong gen3_clk_get_rate(struct clk *clk) static ulong gen3_clk_set_rate(struct clk *clk, ulong rate) { /* Force correct SD-IF divider configuration if applicable */ - gen3_clk_setup_sdif_div(clk); + gen3_clk_setup_sdif_div(clk, rate); return gen3_clk_get_rate64(clk); } -- 2.18.0

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