November 2018 - U-Boot

[U-Boot] [PATCH] cmd: ubi: Make ubi_detach() static
by Stefan Roese 22 Nov '18

22 Nov '18

Its only called from this file, so make it static. While at it, remove some occurances of multiple blank lines as well. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Boris Brezillon <boris.brezillon(a)bootlin.com> Cc: Miquel Raynal <miquel.raynal(a)bootlin.com> Cc: Jagan Teki <jagan(a)openedev.com> --- cmd/ubi.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/cmd/ubi.c b/cmd/ubi.c index 2b74a98144..a12ac703eb 100644 --- a/cmd/ubi.c +++ b/cmd/ubi.c @@ -101,7 +101,6 @@ static int ubi_check(char *name) return 1; } - static int verify_mkvol_req(const struct ubi_device *ubi, const struct ubi_mkvol_req *req) { @@ -415,7 +414,7 @@ static int ubi_dev_scan(struct mtd_info *info, const char *vid_header_offset) return 0; } -int ubi_detach(void) +static int ubi_detach(void) { #ifdef CONFIG_CMD_UBIFS /* @@ -473,7 +472,6 @@ static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (argc < 2) return CMD_RET_USAGE; - if (strcmp(argv[1], "detach") == 0) { if (argc < 2) return CMD_RET_USAGE; @@ -481,7 +479,6 @@ static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return ubi_detach(); } - if (strcmp(argv[1], "part") == 0) { const char *vid_header_offset = NULL; -- 2.19.1

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[U-Boot] [PATCH 0/3] Add raw read support and use it in pxa3xx NAND driver
by Miquel Raynal 22 Nov '18

22 Nov '18

When using 2kiB-pages NAND chips requesting an 8-bit strength ECC, the layout used is a bit particular and it happens that the ECC engine tries to correct uncorrectable errors on empty pages, producing bitflips. To avoid such situation, raw read support is added to the pxa3xx_nand driver, and then used to re-read the page (in raw mode) upon uncorrectable error detection to know if there is an actual ECC mismatch or if the page is empty. This way we avoid seeing the bitflips created by the hardware ECC engine. Once this done, we can revert the hack that was done in the driver to enlarge the last spare area for this layout to 64B instead of 32B, breaking U-Boot/Linux compatibility and preventing the BootROM to boot from NAND. Thanks, Miquèl Miquel Raynal (3): mtd: nand: pxa3xx: add raw read support mtd: nand: pxa3xx: re-read a page in raw mode on uncorrectable error mtd: rawnand: pxa3xx: fix 2kiB pages with 8b strength chips layout drivers/mtd/nand/raw/pxa3xx_nand.c | 143 +++++++++++++++++++++++++---- 1 file changed, 124 insertions(+), 19 deletions(-) -- 2.17.1

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[U-Boot] armada_38x can't detect USB device
by 吳冠勳 22 Nov '18

22 Nov '18

Hi all, I've tried the first time booting a self compiled u-boot on armada_38x:CUSTOMER_BOARD_0. Here is the Boot messages: Board: A38x-Customer-Board-0 SoC: MV88F6820 Rev B0 running 2 CPUs CPU: ARM Cortex A9 MPCore (Rev 1) LE CPU 0 CPU @ 1600 [MHz] L2 @ 800 [MHz] TClock @ 200 [MHz] DDR3 @ 800 [MHz] DDR3 32 Bit Width,FastPath Memory Access, DLB Enabled, ECC Disabled RAM Configuration: Bank #0: 00000000 1 GiB Bank #1: 00000000 0 Bytes MMC: mv_sdh: 0 *** Warning - bad CRC, using default environment PCI-e 0: Detected No Link. maxUsbport=1 USB2.0 0: Host Mode USB3.0 0: Host Mode USB3.0 1: Host Mode Map: Code: 0x3fed6000:0x3ff963b0 BSS: 0x3ffef488 Stack: 0x3f4b5f20 Heap: 0x3f4b6000:0x3fed6000 U-Boot Environment: 0x00100000:0x00120000 Board configuration detected: Net: | port | Interface | PHY address | |--------|-----------|--------------| | egiga0 | RGMII | 0x00 | | egiga1 | SGMII | 0x01 | egiga0 [PRIME], egiga1 Hit any key to stop autoboot: 0 Marvell>> usb start (Re)start USB... USB0: usbActive = 0, usbType = 2, usb3HostNum = 2, usb2HostNum = 1 Port (usbActive) : 0 Interface (usbType = 2) : USB EHCI 1.00 scanning bus 0 for devices... New Device 0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length 0x40 ==== get_descriptor:18 ==== set address 1 usb_control_msg: request: 0x5, requesttype: 0x0, value 0x1 index 0x0 length 0x0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length 0x12 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 0x9 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x200 index 0x0 length 0x19 get_conf_no 0 Result 25, wLength 25 if 0, ep 0 ##EP epmaxpacketin[1] = 8 set configuration 1 usb_control_msg: request: 0x9, requesttype: 0x0, value 0x1 index 0x0 length 0x0 new device strings: Mfr=1, Product=2, SerialNumber=0 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x300 index 0x0 length 0xFF USB device number 1 default language ID 0x1 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x301 index 0x1 length 0xFF usb_control_msg: request: 0x6, requesttype: 0x80, value 0x302 index 0x1 length 0xFF Manufacturer u-boot Product EHCI Host Controller SerialNumber USB hub found usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2900 index 0x0 length 0x4 usb_control_msg: request: 0x6, requesttype: 0xA0, value 0x2900 index 0x0 length 0x8 1 ports detected individual port power switching standalone hub global over-current protection Single TT TT requires at most 8 FS bit times (666 ns) power on to power good time: 20ms hub controller current requirement: 0mA port 1 is removable usb_control_msg: request: 0x0, requesttype: 0xA0, value 0x0 index 0x0 length 0x4 get_hub_status returned status 1, change 8101 local power source is lost (inactive) no over-current condition exists enabling power on all ports usb_control_msg: request: 0x3, requesttype: 0x23, value 0x8 index 0x1 length 0x0 port 1 returns 0 pgood_delay=20ms ==== Power On ==== devnum=1 poweron: query_delay=100 connect_timeout=1100 usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4 === Port Status === Port 1 Status 101 Change 1 devnum=1 port=1: USB dev found usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4 ##(check port connect)## portstatus 101, change 1, 12 Mb/s usb_control_msg: request: 0x1, requesttype: 0x23, value 0x10 index 0x1 length 0x0 hub_port_reset: resetting port 1... usb_control_msg: request: 0x3, requesttype: 0x23, value 0x4 index 0x1 length 0x0 usb_control_msg: request: 0x0, requesttype: 0xA3, value 0x0 index 0x1 length 0x4 portstatus 103, change 10, 12 Mb/s STAT_C_CONNECTION = 0 STAT_CONNECTION = 1 USB_PORT_STAT_ENABLE 1 usb_control_msg: request: 0x1, requesttype: 0x23, value 0x14 index 0x1 length 0x0 New Device 1 usb_control_msg: request: 0x6, requesttype: 0x80, value 0x100 index 0x0 length 0x40 EHCI timed out on TD - token=0x80008c80 EHCI timed out on TD - token=0x80a88 ==== get_descriptor:-1 ==== usb_new_device: usb_get_descriptor() failed Freeing device node: 1 hub: disabling port 1 usb_control_msg: request: 0x1, requesttype: 0x23, value 0x1 index 0x1 length 0x0 1 USB Device(s) found scan end scanning usb for storage devices... 0 Storage Device(s) found scanning usb for ethernet devices... 0 Ethernet Device(s) found As I plug in USB2.0 storage device,it detected the speed is 12 Mb/s. What causes this happen? Do I have to change something in the default board configuration to successfully use USB on the armada38x? Any help would be appreciated, Pete

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[U-Boot] [PATCH v3] riscv: cache: Implement i/dcache [status, enable, disable]
by Andes 22 Nov '18

22 Nov '18

From: Rick Chen <rick(a)andestech.com> AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick(a)andestech.com> Cc: Greentime Hu <greentime(a)andestech.com> --- Changes in v3 Bin suggested: 1. Move RISCV_NDS to arch/riscv/cpu/ax25/Kconfig Lukas suggested: 1. Add CONFIG_SYS_ICACHE_OFF in i/dcache_disable() 2. Remove duplicate declaration in arch/riscv/include/asm/cache.h 3. Add s space after "volatile" and ":::" to match the style. 4. Implement flush_dcache_range() and flush_cache() in arch/riscv/lib/cache.c arch/riscv/Kconfig | 6 +++ arch/riscv/cpu/ax25/Kconfig | 7 ++++ arch/riscv/cpu/ax25/Makefile | 1 + arch/riscv/cpu/ax25/cache.c | 95 ++++++++++++++++++++++++++++++++++++++++++ arch/riscv/cpu/ax25/cpu.c | 4 ++ arch/riscv/cpu/qemu/cpu.c | 2 +- arch/riscv/cpu/start.S | 6 +++ arch/riscv/include/asm/cache.h | 3 ++ arch/riscv/lib/cache.c | 32 ++++++++++---- 9 files changed, 146 insertions(+), 10 deletions(-) create mode 100644 arch/riscv/cpu/ax25/Kconfig create mode 100644 arch/riscv/cpu/ax25/cache.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 371921b..6a86e9c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -16,9 +16,15 @@ config TARGET_QEMU_VIRT endchoice +# board-specific options below source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" +# platform-specific options below +source "arch/riscv/cpu/ax25/Kconfig" + +# architecture-specific options below + choice prompt "Base ISA" default ARCH_RV32I diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig new file mode 100644 index 0000000..6c7022f --- /dev/null +++ b/arch/riscv/cpu/ax25/Kconfig @@ -0,0 +1,7 @@ +config RISCV_NDS + bool "AndeStar V5 ISA support" + default n + help + Say Y here if you plan to run U-Boot on AndeStar v5 + platforms and use some specific features which are + provided by Andes Technology AndeStar V5 Families. diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/ax25/Makefile index 2ab0342..318bacc 100644 --- a/arch/riscv/cpu/ax25/Makefile +++ b/arch/riscv/cpu/ax25/Makefile @@ -4,3 +4,4 @@ # Rick Chen, Andes Technology Corporation <rick(a)andestech.com> obj-y := cpu.o +obj-y += cache.o diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c new file mode 100644 index 0000000..6600ac2 --- /dev/null +++ b/arch/riscv/cpu/ax25/cache.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation <rick(a)andestech.com> + */ + +#include <common.h> + +void icache_enable(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF +#ifdef CONFIG_RISCV_NDS + asm volatile ( + "csrr t1, mcache_ctl\n\t" + "ori t0, t1, 0x1\n\t" + "csrw mcache_ctl, t0\n\t" + ); +#endif +#endif +} + +void icache_disable(void) +{ +#ifndef CONFIG_SYS_ICACHE_OFF +#ifdef CONFIG_RISCV_NDS + asm volatile ( + "fence.i\n\t" + "csrr t1, mcache_ctl\n\t" + "andi t0, t1, ~0x1\n\t" + "csrw mcache_ctl, t0\n\t" + ); +#endif +#endif +} + +void dcache_enable(void) +{ +#ifndef CONFIG_SYS_DCACHE_OFF +#ifdef CONFIG_RISCV_NDS + asm volatile ( + "csrr t1, mcache_ctl\n\t" + "ori t0, t1, 0x2\n\t" + "csrw mcache_ctl, t0\n\t" + ); +#endif +#endif +} + +void dcache_disable(void) +{ +#ifndef CONFIG_SYS_DCACHE_OFF +#ifdef CONFIG_RISCV_NDS + asm volatile ( + "fence\n\t" + "csrr t1, mcache_ctl\n\t" + "andi t0, t1, ~0x2\n\t" + "csrw mcache_ctl, t0\n\t" + ); +#endif +#endif +} + +int icache_status(void) +{ + int ret = 0; + +#ifdef CONFIG_RISCV_NDS + asm volatile ( + "csrr t1, mcache_ctl\n\t" + "andi %0, t1, 0x01\n\t" + : "=r" (ret) + : + : "memory" + ); +#endif + + return ret; +} + +int dcache_status(void) +{ + int ret = 0; + +#ifdef CONFIG_RISCV_NDS + asm volatile ( + "csrr t1, mcache_ctl\n\t" + "andi %0, t1, 0x02\n\t" + : "=r" (ret) + : + : "memory" + ); +#endif + + return ret; +} diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c index fddcc15..76689b2 100644 --- a/arch/riscv/cpu/ax25/cpu.c +++ b/arch/riscv/cpu/ax25/cpu.c @@ -6,6 +6,7 @@ /* CPU specific code */ #include <common.h> +#include <asm/cache.h> /* * cleanup_before_linux() is called just before we call linux @@ -18,6 +19,9 @@ int cleanup_before_linux(void) disable_interrupts(); /* turn off I/D-cache */ + cache_flush(); + icache_disable(); + dcache_disable(); return 0; } diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/qemu/cpu.c index 6c7a327..25d97d0 100644 --- a/arch/riscv/cpu/qemu/cpu.c +++ b/arch/riscv/cpu/qemu/cpu.c @@ -15,7 +15,7 @@ int cleanup_before_linux(void) { disable_interrupts(); - /* turn off I/D-cache */ + cache_flush(); return 0; } diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 331a534..15e1b81 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -46,6 +46,10 @@ _start: /* mask all interrupts */ csrw mie, zero + /* Enable cache */ + jal icache_enable + jal dcache_enable + /* * Set stackpointer in internal/ex RAM to call board_init_f */ @@ -181,6 +185,8 @@ clbss_l: * initialization, now running from RAM. */ call_board_init_r: + jal invalidate_icache_all + jal flush_dcache_all la t0, board_init_r mv t4, t0 /* offset of board_init_r() */ add t4, t4, t6 /* real address of board_init_r() */ diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index ca83dd6..ec8fe20 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -7,6 +7,9 @@ #ifndef _ASM_RISCV_CACHE_H #define _ASM_RISCV_CACHE_H +/* cache */ +void cache_flush(void); + /* * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. * We use that value for aligning DMA buffers unless the board config has diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index d642a38..ae5c607 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -6,8 +6,18 @@ #include <common.h> +void invalidate_icache_all(void) +{ + asm volatile ("fence.i" ::: "memory"); +} + +void flush_dcache_all(void) +{ + asm volatile ("fence" :::"memory"); +} void flush_dcache_range(unsigned long start, unsigned long end) { + flush_dcache_all(); } void invalidate_icache_range(unsigned long start, unsigned long end) @@ -19,41 +29,45 @@ void invalidate_icache_range(unsigned long start, unsigned long end) invalidate_icache_all(); } -void invalidate_icache_all(void) +void invalidate_dcache_range(unsigned long start, unsigned long end) { - asm volatile ("fence.i" ::: "memory"); + flush_dcache_all(); } -void invalidate_dcache_range(unsigned long start, unsigned long end) +void cache_flush(void) { + invalidate_icache_all(); + flush_dcache_all(); } void flush_cache(unsigned long addr, unsigned long size) { + invalidate_icache_all(); + flush_dcache_all(); } -void icache_enable(void) +__weak void icache_enable(void) { } -void icache_disable(void) +__weak void icache_disable(void) { } -int icache_status(void) +__weak int icache_status(void) { return 0; } -void dcache_enable(void) +__weak void dcache_enable(void) { } -void dcache_disable(void) +__weak void dcache_disable(void) { } -int dcache_status(void) +__weak int dcache_status(void) { return 0; } -- 2.7.4

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[U-Boot] use of dm_spi_flash
by C Michael Sundius 21 Nov '18

21 Nov '18

I am a bit confused about the use of the driver model when it comes to spi flash. It seems from the description in the Kconfig help that both the legacy and dm interfaces for spi flash can coexist, thus you can use both the "sf xxxx" commands as well as use the driver model interface for the likes of flash.. is that correct? or is it one or the other? 2ndly, I've been trying to build u-boot for an TI am335x_evm (well our board is designed largely the same as that) attached to the spi flash is is25lp512 nor flash. when I try to configure both the CONFIG_SPI_FLASH and the CONFIG_DM_SPI + CONFIG_DM_SPI_FLASH i get lots of build errors. I have a version of u-boot from 2017-09, I'll update to the newer version next but just wondering if anyone has done this and knows which config options to set/not set thanks mike

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[U-Boot] [PATCH 0/3] ARM: liteboard: move towards driver model and device-tree boot
by Marcin Niestroj 21 Nov '18

21 Nov '18

Hi, This patch moves board support code to use driver model where possible and device-tree bot. As part of that we import DTS files from Linux v4.19. One minor patch here is to use random ethaddr in order to make network usable on that board by default. Marcin Niestroj (3): ARM: dts: imx6ul-lite*: add DTS files for liteSOM and liteboard ARM: liteboard: move towards driver model and device-tree boot ARM: liteboard: use random ethaddr arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx6ul-liteboard.dts | 151 ++++++++++++++++++++++++++++++ arch/arm/dts/imx6ul-litesom.dtsi | 82 ++++++++++++++++ board/grinn/liteboard/board.c | 36 ------- configs/liteboard_defconfig | 12 ++- 5 files changed, 246 insertions(+), 38 deletions(-) create mode 100644 arch/arm/dts/imx6ul-liteboard.dts create mode 100644 arch/arm/dts/imx6ul-litesom.dtsi -- 2.19.1

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Re: [U-Boot] uboot to read kernel and rootfs from a bootfs.
by Wolfgang Denk 21 Nov '18

21 Nov '18

Dear Michael, In message <CAGVhguGjKWY+qaHmfCRSZfSRSsGG8Gep2BV6-gKx6zDCoU0obg(a)mail.gmail.com> you wrote: > > as I asked in my email... since I'm using spi-flash for the fs access, it > seems I'll need to use the DM_SPI_FLASH support. For new code, yes. > I'm using the 2017.09 version of u-boot with openembedded/poky and the 4.4 > kernel > > would it be worth me using a newer version of u-boot? would that give me > better support of my spi-flash? You should always go with top-of-tree from the respective mainline repositoruy for any new developments. > my board is basically an am335x_evm with an is25lp512 nor spi-flash instead > of emmc. SPI NOR is used on a zillion of boards and should work pretty well. > when I tried to turn on the dm flash support it didn't compile. just > wondering if that is supported more thouroughly in > newer versions of u-boot..... sorry, I don't know. Again, here the ML is a much better reource to ask such things. In any case you should not use JFFS2 any more; it is really, really dead code. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Der Dativ ist dem Genitiv sein Tod.

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[U-Boot] [PATCH] arm64: zynqmp: Reflect emmc controller ID in model in DT
by Michal Simek 21 Nov '18

21 Nov '18

Make sense to add controller ID to model name to have it visible through the logs to know which controller is used by which configuration. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynqmp-mini-emmc0.dts | 2 +- arch/arm/dts/zynqmp-mini-emmc1.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts index 24dd1ab9df02..13d0813ed41d 100644 --- a/arch/arm/dts/zynqmp-mini-emmc0.dts +++ b/arch/arm/dts/zynqmp-mini-emmc0.dts @@ -10,7 +10,7 @@ /dts-v1/; / { - model = "ZynqMP MINI EMMC"; + model = "ZynqMP MINI EMMC0"; compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts index 530ab3cdc22e..0538da468b3e 100644 --- a/arch/arm/dts/zynqmp-mini-emmc1.dts +++ b/arch/arm/dts/zynqmp-mini-emmc1.dts @@ -10,7 +10,7 @@ /dts-v1/; / { - model = "ZynqMP MINI EMMC"; + model = "ZynqMP MINI EMMC1"; compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; -- 1.9.1

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[U-Boot] [PATCH] arm64: zynqmp: Disable bootelf and fdt commands for mini configurations
by Michal Simek 21 Nov '18

21 Nov '18

There is no reason to enable these commands for mini configurations. It saves some space: aarch64: (for 2/2 boards) all -19076.0 bss -1048.0 data -1720.0 rodata -3840.0 text -12468.0 xilinx_zynqmp_mini_emmc1: all -19076 bss -1048 data -1720 rodata -3840 text -12468 xilinx_zynqmp_mini_emmc0: all -19076 bss -1048 data -1720 rodata -3840 text -12468 Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- configs/xilinx_zynqmp_mini_emmc0_defconfig | 2 ++ configs/xilinx_zynqmp_mini_emmc1_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index 917637ddacd0..71c320cc3e23 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -20,6 +20,8 @@ CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set # CONFIG_CMD_GO is not set # CONFIG_CMD_RUN is not set # CONFIG_CMD_IMI is not set diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index 1ffa528d6d54..3298341d190d 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -20,6 +20,8 @@ CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_BOOTM is not set # CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set # CONFIG_CMD_GO is not set # CONFIG_CMD_RUN is not set # CONFIG_CMD_IMI is not set -- 1.9.1

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[U-Boot] [PATCH 1/3] ARM: zynq: cse: Disable distro bootcommands
by Michal Simek 21 Nov '18

21 Nov '18

cse targets shouldn't never have distro default enabled because these targets are not designed for booting images. It was enabled by: "configs: Re-sync with CONFIG_DISTRO_DEFAULTS" (sha1: fa2c14676c7c6f3115dd4d9b2a4cc3b35c3ad2a2) Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- configs/zynq_cse_qspi_defconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index 2e1e34d0aec7..e271cca690fd 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -11,15 +11,15 @@ CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SYS_MALLOC_LEN=0x1000 # CONFIG_CMD_ZYNQ is not set CONFIG_DEBUG_UART=y -CONFIG_DISTRO_DEFAULTS=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set -CONFIG_BOOTDELAY=-1 -# CONFIG_USE_BOOTCOMMAND is not set # CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_ARCH_EARLY_INIT_R is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_SPI_LOAD=y +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set CONFIG_SYS_PROMPT="Zynq> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set -- 1.9.1

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