November 2018 - U-Boot

[U-Boot] [PATCH] rockchp: rock_defconfig: remove TPL_TINY_MEMSET
by Kever Yang 30 Nov '18

30 Nov '18

The rk3188 rock board does not need TPL, remove relate MACRO. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- configs/rock_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/rock_defconfig b/configs/rock_defconfig index 28dcd5bccc..0c41ac9f20 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -56,6 +56,5 @@ CONFIG_ROCKCHIP_TIMER=y CONFIG_USB=y CONFIG_ROCKCHIP_USB2_PHY=y CONFIG_SPL_TINY_MEMSET=y -CONFIG_TPL_TINY_MEMSET=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y -- 2.18.0

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[U-Boot] [PATCH] rockchip: rk3399-puma: reduce sd card max-frequency to 40MHz
by Philipp Tomsich 30 Nov '18

30 Nov '18

Some SanDisk Ultra cards trigger intermittent errors on detection resulting in an -EOPNOTSUPP, when running at 50MHz. Waveform analysis suggest that the level shifters that are used on the RK3399-Q7 module (for voltage translation between the on-module voltages and the 3.3V required on the card-edge) don't handle clock rates at or above 48MHz properly. This change reduces the maximum frequency on the external SD-interface to 40MHz (for a safety margin of 20%). Reported-by: Jakob Unterwurzacher <jakob.unterwurzacher(a)theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> Tested-by: Christoph Muellner <christoph.muellner(a)theobroma-systems.com> --- arch/arm/dts/rk3399-puma.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index 261df42..ba9bb4c 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -505,7 +505,7 @@ &sdmmc { u-boot,dm-pre-reloc; clock-frequency = <150000000>; - clock-freq-min-max = <100000 150000000>; + max-frequency = <40000000>; supports-sd; bus-width = <4>; cap-mmc-highspeed; -- 2.1.4

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[U-Boot] [PATCH v2] efi_loader: Reserve unaccessible memory
by Alexander Graf 30 Nov '18

30 Nov '18

On some systems, not all RAM may be usable within U-Boot. Maybe the memory maps are incomplete, maybe it's used as workaround for broken DMA. But whatever the reason may be, a platform can say that it does not wish to have its RAM accessed above a certain address by defining board_get_usable_ram_top(). In the efi_loader world, we ignored that hint, mostly because very few boards actually have real restrictions around this. So let's honor the board's wish to not access high addresses during boot time. The best way to do so is by indicating the respective pages as "allocated by firmware". That way, Operating Systems will still use the pages after boot, but before boot no allocation will use them. Reported-by: Baruch Siach <baruch(a)tkos.co.il> Signed-off-by: Alexander Graf <agraf(a)suse.de> --- v1 -> v2: - Reserve banks that start above ram_top - Improve inline comments - Fix 32bit target with ram_top = 0 (>=4G) --- include/common.h | 11 +++++++++++ lib/efi_loader/efi_memory.c | 32 +++++++++++++++++++++++++++++--- 2 files changed, 40 insertions(+), 3 deletions(-) diff --git a/include/common.h b/include/common.h index 3f69943887..8f295c2f30 100644 --- a/include/common.h +++ b/include/common.h @@ -106,6 +106,17 @@ int mdm_init(void); void board_show_dram(phys_size_t size); /** + * Get the uppermost pointer that is valid to access + * + * Some systems may not map all of their address space. This function allows + * boards to indicate what their highest support pointer value is for DRAM + * access. + * + * @param total_size Size of U-Boot (unused?) + */ +ulong board_get_usable_ram_top(ulong total_size); + +/** * arch_fixup_fdt() - Write arch-specific information to fdt * * Defined in arch/$(ARCH)/lib/bootm-fdt.c diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index f225a9028c..3392af59a1 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -551,8 +551,13 @@ efi_status_t efi_get_memory_map(efi_uintn_t *memory_map_size, __weak void efi_add_known_memory(void) { + u64 ram_top = board_get_usable_ram_top(0) & ~EFI_PAGE_MASK; int i; + /* Fix for 32bit targets with ram_top at 4G */ + if (!ram_top) + ram_top = U32_MAX; + /* Add RAM */ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { u64 ram_end, ram_start, pages; @@ -564,11 +569,32 @@ __weak void efi_add_known_memory(void) ram_end &= ~EFI_PAGE_MASK; ram_start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK; - if (ram_end > ram_start) { - pages = (ram_end - ram_start) >> EFI_PAGE_SHIFT; + if (ram_end <= ram_start) { + /* Invalid mapping, keep going. */ + continue; + } + + pages = (ram_end - ram_start) >> EFI_PAGE_SHIFT; + efi_add_memory_map(ram_start, pages, + EFI_CONVENTIONAL_MEMORY, false); + + /* + * Boards may indicate to the U-Boot memory core that they + * can not support memory above ram_top. Let's honor this + * in the efi_loader subsystem too by declaring any memory + * above ram_top as "already occupied by firmware". + */ + if (ram_top < ram_start) { + /* ram_top is before this region, reserve all */ efi_add_memory_map(ram_start, pages, - EFI_CONVENTIONAL_MEMORY, false); + EFI_BOOT_SERVICES_DATA, true); + } else if ((ram_top >= ram_start) && (ram_top < ram_end)) { + /* ram_top is inside this region, reserve parts */ + pages = (ram_end - ram_top) >> EFI_PAGE_SHIFT; + + efi_add_memory_map(ram_top, pages, + EFI_BOOT_SERVICES_DATA, true); } } } -- 2.12.3

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[U-Boot] [PATCH] rockchip: rk3399: Initialize CPU B clock.
by Christoph Muellner 30 Nov '18

30 Nov '18

This patch sets the PLL of CPU cluster B (BPLL) to 600 MHz. This decreases the boot time of Linux 4.19 by about 8%. The 600 MHz are inspired by the 600 MHz used for LPLL initialization (came in with commit 9f636a249c1). Tested on RK3399-Q7 on Haikou base board. Signed-off-by: Christoph Muellner <christoph.muellner(a)theobroma-systems.com> --- arch/arm/include/asm/arch-rockchip/cru_rk3399.h | 22 +++++-- drivers/clk/rockchip/clk_rk3399.c | 79 ++++++++++++++++++++++--- 2 files changed, 88 insertions(+), 13 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h index b18de9f7c2e..15eeb9c4407 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h @@ -69,16 +69,21 @@ check_member(rk3399_cru, sdio1_con[1], 0x594); #define MHz 1000000 #define KHz 1000 #define OSC_HZ (24*MHz) -#define APLL_HZ (600*MHz) +#define LPLL_HZ (600*MHz) +#define BPLL_HZ (600*MHz) #define GPLL_HZ (594*MHz) #define CPLL_HZ (384*MHz) #define PPLL_HZ (676*MHz) #define PMU_PCLK_HZ (48*MHz) -#define ACLKM_CORE_HZ (300*MHz) -#define ATCLK_CORE_HZ (300*MHz) -#define PCLK_DBG_HZ (100*MHz) +#define ACLKM_CORE_L_HZ (300*MHz) +#define ATCLK_CORE_L_HZ (300*MHz) +#define PCLK_DBG_L_HZ (100*MHz) + +#define ACLKM_CORE_B_HZ (300*MHz) +#define ATCLK_CORE_B_HZ (300*MHz) +#define PCLK_DBG_B_HZ (100*MHz) #define PERIHP_ACLK_HZ (148500*KHz) #define PERIHP_HCLK_HZ (148500*KHz) @@ -98,4 +103,13 @@ enum apll_l_frequencies { APLL_L_600_MHZ, }; +enum apll_b_frequencies { + APLL_B_600_MHZ, +}; + +void rk3399_configure_cpu_l(struct rk3399_cru *cru, + enum apll_l_frequencies apll_l_freq); +void rk3399_configure_cpu_b(struct rk3399_cru *cru, + enum apll_b_frequencies apll_b_freq); + #endif /* __ASM_ARCH_CRU_RK3399_H_ */ diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 26faf88116b..0a8178466dc 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -61,6 +61,11 @@ static const struct pll_div *apll_l_cfgs[] = { [APLL_L_600_MHZ] = &apll_l_600_cfg, }; +static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); +static const struct pll_div *apll_b_cfgs[] = { + [APLL_B_600_MHZ] = &apll_b_600_cfg, +}; + enum { /* PLL_CON0 */ PLL_FBDIV_MASK = 0xfff, @@ -128,6 +133,24 @@ enum { ATCLK_CORE_L_DIV_SHIFT = 0, ATCLK_CORE_L_DIV_MASK = 0x1f << ATCLK_CORE_L_DIV_SHIFT, + /* CLKSEL_CON2 */ + ACLKM_CORE_B_DIV_CON_SHIFT = 8, + ACLKM_CORE_B_DIV_CON_MASK = 0x1f << ACLKM_CORE_B_DIV_CON_SHIFT, + CLK_CORE_B_PLL_SEL_SHIFT = 6, + CLK_CORE_B_PLL_SEL_MASK = 3 << CLK_CORE_B_PLL_SEL_SHIFT, + CLK_CORE_B_PLL_SEL_ALPLL = 0x0, + CLK_CORE_B_PLL_SEL_ABPLL = 0x1, + CLK_CORE_B_PLL_SEL_DPLL = 0x10, + CLK_CORE_B_PLL_SEL_GPLL = 0x11, + CLK_CORE_B_DIV_MASK = 0x1f, + CLK_CORE_B_DIV_SHIFT = 0, + + /* CLKSEL_CON3 */ + PCLK_DBG_B_DIV_SHIFT = 0x8, + PCLK_DBG_B_DIV_MASK = 0x1f << PCLK_DBG_B_DIV_SHIFT, + ATCLK_CORE_B_DIV_SHIFT = 0, + ATCLK_CORE_B_DIV_MASK = 0x1f << ATCLK_CORE_B_DIV_SHIFT, + /* CLKSEL_CON14 */ PCLK_PERIHP_DIV_CON_SHIFT = 12, PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT, @@ -395,25 +418,26 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div) return 0; } -void rk3399_configure_cpu(struct rk3399_cru *cru, - enum apll_l_frequencies apll_l_freq) +void rk3399_configure_cpu_l(struct rk3399_cru *cru, + enum apll_l_frequencies apll_l_freq) { u32 aclkm_div; u32 pclk_dbg_div; u32 atclk_div; + /* Setup cluster L */ rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]); - aclkm_div = APLL_HZ / ACLKM_CORE_HZ - 1; - assert((aclkm_div + 1) * ACLKM_CORE_HZ == APLL_HZ && + aclkm_div = LPLL_HZ / ACLKM_CORE_L_HZ - 1; + assert((aclkm_div + 1) * ACLKM_CORE_L_HZ == LPLL_HZ && aclkm_div < 0x1f); - pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ - 1; - assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == APLL_HZ && + pclk_dbg_div = LPLL_HZ / PCLK_DBG_L_HZ - 1; + assert((pclk_dbg_div + 1) * PCLK_DBG_L_HZ == LPLL_HZ && pclk_dbg_div < 0x1f); - atclk_div = APLL_HZ / ATCLK_CORE_HZ - 1; - assert((atclk_div + 1) * ATCLK_CORE_HZ == APLL_HZ && + atclk_div = LPLL_HZ / ATCLK_CORE_L_HZ - 1; + assert((atclk_div + 1) * ATCLK_CORE_L_HZ == LPLL_HZ && atclk_div < 0x1f); rk_clrsetreg(&cru->clksel_con[0], @@ -428,6 +452,42 @@ void rk3399_configure_cpu(struct rk3399_cru *cru, pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT | atclk_div << ATCLK_CORE_L_DIV_SHIFT); } + +void rk3399_configure_cpu_b(struct rk3399_cru *cru, + enum apll_b_frequencies apll_b_freq) +{ + u32 aclkm_div; + u32 pclk_dbg_div; + u32 atclk_div; + + /* Setup cluster B */ + rkclk_set_pll(&cru->apll_b_con[0], apll_b_cfgs[apll_b_freq]); + + aclkm_div = BPLL_HZ / ACLKM_CORE_B_HZ - 1; + assert((aclkm_div + 1) * ACLKM_CORE_B_HZ == BPLL_HZ && + aclkm_div < 0x1f); + + pclk_dbg_div = BPLL_HZ / PCLK_DBG_B_HZ - 1; + assert((pclk_dbg_div + 1) * PCLK_DBG_B_HZ == BPLL_HZ && + pclk_dbg_div < 0x1f); + + atclk_div = BPLL_HZ / ATCLK_CORE_B_HZ - 1; + assert((atclk_div + 1) * ATCLK_CORE_B_HZ == BPLL_HZ && + atclk_div < 0x1f); + + rk_clrsetreg(&cru->clksel_con[2], + ACLKM_CORE_B_DIV_CON_MASK | CLK_CORE_B_PLL_SEL_MASK | + CLK_CORE_B_DIV_MASK, + aclkm_div << ACLKM_CORE_B_DIV_CON_SHIFT | + CLK_CORE_B_PLL_SEL_ALPLL << CLK_CORE_B_PLL_SEL_SHIFT | + 0 << CLK_CORE_B_DIV_SHIFT); + + rk_clrsetreg(&cru->clksel_con[3], + PCLK_DBG_B_DIV_MASK | ATCLK_CORE_B_DIV_MASK, + pclk_dbg_div << PCLK_DBG_B_DIV_SHIFT | + atclk_div << ATCLK_CORE_B_DIV_SHIFT); +} + #define I2C_CLK_REG_MASK(bus) \ (I2C_DIV_CON_MASK << \ CLK_I2C ##bus## _DIV_CON_SHIFT | \ @@ -1026,7 +1086,8 @@ static void rkclk_init(struct rk3399_cru *cru) u32 hclk_div; u32 pclk_div; - rk3399_configure_cpu(cru, APLL_L_600_MHZ); + rk3399_configure_cpu_l(cru, APLL_L_600_MHZ); + rk3399_configure_cpu_b(cru, APLL_B_600_MHZ); /* * some cru registers changed by bootrom, we'd better reset them to * reset/default values described in TRM to avoid confusion in kernel. -- 2.11.0

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[U-Boot] [PATCH v2 0/5] Migrate BOUNCE_BUFFER
by Philipp Tomsich 30 Nov '18

30 Nov '18

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[U-Boot] [PATCH 0/6] Migrate BOUNCE_BUFFER
by Philipp Tomsich 30 Nov '18

30 Nov '18

A number of MMC drivers uses BOUNCE_BUFFER for their DMA buffers. This moves it into Kconfig and performs a step-by-step migration for the affected boards/drivers. In doing so, it turns out that a few boards/configs enabled CONFIG_BOUNCE_BUFFER in their config headers without an apparent need. The migration (using moveconfig) for those boards is kept in a separate patch, so it can be more easily reviewed by the affected parties to make a determination whether it is actually needed. Given that BOUNCE_BUFFER only controls whether the bounce_buffer_* functions are build and linked, this configuration option could be entirely removed and the utility functions built unconditionally. For platforms that don't make use of these functions, the linker will then remove the unused symbols. I'll leave the final decision if this would be a better implementation (or if this should be done in a two-stage process) to someone else... END. Philipp Tomsich (6): Kconfig: Migrate BOUNCE_BUFFER mmc: dw_mmc: depend on BOUNCE_BUFFER mmc: mxsmmc: select BOUNCE_BUFFER unconditionally mmc: tegra: select BOUNCE_BUFFER unconditionally arc: select BOUNCE_BUFFER for CMD_NAND on AXS10x Kconfig: migrate BOUNCE_BUFFER (final moveconfig) arch/arc/Kconfig | 2 ++ common/Kconfig | 8 ++++++++ configs/bcm911360_entphn-ns_defconfig | 1 + configs/bcm911360_entphn_defconfig | 1 + configs/bcm911360k_defconfig | 1 + configs/bcm958300k-ns_defconfig | 1 + configs/bcm958300k_defconfig | 1 + configs/bcm958305k_defconfig | 1 + configs/bcm958622hr_defconfig | 1 + configs/socfpga_arria10_defconfig | 1 + drivers/mmc/Kconfig | 3 +++ include/configs/axs10x.h | 5 ----- include/configs/bcm_ep_board.h | 3 --- include/configs/emsdp.h | 3 --- include/configs/exynos-common.h | 3 --- include/configs/hikey.h | 3 --- include/configs/hsdk.h | 5 ----- include/configs/iot_devkit.h | 3 --- include/configs/mx6_common.h | 1 - include/configs/mx7_common.h | 1 - include/configs/mx7ulp_evk.h | 1 - include/configs/mxs.h | 5 ----- include/configs/poplar.h | 3 --- include/configs/rk3036_common.h | 2 -- include/configs/rk3128_common.h | 3 --- include/configs/rk3188_common.h | 3 --- include/configs/rk322x_common.h | 3 --- include/configs/rk3288_common.h | 3 --- include/configs/rk3328_common.h | 3 --- include/configs/rk3368_common.h | 2 -- include/configs/rk3399_common.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/socfpga_stratix10_socdk.h | 1 - include/configs/tegra-common.h | 3 --- scripts/config_whitelist.txt | 1 - 35 files changed, 21 insertions(+), 62 deletions(-) -- 2.1.4

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[U-Boot] [PULL] u-boot-socfpga/master
by Marek Vasut 30 Nov '18

30 Nov '18

The following changes since commit 67cf22cbdef8c62ffa28b4caf935825fe410c68d: Merge branch 'master' of git://git.denx.de/u-boot-usb (2018-11-27 14:01:45 -0500) are available in the Git repository at: git://git.denx.de/u-boot-socfpga.git master for you to fetch changes up to 30bade20a67a8205e10d006d8e1ac66552c1b137: arm: socfpga: fix SPL booting from fpga OnChip RAM (2018-11-29 12:45:15 +0100) ---------------------------------------------------------------- Simon Goldschmidt (6): arm: socfpga: make config structs const gpio: dwapb_gpio: fix binding without bank-name property spi: cadence_qspi: use "cdns,qspi-nor" as compatible dts: arm: socfpga: merge gen5 devicetrees from linux arm: socfpga: make socfpga_socrates_defconfig boot from QSPI arm: socfpga: fix SPL booting from fpga OnChip RAM arch/arm/dts/keystone-k2g.dtsi | 2 +- arch/arm/dts/socfpga.dtsi | 404 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------------------------- arch/arm/dts/socfpga_arria10.dtsi | 2 +- arch/arm/dts/socfpga_arria5.dtsi | 11 ++-- arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi | 56 +++++++++++++++++++ arch/arm/dts/socfpga_arria5_socdk.dts | 97 +++++++++++++++++++++++--------- arch/arm/dts/socfpga_cyclone5.dtsi | 9 +-- arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 17 +++++- arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi | 46 +++++++++++++++ arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts | 69 ++++++++++++++--------- arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 16 ++++++ arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 16 ++++++ arch/arm/dts/socfpga_cyclone5_is1.dts | 8 +++ arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi | 72 ++++++++++++++++++++++++ arch/arm/dts/socfpga_cyclone5_socdk.dts | 88 ++++++++++++++++++++++------- arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi | 56 +++++++++++++++++++ arch/arm/dts/socfpga_cyclone5_sockit.dts | 149 +++++++++++++++++++++++++++++++++++++++---------- arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi | 60 ++++++++++++++++++++ arch/arm/dts/socfpga_cyclone5_socrates.dts | 87 +++++++++++++++-------------- arch/arm/dts/socfpga_cyclone5_sr1500.dts | 12 ++++ arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 60 ++++++++++++++++++++ arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 222 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------- arch/arm/dts/stv0991.dts | 2 +- arch/arm/mach-socfpga/include/mach/base_addr_ac5.h | 1 + arch/arm/mach-socfpga/include/mach/misc.h | 9 +++ arch/arm/mach-socfpga/misc_gen5.c | 9 ++- arch/arm/mach-socfpga/spl_gen5.c | 10 +++- arch/arm/mach-socfpga/wrap_sdram_config.c | 4 +- doc/device-tree-bindings/spi/spi-cadence.txt | 2 +- drivers/gpio/dwapb_gpio.c | 7 +++ drivers/spi/cadence_qspi.c | 2 +- 31 files changed, 1264 insertions(+), 341 deletions(-) create mode 100644 arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi

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[U-Boot] [PATCH 1/3] mips: mt7628: Change compatible property of the ethernet DT node
by Stefan Roese 30 Nov '18

30 Nov '18

As the driver has been changed to be more specific, the DT compatible property also needs to be adapted. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> --- arch/mips/dts/mt7628a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index 70e34cfdbc..1e7d0a6ec5 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -164,7 +164,7 @@ }; eth@10110000 { - compatible = "mediatek,mt7622-eth"; + compatible = "mediatek,mt7628-eth"; reg = <0x10100000 0x10000 0x10110000 0x8000>; -- 2.19.2

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[U-Boot] [PATCH v2 0/7] Add support for the SoCs found in Microsemi switches
by Gregory CLEMENT 30 Nov '18

30 Nov '18

Hello, For the record this the second version of the series adding the support of 2 SoCs: Ocelot and Luton from Microsemi. Both of them belongs to the same family Vcore III. We found them on various advanced switches product. The support for Ocelot already have been submit to Linux, but not yet the Luton support. Since the v1 many changes had been done: - a big clean-up for indentation and some style issue - usage of the clrsetbits family functions where it was possible - split the patches for Ocelot and Luton - add a new patch to introduce the icache_lock function which was in the mscc directory in the first version - remove more unused define in the platform header files - use the automatic cache size detection instead of hard coding it - reduce the tlb init to only two entries for the IO as needed by the kernel - remove the interrupt disabling - fix the ddr init for luton Gregory CLEMENT (7): MIPS: move create_tlb() in an proper header: mipsregs.h MIPS: Allow to prefetch and lock instructions into cache MSCC: add support for Ocelot SoCs MSCC: add support for Luton SoCs MSCC: add board support for the Ocelots based evaluation boards MSCC: add board support for the Luton based evaluation board MIPS: bootm: Add support for Vcore III linux kernel arch/mips/Kconfig | 6 + arch/mips/Makefile | 1 + arch/mips/cpu/cpu.c | 10 - arch/mips/dts/luton_pcb091.dts | 36 + arch/mips/dts/mscc,luton.dtsi | 87 ++ arch/mips/dts/mscc,ocelot.dtsi | 132 +++ arch/mips/dts/mscc,ocelot_pcb.dtsi | 33 + arch/mips/dts/ocelot_pcb120.dts | 12 + arch/mips/dts/ocelot_pcb123.dts | 12 + arch/mips/include/asm/cacheops.h | 19 + arch/mips/include/asm/mipsregs.h | 11 + arch/mips/lib/bootm.c | 77 +- arch/mips/mach-mscc/Kconfig | 86 ++ arch/mips/mach-mscc/Makefile | 6 + arch/mips/mach-mscc/cpu.c | 55 ++ arch/mips/mach-mscc/dram.c | 63 ++ arch/mips/mach-mscc/include/ioremap.h | 51 ++ arch/mips/mach-mscc/include/mach/common.h | 31 + arch/mips/mach-mscc/include/mach/ddr.h | 786 ++++++++++++++++++ .../mips/mach-mscc/include/mach/luton/luton.h | 37 + .../include/mach/luton/luton_devcpu_gcb.h | 14 + .../include/mach/luton/luton_icpu_cfg.h | 245 ++++++ .../mach-mscc/include/mach/ocelot/ocelot.h | 35 + .../include/mach/ocelot/ocelot_devcpu_gcb.h | 21 + .../include/mach/ocelot/ocelot_icpu_cfg.h | 274 ++++++ arch/mips/mach-mscc/include/mach/tlb.h | 55 ++ arch/mips/mach-mscc/lowlevel_init.S | 30 + arch/mips/mach-mscc/lowlevel_init_luton.S | 62 ++ arch/mips/mach-mscc/reset.c | 36 + board/mscc/luton/Kconfig | 14 + board/mscc/luton/Makefile | 3 + board/mscc/luton/luton.c | 28 + board/mscc/ocelot/Kconfig | 14 + board/mscc/ocelot/Makefile | 4 + board/mscc/ocelot/ocelot.c | 48 ++ configs/mscc_luton_defconfig | 66 ++ configs/mscc_ocelot_defconfig | 57 ++ configs/mscc_ocelot_pcb120_defconfig | 56 ++ include/configs/vcoreiii.h | 77 ++ 39 files changed, 2660 insertions(+), 30 deletions(-) create mode 100644 arch/mips/dts/luton_pcb091.dts create mode 100644 arch/mips/dts/mscc,luton.dtsi create mode 100644 arch/mips/dts/mscc,ocelot.dtsi create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi create mode 100644 arch/mips/dts/ocelot_pcb120.dts create mode 100644 arch/mips/dts/ocelot_pcb123.dts create mode 100644 arch/mips/mach-mscc/Kconfig create mode 100644 arch/mips/mach-mscc/Makefile create mode 100644 arch/mips/mach-mscc/cpu.c create mode 100644 arch/mips/mach-mscc/dram.c create mode 100644 arch/mips/mach-mscc/include/ioremap.h create mode 100644 arch/mips/mach-mscc/include/mach/common.h create mode 100644 arch/mips/mach-mscc/include/mach/ddr.h create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton.h create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h create mode 100644 arch/mips/mach-mscc/include/mach/tlb.h create mode 100644 arch/mips/mach-mscc/lowlevel_init.S create mode 100644 arch/mips/mach-mscc/lowlevel_init_luton.S create mode 100644 arch/mips/mach-mscc/reset.c create mode 100644 board/mscc/luton/Kconfig create mode 100644 board/mscc/luton/Makefile create mode 100644 board/mscc/luton/luton.c create mode 100644 board/mscc/ocelot/Kconfig create mode 100644 board/mscc/ocelot/Makefile create mode 100644 board/mscc/ocelot/ocelot.c create mode 100644 configs/mscc_luton_defconfig create mode 100644 configs/mscc_ocelot_defconfig create mode 100644 configs/mscc_ocelot_pcb120_defconfig create mode 100644 include/configs/vcoreiii.h -- 2.19.1

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[U-Boot] [GIT] Pull request: u-boot-dfu (24.11.2018)
by Lukasz Majewski 30 Nov '18

30 Nov '18

Dear Marek, The following changes since commit 5830791d91d1200854ef78fcb32f808c8080f0f0: Merge tag 'pull-tg18' of git://git.denx.de/u-boot-dm (2018-11-23 17:25:27 -0500) are available in the git repository at: git://git.denx.de/u-boot-dfu.git for you to fetch changes up to 0edf2bd52772d8202469b77ba63a6cd9867d1053: board: ti: am57xx: remove USB platform code (2018-11-24 22:59:55 +0100) NOTE: ----- This series has a dependency on following patch: "spl: Add support for logging in SPL and TPL" by Simon Glass http://patchwork.ozlabs.org/patch/998686/ Travis-CI "clear" build: https://travis-ci.org/lmajewski/u-boot-dfu/builds/459112024 Those are first two of total four patches prepared by Jean-Jacques. Let's apply them in step-by-step way (as other have some build issues). ---------------------------------------------------------------- Jean-Jacques Hiblot (18): usb: gadget: Do not call board_usb_xxx() directly in USB gadget drivers usb: introduce a separate config option for DM USB device usb: udc: implement DM versions of usb_gadget_initialize()/_release()/_handle_interrupt() dwc3_generic: do not probe the USB device driver when it's bound dwc3: move phy operation to core.c configs: evb-rk3328: Enable CONFIG_USB_DWC3 dwc3-generic: Handle the PHYs, the clocks and the reset lines dwc3-generic: Add select_dr_mode operation usb: dwc3: Fix a compilation error with the edison defconfig syscon: dm: Add a new method to get a regmap from DTS phy: Add a new driver for OMAP's USB2 PHYs dwc3-generic: Add support for the TI DWC3 glue board: ti: dra7xx-evm: turn on USB clocks in late init stage dts: dra7x: make ocp2scp@4a080000 compatible with simple-bus configs: enable DM_USB and DM_USB_DEV for all DRA7 platforms configs: am57xx_evm: Enable DM_USB and DM_USB_DEV board: ti: dra7-evm: remove USB platform code board: ti: am57xx: remove USB platform code Vignesh R (2): phy: ti-pip3-phy: Add support for USB3 PHY board; ti: am57xx: turn on USB clocks arch/arm/Kconfig | 2 + arch/arm/dts/omap5-u-boot.dtsi | 4 ++ arch/sandbox/dts/test.dts | 6 +- board/ti/am57xx/board.c | 106 +++++++----------------------------- board/ti/dra7xx/evm.c | 123 +++++++---------------------------------- cmd/fastboot.c | 4 +- cmd/rockusb.c | 4 +- cmd/thordown.c | 4 +- cmd/usb_gadget_sdp.c | 4 +- cmd/usb_mass_storage.c | 4 +- common/dfu.c | 6 +- configs/am57xx_evm_defconfig | 10 +++- configs/am57xx_hs_evm_defconfig | 10 +++- configs/dra7xx_evm_defconfig | 8 +-- configs/dra7xx_hs_evm_defconfig | 8 +-- configs/evb-rk3328_defconfig | 1 + drivers/core/syscon-uclass.c | 23 ++++++++ drivers/phy/Kconfig | 9 +++ drivers/phy/Makefile | 1 + drivers/phy/omap-usb2-phy.c | 196 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/phy/ti-pipe3-phy.c | 32 ++++++++--- drivers/usb/Kconfig | 6 ++ drivers/usb/dwc3/Kconfig | 7 ++- drivers/usb/dwc3/core.c | 89 +++++++++++++++++++++++++++++- drivers/usb/dwc3/dwc3-generic.c | 292 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--------------- drivers/usb/dwc3/ep0.c | 3 +- drivers/usb/gadget/ether.c | 38 ++----------- drivers/usb/gadget/udc/udc-core.c | 44 ++++++++++++++- drivers/usb/host/xhci-dwc3.c | 95 +++----------------------------- include/dwc3-uboot.h | 19 +++++++ include/linux/usb/gadget.h | 18 ++++++ include/syscon.h | 13 +++++ test/dm/syscon.c | 29 ++++++++++ 33 files changed, 816 insertions(+), 402 deletions(-) create mode 100644 drivers/phy/omap-usb2-phy.c Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma(a)denx.de

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