November 2018 - U-Boot

[U-Boot] [PATCH V2 1/2] SPL: Add HAB image authentication to FIT
by Peng Fan 11 Dec '18

11 Dec '18

From: Ye Li <ye.li(a)nxp.com> Introduce two board level callback functions to FIT image loading process, and a SPL_FIT_FOUND flag to differentiate FIT image or RAW image. Implement functions in imx common SPL codes to call HAB funtion to authenticate the FIT image. Generally, we have to sign multiple regions in FIT image: 1. Sign FIT FDT data (configuration) 2. Sign FIT external data (Sub-images) Because the CSF supports to sign multiple memory blocks, so that we can use one signature to cover all regions in FIT image and only authenticate once. The authentication should be done after the entire FIT image is loaded into memory including all sub-images. We use "-p" option to generate FIT image to reserve a space for FIT IVT and FIT CSF, also this help to fix the offset of the external data (u-boot-nodtb.bin, ATF, u-boot DTB). The signed FIT image layout is as below: -------------------------------------------------- | | | | | | | | | FIT | FIT | FIT | | U-BOOT | ATF | U-BOOT | | FDT | IVT | CSF | | nodtb.bin | | DTB | | | | | | | | | -------------------------------------------------- Signed-off-by: Ye Li <ye.li(a)nxp.com> Reviewed-by: Peng Fan <peng.fan(a)nxp.com> Reviewed-by: Tom Rini <trini(a)konsulko.com> Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- V2: Add Tom's review tag arch/arm/mach-imx/spl.c | 44 ++++++++++++++++++++++++++++++++++++++------ common/spl/spl_fit.c | 21 +++++++++++++++++++-- include/spl.h | 1 + 3 files changed, 58 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index a20b30d154..6f0b5cdb4c 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -220,14 +220,46 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) debug("image entry point: 0x%lX\n", spl_image->entry_point); - /* HAB looks for the CSF at the end of the authenticated data therefore, - * we need to subtract the size of the CSF from the actual filesize */ - offset = spl_image->size - CONFIG_CSF_SIZE; - if (!imx_hab_authenticate_image(spl_image->load_addr, - offset + IVT_SIZE + CSF_PAD_SIZE, - offset)) { + if (spl_image->flags & SPL_FIT_FOUND) { image_entry(); } else { + /* + * HAB looks for the CSF at the end of the authenticated + * data therefore, we need to subtract the size of the + * CSF from the actual filesize + */ + offset = spl_image->size - CONFIG_CSF_SIZE; + if (!imx_hab_authenticate_image(spl_image->load_addr, + offset + IVT_SIZE + + CSF_PAD_SIZE, offset)) { + image_entry(); + } else { + puts("spl: ERROR: image authentication fail\n"); + hang(); + } + } +} + +ulong board_spl_fit_size_align(ulong size) +{ + /* + * HAB authenticate_image requests the IVT offset is + * aligned to 0x1000 + */ + + size = ALIGN(size, 0x1000); + size += CONFIG_CSF_SIZE; + + return size; +} + +void board_spl_fit_post_load(ulong load_addr, size_t length) +{ + u32 offset = length - CONFIG_CSF_SIZE; + + if (imx_hab_authenticate_image(load_addr, + offset + IVT_SIZE + CSF_PAD_SIZE, + offset)) { puts("spl: ERROR: image authentication unsuccessful\n"); hang(); } diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index faf4ddbd1f..db436268cb 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -15,6 +15,15 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) #endif +__weak void board_spl_fit_post_load(ulong load_addr, size_t length) +{ +} + +__weak ulong board_spl_fit_size_align(ulong size) +{ + return size; +} + /** * spl_fit_get_image_name(): By using the matching configuration subnode, * retrieve the name of an image, specified by a property name and an index @@ -350,6 +359,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, */ size = fdt_totalsize(fit); size = (size + 3) & ~3; + size = board_spl_fit_size_align(size); base_offset = (size + 3) & ~3; /* @@ -373,8 +383,9 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, fit = spl_get_load_buffer(-hsize, hsize); sectors = get_aligned_image_size(info, size, 0); count = info->read(info, sector, sectors, fit); - debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu\n", - sector, sectors, fit, count); + debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu, size=0x%lx\n", + sector, sectors, fit, count, size); + if (count == 0) return -EIO; @@ -510,5 +521,11 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, if (spl_image->entry_point == FDT_ERROR || spl_image->entry_point == 0) spl_image->entry_point = spl_image->load_addr; + spl_image->flags |= SPL_FIT_FOUND; + +#ifdef CONFIG_SECURE_BOOT + board_spl_fit_post_load((ulong)fit, size); +#endif + return 0; } diff --git a/include/spl.h b/include/spl.h index 9a439f468b..5dd25ab611 100644 --- a/include/spl.h +++ b/include/spl.h @@ -77,6 +77,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, struct spl_load_info *info, ulong sector, void *fdt); #define SPL_COPY_PAYLOAD_ONLY 1 +#define SPL_FIT_FOUND 2 /* SPL common functions */ void preloader_console_init(void); -- 2.14.1

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[U-Boot] [PATCH] blk: Rework guard around part_init call
by Tom Rini 11 Dec '18

11 Dec '18

The function part_init() will only be built when we have both CONFIG_PARTITIONS and CONFIG_HAVE_BLOCK_DEVICE set. Protect the call to this function with both of these tests now. Cc: Simon Glass <sjg(a)chromium.org> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- drivers/block/blk-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c index 65a766e586d6..baaf431e5e0c 100644 --- a/drivers/block/blk-uclass.c +++ b/drivers/block/blk-uclass.c @@ -639,7 +639,7 @@ int blk_unbind_all(int if_type) static int blk_post_probe(struct udevice *dev) { -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) +#if defined(CONFIG_PARTITIONS) && defined(CONFIG_HAVE_BLOCK_DEVICE) struct blk_desc *desc = dev_get_uclass_platdata(dev); part_init(desc); -- 2.7.4

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[U-Boot] [PATCH v2 00/32] spi: DM_SPI migration timeout, remainder(2)
by Jagan Teki 11 Dec '18

11 Dec '18

This series fix, build issues and comments from previous series [1]. We have not heard any positive feed back about dm-conversion on spi drivers along with no response for the work done by Akash and me. Plan is to send the same series remainder recursively based on the dm conversion updates and finally merged into v2019.04 MW. So expecting inputs from relevant developers to move their board/drivers to support DM_SPI. - cf_spi, lpc32xx_ssp, mxs_spi, sh_spi, soft_spi_legacy, fsl_espi drivers are drooped with their respective CONFIG items. the spi/spi-flash usage commands still build but the used spi core function calls return 0. - non-dm code in davinci, kirkwood, ti_qspi, mpc8xxx, mxc, omap3, atmel, fsl_dspi drivers were drooped and u-boot build system will trigger warning for the same. Note: - Let's discuss if any foot-print issues? Any inputs, Jagan. [1] https://patchwork.ozlabs.org/cover/1000444/ Jagan Teki (15): spi: davinci: Full dm conversion spi: kirkwood: Full dm conversion spi: ti_qspi: Full dm conversion spi: mpc8xxx: Convert to DM spi: Zap cf_spi driver-related code spi: Zap lpc32xx_ssp driver-related code spi: Zap mxs_spi driver-related code spi: Zap sh_spi driver-related code spi: Zap soft_spi_legacy driver-related code spi: mxc: Drop non-dm code spi: omap3: Drop non-dm code spi: atmel: Drop non-dm code spi: Zap fsl_espi driver-related code spi: fsl_dspi: Drop non-dm code dm: MIGRATION: spi: Update SPI driver status Mario Six (17): spi: mpc8xxx: Use short type names spi: mpc8xxx: Fix comments spi: mpc8xxx: Rename camel-case variables spi: mpc8xxx: Fix space after cast spi: mpc8xxx: Fix function names in strings spi: mpc8xxx: Replace defines with enums spi: mpc8xxx: Use IO accessors spi: mpc8xxx: Simplify if spi: mpc8xxx: Get rid of is_read spi: mpc8xxx: Simplify logic a bit spi: mpc8xxx: Reduce scope of loop variables spi: mpc8xxx: Make code more readable spi: mpc8xxx: Rename variable spi: mpc8xxx: Document LEN setting better spi: mpc8xxx: Re-order transfer setup spi: mpc8xxx: Fix if check spi: mpc8xxx: Use get_timer Makefile | 11 + arch/m68k/cpu/mcf5227x/cpu_init.c | 54 -- arch/m68k/cpu/mcf5445x/cpu_init.c | 113 ---- board/Arcturus/ucp1020/ucp1020.c | 6 + configs/M52277EVB_defconfig | 1 - configs/M52277EVB_stmicro_defconfig | 1 - configs/M54418TWR_defconfig | 1 - configs/M54418TWR_nand_mii_defconfig | 1 - configs/M54418TWR_nand_rmii_defconfig | 1 - configs/M54418TWR_nand_rmii_lowfreq_defconfig | 1 - configs/M54418TWR_serial_mii_defconfig | 1 - configs/M54418TWR_serial_rmii_defconfig | 1 - configs/M54451EVB_defconfig | 1 - configs/M54451EVB_stmicro_defconfig | 1 - configs/M54455EVB_a66_defconfig | 1 - configs/M54455EVB_defconfig | 1 - configs/M54455EVB_i66_defconfig | 1 - configs/M54455EVB_intel_defconfig | 1 - configs/M54455EVB_stm33_defconfig | 1 - configs/bg0900_defconfig | 1 - configs/devkit3250_defconfig | 1 - configs/mx28evk_auart_console_defconfig | 1 - configs/mx28evk_defconfig | 1 - configs/mx28evk_nand_defconfig | 1 - configs/mx28evk_spi_defconfig | 1 - configs/sh7752evb_defconfig | 1 - configs/sh7753evb_defconfig | 1 - configs/sh7757lcr_defconfig | 1 - configs/stmark2_defconfig | 1 - configs/work_92105_defconfig | 1 - doc/driver-model/MIGRATION.txt | 18 +- drivers/spi/Kconfig | 42 +- drivers/spi/Makefile | 22 +- drivers/spi/atmel_spi.c | 198 ------- drivers/spi/cf_spi.c | 335 ------------ drivers/spi/davinci_spi.c | 157 ------ drivers/spi/fsl_dspi.c | 132 ----- drivers/spi/fsl_espi.c | 383 -------------- drivers/spi/kirkwood_spi.c | 218 ++------ drivers/spi/lpc32xx_ssp.c | 134 ----- drivers/spi/mpc8xxx_spi.c | 279 ++++++---- drivers/spi/mxc_spi.c | 123 +---- drivers/spi/mxs_spi.c | 358 ------------- drivers/spi/omap3_spi.c | 126 ----- drivers/spi/sh_spi.c | 249 --------- drivers/spi/sh_spi.h | 67 --- drivers/spi/soft_spi_legacy.c | 168 ------ drivers/spi/spi.c | 38 ++ drivers/spi/ti_qspi.c | 490 +++++++----------- include/configs/M52277EVB.h | 1 - include/configs/M54418TWR.h | 1 - include/configs/M54451EVB.h | 1 - include/configs/M54455EVB.h | 1 - include/configs/MPC8349EMDS.h | 3 - include/configs/devkit3250.h | 5 - include/configs/sh7752evb.h | 3 - include/configs/sh7753evb.h | 3 - include/configs/sh7757lcr.h | 3 - include/configs/stmark2.h | 1 - include/configs/work_92105.h | 5 - include/configs/zipitz2.h | 1 - include/dm/platform_data/spi_kirkwood.h | 15 + include/dm/platform_data/spi_ti_qspi.h | 19 + scripts/config_whitelist.txt | 3 - 64 files changed, 502 insertions(+), 3310 deletions(-) delete mode 100644 drivers/spi/cf_spi.c delete mode 100644 drivers/spi/fsl_espi.c delete mode 100644 drivers/spi/lpc32xx_ssp.c delete mode 100644 drivers/spi/mxs_spi.c delete mode 100644 drivers/spi/sh_spi.c delete mode 100644 drivers/spi/sh_spi.h delete mode 100644 drivers/spi/soft_spi_legacy.c create mode 100644 include/dm/platform_data/spi_kirkwood.h create mode 100644 include/dm/platform_data/spi_ti_qspi.h -- 2.18.0.321.gffc6fa0e3

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[U-Boot] [PATCH 00/19] riscv: Adding RISC-V CPU and timer driver
by Bin Meng 11 Dec '18

11 Dec '18

This adds DM drivers to support RISC-V CPU and timer. The U-Boot RISC-V SBI support is still working in progress. Some patches in this series like adding CSR numbers, exception numbers, are prerequisites for the SBI implementation, but it does no harm to include them as part of this series. This series is dependent on Lukas's riscv series @ http://patchwork.ozlabs.org/project/uboot/list/?series=74999 This series is available at u-boot-x86/riscv-working for testing. Bin Meng (18): dm: cpu: Add timebase frequency to the platdata riscv: qemu: Create a simple-bus driver for the soc node cpu: Add a RISC-V CPU driver riscv: Add a SYSCON driver for Core Local Interruptor timer: Add driver for RISC-V privileged architecture defined timer riscv: kconfig: Allow platform to specify Kconfig options riscv: Enlarge the default SYS_MALLOC_F_LEN riscv: qemu: Probe cpus during boot riscv: Add CSR numbers riscv: Add exception codes for xcause register riscv: Do some basic architecture level cpu initialization riscv: Move trap handler codes to mtrap.S riscv: Fix context restore before returning from trap handler riscv: Return to previous privilege level after trap handling riscv: Adjust the _exit_trap() position to come before handle_trap() riscv: Pass correct exception code to _exit_trap() riscv: Refactor handle_trap() a little for future extension riscv: Allow U-Boot to run on hart 0 only Lukas Auer (1): riscv: add Kconfig entries for the code model arch/riscv/Kconfig | 35 ++++++ arch/riscv/Makefile | 9 +- arch/riscv/cpu/Makefile | 2 +- arch/riscv/cpu/cpu.c | 21 ++++ arch/riscv/cpu/mtrap.S | 103 ++++++++++++++++ arch/riscv/cpu/qemu/Kconfig | 10 ++ arch/riscv/cpu/qemu/cpu.c | 27 +++++ arch/riscv/cpu/start.S | 86 +------------- arch/riscv/include/asm/clint.h | 24 ++++ arch/riscv/include/asm/encoding.h | 234 +++++++++++++++++++++++++++++++++++++ arch/riscv/lib/Makefile | 1 + arch/riscv/lib/clint.c | 69 +++++++++++ arch/riscv/lib/interrupts.c | 78 +++++++------ board/emulation/qemu-riscv/Kconfig | 1 + drivers/cpu/Kconfig | 6 + drivers/cpu/Makefile | 1 + drivers/cpu/riscv_cpu.c | 117 +++++++++++++++++++ drivers/timer/Kconfig | 8 ++ drivers/timer/Makefile | 1 + drivers/timer/riscv_timer.c | 50 ++++++++ include/cpu.h | 3 + 21 files changed, 764 insertions(+), 122 deletions(-) create mode 100644 arch/riscv/cpu/mtrap.S create mode 100644 arch/riscv/cpu/qemu/Kconfig create mode 100644 arch/riscv/include/asm/clint.h create mode 100644 arch/riscv/lib/clint.c create mode 100644 drivers/cpu/riscv_cpu.c create mode 100644 drivers/timer/riscv_timer.c -- 2.7.4

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[U-Boot] [PATCH][v3] armv8: lx2160a: Add LX2160A SoC Support
by Priyanka Jain 10 Dec '18

10 Dec '18

LX2160A Soc is based on Layerscape Chassis Generation 3.2 Architecture. Features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, two 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao(a)nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal(a)nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma(a)nxp.com> Signed-off-by: Sriram Dash <sriram.dash(a)nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- Changes for v3: Add CONFIG_SYS_FSL_RST_ADDR define Changes for v2: Add CCN508 define Rebased on TF-A Boot support for NXP Chassis 2 platforms Removed eSDHC nodes from dts, will be send in separate patch. Add reset related changes arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 52 +++++++- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 6 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 15 ++- arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 57 +++++++++ .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 36 ++++++ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 +- arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 132 +++++++++++++++++++++ arch/arm/dts/fsl-lx2160a.dtsi | 118 ++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 56 +++++++++ .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 28 +++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 26 ++++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 6 + .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 9 +- drivers/ddr/fsl/Kconfig | 1 + drivers/net/ldpaa_eth/Makefile | 3 +- drivers/net/ldpaa_eth/lx2160a.c | 107 +++++++++++++++++ 16 files changed, 644 insertions(+), 10 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c create mode 100644 arch/arm/dts/fsl-lx2160a.dtsi create mode 100644 drivers/net/ldpaa_eth/lx2160a.c diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 650ac94..2b086da 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -170,6 +170,42 @@ config ARCH_LS2080A imply DISTRO_DEFAULTS imply PANIC_HANG +config ARCH_LX2160A + bool + select ARMV8_SET_SMPEN + select FSL_LSCH3 + select NXP_LSCH3_2 + select SYS_HAS_SERDES + select SYS_FSL_SRDS_1 + select SYS_FSL_SRDS_2 + select SYS_NXP_SRDS_3 + select SYS_FSL_DDR + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_EC1 + select SYS_FSL_EC2 + select SYS_FSL_HAS_RGMII + select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_CCN508 + select SYS_FSL_HAS_DDR4 + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 + select SYS_I2C_MXC_I2C5 + select SYS_I2C_MXC_I2C6 + select SYS_I2C_MXC_I2C7 + select SYS_I2C_MXC_I2C8 + imply DISTRO_DEFAULTS + imply PANIC_HANG + imply SCSI + imply SCSI_AHCI + config FSL_LSCH2 bool select SYS_FSL_HAS_CCI400 @@ -185,7 +221,7 @@ config NXP_LSCH3_2 config FSL_MC_ENET bool "Management Complex network" - depends on ARCH_LS2080A || ARCH_LS1088A + depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A default y select RESV_RAM help @@ -202,6 +238,7 @@ config FSL_PCIE_COMPAT default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A default "fsl,ls1088a-pcie" if ARCH_LS1088A + default "fsl,lx2160a-pcie" if ARCH_LX2160A help This compatible is used to find pci controller node in Kernel DT to complete fixup. @@ -300,6 +337,7 @@ config MAX_CPUS default 4 if ARCH_LS1046A default 16 if ARCH_LS2080A default 8 if ARCH_LS1088A + default 16 if ARCH_LX2160A default 1 help Set this number to the maximum number of possible CPUs in the SoC. @@ -342,6 +380,9 @@ config SYS_FSL_HAS_CCI400 config SYS_FSL_HAS_CCN504 bool +config SYS_FSL_HAS_CCN508 + bool + config SYS_FSL_HAS_DP_DDR bool @@ -404,6 +445,7 @@ config SYS_FSL_DSPI_CLK_DIV config SYS_FSL_DUART_CLK_DIV int "DUART clock divider" default 1 if ARCH_LS1043A + default 4 if ARCH_LX2160A default 2 help This is the divider that is used to derive DUART clock from Platform @@ -464,13 +506,15 @@ config RESV_RAM config SYS_FSL_EC1 bool help - Ethernet controller 1, this is connected to MAC3. + Ethernet controller 1, this is connected to + MAC17 for LX2160A or to MAC3 for other SoCs Provides DPAA2 capabilities config SYS_FSL_EC2 bool help - Ethernet controller 2, this is connected to MAC4. + Ethernet controller 2, this is connected to + MAC18 for LX2160A or to MAC4 for other SoCs Provides DPAA2 capabilities config SYS_FSL_ERRATUM_A008336 @@ -506,7 +550,7 @@ config SYS_FSL_HAS_RGMII config SYS_MC_RSV_MEM_ALIGN hex "Management Complex reserved memory alignment" depends on RESV_RAM - default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A + default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A help Reserved memory needs to be aligned for MC to use. Default value is 512MB. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 91fdbad..e9bc987 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# +# Copyright 2016-2018 NXP # Copyright 2014-2015, Freescale Semiconductor obj-y += cpu.o @@ -22,6 +22,10 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o endif endif +ifneq ($(CONFIG_ARCH_LX2160A),) +obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o +endif + ifneq ($(CONFIG_ARCH_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 60b0575..a35958a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -60,6 +60,9 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), CPU_TYPE_ENTRY(LS1048A, LS1048A, 4), CPU_TYPE_ENTRY(LS1044A, LS1044A, 4), + CPU_TYPE_ENTRY(LX2160A, LX2160A, 16), + CPU_TYPE_ENTRY(LX2120A, LX2120A, 12), + CPU_TYPE_ENTRY(LX2080A, LX2080A, 8), }; #define EARLY_PGTABLE_SIZE 0x5000 @@ -246,7 +249,7 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#ifdef CONFIG_ARCH_LS2080A +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | @@ -366,6 +369,10 @@ void cpu_name(char *name) for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { strcpy(name, cpu_type_list[i].name); +#ifdef CONFIG_ARCH_LX2160A + if (IS_C_PROCESSOR(svr)) + strcat(name, "C"); +#endif if (IS_E_PROCESSOR(svr)) strcat(name, "E"); @@ -1165,10 +1172,16 @@ void __efi_runtime reset_cpu(ulong addr) { u32 val; +#ifdef CONFIG_ARCH_LX2160A + val = in_le32(rstcr); + val |= 0x01; + out_le32(rstcr, val); +#else /* Raise RESET_REQ_B */ val = scfg_in32(rstcr); val |= 0x02; scfg_out32(rstcr, val); +#endif } #ifdef CONFIG_EFI_LOADER diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index 276ab90..a0e2621 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -7,6 +7,7 @@ SoC overview 5. LS1046A 6. LS2088A 7. LS2081A + 8. LX2160A LS1043A --------- @@ -271,3 +272,59 @@ Refer to LS2084A(LS2088A) section above for details. It has one more similar SoC personality 1)LS2041A, few difference w.r.t. LS2081A: a) Four 64-bit ARM v8 Cortex-A72 CPUs + +LX2160A +-------- +The QorIQ LX2160A processor is built in the 16FFC process on +the Layerscape architecture combining sixteen ARM A72 processor +cores with advanced, high-performance datapath acceleration and +network, peripheral interfaces required for networking, wireless +infrastructure, storage, and general-purpose embedded applications. + +LX2160A is compliant with the Layerscape Chassis Generation 3.2. + +The LX2160A SoC includes the following function and features: + Sixteen 32-bit / 64-bit ARM v8 A72 CPUs + Cache Coherent Interconnect Fabric (CCN508 aka “Eliot”) + Two 64-bit 3.2GT/s DDR4 SDRAM memory controllers with ECC. + Data path acceleration architecture (DPAA2) + 24 Serdes lanes at up to 25 GHz + Ethernet interfaces + Single WRIOP tile supporting 130Gbps using 18 MACs + Support for 10G-SXGMII (aka USXGMII). + Support for SGMII (and 1000Base-KX) + Support for XFI (and 10GBase-KR) + Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G). + Support for XLAUI (and 40GBase-KR4) for 40G. + Support for two RGMII parallel interfaces. + Energy efficient Ethernet support (802.3az) + IEEE 1588 support. + High-speed peripheral interfaces + Two PCIe Gen 4.0 8-lane controllers supporting SR-IOV, + Four PCIe Gen 4.0 4-lane controllers. + Four serial ATA (SATA 3.0) controllers. + Two USB 3.0 controllers with integrated PHY + Two Enhanced secure digital host controllers + Two Controller Area Network (CAN) modules + Flexible Serial peripheral interface (FlexSPI) controller. + Three Serial peripheral interface (SPI) controllers. + Eight I2C Controllers. + Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports. + General Purpose IO (GPIO) + Support for hardware virtualization and partitioning (ARM MMU-500) + Support for GIC (ARM GIC-500) + QorIQ platform Trust Architecture 3.0 + One Secure WatchDog timer and one Non-Secure Watchdog timer. + ARM Generic Timer + Two Flextimers + Debug supporting run control, data acquisition, high-speed trace, + performance/event monitoring + Thermal Monitor Unit (TMU) with +/- 2C accuracy + Support for Voltage ID (VID) for yield improvement + +LX2160A SoC has 2 more similar SoC personalities +1)LX2120A, few difference w.r.t. LX2160A: + a) Twelve 64-bit ARM v8 Cortex-A72 CPUs + +2)LX2080A, few difference w.r.t. LX2160A: + a) Eight 64-bit ARM v8 Cortex-A72 CPUs diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index bb50e3d..ab1be3f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -22,9 +22,18 @@ static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT]; #endif #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_ARCH_LX2160A +int xfi_dpmac[XFI14 + 1]; +int sgmii_dpmac[SGMII18 + 1]; +int a25gaui_dpmac[_25GE10 + 1]; +int xlaui_dpmac[_40GE2 + 1]; +int caui2_dpmac[_50GE2 + 1]; +int caui4_dpmac[_100GE2 + 1]; +#else int xfi_dpmac[XFI8 + 1]; int sgmii_dpmac[SGMII16 + 1]; #endif +#endif __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) { @@ -146,6 +155,32 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, else { serdes_prtcl_map[lane_prtcl] = 1; #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_ARCH_LX2160A + if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14) + wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18) + wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10) + wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2) + wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2) + wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2) + wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl], + (int)lane_prtcl); + +#else switch (lane_prtcl) { case QSGMII_A: case QSGMII_B: @@ -167,6 +202,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, break; } #endif +#endif } } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index cbc9112..6721a57 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -354,7 +354,7 @@ get_svr: ret #endif -#ifdef CONFIG_SYS_FSL_HAS_CCN504 +#if defined(CONFIG_SYS_FSL_HAS_CCN504) || defined(CONFIG_SYS_FSL_HAS_CCN508) hnf_pstate_poll: /* x0 has the desired status, return 0 for success, 1 for timeout * clobber x1, x2, x3, x4, x6, x7 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c new file mode 100644 index 0000000..a04a370 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <asm/arch/fsl_serdes.h> + +struct serdes_config { + u8 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x02, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII6, SGMII5, SGMII4, SGMII3 } }, + {0x03, {PCIE2, PCIE2, PCIE2, PCIE2, XFI6, XFI5, XFI4, + XFI3 } }, + {0x04, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, + SGMII3 } }, + {0x05, {XFI10, XFI9, XFI8, XFI7, PCIE1, PCIE1, PCIE1, + PCIE1 } }, + {0x06, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, XFI4, + XFI3 } }, + {0x07, {SGMII10, SGMII9, SGMII8, SGMII7, XFI6, XFI5, XFI4, + XFI3 } }, + {0x08, {XFI10, XFI9, XFI8, XFI7, XFI6, XFI5, XFI4, XFI3 } }, + {0x09, {SGMII10, SGMII9, SGMII8, PCIE2, SGMII6, SGMII5, SGMII4, + PCIE1 } }, + {0x0A, {XFI10, XFI9, XFI8, PCIE2, XFI6, XFI5, XFI4, PCIE1 } }, + {0x0B, {SGMII10, SGMII9, PCIE2, PCIE2, SGMII6, SGMII5, PCIE1, PCIE1 } }, + {0x0C, {SGMII10, SGMII9, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x0D, {_100GE2, _100GE2, _100GE2, _100GE2, _100GE1, _100GE1, _100GE1, + _100GE1 } }, + {0x0E, {PCIE2, PCIE2, PCIE2, PCIE2, _100GE1, _100GE1, _100GE1, + _100GE1 } }, + {0x0F, {PCIE2, PCIE2, PCIE2, PCIE2, _50GE2, _50GE2, _50GE1, _50GE1 } }, + {0x10, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _50GE1, _50GE1 } }, + {0x11, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, _25GE3 } }, + {0x12, {XFI10, XFI9, XFI8, XFI7, _25GE6, _25GE5, XFI4, + XFI3 } }, + {0x13, {_40GE2, _40GE2, _40GE2, _40GE2, _25GE6, _25GE5, XFI4, XFI3 } }, + {0x14, {_40GE2, _40GE2, _40GE2, _40GE2, _40GE1, _40GE1, _40GE1, + _40GE1 } }, + {0x15, {_25GE10, _25GE9, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, + _25GE3 } }, + {0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } }, + {} +}; + +static struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {0x01, {PCIE3, PCIE3, SATA1, SATA2, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x02, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, + {0x03, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x04, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, + {0x05, {PCIE3, PCIE3, PCIE3, PCIE3, SATA3, SATA4, SATA1, SATA2 } }, + {0x06, {PCIE3, PCIE3, PCIE3, PCIE3, SGMII15, SGMII16, XFI13, + XFI14 } }, + {0x07, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, XFI13, + XFI14 } }, + {0x08, {NONE, NONE, SATA1, SATA2, SATA3, SATA4, XFI13, XFI14 } }, + {0x09, {SGMII11, SGMII12, SGMII17, SGMII18, SGMII15, SGMII16, SGMII13, + SGMII14} }, + {0x0A, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, PCIE4, + PCIE4 } }, + {0x0B, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, SGMII13, + SGMII14 } }, + {0x0C, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, SATA1, + SATA2 } }, + {0x0D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII13, SGMII14 } }, + {0x0E, {PCIE3, PCIE3, SGMII17, SGMII18, PCIE4, PCIE4, SGMII13, + SGMII14 } }, + {} +}; + +static struct serdes_config serdes3_cfg_tbl[] = { + /* SerDes 3 */ + {0x02, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5 } }, + {0x03, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE6, PCIE6, PCIE6, PCIE6 } }, + {} +}; + +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, + serdes2_cfg_tbl, + serdes3_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi new file mode 100644 index 0000000..b407dc6 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP lx2160a SOC common device tree source + * + * Copyright 2018 NXP + * + */ + +/ { + compatible = "fsl,lx2160a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>; + /* DRAM space - 1, size : 2 GB DRAM */ + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + clockgen: clocking@1300000 { + compatible = "fsl,ls2080a-clockgen"; + reg = <0 0x1300000 0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + gic: interrupt-controller@6000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + <0x0 0x06200000 0 0x100000>; /* GICR */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <1 9 0x4>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ + <1 14 0x8>, /* Physical NS PPI, active-low */ + <1 11 0x8>, /* Virtual PPI, active-low */ + <1 10 0x8>; /* Hypervisor PPI, active-low */ + }; + + uart0: serial@21c0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21c0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + }; + + uart1: serial@21d0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21d0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + }; + + uart2: serial@21e0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21e0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + uart3: serial@21f0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21f0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 26 0x4>; /* Level high type */ + num-cs = <6>; + }; + + dspi1: dspi@2110000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <0 240 0x4>; /* Level high type */ + num-cs = <6>; + }; + + dspi2: dspi@2120000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2120000 0x0 0x10000>; + interrupts = <0 241 0x4>; /* Level high type */ + num-cs = <6>; + }; + + usb0: usb3@3100000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; /* Level high type */ + dr_mode = "host"; + }; + + usb1: usb3@3110000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; /* Level high type */ + dr_mode = "host"; + }; +}; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index bd4ca88..d4f80a2 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright 2016-2018 NXP * Copyright 2015, Freescale Semiconductor */ @@ -176,6 +177,61 @@ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ +/* LX2160A Soc Support */ +#elif defined(CONFIG_ARCH_LX2160A) +#define TZPC_BASE 0x02200000 +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_EARLY_INIT +#define SRDS_MAX_LANES 8 +#ifndef L1_CACHE_BYTES +#define L1_CACHE_SHIFT 6 +#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) +#endif +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 } +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 + +#define CONFIG_SYS_PAGE_SIZE 0x10000 + +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ + +/* DDR */ +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE + +#define CONFIG_SYS_FSL_CCSR_GUR_LE +#define CONFIG_SYS_FSL_CCSR_SCFG_LE +#define CONFIG_SYS_FSL_ESDHC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE + +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06200000 + +/* SMMU Definitions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */ + +/* SFP */ +#define CONFIG_SYS_FSL_SFP_VER_3_4 +#define CONFIG_SYS_FSL_SFP_LE +#define CONFIG_SYS_FSL_SRK_LE + +/* Security Monitor */ +#define CONFIG_SYS_FSL_SEC_MON_LE + +/* Secure Boot */ +#define CONFIG_ESBC_HDR_LS + +/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE + +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + #elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index c041a31..68354ff 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -20,8 +20,12 @@ enum srds_prtcl { PCIE2, PCIE3, PCIE4, + PCIE5, + PCIE6, SATA1, SATA2, + SATA3, + SATA4, XAUI1, XAUI2, XFI1, @@ -32,6 +36,12 @@ enum srds_prtcl { XFI6, XFI7, XFI8, + XFI9, + XFI10, + XFI11, + XFI12, + XFI13, + XFI14, SGMII1, SGMII2, SGMII3, @@ -48,10 +58,28 @@ enum srds_prtcl { SGMII14, SGMII15, SGMII16, + SGMII17, + SGMII18, QSGMII_A, QSGMII_B, QSGMII_C, QSGMII_D, + _25GE1, + _25GE2, + _25GE3, + _25GE4, + _25GE5, + _25GE6, + _25GE7, + _25GE8, + _25GE9, + _25GE10, + _40GE1, + _40GE2, + _50GE1, + _50GE2, + _100GE1, + _100GE2, SERDES_PRCTL_COUNT }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 4e01781..2ed6b99 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -15,7 +15,11 @@ #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) +#ifdef CONFIG_ARCH_LX2160A +#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180) +#else #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) +#endif #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) @@ -324,6 +328,28 @@ struct ccsr_gur { #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT #define FSL_CHASSIS3_SRDS1_REGSR 29 #define FSL_CHASSIS3_SRDS2_REGSR 29 +#elif defined(CONFIG_ARCH_LX2160A) +#define FSL_CHASSIS3_EC1_REGSR 27 +#define FSL_CHASSIS3_EC2_REGSR 27 +#define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003 +#define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT 0 +#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x00000007 +#define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT 2 +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000 +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0x03E00000 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 21 +#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK 0x7C000000 +#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT 26 +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK +#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS3_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK +#define FSL_CHASSIS3_SRDS3_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS1_REGSR 29 +#define FSL_CHASSIS3_SRDS2_REGSR 29 +#define FSL_CHASSIS3_SRDS3_REGSR 29 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_CHASSIS3_EC1_REGSR 26 #define FSL_CHASSIS3_EC2_REGSR 26 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index daa1c70..f5bef6d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -96,12 +96,18 @@ enum boot_src get_boot_src(void); #define SVR_LS2044A 0x870930 #define SVR_LS2081A 0x870918 #define SVR_LS2041A 0x870914 +#define SVR_LX2160A 0x873601 +#define SVR_LX2120A 0x873621 +#define SVR_LX2080A 0x873603 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_REV(svr) (((svr) >> 0) & 0xff) #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) +#ifdef CONFIG_ARCH_LX2160A +#define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1)) +#endif #define IS_SVR_REV(svr, maj, min) \ ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) #define SVR_DEV(svr) ((svr) >> 8) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 8d002da..e017d8b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright 2015-2018 NXP * Copyright 2014 Freescale Semiconductor, Inc. * */ @@ -69,11 +70,11 @@ #define FSL_SDMMC_STREAM_ID 3 #define FSL_SATA1_STREAM_ID 4 -#if defined(CONFIG_ARCH_LS2080A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) #define FSL_SATA2_STREAM_ID 5 #endif -#if defined(CONFIG_ARCH_LS2080A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) #define FSL_DMA_STREAM_ID 6 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_DMA_STREAM_ID 5 @@ -82,6 +83,10 @@ /* PCI - programmed in PEXn_LUT */ #define FSL_PEX_STREAM_ID_START 7 +#ifdef CONFIG_ARCH_LX2160A +#define FSL_PEX_STREAM_ID_NUM (0x100) +#endif + #if defined(CONFIG_ARCH_LS2080A) #define FSL_PEX_STREAM_ID_END 22 #elif defined(CONFIG_ARCH_LS1088A) diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index a3d2bd5..c5bd8a8 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -34,6 +34,7 @@ config SYS_NUM_DDR_CTLRS ARCH_P4080 || \ ARCH_P5020 || \ ARCH_P5040 || \ + ARCH_LX2160A || \ ARCH_T4160 default 1 diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile index 477ee4f..1d85b2c 100644 --- a/drivers/net/ldpaa_eth/Makefile +++ b/drivers/net/ldpaa_eth/Makefile @@ -1,8 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ -# +# Copyright 2015-2018 NXP # Copyright 2014 Freescale Semiconductor, Inc. obj-y += ldpaa_wriop.o obj-y += ldpaa_eth.o obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o +obj-$(CONFIG_ARCH_LX2160A) += lx2160a.o diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c new file mode 100644 index 0000000..7dd46c0 --- /dev/null +++ b/drivers/net/ldpaa_eth/lx2160a.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ +#include <common.h> +#include <phy.h> +#include <fsl-mc/ldpaa_wriop.h> +#include <asm/io.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> + +u32 dpmac_to_devdisr[] = { + [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1, + [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2, + [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3, + [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4, + [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5, + [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6, + [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7, + [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8, + [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9, + [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10, + [WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11, + [WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12, + [WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13, + [WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14, + [WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15, + [WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16, + [WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17, + [WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18, +}; + +static int is_device_disabled(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 devdisr2 = in_le32(&gur->devdisr2); + + return dpmac_to_devdisr[dpmac_id] & devdisr2; +} + +void wriop_dpmac_disable(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); +} + +void wriop_dpmac_enable(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); +} + +phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl) +{ + enum srds_prtcl; + + if (is_device_disabled(dpmac_id + 1)) + return PHY_INTERFACE_MODE_NONE; + + if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18) + return PHY_INTERFACE_MODE_SGMII; + + if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14) + return PHY_INTERFACE_MODE_XGMII; + + if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10) + return PHY_INTERFACE_MODE_25G_AUI; + + if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2) + return PHY_INTERFACE_MODE_XLAUI; + + if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2) + return PHY_INTERFACE_MODE_CAUI2; + + if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2) + return PHY_INTERFACE_MODE_CAUI4; + + return PHY_INTERFACE_MODE_NONE; +} + +#ifdef CONFIG_SYS_FSL_HAS_RGMII +void fsl_rgmii_init(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 ec; + +#ifdef CONFIG_SYS_FSL_EC1 + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1]) + & FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK; + ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT; + + if (!ec) + wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID); +#endif + +#ifdef CONFIG_SYS_FSL_EC2 + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1]) + & FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK; + ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT; + + if (!ec) + wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID); +#endif +} +#endif -- 2.7.4

2 1

[U-Boot] [PATCH][v2] armv8:fsl-layerscape: Add support for Chassis 3.2
by Priyanka Jain 10 Dec '18

10 Dec '18

NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash(a)nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- Changes for v2: Rebased on top of test_qoriq branch of u-boot-fsl-qoriq.git arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 3 +++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 18 +++++++++++++-- .../cpu/armv8/fsl-layerscape/doc/README.lsch3_2 | 27 ++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 13 ++++++++++- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 12 ++++++++-- 5 files changed, 68 insertions(+), 5 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 2d1946c..650ac94 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -180,6 +180,9 @@ config FSL_LSCH2 config FSL_LSCH3 bool +config NXP_LSCH3_2 + bool + config FSL_MC_ENET bool "Management Complex network" depends on ARCH_LS2080A || ARCH_LS1088A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index f2ac1a1..60b0575 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -120,6 +120,13 @@ static struct mm_region early_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, +#ifdef CONFIG_SYS_FSL_DRAM_BASE3 + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, + CONFIG_SYS_FSL_DRAM_SIZE3, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_SIZE, @@ -266,6 +273,13 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, +#ifdef CONFIG_SYS_FSL_DRAM_BASE3 + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, + CONFIG_SYS_FSL_DRAM_SIZE3, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_SIZE, @@ -595,13 +609,13 @@ enum boot_src __get_boot_src(u32 porsr1) { enum boot_src src = BOOT_SOURCE_RESERVED; uint32_t rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT; -#if !defined(CONFIG_FSL_LSCH3_2) +#if !defined(CONFIG_NXP_LSCH3_2) uint32_t val; #endif debug("%s: rcw_src 0x%x\n", __func__, rcw_src); #if defined(CONFIG_FSL_LSCH3) -#if defined(CONFIG_FSL_LSCH3_2) +#if defined(CONFIG_NXP_LSCH3_2) switch (rcw_src) { case RCW_SRC_SDHC1_VAL: src = BOOT_SOURCE_SD_MMC; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 new file mode 100644 index 0000000..6d4bd0b --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 @@ -0,0 +1,27 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +NXP LayerScape with Chassis Generation 3.2 + +This architecture supports NXP ARMv8 SoCs with Chassis generation 3.2 +for example LX2160A. + +This architecture is enhancement over Chassis Generation 3 with +few differences mentioned below + +1)DDR Layout +============ +Entire DDR region splits into three regions. + - Region 1 is at address 0x8000_0000 to 0xffff_ffff. + - Region 2 is at address 0x20_8000_0000 to 0x3f_ffff_ffff, + - Region 3 is at address 0x60_0000_0000 to the top of memory, + for example 140GB, 0x63_7fff_ffff. + +All DDR memory is marked as cache-enabled. + +2)IFC is removed + +3)Number of I2C controllers increased to 8 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 3926aa3..eaa9ed2 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017-2018 NXP * Copyright 2014-2015, Freescale Semiconductor */ @@ -12,15 +12,19 @@ #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 +#ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 +#endif #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 +#ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 +#endif #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 #define CONFIG_SYS_FSL_MC_BASE 0x80c000000 @@ -40,8 +44,15 @@ #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 +#ifdef CONFIG_NXP_LSCH3_2 +#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000 +#define CONFIG_SYS_FSL_DRAM_SIZE2 0x1F80000000 +#define CONFIG_SYS_FSL_DRAM_BASE3 0x6000000000 +#define CONFIG_SYS_FSL_DRAM_SIZE3 0x2000000000 +#else #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 +#endif #elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_BOOTROM_BASE 0x0 #define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 816d960..4e01781 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -2,7 +2,7 @@ /* * LayerScape Internal Memory Map * - * Copyright (C) 2017 NXP Semiconductors + * Copyright 2017-2018 NXP * Copyright 2014 Freescale Semiconductor, Inc. */ @@ -21,7 +21,9 @@ #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) +#ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) +#endif #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000 @@ -45,6 +47,12 @@ #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) +#ifdef CONFIG_NXP_LSCH3_2 +#define I2C5_BASE_ADDR (CONFIG_SYS_IMMR + 0x01040000) +#define I2C6_BASE_ADDR (CONFIG_SYS_IMMR + 0x01050000) +#define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000) +#define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000) +#endif #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000) #define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0) #define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8) @@ -83,7 +91,7 @@ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) #ifdef CONFIG_TFABOOT -#ifdef CONFIG_FSL_LSCH3_2 +#ifdef CONFIG_NXP_LSCH3_2 /* RCW_SRC field in Power-On Reset Control Register 1 */ #define RCW_SRC_MASK 0x07800000 #define RCW_SRC_BIT 23 -- 2.7.4

2 1

[U-Boot] [PATCH] board/freescale/vid: Add vdd table for NXP LX2160A SoC
by Priyanka Jain 10 Dec '18

10 Dec '18

Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- board/freescale/common/vid.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index eb5cf88..8d90135 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -379,6 +379,42 @@ int adjust_vdd(ulong vdd_override) int ret, i2caddress; unsigned long vdd_string_override; char *vdd_string; +#ifdef CONFIG_ARCH_LX2160A + static const u16 vdd[32] = { + 8250, + 7875, + 7750, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 8000, + 8125, + 8250, + 0, /* reserved */ + 8500, + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + 0, /* reserved */ + }; +#else #ifdef CONFIG_ARCH_LS1088A static const uint16_t vdd[32] = { 10250, @@ -451,6 +487,7 @@ int adjust_vdd(ulong vdd_override) 0, /* reserved */ }; #endif +#endif struct vdd_drive { u8 vid; unsigned voltage; -- 2.7.4

2 1

[U-Boot] [PATCH][v2] armv8: lsch3: Add support of serdes3 module
by Priyanka Jain 10 Dec '18

10 Dec '18

Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- Changes for v2: Updated copyright Renamed CONFIG_SYS_FSL_SRDS_3 to CONFIG_SYS_NXP_SRDS_3 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 3 + .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 71 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 + 3 files changed, 76 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f2111fa..fd31ae1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -348,6 +348,9 @@ config SYS_FSL_SRDS_1 config SYS_FSL_SRDS_2 bool +config SYS_NXP_SRDS_3 + bool + config SYS_HAS_SERDES bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index 2bef841..bfd2868 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * Copyright 2016-2018 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. */ @@ -16,6 +17,9 @@ static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; #ifdef CONFIG_SYS_FSL_SRDS_2 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 +static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT]; +#endif #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) int xfi_dpmac[XFI8 + 1]; @@ -57,6 +61,12 @@ int is_serdes_configured(enum srds_prtcl device) ret |= serdes2_prtcl_map[device]; #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + if (!serdes3_prtcl_map[NONE]) + fsl_serdes_init(); + + ret |= serdes3_prtcl_map[device]; +#endif return !!ret; } @@ -82,6 +92,13 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device) cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT; break; #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + case NXP_SRDS_3: + cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]); + cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT; + break; +#endif default: printf("invalid SerDes%d\n", sd); break; @@ -201,6 +218,12 @@ struct serdes_prctl_info srds_prctl_info[] = { .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT }, #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + {.id = 3, + .mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK, + .shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT + }, +#endif {} /* NULL ENTRY */ }; @@ -341,6 +364,11 @@ int setup_serdes_volt(u32 svdd) (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000); u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + struct ccsr_serdes __iomem *serdes3_base = + (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000); + u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]); +#endif u32 cfg_tmp; int svdd_cur, svdd_tar; int ret = 1; @@ -370,6 +398,9 @@ int setup_serdes_volt(u32 svdd) #ifdef CONFIG_SYS_FSL_SRDS_2 do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false); +#endif /* Put the all enabled PLL in reset */ #ifdef CONFIG_SYS_FSL_SRDS_1 @@ -383,6 +414,12 @@ int setup_serdes_volt(u32 svdd) do_pll_reset(cfg_tmp, serdes2_base); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_pll_reset(cfg_tmp, serdes3_base); +#endif + /* Put the Rx/Tx calibration into reset */ #ifdef CONFIG_SYS_FSL_SRDS_1 do_rx_tx_cal_reset(serdes1_base); @@ -392,6 +429,10 @@ int setup_serdes_volt(u32 svdd) do_rx_tx_cal_reset(serdes2_base); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + do_rx_tx_cal_reset(serdes3_base); +#endif + ret = set_serdes_volt(svdd); if (ret < 0) { printf("could not change SVDD\n"); @@ -408,6 +449,11 @@ int setup_serdes_volt(u32 svdd) cfg_tmp >>= 2; do_serdes_enable(cfg_tmp, serdes2_base); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_serdes_enable(cfg_tmp, serdes3_base); +#endif /* Wait for at at least 625us, ensure the PLLs being reset are locked */ udelay(800); @@ -422,6 +468,13 @@ int setup_serdes_volt(u32 svdd) cfg_tmp >>= 2; do_pll_lock(cfg_tmp, serdes2_base); #endif + +#ifdef CONFIG_SYS_NXP_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_pll_lock(cfg_tmp, serdes3_base); +#endif + /* Take the all enabled lanes out of reset */ #ifdef CONFIG_SYS_FSL_SRDS_1 do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true); @@ -430,6 +483,10 @@ int setup_serdes_volt(u32 svdd) do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true); +#endif + /* For each PLL being reset, and achieved PLL lock set RST_DONE */ #ifdef CONFIG_SYS_FSL_SRDS_1 cfg_tmp = cfg_rcwsrds1 & 0x3; @@ -441,6 +498,12 @@ int setup_serdes_volt(u32 svdd) do_pll_reset_done(cfg_tmp, serdes2_base); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + cfg_tmp = cfg_rcwsrds3 & 0x30; + cfg_tmp >>= 4; + do_pll_reset_done(cfg_tmp, serdes3_base); +#endif + return ret; } @@ -472,4 +535,12 @@ void fsl_serdes_init(void) FSL_CHASSIS3_SRDS2_PRTCL_SHIFT, serdes2_prtcl_map); #endif +#ifdef CONFIG_SYS_NXP_SRDS_3 + serdes_init(NXP_SRDS_3, + CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000, + FSL_CHASSIS3_SRDS3_REGSR, + FSL_CHASSIS3_SRDS3_PRTCL_MASK, + FSL_CHASSIS3_SRDS3_PRTCL_SHIFT, + serdes3_prtcl_map); +#endif } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 6981076..bec35e8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright 2018 NXP * Copyright 2015 Freescale Semiconductor, Inc. */ @@ -57,6 +58,7 @@ enum srds_prtcl { enum srds { FSL_SRDS_1 = 0, FSL_SRDS_2 = 1, + NXP_SRDS_3 = 2, }; #elif defined(CONFIG_FSL_LSCH2) enum srds_prtcl { -- 2.7.4

2 1

[U-Boot] [PATCH] board/freescale/vid: Add correction for ltc3882 read error.
by Priyanka Jain 10 Dec '18

10 Dec '18

Voltage regulator LTC3882 device has 0.5% voltage read error. So for NXP SoC devices this generally equates to 2mV Update set_voltage_to_LTC for below: 1.Add coorection of upto 2mV in voltage comparison to take care of voltage read error of voltage regulator 2.Add loop max count kept as 100 to avoid infinte loop. Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- board/freescale/common/vid.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index eb5cf88..db158cb 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -318,6 +318,7 @@ static int set_voltage_to_IR(int i2caddress, int vdd) static int set_voltage_to_LTC(int i2caddress, int vdd) { int ret, vdd_last, vdd_target = vdd; + int count = 100, temp = 0; /* Scale up to the LTC resolution is 1/4096V */ vdd = (vdd * 4096) / 1000; @@ -343,7 +344,9 @@ static int set_voltage_to_LTC(int i2caddress, int vdd) printf("VID: Couldn't read sensor abort VID adjust\n"); return -1; } - } while (vdd_last != vdd_target); + count--; + temp = vdd_last - vdd_target; + } while ((abs(temp) > 2) && (count > 0)); return vdd_last; } -- 1.9.1

2 1

[U-Boot] [PATCH] ls1088a: Move CONFIG_FSL_QSPI to defconfig
by Ashish Kumar 10 Dec '18

10 Dec '18

Signed-off-by: Rajat Srivastava <rajat.srivastava(a)nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> --- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088aqds_qspi_defconfig | 1 + configs/ls1088aqds_sdcard_qspi_defconfig | 1 + configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_qspi_defconfig | 1 + configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_sdcard_qspi_defconfig | 1 + include/configs/ls1088aqds.h | 1 - include/configs/ls1088ardb.h | 1 - 9 files changed, 7 insertions(+), 2 deletions(-) diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index 0214e4185d..89e4b09954 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -44,6 +44,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index 234f44bc07..8f6f737650 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -44,6 +44,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index 397ce2d088..c93e5a6285 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index 6d1889e603..9f6ef7b5bc 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -45,6 +45,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 630e0ee61e..42e6d416d0 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -45,6 +45,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index fcf9ee5019..bb796ccf94 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -58,6 +58,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index 2ab5fd8cff..3e2290fa96 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -55,6 +55,7 @@ CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 25f680c864..69572cb3e3 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -327,7 +327,6 @@ unsigned long get_board_ddr_clk(void); /* QSPI device */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_FSL_QSPI #define FSL_QSPI_FLASH_SIZE (1 << 26) #define FSL_QSPI_FLASH_NUM 2 diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index eb220bf6e9..fb693d7ecb 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -278,7 +278,6 @@ #ifndef SPL_NO_QSPI /* QSPI device */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_FSL_QSPI #define FSL_QSPI_FLASH_SIZE (1 << 26) #define FSL_QSPI_FLASH_NUM 2 #endif -- 2.17.1

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