October 2018 - U-Boot

[U-Boot] [PATCH] arm: socfpga: fix SPL booting from fpga OnChip RAM
by Simon Goldschmidt 08 Oct '18

08 Oct '18

This patch prevents disabling the FPGA bridges when SPL or U-Boot is executed from FPGA onchip RAM. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- There are other patches required to make boot from FPGA work correctly: - CONFIG_SPL_TEXT_BASE needs to be set to 0xC0000000 ideally this is done by moving SPL_TEXT_BASE to Kconfig: https://patchwork.ozlabs.org/patch/976918/ - spl_ram.c needs this patch by Michal Simek: https://patchwork.ozlabs.org/patch/978694/ - For U-Boot to be run from FPGA onchip RAM, either CONFIG_SYS_EXTRA_ENV_RELOC needs to be used or this patch is required to relocate gd->env_addr: https://patchwork.ozlabs.org/patch/975702/ --- arch/arm/mach-socfpga/include/mach/base_addr_ac5.h | 1 + arch/arm/mach-socfpga/misc_gen5.c | 8 ++++++++ arch/arm/mach-socfpga/spl_gen5.c | 4 ++++ 3 files changed, 13 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h index bb9e3faa29..2725e9fcc3 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h @@ -6,6 +6,7 @@ #ifndef _SOCFPGA_BASE_ADDRS_H_ #define _SOCFPGA_BASE_ADDRS_H_ +#define SOCFPGA_FPGA_SLAVES_ADDRESS 0xc0000000 #define SOCFPGA_STM_ADDRESS 0xfc000000 #define SOCFPGA_DAP_ADDRESS 0xff000000 #define SOCFPGA_EMAC0_ADDRESS 0xff700000 diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 429c3d6cd5..fa66484783 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -187,7 +187,15 @@ void socfpga_sdram_remap_zero(void) setbits_le32(&scu_regs->sacr, 0xfff); /* Configure the L2 controller to make SDRAM start at 0 */ +#if (defined(CONFIG_SPL_BUILD) && \ + (CONFIG_SPL_TEXT_BASE == SOCFPGA_FPGA_SLAVES_ADDRESS)) || \ + ((CONFIG_SYS_TEXT_BASE >= SOCFPGA_FPGA_SLAVES_ADDRESS) && \ + (CONFIG_SYS_TEXT_BASE < SOCFPGA_STM_ADDRESS)) + /* remap.mpuzero, keep fpga bridge enabled */ + writel(0x9, &nic301_regs->remap); +#else writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ +#endif writel(0x1, &pl310->pl310_addr_filter_start); } diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index be318cc0d9..41e7787f11 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -92,8 +92,10 @@ void board_init_f(ulong dummy) /* Put everything into reset but L4WD0. */ socfpga_per_reset_all(); +#if CONFIG_SPL_TEXT_BASE != SOCFPGA_FPGA_SLAVES_ADDRESS /* Put FPGA bridges into reset too. */ socfpga_bridges_reset(1); +#endif socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0); @@ -163,5 +165,7 @@ void board_init_f(ulong dummy) hang(); } +#if CONFIG_SPL_TEXT_BASE != SOCFPGA_FPGA_SLAVES_ADDRESS socfpga_bridges_reset(1); +#endif } -- 2.17.1

3 7

[U-Boot] Keystone 2 sram scratch address?
by Tom Rini 08 Oct '18

08 Oct '18

Hey folks, So as part of Simon's patch[1] to move CONFIG_SPL_TEXT_BASE to Kconfig I've run into a problem on Keystone 2 platforms, specifically the HS variants. What keystone does is define the SRAM scratch address relative to the end of our regular SRAM usage for SPL. This is I think in part due to the large variation in the SRAM size on these parts contain and a desire to be able to more easily support the larger sizes. This is fine on the non-HS parts where we enable and build SPL so can play these games. But on the HS parts (or at least k2l_hs_evm k2e_hs_evm k2hk_hs_evm k2g_hs_evm) we don't use SPL, so once moving CONFIG_SPL_TEXT_BASE to Kconfig we don't have it defined and a few places fall apart. Can we find some constant we could use for CONFIG_SYS_INIT_SP_ADDR and then for the EEPROM copy we make on K2G? Thanks! [1]: https://patchwork.ozlabs.org/patch/976918/ -- Tom

2 2

[U-Boot] [PATCH 1/3] arm64: zynqmp: Move TCM initialization to a separate routine
by Michal Simek 08 Oct '18

08 Oct '18

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> This patch moves TCM initialization to a separate routine to make it modular and can be reused if required. It also prints warning message now as it writes to TCM. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/cpu/armv8/zynqmp/cpu.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index 43ba739d2f7c..3ed631e505af 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -105,10 +105,16 @@ u64 get_page_table_size(void) } #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU -int reserve_mmu(void) +static void tcm_init(u8 mode) { - initialize_tcm(TCM_LOCK); + puts("WARNING: Initializing TCM overwrites TCM content\n"); + initialize_tcm(mode); memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE); +} + +int reserve_mmu(void) +{ + tcm_init(TCM_LOCK); gd->arch.tlb_size = PGTABLE_SIZE; gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR; -- 1.9.1

1 2

[U-Boot] [PATCH v2] sf: Add auto detection of 4-byte mode (vs standard 3-byte mode)
by Stefan Roese 08 Oct '18

08 Oct '18

Some SPI NOR chips only support 4-byte mode addressing. Here the default 3-byte mode does not work and leads to incorrect accesses. This patch now reads the 4-byte mode status bit (in this case in the CR register of the Macronix SPI NOR) and configures the SPI transfers accordingly. This was noticed on the LinkIt Smart 7688 modul, which is equipped with an Macronix MX25L25635F device. But this device does *NOT* support switching to 3-byte mode via the EX4B command. This should also work when the bootrom configures the SPI flash to 4-byte mode and runs U-Boot after this. U-Boot should dectect this mode (if the 4-byte mode detection is available for this chip) and use the correct OPs in this case. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Jagan Teki <jagan(a)openedev.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- v2: - Integrated STMICRO 4-byte detection from Simon drivers/mtd/spi/sf_internal.h | 3 +- drivers/mtd/spi/spi_flash.c | 131 ++++++++++++++++++++++++++++------ include/spi_flash.h | 5 ++ 3 files changed, 118 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 4f63cacc64..eb076401d1 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -26,7 +26,8 @@ enum spi_nor_option_flags { }; #define SPI_FLASH_3B_ADDR_LEN 3 -#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) +#define SPI_FLASH_4B_ADDR_LEN 4 +#define SPI_FLASH_CMD_MAX_LEN (1 + SPI_FLASH_4B_ADDR_LEN) #define SPI_FLASH_16MB_BOUN 0x1000000 /* CFI Manufacture ID's */ diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index c159124259..e41c5a961b 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -20,12 +20,19 @@ #include "sf_internal.h" -static void spi_flash_addr(u32 addr, u8 *cmd) +static void spi_flash_addr(struct spi_flash *flash, u32 addr, u8 *cmd) { /* cmd[0] is actual command */ - cmd[1] = addr >> 16; - cmd[2] = addr >> 8; - cmd[3] = addr >> 0; + if (flash->in_4byte_mode) { + cmd[1] = addr >> 24; + cmd[2] = addr >> 16; + cmd[3] = addr >> 8; + cmd[4] = addr >> 0; + } else { + cmd[1] = addr >> 16; + cmd[2] = addr >> 8; + cmd[3] = addr >> 0; + } } static int read_sr(struct spi_flash *flash, u8 *rs) @@ -110,6 +117,72 @@ static int write_cr(struct spi_flash *flash, u8 wc) } #endif +#if defined(CONFIG_SPI_FLASH_MACRONIX) +static bool flash_in_4byte_mode_macronix(struct spi_flash *flash) +{ + int ret; + u8 cr; + u8 cmd; + + cmd = 0x15; /* Macronix: read configuration register RDCR */ + ret = spi_flash_read_common(flash, &cmd, 1, &cr, 1); + if (ret < 0) { + debug("SF: fail to read config register\n"); + return false; + } + + /* Return true, if 4-byte mode is enabled */ + if (cr & BIT(5)) + return true; + + return false; +} +#else +static bool flash_in_4byte_mode_macronix(struct spi_flash *flash) +{ + return false; +} +#endif + +#if defined(CONFIG_SPI_FLASH_STMICRO) +static bool flash_in_4byte_mode_stmicro(struct spi_flash *flash) +{ + int ret; + u8 fsr; + u8 cmd; + + cmd = 0x70; /* STMicro/Micron: read flag status register */ + ret = spi_flash_read_common(flash, &cmd, 1, &fsr, 1); + if (ret < 0) { + debug("SF: fail to read config register\n"); + return false; + } + + /* Return true, if 4-byte mode is enabled */ + if (fsr & BIT(0)) + return true; + + return false; +} +#else +static bool flash_in_4byte_mode_stmicro(struct spi_flash *flash) +{ + return false; +} +#endif + +static bool flash_in_4byte_mode(struct spi_flash *flash, + const struct spi_flash_info *info) +{ + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) + return flash_in_4byte_mode_macronix(flash); + + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_STMICRO) + return flash_in_4byte_mode_stmicro(flash); + + return false; +} + #ifdef CONFIG_SPI_FLASH_BAR /* * This "clean_bar" is necessary in a situation when one was accessing @@ -314,7 +387,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) { u32 erase_size, erase_addr; - u8 cmd[SPI_FLASH_CMD_LEN]; + u8 cmd[SPI_FLASH_CMD_MAX_LEN]; int ret = -1; erase_size = flash->erase_size; @@ -344,12 +417,13 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) if (ret < 0) return ret; #endif - spi_flash_addr(erase_addr, cmd); + spi_flash_addr(flash, erase_addr, cmd); debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], cmd[2], cmd[3], erase_addr); - ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); + ret = spi_flash_write_common(flash, cmd, flash->cmdlen, + NULL, 0); if (ret < 0) { debug("SF: erase failed\n"); break; @@ -373,7 +447,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, unsigned long byte_addr, page_size; u32 write_addr; size_t chunk_len, actual; - u8 cmd[SPI_FLASH_CMD_LEN]; + u8 cmd[SPI_FLASH_CMD_MAX_LEN]; int ret = -1; page_size = flash->page_size; @@ -404,15 +478,15 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, if (spi->max_write_size) chunk_len = min(chunk_len, - spi->max_write_size - sizeof(cmd)); + spi->max_write_size - flash->cmdlen); - spi_flash_addr(write_addr, cmd); + spi_flash_addr(flash, write_addr, cmd); debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); - ret = spi_flash_write_common(flash, cmd, sizeof(cmd), - buf + actual, chunk_len); + ret = spi_flash_write_common(flash, cmd, flash->cmdlen, + buf + actual, chunk_len); if (ret < 0) { debug("SF: write failed\n"); break; @@ -469,9 +543,11 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, { struct spi_slave *spi = flash->spi; u8 *cmd, cmdsz; - u32 remain_len, read_len, read_addr; + u64 remain_len; + u32 read_len, read_addr; int bank_sel = 0; int ret = -1; + int shift; /* Handle memory-mapped SPI */ if (flash->memory_map) { @@ -487,7 +563,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, return 0; } - cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; + cmdsz = flash->cmdlen + flash->dummy_byte; cmd = calloc(1, cmdsz); if (!cmd) { debug("SF: Failed to allocate cmd\n"); @@ -508,8 +584,13 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, return ret; bank_sel = flash->bank_curr; #endif - remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * - (bank_sel + 1)) - offset; + shift = flash->shift; + if (flash->in_4byte_mode) + shift += 8; + + remain_len = (((u64)SPI_FLASH_16MB_BOUN << shift) * + (bank_sel + 1)) - offset; + if (len < remain_len) read_len = len; else @@ -518,7 +599,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, if (spi->max_read_size) read_len = min(read_len, spi->max_read_size); - spi_flash_addr(read_addr, cmd); + spi_flash_addr(flash, read_addr, cmd); ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); if (ret < 0) { @@ -1160,6 +1241,13 @@ int spi_flash_scan(struct spi_flash *flash) write_sr(flash, sr); } + /* Set default value for cmd length */ + flash->cmdlen = 1 + SPI_FLASH_3B_ADDR_LEN; + if (flash_in_4byte_mode(flash, info)) { + flash->in_4byte_mode = true; + flash->cmdlen = 1 + SPI_FLASH_4B_ADDR_LEN; + } + flash->name = info->name; flash->memory_map = spi->memory_map; @@ -1311,14 +1399,17 @@ int spi_flash_scan(struct spi_flash *flash) print_size(flash->size, ""); if (flash->memory_map) printf(", mapped at %p", flash->memory_map); + if (flash->in_4byte_mode) + printf(" (4-byte mode)"); puts("\n"); #endif #ifndef CONFIG_SPI_FLASH_BAR - if (((flash->dual_flash == SF_SINGLE_FLASH) && - (flash->size > SPI_FLASH_16MB_BOUN)) || + if ((((flash->dual_flash == SF_SINGLE_FLASH) && + (flash->size > SPI_FLASH_16MB_BOUN)) || ((flash->dual_flash > SF_SINGLE_FLASH) && - (flash->size > SPI_FLASH_16MB_BOUN << 1))) { + (flash->size > SPI_FLASH_16MB_BOUN << 1))) && + !flash->in_4byte_mode) { puts("SF: Warning - Only lower 16MiB accessible,"); puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); } diff --git a/include/spi_flash.h b/include/spi_flash.h index 0ec98fb55d..b5bc4a85f6 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -36,6 +36,8 @@ struct spi_slave; * @dual_flash: Indicates dual flash memories - dual stacked, parallel * @shift: Flash shift useful in dual parallel * @flags: Indication of spi flash flags + * @in_4byte_mode: True if flash is detected to be in 4-byte mode + * @cmdlen: CMD length (3-byte vs 4-byte mode) * @size: Total flash size * @page_size: Write (page) size * @sector_size: Sector size @@ -69,6 +71,9 @@ struct spi_flash { u8 shift; u16 flags; + bool in_4byte_mode; + int cmdlen; + u32 size; u32 page_size; u32 sector_size; -- 2.19.1

2 1

[U-Boot] [PATCH] sf: Add auto detection of 4-byte mode (vs standard 3-byte mode)
by Stefan Roese 08 Oct '18

08 Oct '18

Some SPI NOR chips only support 4-byte mode addressing. Here the default 3-byte mode does not work and leads to incorrect accesses. This patch now reads the 4-byte mode status bit (in this case in the CR register of the Macronix SPI NOR) and configures the SPI transfers accordingly. This was noticed on the LinkIt Smart 7688 modul, which is equipped with an Macronix MX25L25635F device. But this device does *NOT* support switching to 3-byte mode via the EX4B command. This should also work when the bootrom configures the SPI flash to 4-byte mode and runs U-Boot after this. U-Boot should dectect this mode (if the 4-byte mode detection is available for this chip) and use the correct OPs in this case. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Jagan Teki <jagan(a)openedev.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- Please note that this patch replaces this one: [PATCH] sf: Add SPI_FLASH_4BYTE_MODE_ONLY option to support 4-byte mode which introduced a CONFIG option to enable this 4-byte mode. In discussion with Simon we agreed, that an auto detection would be much better. Hence this new version now. drivers/mtd/spi/sf_internal.h | 3 +- drivers/mtd/spi/spi_flash.c | 94 +++++++++++++++++++++++++++-------- include/spi_flash.h | 5 ++ 3 files changed, 81 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 4f63cacc64..eb076401d1 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -26,7 +26,8 @@ enum spi_nor_option_flags { }; #define SPI_FLASH_3B_ADDR_LEN 3 -#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) +#define SPI_FLASH_4B_ADDR_LEN 4 +#define SPI_FLASH_CMD_MAX_LEN (1 + SPI_FLASH_4B_ADDR_LEN) #define SPI_FLASH_16MB_BOUN 0x1000000 /* CFI Manufacture ID's */ diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index c159124259..357b4f2422 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -20,12 +20,19 @@ #include "sf_internal.h" -static void spi_flash_addr(u32 addr, u8 *cmd) +static void spi_flash_addr(struct spi_flash *flash, u32 addr, u8 *cmd) { /* cmd[0] is actual command */ - cmd[1] = addr >> 16; - cmd[2] = addr >> 8; - cmd[3] = addr >> 0; + if (flash->in_4byte_mode) { + cmd[1] = addr >> 24; + cmd[2] = addr >> 16; + cmd[3] = addr >> 8; + cmd[4] = addr >> 0; + } else { + cmd[1] = addr >> 16; + cmd[2] = addr >> 8; + cmd[3] = addr >> 0; + } } static int read_sr(struct spi_flash *flash, u8 *rs) @@ -110,6 +117,33 @@ static int write_cr(struct spi_flash *flash, u8 wc) } #endif +#if defined(CONFIG_SPI_FLASH_MACRONIX) +static bool flash_in_4byte_mode(struct spi_flash *flash) +{ + int ret; + u8 cr; + u8 cmd; + + cmd = 0x15; /* Macronix: read configuration register RDCR */ + ret = spi_flash_read_common(flash, &cmd, 1, &cr, 1); + if (ret < 0) { + debug("SF: fail to read config register\n"); + return false; + } + + /* Return true, if 4-byte mode is enabled */ + if (cr & BIT(5)) + return true; + + return false; +} +#else +static bool flash_in_4byte_mode(struct spi_flash *flash) +{ + return false; +} +#endif + #ifdef CONFIG_SPI_FLASH_BAR /* * This "clean_bar" is necessary in a situation when one was accessing @@ -314,7 +348,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) { u32 erase_size, erase_addr; - u8 cmd[SPI_FLASH_CMD_LEN]; + u8 cmd[SPI_FLASH_CMD_MAX_LEN]; int ret = -1; erase_size = flash->erase_size; @@ -344,12 +378,13 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) if (ret < 0) return ret; #endif - spi_flash_addr(erase_addr, cmd); + spi_flash_addr(flash, erase_addr, cmd); debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], cmd[2], cmd[3], erase_addr); - ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); + ret = spi_flash_write_common(flash, cmd, flash->cmdlen, + NULL, 0); if (ret < 0) { debug("SF: erase failed\n"); break; @@ -373,7 +408,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, unsigned long byte_addr, page_size; u32 write_addr; size_t chunk_len, actual; - u8 cmd[SPI_FLASH_CMD_LEN]; + u8 cmd[SPI_FLASH_CMD_MAX_LEN]; int ret = -1; page_size = flash->page_size; @@ -404,15 +439,15 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, if (spi->max_write_size) chunk_len = min(chunk_len, - spi->max_write_size - sizeof(cmd)); + spi->max_write_size - flash->cmdlen); - spi_flash_addr(write_addr, cmd); + spi_flash_addr(flash, write_addr, cmd); debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); - ret = spi_flash_write_common(flash, cmd, sizeof(cmd), - buf + actual, chunk_len); + ret = spi_flash_write_common(flash, cmd, flash->cmdlen, + buf + actual, chunk_len); if (ret < 0) { debug("SF: write failed\n"); break; @@ -469,9 +504,11 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, { struct spi_slave *spi = flash->spi; u8 *cmd, cmdsz; - u32 remain_len, read_len, read_addr; + u64 remain_len; + u32 read_len, read_addr; int bank_sel = 0; int ret = -1; + int shift; /* Handle memory-mapped SPI */ if (flash->memory_map) { @@ -487,7 +524,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, return 0; } - cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; + cmdsz = flash->cmdlen + flash->dummy_byte; cmd = calloc(1, cmdsz); if (!cmd) { debug("SF: Failed to allocate cmd\n"); @@ -508,8 +545,13 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, return ret; bank_sel = flash->bank_curr; #endif - remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * - (bank_sel + 1)) - offset; + shift = flash->shift; + if (flash->in_4byte_mode) + shift += 8; + + remain_len = (((u64)SPI_FLASH_16MB_BOUN << shift) * + (bank_sel + 1)) - offset; + if (len < remain_len) read_len = len; else @@ -518,7 +560,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, if (spi->max_read_size) read_len = min(read_len, spi->max_read_size); - spi_flash_addr(read_addr, cmd); + spi_flash_addr(flash, read_addr, cmd); ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); if (ret < 0) { @@ -1160,6 +1202,15 @@ int spi_flash_scan(struct spi_flash *flash) write_sr(flash, sr); } + /* Set default value for cmd length */ + flash->cmdlen = 1 + SPI_FLASH_3B_ADDR_LEN; + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { + if (flash_in_4byte_mode(flash)) { + flash->in_4byte_mode = true; + flash->cmdlen = 1 + SPI_FLASH_4B_ADDR_LEN; + } + } + flash->name = info->name; flash->memory_map = spi->memory_map; @@ -1311,14 +1362,17 @@ int spi_flash_scan(struct spi_flash *flash) print_size(flash->size, ""); if (flash->memory_map) printf(", mapped at %p", flash->memory_map); + if (flash->in_4byte_mode) + printf(" (4-byte mode)"); puts("\n"); #endif #ifndef CONFIG_SPI_FLASH_BAR - if (((flash->dual_flash == SF_SINGLE_FLASH) && - (flash->size > SPI_FLASH_16MB_BOUN)) || + if ((((flash->dual_flash == SF_SINGLE_FLASH) && + (flash->size > SPI_FLASH_16MB_BOUN)) || ((flash->dual_flash > SF_SINGLE_FLASH) && - (flash->size > SPI_FLASH_16MB_BOUN << 1))) { + (flash->size > SPI_FLASH_16MB_BOUN << 1))) && + !flash->in_4byte_mode) { puts("SF: Warning - Only lower 16MiB accessible,"); puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); } diff --git a/include/spi_flash.h b/include/spi_flash.h index 0ec98fb55d..b5bc4a85f6 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -36,6 +36,8 @@ struct spi_slave; * @dual_flash: Indicates dual flash memories - dual stacked, parallel * @shift: Flash shift useful in dual parallel * @flags: Indication of spi flash flags + * @in_4byte_mode: True if flash is detected to be in 4-byte mode + * @cmdlen: CMD length (3-byte vs 4-byte mode) * @size: Total flash size * @page_size: Write (page) size * @sector_size: Sector size @@ -69,6 +71,9 @@ struct spi_flash { u8 shift; u16 flags; + bool in_4byte_mode; + int cmdlen; + u32 size; u32 page_size; u32 sector_size; -- 2.19.0

2 2

[U-Boot] [PATCH 1/4] sunxi: display: Fix h/vsync TCON polarity bits to indicate active-high
by Paul Kocialkowski 08 Oct '18

08 Oct '18

Contrary to what is implemented in the Linux kernel, the U-Boot driver supporting the sunxi TCON was assuming that the TCON0_IO_POL bits indicate active-low signals when set for the hsync and vsync signals. After looking at it with a logic analyzer, it appears that the signals are active-low with the bits unset and active-high with the bits set. Fix this by looking for the right flag (high instead of low) and inverting the sync bits in the VIDEO_LCD_MODE declarations. Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- configs/A33-OLinuXino_defconfig | 2 +- configs/Ainol_AW1_defconfig | 2 +- configs/Ampe_A76_defconfig | 2 +- configs/Chuwi_V7_CW0825_defconfig | 2 +- configs/Colombus_defconfig | 2 +- configs/Empire_electronix_d709_defconfig | 2 +- configs/Empire_electronix_m712_defconfig | 2 +- configs/Hyundai_A7HD_defconfig | 2 +- configs/MSI_Primo73_defconfig | 2 +- configs/MSI_Primo81_defconfig | 2 +- configs/Sinlinx_SinA33_defconfig | 2 +- configs/UTOO_P66_defconfig | 2 +- configs/Wexler_TAB7200_defconfig | 2 +- configs/Wits_Pro_A20_DKT_defconfig | 2 +- configs/Yones_Toptech_BD1078_defconfig | 2 +- configs/Yones_Toptech_BS1078_V2_defconfig | 2 +- configs/colorfly_e708_q1_defconfig | 2 +- configs/difrnce_dit4350_defconfig | 2 +- configs/dserve_dsrv9703c_defconfig | 2 +- configs/ga10h_v1_1_defconfig | 2 +- configs/gt90h_v4_defconfig | 2 +- configs/iNet_3F_defconfig | 2 +- configs/iNet_3W_defconfig | 2 +- configs/iNet_86VS_defconfig | 2 +- configs/iNet_D978_rev2_defconfig | 2 +- configs/icnova-a20-swac_defconfig | 2 +- configs/inet1_defconfig | 2 +- configs/inet86dz_defconfig | 2 +- configs/inet97fv2_defconfig | 2 +- configs/inet98v_rev2_defconfig | 2 +- configs/inet9f_rev03_defconfig | 2 +- configs/inet_q972_defconfig | 2 +- configs/polaroid_mid2407pxe03_defconfig | 2 +- configs/polaroid_mid2809pxe04_defconfig | 2 +- configs/pov_protab2_ips9_defconfig | 2 +- configs/q8_a13_tablet_defconfig | 2 +- configs/q8_a23_tablet_800x480_defconfig | 2 +- configs/q8_a33_tablet_1024x600_defconfig | 2 +- configs/q8_a33_tablet_800x480_defconfig | 2 +- configs/sunxi_Gemei_G9_defconfig | 2 +- drivers/video/sunxi/lcdc.c | 4 ++-- 41 files changed, 42 insertions(+), 42 deletions(-) diff --git a/configs/A33-OLinuXino_defconfig b/configs/A33-OLinuXino_defconfig index 744e7ef511..e456703be7 100644 --- a/configs/A33-OLinuXino_defconfig +++ b/configs/A33-OLinuXino_defconfig @@ -10,7 +10,7 @@ CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PB3" CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PB2" CONFIG_VIDEO_LCD_BL_PWM="PH0" diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig index 3e47ca2466..0d449cc53d 100644 --- a/configs/Ainol_AW1_defconfig +++ b/configs/Ainol_AW1_defconfig @@ -8,7 +8,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:40000,le:87,ri:112,up:38,lo:141,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:40000,le:87,ri:112,up:38,lo:141,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig index b0d6047789..1e18458179 100644 --- a/configs/Ampe_A76_defconfig +++ b/configs/Ampe_A76_defconfig @@ -9,7 +9,7 @@ CONFIG_USB0_VBUS_DET="PG1" CONFIG_USB0_ID_DET="PG2" CONFIG_AXP_GPIO=y # CONFIG_VIDEO_HDMI is not set -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig index 645a759fc2..e08d1ac3cc 100644 --- a/configs/Chuwi_V7_CW0825_defconfig +++ b/configs/Chuwi_V7_CW0825_defconfig @@ -7,7 +7,7 @@ CONFIG_DRAM_EMR1=4 CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="PH5" CONFIG_USB0_ID_DET="PH4" -CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:51000,le:19,ri:300,up:6,lo:31,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:51000,le:19,ri:300,up:6,lo:31,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index c85e47cb11..ef8572d10c 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -7,7 +7,7 @@ CONFIG_DRAM_ZQ=251 CONFIG_USB1_VBUS_PIN="" CONFIG_I2C0_ENABLE=y CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:2048,y:1536,depth:24,pclk_khz:208000,le:5,ri:150,up:9,lo:24,hs:5,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:2048,y:1536,depth:24,pclk_khz:208000,le:5,ri:150,up:9,lo:24,hs:5,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH27" CONFIG_VIDEO_LCD_BL_EN="PM1" diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig index bac5859130..d0a60fbba2 100644 --- a/configs/Empire_electronix_d709_defconfig +++ b/configs/Empire_electronix_d709_defconfig @@ -10,7 +10,7 @@ CONFIG_USB0_VBUS_DET="PG1" CONFIG_USB0_ID_DET="PG2" CONFIG_AXP_GPIO=y # CONFIG_VIDEO_HDMI is not set -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig index 47f3fe7e2e..862b32b2c8 100644 --- a/configs/Empire_electronix_m712_defconfig +++ b/configs/Empire_electronix_m712_defconfig @@ -9,7 +9,7 @@ CONFIG_USB0_VBUS_DET="PG1" CONFIG_USB0_ID_DET="PG2" CONFIG_AXP_GPIO=y # CONFIG_VIDEO_HDMI is not set -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig index 72327c90fc..9005d196e7 100644 --- a/configs/Hyundai_A7HD_defconfig +++ b/configs/Hyundai_A7HD_defconfig @@ -7,7 +7,7 @@ CONFIG_USB0_VBUS_PIN="PB09" CONFIG_USB0_VBUS_DET="PH5" CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="PH6" -CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:45,ri:274,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:45,ri:274,up:22,lo:12,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_POWER="PH2" CONFIG_VIDEO_LCD_BL_EN="PH9" CONFIG_VIDEO_LCD_BL_PWM="PB2" diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig index 309b384a4e..2c2b48c5bf 100644 --- a/configs/MSI_Primo73_defconfig +++ b/configs/MSI_Primo73_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 -CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:60000,le:60,ri:160,up:13,lo:12,hs:100,vs:10,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:60000,le:60,ri:160,up:13,lo:12,hs:100,vs:10,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig index 04b0b63259..425ec6ca15 100644 --- a/configs/MSI_Primo81_defconfig +++ b/configs/MSI_Primo81_defconfig @@ -7,7 +7,7 @@ CONFIG_DRAM_ZQ=122 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:768,y:1024,depth:18,pclk_khz:66000,le:56,ri:60,up:30,lo:36,hs:64,vs:50,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:768,y:1024,depth:18,pclk_khz:66000,le:56,ri:60,up:30,lo:36,hs:64,vs:50,sync:0,vmode:0" CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index 9e6267200b..9ed3848b3d 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -7,7 +7,7 @@ CONFIG_DRAM_ZQ=15291 CONFIG_MMC0_CD_PIN="PB4" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB0_ID_DET="PH8" -CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig index a666e419db..ee0b8ed930 100644 --- a/configs/UTOO_P66_defconfig +++ b/configs/UTOO_P66_defconfig @@ -11,7 +11,7 @@ CONFIG_USB0_VBUS_DET="PG01" CONFIG_USB0_ID_DET="PG2" CONFIG_AXP_GPIO=y # CONFIG_VIDEO_HDMI is not set -CONFIG_VIDEO_LCD_MODE="x:480,y:800,depth:18,pclk_khz:25000,le:2,ri:93,up:2,lo:93,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:480,y:800,depth:18,pclk_khz:25000,le:2,ri:93,up:2,lo:93,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PG4" CONFIG_VIDEO_LCD_RESET="PG11" diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig index 9a431ee4cd..5c96c24455 100644 --- a/configs/Wexler_TAB7200_defconfig +++ b/configs/Wexler_TAB7200_defconfig @@ -7,7 +7,7 @@ CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH4" CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig index 8065ca2629..53a1ea16ae 100644 --- a/configs/Wits_Pro_A20_DKT_defconfig +++ b/configs/Wits_Pro_A20_DKT_defconfig @@ -4,7 +4,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 CONFIG_VIDEO_VGA=y -CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:65000,le:159,ri:160,up:22,lo:15,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:65000,le:159,ri:160,up:22,lo:15,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig index c49cbcbc3c..8deec0101d 100644 --- a/configs/Yones_Toptech_BD1078_defconfig +++ b/configs/Yones_Toptech_BD1078_defconfig @@ -10,7 +10,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=1 CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:63000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:63000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig index 87c13b0ea8..ef935b5c89 100644 --- a/configs/Yones_Toptech_BS1078_V2_defconfig +++ b/configs/Yones_Toptech_BS1078_V2_defconfig @@ -9,7 +9,7 @@ CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PA15" CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:70000,le:120,ri:180,up:17,lo:15,hs:20,vs:3,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:70000,le:120,ri:180,up:17,lo:15,hs:20,vs:3,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig index e9c82674a2..e3bafe6cbb 100644 --- a/configs/colorfly_e708_q1_defconfig +++ b/configs/colorfly_e708_q1_defconfig @@ -9,7 +9,7 @@ CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PA15" CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:800,y:1280,depth:24,pclk_khz:64000,le:20,ri:34,up:1,lo:16,hs:10,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:800,y:1280,depth:24,pclk_khz:64000,le:20,ri:34,up:1,lo:16,hs:10,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig index a7cdf0fbf7..94358308cf 100644 --- a/configs/difrnce_dit4350_defconfig +++ b/configs/difrnce_dit4350_defconfig @@ -9,7 +9,7 @@ CONFIG_USB0_VBUS_DET="PG1" CONFIG_USB0_ID_DET="PG2" CONFIG_AXP_GPIO=y # CONFIG_VIDEO_HDMI is not set -CONFIG_VIDEO_LCD_MODE="x:480,y:272,depth:18,pclk_khz:12000,le:1,ri:43,up:1,lo:12,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:480,y:272,depth:18,pclk_khz:12000,le:1,ri:43,up:1,lo:12,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig index 8f469fbc34..1013c9d321 100644 --- a/configs/dserve_dsrv9703c_defconfig +++ b/configs/dserve_dsrv9703c_defconfig @@ -6,7 +6,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="PH5" CONFIG_USB0_ID_DET="PH4" -CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:80000,le:479,ri:544,up:5,lo:26,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:80000,le:479,ri:544,up:5,lo:26,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig index 02cc9677aa..e253486991 100644 --- a/configs/ga10h_v1_1_defconfig +++ b/configs/ga10h_v1_1_defconfig @@ -9,7 +9,7 @@ CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH8" CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:52000,le:138,ri:162,up:22,lo:10,hs:20,vs:3,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:52000,le:138,ri:162,up:22,lo:10,hs:20,vs:3,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig index caff63eb59..66612ba5c1 100644 --- a/configs/gt90h_v4_defconfig +++ b/configs/gt90h_v4_defconfig @@ -9,7 +9,7 @@ CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH8" CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:55000,le:159,ri:160,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:55000,le:159,ri:160,up:22,lo:12,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig index b1d6ed11f1..a7b2895634 100644 --- a/configs/iNet_3F_defconfig +++ b/configs/iNet_3F_defconfig @@ -7,7 +7,7 @@ CONFIG_DRAM_EMR1=4 CONFIG_MMC0_CD_PIN="PH1" CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="PH5" -CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:799,ri:260,up:15,lo:16,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:799,ri:260,up:15,lo:16,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig index bfd8f002e1..b9c8356149 100644 --- a/configs/iNet_3W_defconfig +++ b/configs/iNet_3W_defconfig @@ -8,7 +8,7 @@ CONFIG_DRAM_EMR1=4 CONFIG_MMC0_CD_PIN="PH20" CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="PH5" -CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:65000,le:159,ri:160,up:22,lo:15,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:65000,le:159,ri:160,up:22,lo:15,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig index b370eacc05..1487cc1ff7 100644 --- a/configs/iNet_86VS_defconfig +++ b/configs/iNet_86VS_defconfig @@ -7,7 +7,7 @@ CONFIG_USB0_VBUS_PIN="PG12" CONFIG_USB0_VBUS_DET="PG1" CONFIG_AXP_GPIO=y # CONFIG_VIDEO_HDMI is not set -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" diff --git a/configs/iNet_D978_rev2_defconfig b/configs/iNet_D978_rev2_defconfig index 29f807ab97..9ef82342a4 100644 --- a/configs/iNet_D978_rev2_defconfig +++ b/configs/iNet_D978_rev2_defconfig @@ -9,7 +9,7 @@ CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH8" CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:65000,le:120,ri:180,up:22,lo:13,hs:20,vs:3,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:65000,le:120,ri:180,up:22,lo:13,hs:20,vs:3,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig index 8fca6e81ed..7d2f70544f 100644 --- a/configs/icnova-a20-swac_defconfig +++ b/configs/icnova-a20-swac_defconfig @@ -8,7 +8,7 @@ CONFIG_MMC0_CD_PIN="PI5" CONFIG_USB0_VBUS_PIN="PG11" CONFIG_USB0_VBUS_DET="PH7" CONFIG_USB1_VBUS_PIN="PG10" -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_POWER="PH22" CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-swac" diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig index 100d075960..c2cdbeb073 100644 --- a/configs/inet1_defconfig +++ b/configs/inet1_defconfig @@ -7,7 +7,7 @@ CONFIG_DRAM_EMR1=4 CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="PH5" CONFIG_USB0_ID_DET="PH4" -CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:52000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:52000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" diff --git a/configs/inet86dz_defconfig b/configs/inet86dz_defconfig index 9d6e340f08..3c47dd1a71 100644 --- a/configs/inet86dz_defconfig +++ b/configs/inet86dz_defconfig @@ -9,7 +9,7 @@ CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH8" CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:138,ri:162,up:22,lo:10,hs:20,vs:3,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:138,ri:162,up:22,lo:10,hs:20,vs:3,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig index 4caf3075cd..ba8474c15d 100644 --- a/configs/inet97fv2_defconfig +++ b/configs/inet97fv2_defconfig @@ -7,7 +7,7 @@ CONFIG_DRAM_EMR1=4 CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="PH5" CONFIG_USB0_ID_DET="PH4" -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig index 1eea0c66a5..8c649f3ea8 100644 --- a/configs/inet98v_rev2_defconfig +++ b/configs/inet98v_rev2_defconfig @@ -9,7 +9,7 @@ CONFIG_USB0_VBUS_DET="PG1" CONFIG_USB0_ID_DET="PG2" CONFIG_AXP_GPIO=y # CONFIG_VIDEO_HDMI is not set -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig index 46fa4ee775..bb40ced96a 100644 --- a/configs/inet9f_rev03_defconfig +++ b/configs/inet9f_rev03_defconfig @@ -7,7 +7,7 @@ CONFIG_DRAM_EMR1=4 CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="PH5" CONFIG_USB0_ID_DET="PH4" -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" diff --git a/configs/inet_q972_defconfig b/configs/inet_q972_defconfig index b928622813..90fd016072 100644 --- a/configs/inet_q972_defconfig +++ b/configs/inet_q972_defconfig @@ -9,7 +9,7 @@ CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PA15" CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:65000,le:280,ri:20,up:22,lo:8,hs:20,vs:8,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:65000,le:280,ri:20,up:22,lo:8,hs:20,vs:8,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" diff --git a/configs/polaroid_mid2407pxe03_defconfig b/configs/polaroid_mid2407pxe03_defconfig index 03931c8f05..9e06cb2d10 100644 --- a/configs/polaroid_mid2407pxe03_defconfig +++ b/configs/polaroid_mid2407pxe03_defconfig @@ -9,7 +9,7 @@ CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH8" CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig index f6ba2370db..2961a6cc1e 100644 --- a/configs/polaroid_mid2809pxe04_defconfig +++ b/configs/polaroid_mid2809pxe04_defconfig @@ -9,7 +9,7 @@ CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH8" CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:36,ri:210,up:18,lo:22,hs:10,vs:5,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:36,ri:210,up:18,lo:22,hs:10,vs:5,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig index fd829f57ea..5f42b0d14e 100644 --- a/configs/pov_protab2_ips9_defconfig +++ b/configs/pov_protab2_ips9_defconfig @@ -6,7 +6,7 @@ CONFIG_DRAM_CLK=432 CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="PH5" CONFIG_USB0_ID_DET="PH4" -CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:480,ri:260,up:6,lo:16,hs:320,vs:10,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:480,ri:260,up:6,lo:16,hs:320,vs:10,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig index 0ef7e2c473..1816bfc3f6 100644 --- a/configs/q8_a13_tablet_defconfig +++ b/configs/q8_a13_tablet_defconfig @@ -9,7 +9,7 @@ CONFIG_USB0_VBUS_DET="PG1" CONFIG_USB0_ID_DET="PG2" CONFIG_AXP_GPIO=y # CONFIG_VIDEO_HDMI is not set -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig index 18e0849853..d8b413f855 100644 --- a/configs/q8_a23_tablet_800x480_defconfig +++ b/configs/q8_a23_tablet_800x480_defconfig @@ -9,7 +9,7 @@ CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH8" CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:36,ri:210,up:18,lo:22,hs:10,vs:5,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:36,ri:210,up:18,lo:22,hs:10,vs:5,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig index 0b3973dadc..ac89a29908 100644 --- a/configs/q8_a33_tablet_1024x600_defconfig +++ b/configs/q8_a33_tablet_1024x600_defconfig @@ -9,7 +9,7 @@ CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH8" CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:159,ri:160,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:159,ri:160,up:22,lo:12,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig index 322d01d8a4..1dca714453 100644 --- a/configs/q8_a33_tablet_800x480_defconfig +++ b/configs/q8_a33_tablet_800x480_defconfig @@ -9,7 +9,7 @@ CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH8" CONFIG_AXP_GPIO=y -CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig index d88dd4ebad..ee77e5d0cd 100644 --- a/configs/sunxi_Gemei_G9_defconfig +++ b/configs/sunxi_Gemei_G9_defconfig @@ -4,7 +4,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_EMR1=4 -CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:799,ri:260,up:15,lo:16,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:799,ri:260,up:15,lo:16,hs:1,vs:1,sync:0,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" diff --git a/drivers/video/sunxi/lcdc.c b/drivers/video/sunxi/lcdc.c index 63c47bf1bc..ef851070b2 100644 --- a/drivers/video/sunxi/lcdc.c +++ b/drivers/video/sunxi/lcdc.c @@ -131,9 +131,9 @@ void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc, } val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(dclk_phase); - if (mode->flags & DISPLAY_FLAGS_HSYNC_LOW) + if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH) val |= SUNXI_LCDC_TCON_HSYNC_MASK; - if (mode->flags & DISPLAY_FLAGS_VSYNC_LOW) + if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH) val |= SUNXI_LCDC_TCON_VSYNC_MASK; #ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH -- 2.19.0

2 5

[U-Boot] [PATCH 1/6] ofnode: Add missing address translation into ofnode_get_addr_size()
by Marek Vasut 08 Oct '18

08 Oct '18

Of CONFIG_OF_TRANSLATE is enabled, this function still returns untranslated bogus results. Add the missing translation. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)konsulko.com> --- drivers/core/ofnode.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index a7e1927723..035023ca91 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -542,8 +542,15 @@ fdt_addr_t ofnode_get_addr_size(ofnode node, const char *property, return FDT_ADDR_T_NONE; na = of_n_addr_cells(np); ns = of_n_addr_cells(np); + *sizep = of_read_number(prop + na, ns); - return of_read_number(prop, na); + + if (IS_ENABLED(CONFIG_OF_TRANSLATE) && ns > 0) { + return of_translate_address(ofnode_to_np(node), prop); + } else { + na = of_n_addr_cells(ofnode_to_np(node)); + return of_read_number(prop, na); + } } else { return fdtdec_get_addr_size(gd->fdt_blob, ofnode_to_offset(node), property, -- 2.18.0

3 19

[U-Boot] U-boot does not silence its output
by mrigendra 07 Oct '18

07 Oct '18

I have this uboot VERSION = 2017 PATCHLEVEL = 03 I am trying to silent the console using the silent variable.I defined this `#define CONFIG_SILENT_CONSOLE` So at boot time I am interrupting the console, and entering setenv silent 1 save reset Now after reset, or power on reset I try again get console logs.After seeing env variables printenv I see my saved variable correctly in env varibles silent=1 but still u-boot is not silent. I suspect this function is failing at checking for this env variable, char *getenv(const char *name) { if (gd->flags & GD_FLG_ENV_READY) { /* after import into hashtable */ ENTRY e, *ep; WATCHDOG_RESET(); e.key = name; e.data = NULL; hsearch_r(e, FIND, &ep, &env_htab, 0); /*this function is maybe returning*/ return ep ? ep->data : NULL; } /* restricted capabilities before import */ if (getenv_f(name, (char *)(gd->env_buf), sizeof(gd->env_buf)) > 0) return (char *)(gd->env_buf); return NULL; } But what exactly is happening? Is there something like before relocation time env variables and after relocation env variables because the function, static void console_update_silent(void) { #ifdef CONFIG_SILENT_CONSOLE if (getenv("silent") != NULL){ puts("silent"); gd->flags |= GD_FLG_SILENT; } else{ puts("Non silent"); gd->flags &= ~GD_FLG_SILENT; } #endif } /* Called before relocation - use serial functions */ int console_init_f(void) { gd->have_console = 1; console_update_silent(); print_pre_console_buffer(PRE_CONSOLE_FLUSHPOINT1_SERIAL); return 0; } `console_init_f` says its before relocation. I have put some prints to see and always gets non silent, even if I have saved the silent variable, I am using a sd card to boot(mmc), I don't have any debugger, so I I tried printing default environment, as env print default ## Error: "default" not defined So there is not default environment too. Any tips or help will make me understand. P.S. I explicitly defined silent in `#define CONFIG_EXTRA_ENV_SETTINGS` Now u-boot is silent. Doing a `setenv silent` should remove this from env variable, and I can see that its gone, but still on reboot my uboot is silent. So something about environment variable is clearly mystery to me. -- Sent from: http://u-boot.10912.n7.nabble.com/

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[U-Boot] [PATCH] ARM: da850evm: Remove DM_I2C_COMPAT
by Adam Ford 07 Oct '18

07 Oct '18

The da850evm does not need this enabled, so this removes a notice that appears during compile time that says "Please remove" Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig index 6745cd10fa..c3d7cff18e 100644 --- a/configs/da850_am18xxevm_defconfig +++ b/configs/da850_am18xxevm_defconfig @@ -39,7 +39,6 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_MTD_DEVICE=y CONFIG_MTD_PARTITIONS=y diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index 8ea522af93..b7423034db 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -40,7 +40,6 @@ CONFIG_DM=y CONFIG_BLK=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y CONFIG_SYS_I2C_DAVINCI=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 319f6aadf5..167bd4b5c4 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -26,7 +26,6 @@ #undef CONFIG_DM_SPI #undef CONFIG_DM_SPI_FLASH #undef CONFIG_DM_I2C -#undef CONFIG_DM_I2C_COMPAT #endif /* * SoC Configuration -- 2.17.1

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[U-Boot] [PATCH v2 30/33] armv8: ls1012ardb: Add TFABOOT defconfig for secure boot
by Rajesh Bhagat 07 Oct '18

07 Oct '18

From: Vinitha V Pillai <vinitha.pillai(a)nxp.com> This defconfig is for Secure TFABOOT, to be loaded by trusted firmware Signed-off-by: Vinitha V Pillai <vinitha.pillai(a)nxp.com> --- Change in v2: None configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 62 ++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 configs/ls1012ardb_tfa_SECURE_BOOT_defconfig diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..1161ae8d0f --- /dev/null +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1012ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SECURE_BOOT=y +CONFIG_QSPI_AHB_INIT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_TFABOOT=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" +# CONFIG_USE_BOOTCOMMAND is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +# CONFIG_BLK is not set +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SPI_FLASH=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DM_ETH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_DM_SCSI=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y -- 2.17.1

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