October 2018 - U-Boot

[U-Boot] U-Boot SPL and LTO (armv7)
by Adam Ford 10 Oct '18

10 Oct '18

I am wondering if anyone has done any tests using LTO in SPL? For those of us with limited resources, I noticed that we're creeping up in size, especially when using DM in SPL. I made a few attempts to enable -flto during compile, but the .S files fail to assemble. I found some references that indicating not to use -flto when running the assembler, but we appear to be using CFLAGS for assembly and I am not entirely sure how to apply -fno-lto to just the assembly files. I am focusing on ARMv7 right now, but if anyone has any suggestions or have started something, on a different architecture, I'd like to experiment a little. I am not sure if the LTO will buy us much anyway, but any little improvement during SPL would be appreciated. thanks adam

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[U-Boot] [PATCH V3] mtd: uboot: Fix hanging during mtd list command
by Adam Ford 10 Oct '18

10 Oct '18

Some boards (like omap3_logic) hang when trying to access address 0. This happens when executing the new 'mtd list' command. This patch enhances the checks for conditions that would preclude mtd_probe_devices() from operating. Fixes: 5db66b3aee6f ("cmd: mtd: add 'mtd' command") Suggested-by: Boris Brezillon <boris.brezillon(a)bootlin.com> Signed-off-by: Adam Ford <aford173(a)gmail.com> Reviewed-by: Boris Brezillon <boris.brezillon(a)bootlin.com> --- V3: No code change. Just fix commit comment and typos. V2: Move the check for NULL mtdparts or mtdids until after the partitions have been removed. diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c index 6a211d52ff..7d7a11c990 100644 --- a/drivers/mtd/mtd_uboot.c +++ b/drivers/mtd/mtd_uboot.c @@ -104,7 +104,10 @@ int mtd_probe_devices(void) mtd_probe_uclass_mtd_devs(); /* Check if mtdparts/mtdids changed since last call, otherwise: exit */ - if (!strcmp(mtdparts, old_mtdparts) && !strcmp(mtdids, old_mtdids)) + if ((!mtdparts && !old_mtdparts && !mtdids && !old_mtdids) || + (mtdparts && old_mtdparts && mtdids && old_mtdids && + !strcmp(mtdparts, old_mtdparts) && + !strcmp(mtdids, old_mtdids))) return 0; /* Update the local copy of mtdparts */ @@ -140,6 +143,10 @@ int mtd_probe_devices(void) } } + /* If either mtdparts or mtdids is empty, then exit */ + if (!mtdparts || !mtdids) + return 0; + /* Start the parsing by ignoring the extra 'mtdparts=' prefix, if any */ if (strstr(mtdparts, "mtdparts=")) mtdparts += 9; -- 2.17.1

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[U-Boot] [PATCH v4] arm: socfpga: fix SPL booting from fpga OnChip RAM
by Simon Goldschmidt 10 Oct '18

10 Oct '18

This patch prevents disabling the FPGA bridges when SPL or U-Boot is executed from FPGA onchip RAM. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- Changes in v4: - use an inline function in misc.h to check for the address range instead of a macro in base_addr_ac5.h Changes in v3: - use __image_copy_start to check if we are executing from FPGA Changes in v2: - use less ifdefs and more C code for address checks (but this gives a checkpatch warning because of comparing two upper case constants) - changed comments arch/arm/mach-socfpga/include/mach/base_addr_ac5.h | 1 + arch/arm/mach-socfpga/include/mach/misc.h | 7 +++++++ arch/arm/mach-socfpga/misc_gen5.c | 10 +++++++++- arch/arm/mach-socfpga/spl_gen5.c | 10 +++++++--- 4 files changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h index bb9e3faa29..2725e9fcc3 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h @@ -6,6 +6,7 @@ #ifndef _SOCFPGA_BASE_ADDRS_H_ #define _SOCFPGA_BASE_ADDRS_H_ +#define SOCFPGA_FPGA_SLAVES_ADDRESS 0xc0000000 #define SOCFPGA_STM_ADDRESS 0xfc000000 #define SOCFPGA_DAP_ADDRESS 0xff000000 #define SOCFPGA_EMAC0_ADDRESS 0xff700000 diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 4fc9570a04..e78a86503e 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -23,6 +23,13 @@ static inline void socfpga_fpga_add(void) {} #ifdef CONFIG_TARGET_SOCFPGA_GEN5 void socfpga_sdram_remap_zero(void); +static inline bool socfpga_is_fpga_slaves_addr(void *addr) +{ + if ((addr >= (void *)SOCFPGA_FPGA_SLAVES_ADDRESS) && + (addr < (void *)SOCFPGA_STM_ADDRESS)) + return true; + return false; +} #endif #ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 429c3d6cd5..030f43d80a 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -20,6 +20,7 @@ #include <asm/arch/nic301.h> #include <asm/arch/scu.h> #include <asm/pl310.h> +#include <asm/sections.h> #include <dt-bindings/reset/altr,rst-mgr.h> @@ -177,6 +178,8 @@ static void socfpga_nic301_slave_ns(void) void socfpga_sdram_remap_zero(void) { + u32 remap; + socfpga_nic301_slave_ns(); /* @@ -187,7 +190,12 @@ void socfpga_sdram_remap_zero(void) setbits_le32(&scu_regs->sacr, 0xfff); /* Configure the L2 controller to make SDRAM start at 0 */ - writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ + remap = 0x1; /* remap.mpuzero */ + /* Keep fpga bridge enabled when running from FPGA onchip RAM */ + if (socfpga_is_fpga_slaves_addr(__image_copy_start)) + remap |= 0x8; /* remap.hps2fpga */ + writel(remap, &nic301_regs->remap); + writel(0x1, &pl310->pl310_addr_filter_start); } diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index be318cc0d9..db1c4b722c 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -92,8 +92,11 @@ void board_init_f(ulong dummy) /* Put everything into reset but L4WD0. */ socfpga_per_reset_all(); - /* Put FPGA bridges into reset too. */ - socfpga_bridges_reset(1); + + if (!socfpga_is_fpga_slaves_addr(__image_copy_start)) { + /* Put FPGA bridges into reset (unless booting from FPGA). */ + socfpga_bridges_reset(1); + } socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0); @@ -163,5 +166,6 @@ void board_init_f(ulong dummy) hang(); } - socfpga_bridges_reset(1); + if (!socfpga_is_fpga_slaves_addr(__image_copy_start)) + socfpga_bridges_reset(1); } -- 2.17.1

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[U-Boot] [PATCH v2 00/11] m68k: initial devicetree support
by Angelo Dureghello 10 Oct '18

10 Oct '18

This patchset has been successfully tested on stmark2 and amcore ColdFire family boards. Angelo Dureghello (11): m68k: add basic set of devicetrees drivers: spi: cf_spi: add Kconfig option drivers: spi: cf_spi: migrate to DM and DT drivers: serial: mcfuart: add DT support drivers: serial: mcfuart: add Kconfig option m68k: architecture changes to support fdt m68k: add initial dts files for all m68k boards m68k: enabling long jumps on mcf54x5 SoCs configs: enable use of DT for all m68k boards configs: add DM_SPI config option configs: remove CONFIG_SYS_DSPI_XX references arch/Kconfig | 1 + arch/m68k/Kconfig | 33 ++ arch/m68k/cpu/mcf547x_8x/start.S | 6 +- arch/m68k/cpu/u-boot.lds | 2 + arch/m68k/dts/M5208EVBE.dts | 22 + arch/m68k/dts/M52277EVB.dts | 25 + arch/m68k/dts/M52277EVB_stmicro.dts | 22 + arch/m68k/dts/M5235EVB.dts | 22 + arch/m68k/dts/M5235EVB_Flash32.dts | 22 + arch/m68k/dts/M5249EVB.dts | 22 + arch/m68k/dts/M5253DEMO.dts | 22 + arch/m68k/dts/M5272C3.dts | 22 + arch/m68k/dts/M5275EVB.dts | 22 + arch/m68k/dts/M5282EVB.dts | 22 + arch/m68k/dts/M53017EVB.dts | 22 + arch/m68k/dts/M5329AFEE.dts | 22 + arch/m68k/dts/M5329BFEE.dts | 22 + arch/m68k/dts/M5373EVB.dts | 22 + arch/m68k/dts/M54418TWR.dts | 25 + arch/m68k/dts/M54418TWR_nand_mii.dts | 25 + arch/m68k/dts/M54418TWR_nand_rmii.dts | 25 + arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts | 25 + arch/m68k/dts/M54418TWR_serial_mii.dts | 25 + arch/m68k/dts/M54418TWR_serial_rmii.dts | 25 + arch/m68k/dts/M54451EVB.dts | 25 + arch/m68k/dts/M54451EVB_stmicro.dts | 25 + arch/m68k/dts/M54455EVB.dts | 25 + arch/m68k/dts/M54455EVB_a66.dts | 25 + arch/m68k/dts/M54455EVB_i66.dts | 25 + arch/m68k/dts/M54455EVB_intel.dts | 26 + arch/m68k/dts/M54455EVB_stm33.dts | 25 + arch/m68k/dts/M5475AFE.dts | 13 + arch/m68k/dts/M5475BFE.dts | 13 + arch/m68k/dts/M5475CFE.dts | 13 + arch/m68k/dts/M5475DFE.dts | 13 + arch/m68k/dts/M5475EFE.dts | 13 + arch/m68k/dts/M5475FFE.dts | 13 + arch/m68k/dts/M5475GFE.dts | 13 + arch/m68k/dts/M5485AFE.dts | 17 + arch/m68k/dts/M5485BFE.dts | 17 + arch/m68k/dts/M5485CFE.dts | 17 + arch/m68k/dts/M5485DFE.dts | 17 + arch/m68k/dts/M5485EFE.dts | 17 + arch/m68k/dts/M5485FFE.dts | 17 + arch/m68k/dts/M5485GFE.dts | 17 + arch/m68k/dts/M5485HFE.dts | 17 + arch/m68k/dts/Makefile | 58 ++ arch/m68k/dts/amcore.dts | 22 + arch/m68k/dts/astro_mcf5373l.dts | 22 + arch/m68k/dts/cobra5272.dts | 22 + arch/m68k/dts/eb_cpu5282.dts | 22 + arch/m68k/dts/eb_cpu5282_internal.dts | 22 + arch/m68k/dts/mcf5208.dtsi | 36 ++ arch/m68k/dts/mcf5227x.dtsi | 48 ++ arch/m68k/dts/mcf523x.dtsi | 44 ++ arch/m68k/dts/mcf5249.dtsi | 38 ++ arch/m68k/dts/mcf5253.dtsi | 44 ++ arch/m68k/dts/mcf5271.dtsi | 44 ++ arch/m68k/dts/mcf5272.dtsi | 38 ++ arch/m68k/dts/mcf5275.dtsi | 44 ++ arch/m68k/dts/mcf5282.dtsi | 44 ++ arch/m68k/dts/mcf5301x.dtsi | 48 ++ arch/m68k/dts/mcf5307.dtsi | 39 ++ arch/m68k/dts/mcf5329.dtsi | 36 ++ arch/m68k/dts/mcf537x.dtsi | 36 ++ arch/m68k/dts/mcf5441x.dtsi | 87 +++ arch/m68k/dts/mcf5445x.dtsi | 48 ++ arch/m68k/dts/mcf54xx.dtsi | 40 ++ arch/m68k/dts/stmark2.dts | 34 ++ configs/M5208EVBE_defconfig | 2 + configs/M52277EVB_defconfig | 3 + configs/M52277EVB_stmicro_defconfig | 3 + configs/M5235EVB_Flash32_defconfig | 2 + configs/M5235EVB_defconfig | 2 + configs/M5249EVB_defconfig | 2 + configs/M5253DEMO_defconfig | 2 + configs/M5272C3_defconfig | 2 + configs/M5275EVB_defconfig | 3 + configs/M5282EVB_defconfig | 2 + configs/M53017EVB_defconfig | 2 + configs/M5329AFEE_defconfig | 2 + configs/M5329BFEE_defconfig | 2 + configs/M5373EVB_defconfig | 2 + configs/M54418TWR_defconfig | 3 + configs/M54418TWR_nand_mii_defconfig | 3 + configs/M54418TWR_nand_rmii_defconfig | 3 + configs/M54418TWR_nand_rmii_lowfreq_defconfig | 3 + configs/M54418TWR_serial_mii_defconfig | 3 + configs/M54418TWR_serial_rmii_defconfig | 3 + configs/M54451EVB_defconfig | 3 + configs/M54451EVB_stmicro_defconfig | 3 + configs/M54455EVB_a66_defconfig | 3 + configs/M54455EVB_defconfig | 3 + configs/M54455EVB_i66_defconfig | 3 + configs/M54455EVB_intel_defconfig | 3 + configs/M54455EVB_stm33_defconfig | 3 + configs/M5475AFE_defconfig | 2 + configs/M5475BFE_defconfig | 2 + configs/M5475CFE_defconfig | 2 + configs/M5475DFE_defconfig | 2 + configs/M5475EFE_defconfig | 2 + configs/M5475FFE_defconfig | 2 + configs/M5475GFE_defconfig | 2 + configs/M5485AFE_defconfig | 2 + configs/M5485BFE_defconfig | 2 + configs/M5485CFE_defconfig | 2 + configs/M5485DFE_defconfig | 2 + configs/M5485EFE_defconfig | 2 + configs/M5485FFE_defconfig | 2 + configs/M5485GFE_defconfig | 2 + configs/M5485HFE_defconfig | 2 + configs/amcore_defconfig | 2 + configs/astro_mcf5373l_defconfig | 2 + configs/cobra5272_defconfig | 2 + configs/eb_cpu5282_defconfig | 2 + configs/eb_cpu5282_internal_defconfig | 2 + configs/stmark2_defconfig | 4 + doc/device-tree-bindings/serial/mcf-uart.txt | 19 + doc/device-tree-bindings/spi/spi-mcf-dspi.txt | 30 ++ drivers/serial/Kconfig | 9 + drivers/serial/mcfuart.c | 106 +--- drivers/spi/Kconfig | 18 +- drivers/spi/cf_spi.c | 510 +++++++++++------- include/configs/M52277EVB.h | 11 - include/configs/M54418TWR.h | 12 - include/configs/M54451EVB.h | 12 - include/configs/M54455EVB.h | 10 - include/configs/stmark2.h | 11 - include/dm/platform_data/spi_coldfire.h | 29 + 129 files changed, 2378 insertions(+), 335 deletions(-) create mode 100644 arch/m68k/dts/M5208EVBE.dts create mode 100644 arch/m68k/dts/M52277EVB.dts create mode 100644 arch/m68k/dts/M52277EVB_stmicro.dts create mode 100644 arch/m68k/dts/M5235EVB.dts create mode 100644 arch/m68k/dts/M5235EVB_Flash32.dts create mode 100644 arch/m68k/dts/M5249EVB.dts create mode 100644 arch/m68k/dts/M5253DEMO.dts create mode 100644 arch/m68k/dts/M5272C3.dts create mode 100644 arch/m68k/dts/M5275EVB.dts create mode 100644 arch/m68k/dts/M5282EVB.dts create mode 100644 arch/m68k/dts/M53017EVB.dts create mode 100644 arch/m68k/dts/M5329AFEE.dts create mode 100644 arch/m68k/dts/M5329BFEE.dts create mode 100644 arch/m68k/dts/M5373EVB.dts create mode 100644 arch/m68k/dts/M54418TWR.dts create mode 100644 arch/m68k/dts/M54418TWR_nand_mii.dts create mode 100644 arch/m68k/dts/M54418TWR_nand_rmii.dts create mode 100644 arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts create mode 100644 arch/m68k/dts/M54418TWR_serial_mii.dts create mode 100644 arch/m68k/dts/M54418TWR_serial_rmii.dts create mode 100644 arch/m68k/dts/M54451EVB.dts create mode 100644 arch/m68k/dts/M54451EVB_stmicro.dts create mode 100644 arch/m68k/dts/M54455EVB.dts create mode 100644 arch/m68k/dts/M54455EVB_a66.dts create mode 100644 arch/m68k/dts/M54455EVB_i66.dts create mode 100644 arch/m68k/dts/M54455EVB_intel.dts create mode 100644 arch/m68k/dts/M54455EVB_stm33.dts create mode 100644 arch/m68k/dts/M5475AFE.dts create mode 100644 arch/m68k/dts/M5475BFE.dts create mode 100644 arch/m68k/dts/M5475CFE.dts create mode 100644 arch/m68k/dts/M5475DFE.dts create mode 100644 arch/m68k/dts/M5475EFE.dts create mode 100644 arch/m68k/dts/M5475FFE.dts create mode 100644 arch/m68k/dts/M5475GFE.dts create mode 100644 arch/m68k/dts/M5485AFE.dts create mode 100644 arch/m68k/dts/M5485BFE.dts create mode 100644 arch/m68k/dts/M5485CFE.dts create mode 100644 arch/m68k/dts/M5485DFE.dts create mode 100644 arch/m68k/dts/M5485EFE.dts create mode 100644 arch/m68k/dts/M5485FFE.dts create mode 100644 arch/m68k/dts/M5485GFE.dts create mode 100644 arch/m68k/dts/M5485HFE.dts create mode 100644 arch/m68k/dts/Makefile create mode 100644 arch/m68k/dts/amcore.dts create mode 100644 arch/m68k/dts/astro_mcf5373l.dts create mode 100644 arch/m68k/dts/cobra5272.dts create mode 100644 arch/m68k/dts/eb_cpu5282.dts create mode 100644 arch/m68k/dts/eb_cpu5282_internal.dts create mode 100644 arch/m68k/dts/mcf5208.dtsi create mode 100644 arch/m68k/dts/mcf5227x.dtsi create mode 100644 arch/m68k/dts/mcf523x.dtsi create mode 100644 arch/m68k/dts/mcf5249.dtsi create mode 100644 arch/m68k/dts/mcf5253.dtsi create mode 100644 arch/m68k/dts/mcf5271.dtsi create mode 100644 arch/m68k/dts/mcf5272.dtsi create mode 100644 arch/m68k/dts/mcf5275.dtsi create mode 100644 arch/m68k/dts/mcf5282.dtsi create mode 100644 arch/m68k/dts/mcf5301x.dtsi create mode 100644 arch/m68k/dts/mcf5307.dtsi create mode 100644 arch/m68k/dts/mcf5329.dtsi create mode 100644 arch/m68k/dts/mcf537x.dtsi create mode 100644 arch/m68k/dts/mcf5441x.dtsi create mode 100644 arch/m68k/dts/mcf5445x.dtsi create mode 100644 arch/m68k/dts/mcf54xx.dtsi create mode 100644 arch/m68k/dts/stmark2.dts create mode 100644 doc/device-tree-bindings/serial/mcf-uart.txt create mode 100644 doc/device-tree-bindings/spi/spi-mcf-dspi.txt create mode 100644 include/dm/platform_data/spi_coldfire.h -- 2.19.1

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[U-Boot] [PATCH] arm: mx5: Add LDB clock config code
by Marek Vasut 10 Oct '18

10 Oct '18

Add code to configure PLL4, from which the LDB clock are directly derived. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/include/asm/arch-mx5/clock.h | 1 + arch/arm/mach-imx/mx5/clock.c | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index 0ecbdeede5..6f5ca5888a 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -38,6 +38,7 @@ enum mxc_clock { MXC_NFC_CLK, MXC_PERIPH_CLK, MXC_I2C_CLK, + MXC_LDB_CLK, }; u32 imx_get_uartclk(void); diff --git a/arch/arm/mach-imx/mx5/clock.c b/arch/arm/mach-imx/mx5/clock.c index 427cb12415..dcefc4276a 100644 --- a/arch/arm/mach-imx/mx5/clock.c +++ b/arch/arm/mach-imx/mx5/clock.c @@ -838,6 +838,23 @@ static int config_ddr_clk(u32 emi_clk) return 0; } +static int config_ldb_clk(u32 ref, u32 freq) +{ + int ret = 0; + struct pll_param pll_param; + + memset(&pll_param, 0, sizeof(struct pll_param)); + + ret = calc_pll_params(ref, freq, &pll_param); + if (ret != 0) { + printf("Error:Can't find pll parameters: %d\n", + ret); + return ret; + } + + return config_pll_clk(PLL4_CLOCK, &pll_param); +} + /* * This function assumes the expected core clock has to be changed by * modifying the PLL. This is NOT true always but for most of the times, @@ -879,6 +896,10 @@ int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk) if (config_nfc_clk(freq)) return -EINVAL; break; + case MXC_LDB_CLK: + if (config_ldb_clk(ref, freq)) + return -EINVAL; + break; default: printf("Warning:Unsupported or invalid clock type\n"); } -- 2.18.0

2 2

[U-Boot] [PATCH V2] arm: mx5: Add LDB clock config code
by Marek Vasut 10 Oct '18

10 Oct '18

Add code to configure PLL4, from which the LDB clock are directly derived. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> --- V2: Enable config_ldb_clk() for MX53 only by adding ifdef --- arch/arm/include/asm/arch-mx5/clock.h | 1 + arch/arm/mach-imx/mx5/clock.c | 29 +++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index 0ecbdeede5..6f5ca5888a 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -38,6 +38,7 @@ enum mxc_clock { MXC_NFC_CLK, MXC_PERIPH_CLK, MXC_I2C_CLK, + MXC_LDB_CLK, }; u32 imx_get_uartclk(void); diff --git a/arch/arm/mach-imx/mx5/clock.c b/arch/arm/mach-imx/mx5/clock.c index 427cb12415..2fabdd2eae 100644 --- a/arch/arm/mach-imx/mx5/clock.c +++ b/arch/arm/mach-imx/mx5/clock.c @@ -838,6 +838,31 @@ static int config_ddr_clk(u32 emi_clk) return 0; } +#ifdef CONFIG_MX53 +static int config_ldb_clk(u32 ref, u32 freq) +{ + int ret = 0; + struct pll_param pll_param; + + memset(&pll_param, 0, sizeof(struct pll_param)); + + ret = calc_pll_params(ref, freq, &pll_param); + if (ret != 0) { + printf("Error:Can't find pll parameters: %d\n", + ret); + return ret; + } + + return config_pll_clk(PLL4_CLOCK, &pll_param); +} +#else +static int config_ldb_clk(u32 ref, u32 freq) +{ + /* Platform not supported */ + return -EINVAL; +} +#endif + /* * This function assumes the expected core clock has to be changed by * modifying the PLL. This is NOT true always but for most of the times, @@ -879,6 +904,10 @@ int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk) if (config_nfc_clk(freq)) return -EINVAL; break; + case MXC_LDB_CLK: + if (config_ldb_clk(ref, freq)) + return -EINVAL; + break; default: printf("Warning:Unsupported or invalid clock type\n"); } -- 2.18.0

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[U-Boot] [PATCH] sunxi: fix DRAM gate/reset sequence of H6
by Icenowy Zheng 10 Oct '18

10 Oct '18

Currently the DRAM bus gate and reset is changed at the same time in H6 DRAM initialization code, which disobeys the user manual's programming guide. Fix the sequence by follow the sequence suggested by the user manual (ungate the bus clock after release the reset signal). By some experiments it seems to fix the DRAM size detection failure that rarely happens. Signed-off-by: Icenowy Zheng <icenowy(a)aosc.io> --- arch/arm/mach-sunxi/dram_sun50i_h6.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index 6b94cf38c5..5da90a2835 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -299,6 +299,8 @@ static void mctl_sys_init(struct dram_para *para) /* Put all DRAM-related blocks to reset state */ clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET); + clrbits_le32(&ccm->dram_gate_reset, BIT(0)); + udelay(5); writel(0, &ccm->dram_gate_reset); clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); @@ -313,7 +315,9 @@ static void mctl_sys_init(struct dram_para *para) /* Configure DRAM mod clock */ writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg); setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE); - writel(BIT(0) | BIT(RESET_SHIFT), &ccm->dram_gate_reset); + writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset); + udelay(5); + setbits_le32(&ccm->dram_gate_reset, BIT(0)); /* Disable all channels */ writel(0, &mctl_com->maer0); -- 2.18.0

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[U-Boot] [PATCH v3 0/2] Neutis N5 support
by Aleksandr Aleksandrov 10 Oct '18

10 Oct '18

This series of pathes addes Neutis N5 support. Emlid Neutis N5 is a SoM based on Allwinner H5. 1st patch includes device tree file and defconfig for Dev board and dtsi file for SoM needs. Changes from v1 (4 oct 2018): add to maintainers myself and separate dts file: dtsi for SoM and motherboard dts file that inlcudes dtsi file. Changes from v2 (5 oct 2018): 1/2: - put Jagan Teki and Maxime Ripard in Cc - copy DT files from Linux - makefile: dtb-$(CONFIG_MACH_SUN50I_H5) - ordered alphabetically 2/2: - put Tom Rini in Cc Aleksandr Aleksandrov (2): arm: new board - Emlid Neutis N5 support sunxi MAINTAINERS: add new entry for Emlid Neutis N5 arch/arm/dts/Makefile | 1 + .../arm/dts/sun50i-h5-emlid-neutis-n5-devboard.dts | 184 +++++++++++++++++++++ arch/arm/dts/sun50i-h5-emlid-neutis-n5.dtsi | 96 +++++++++++ board/sunxi/MAINTAINERS | 5 + configs/emlid_neutis_n5_devboard_defconfig | 13 ++ 5 files changed, 299 insertions(+) create mode 100644 arch/arm/dts/sun50i-h5-emlid-neutis-n5-devboard.dts create mode 100644 arch/arm/dts/sun50i-h5-emlid-neutis-n5.dtsi create mode 100644 configs/emlid_neutis_n5_devboard_defconfig -- 2.7.4

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[U-Boot] ZYNQ ZC706 Board
by Rama Chandra 10 Oct '18

10 Oct '18

Hi sir, i am using ZYNQ ZC706 Board and i have downloaded u-boot(2016.7),uImage,root file system files from wiki.xilinx.com website downloaded and properly working all the things. But i am doing manually downloaded u-boot from github and ELDK-5.5.3 version taken export PATH=/opt/eldk-5.5.3/armv7a-hf/sysroots/i686-eldk-linux/usr/bin:/opt/eldk-5.5.3/armv7a-hf/sysroots/i686-eldk-linux/usr/bin/arm-linux-gnueabi:$PATH export ARCH=arm export CROSS_COMPILE=arm-linux-gnueabi- source /opt/eldk-5.5.3/armv7a-hf/environment-setup-* cd /home/ram/Desktop/arm/u-boot-2016.07/ make distclean make zynq_zc706_defconfig make all those above things used created u-boot.bin file but in serial monitor nothing displaying its problem with u-boot version (but both are same versions) or ELDK-5.5.3 is not creating properly -- Thanks & Regards, RamaChandra PC +918892147159.

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[U-Boot] [PATCH 1/3] spi: davinci: Add platdata support
by Jagan Teki 10 Oct '18

10 Oct '18

Davanci spi driver has DM support already, this patch add support for platdata so-that SPL can use it for low foot-print. Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- drivers/spi/davinci_spi.c | 47 +++++++++++++++----------- include/dm/platform_data/spi_davinci.h | 15 ++++++++ 2 files changed, 43 insertions(+), 19 deletions(-) create mode 100644 include/dm/platform_data/spi_davinci.h diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index a822858323..07fa5e3b8a 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -14,6 +14,7 @@ #include <asm/io.h> #include <asm/arch/hardware.h> #include <dm.h> +#include <dm/platform_data/spi_davinci.h> /* SPIGCR0 */ #define SPIGCR0_SPIENA_MASK 0x1 @@ -529,50 +530,58 @@ static int davinci_spi_xfer(struct udevice *dev, unsigned int bitlen, return __davinci_spi_xfer(ds, bitlen, dout, din, flags); } +static const struct dm_spi_ops davinci_spi_ops = { + .claim_bus = davinci_spi_claim_bus, + .release_bus = davinci_spi_release_bus, + .xfer = davinci_spi_xfer, + .set_speed = davinci_spi_set_speed, + .set_mode = davinci_spi_set_mode, +}; + static int davinci_spi_probe(struct udevice *bus) { - /* Nothing to do */ + struct davinci_spi_slave *ds = dev_get_priv(bus); + struct davinci_spi_platdata *plat = bus->platdata; + ds->regs = plat->regs; + ds->num_cs = plat->num_cs; + return 0; } +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) static int davinci_ofdata_to_platadata(struct udevice *bus) { - struct davinci_spi_slave *ds = dev_get_priv(bus); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(bus); + struct davinci_spi_platdata *plat = bus->platdata; + fdt_addr_t addr; - ds->regs = devfdt_map_physmem(bus, sizeof(struct davinci_spi_regs)); - if (!ds->regs) { - printf("%s: could not map device address\n", __func__); + addr = devfdt_get_addr(bus); + if (addr == FDT_ADDR_T_NONE) return -EINVAL; - } - ds->num_cs = fdtdec_get_int(blob, node, "num-cs", 4); + + plat->regs = (struct davinci_spi_regs *)addr; + plat->num_cs = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus), "num-cs", 4); return 0; } -static const struct dm_spi_ops davinci_spi_ops = { - .claim_bus = davinci_spi_claim_bus, - .release_bus = davinci_spi_release_bus, - .xfer = davinci_spi_xfer, - .set_speed = davinci_spi_set_speed, - .set_mode = davinci_spi_set_mode, -}; - static const struct udevice_id davinci_spi_ids[] = { { .compatible = "ti,keystone-spi" }, { .compatible = "ti,dm6441-spi" }, { .compatible = "ti,da830-spi" }, { } }; +#endif U_BOOT_DRIVER(davinci_spi) = { .name = "davinci_spi", .id = UCLASS_SPI, +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) .of_match = davinci_spi_ids, - .ops = &davinci_spi_ops, .ofdata_to_platdata = davinci_ofdata_to_platadata, - .priv_auto_alloc_size = sizeof(struct davinci_spi_slave), + .platdata_auto_alloc_size = sizeof(struct davinci_spi_platdata), +#endif .probe = davinci_spi_probe, + .ops = &davinci_spi_ops, + .priv_auto_alloc_size = sizeof(struct davinci_spi_slave), }; #endif diff --git a/include/dm/platform_data/spi_davinci.h b/include/dm/platform_data/spi_davinci.h new file mode 100644 index 0000000000..fbc62c262a --- /dev/null +++ b/include/dm/platform_data/spi_davinci.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2018 Jagan Teki <jagan(a)amarulasolutions.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __spi_davinci_h +#define __spi_davinci_h + +struct davinci_spi_platdata { + struct davinci_spi_regs *regs; + u8 num_cs; /* total no. of CS available */ +}; + +#endif /* __spi_davinci_h */ -- 2.18.0.321.gffc6fa0e3

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