October 2018 - U-Boot

[U-Boot] [PATCH] fs: btrfs: Fix tree traversal with btrfs_next_slot()
by Yevgeny Popovych 11 Oct '18

11 Oct '18

When traversing slots in a btree (via btrfs_path) with btrfs_next_slot(), we didn't correctly identify that the last slot in the leaf was reached and we should jump to the next leaf. This could lead to any kind of runtime errors or corruptions, like: * file data not being read at all, or is read partially * file is read but is corrupted * (any) metadata being corrupted or not read at all, etc The easiest way to reproduce this is to read a large enough file that its EXTENT_DATA items don't fit into a single leaf. Signed-off-by: Yevgeny Popovych <yevgenyp(a)pointgrab.com> Cc: Marek Behun <marek.behun(a)nic.cz> --- fs/btrfs/ctree.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/btrfs/ctree.c b/fs/btrfs/ctree.c index 4da36a9..b44a47e 100644 --- a/fs/btrfs/ctree.c +++ b/fs/btrfs/ctree.c @@ -270,7 +270,7 @@ int btrfs_next_slot(struct btrfs_path *p) { struct btrfs_leaf *leaf = &p->nodes[0]->leaf; - if (p->slots[0] >= leaf->header.nritems) + if (p->slots[0] + 1 >= leaf->header.nritems) return jump_leaf(p, 1); p->slots[0]++; -- 2.7.4

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[U-Boot] [PATCH] rtc: Add read8 and write8 support to isl1208 driver
by Trent Piepho 11 Oct '18

11 Oct '18

This can be used for device register access from board code. This allows access to capabilities in the RTC chip not abstracted in U-Boot's RTC class. E.g., device NVRAM or a tamper detection circuit. Cc: Klaus Goger <klaus.goger(a)theobroma-systems.com> Cc: Philipp Tomsich <philipp.tomsich(a)theobroma-systems.com> Cc: Simon Glass <sjg(a)chromium.org> Signed-off-by: Trent Piepho <tpiepho(a)impinj.com> --- drivers/rtc/isl1208.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/rtc/isl1208.c b/drivers/rtc/isl1208.c index 22ac0d2b08..59a60b75b3 100644 --- a/drivers/rtc/isl1208.c +++ b/drivers/rtc/isl1208.c @@ -51,6 +51,24 @@ #define RTC_STAT_BIT_BAT 0x02 /* BATTERY BIT */ #define RTC_STAT_BIT_RTCF 0x01 /* REAL TIME CLOCK FAIL BIT */ +/* + * Read an RTC register + */ + +static int isl1208_rtc_read8(struct udevice *dev, unsigned int reg) +{ + return dm_i2c_reg_read(dev, reg); +} + +/* + * Write an RTC register + */ + +static int isl1208_rtc_write8(struct udevice *dev, unsigned int reg, int val) +{ + return dm_i2c_reg_write(dev, reg, val); +} + /* * Get the current time from the RTC */ @@ -161,6 +179,8 @@ static const struct rtc_ops isl1208_rtc_ops = { .get = isl1208_rtc_get, .set = isl1208_rtc_set, .reset = isl1208_rtc_reset, + .read8 = isl1208_rtc_read8, + .write8 = isl1208_rtc_write8, }; static const struct udevice_id isl1208_rtc_ids[] = { -- 2.14.3

3 2

[U-Boot] [PULL] u-boot-sh/master
by Marek Vasut 11 Oct '18

11 Oct '18

The following changes since commit 0a60a81ba3860946551cb79aa6486aa076e357f3: Kconfig: sandbox: enable cmd_avb and dependencies (2018-10-07 13:34:19 -0400) are available in the Git repository at: git://git.denx.de/u-boot-sh.git master for you to fetch changes up to ae400fde75703f2c0744fd60a5314a0d7857a67f: ARM: dts: rmobile: Reinstate missing CPLD on ULCB (2018-10-09 17:21:44 +0200) ---------------------------------------------------------------- Marek Vasut (3): mmc: tmio: Pass full address to tmio_sd_addr_is_dmaable() mmc: tmio: Limit DMA to 32bit on R-Car Gen3 ARM: dts: rmobile: Reinstate missing CPLD on ULCB arch/arm/dts/ulcb.dtsi | 9 +++++++++ drivers/mmc/tmio-common.c | 12 ++++++++++-- 2 files changed, 19 insertions(+), 2 deletions(-) -- Best regards, Marek Vasut

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[U-Boot] [PATCH] axs10x/emdk/hsdk/iot_dk: Implement board_mmc_getcd()
by Alexey Brodkin 11 Oct '18

11 Oct '18

So now we may detect MMC/SD-card existence and instead of completely misleading message on missing card: ------------------------>8----------------------- Loading Environment from FAT... Card did not respond to voltage select! ------------------------>8----------------------- we now get very clear one: ------------------------>8----------------------- Loading Environment from FAT... MMC: no card present ------------------------>8----------------------- Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> --- board/synopsys/axs10x/axs10x.c | 7 +++++++ board/synopsys/emdk/emdk.c | 7 +++++++ board/synopsys/hsdk/hsdk.c | 7 +++++++ board/synopsys/iot_devkit/iot_devkit.c | 7 +++++++ 4 files changed, 28 insertions(+) diff --git a/board/synopsys/axs10x/axs10x.c b/board/synopsys/axs10x/axs10x.c index af78127..c95f7af 100644 --- a/board/synopsys/axs10x/axs10x.c +++ b/board/synopsys/axs10x/axs10x.c @@ -33,6 +33,13 @@ int board_mmc_init(bd_t *bis) return 0; } +int board_mmc_getcd(struct mmc *mmc) +{ + struct dwmci_host *host = mmc->priv; + + return !(dwmci_readl(host, DWMCI_CDETECT) & 1); +} + #define AXS_MB_CREG 0xE0011000 int board_early_init_f(void) diff --git a/board/synopsys/emdk/emdk.c b/board/synopsys/emdk/emdk.c index bbb946a..79cafef 100644 --- a/board/synopsys/emdk/emdk.c +++ b/board/synopsys/emdk/emdk.c @@ -34,6 +34,13 @@ int board_mmc_init(bd_t *bis) return 0; } +int board_mmc_getcd(struct mmc *mmc) +{ + struct dwmci_host *host = mmc->priv; + + return !(dwmci_readl(host, DWMCI_CDETECT) & 1); +} + #define CREG_BASE 0xF0001000 #define CREG_BOOT_OFFSET 0 #define CREG_BOOT_WP_OFFSET 8 diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c index 4f46d2e..b6aefdb 100644 --- a/board/synopsys/hsdk/hsdk.c +++ b/board/synopsys/hsdk/hsdk.c @@ -1019,6 +1019,13 @@ int board_late_init(void) return 0; } +int board_mmc_getcd(struct mmc *mmc) +{ + struct dwmci_host *host = mmc->priv; + + return !(dwmci_readl(host, DWMCI_CDETECT) & 1); +} + int board_mmc_init(bd_t *bis) { struct dwmci_host *host = NULL; diff --git a/board/synopsys/iot_devkit/iot_devkit.c b/board/synopsys/iot_devkit/iot_devkit.c index 40c29e7..f8838fb 100644 --- a/board/synopsys/iot_devkit/iot_devkit.c +++ b/board/synopsys/iot_devkit/iot_devkit.c @@ -170,6 +170,13 @@ int board_mmc_init(bd_t *bis) return 0; } +int board_mmc_getcd(struct mmc *mmc) +{ + struct dwmci_host *host = mmc->priv; + + return !(dwmci_readl(host, DWMCI_CDETECT) & 1); +} + #define IOTDK_RESET_SEQ 0x55AA6699 void reset_cpu(ulong addr) -- 2.7.4

1 0

[U-Boot] [PATCH 1/3] Revert "ARM: imx6: Disable DDR DRAM calibration DHCOM i.MX6 PDK"
by lzenz＠dh-electronics.de 11 Oct '18

11 Oct '18

From: Ludwig Zenz <lzenz(a)dh-electronics.de> This reverts commit a637fe6f27fd4c19ef9f43a5f871c244581422ac. The DDR DRAM calibration was enhanced by write leveling correction code. It can be used with T-topology now. Signed-off-by: Ludwig Zenz <lzenz(a)dh-electronics.de> --- board/dhelectronics/dh_imx6/dh_imx6_spl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index dffe4eb..beda389 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -384,6 +384,10 @@ void board_init_f(ulong dummy) &dhcom6sdl_grp_ioregs); mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr); + /* Perform DDR DRAM calibration */ + udelay(100); + mmdc_do_dqs_calibration(&dhcom_ddr_info); + /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); -- 2.7.4

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[U-Boot] [PATCH] fsl/usb: Workaround for USB erratum-A005275
by Chris Packham 11 Oct '18

11 Oct '18

Workaround makes FS as default mode on all affected socs. Add support to check erratum-A005275 validity for an soc. This info is required to determine whether a given soc is affected by this erratum. Add quirk for this erratum "has_fsl_erratum_a005275" . This quirk is used to enable workaround for the errata Force FS mode as default by: - making EPS as FS - setting PFSC bit to disable HS chirping This workaround can be disabled by mentioning "no_erratum_a005275" in hwconfig string Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- This is based on a patch form Freescale's public git repo[1]. I'm not sure why it never made it upstream but I have P2041RDB boards that are affected as well as custom designs using the same SoC. I've cleaned things up a bit to fit with the other errata. [1] - http://git.freescale.com/git/cgit.cgi/ppc/sdk/u-boot.git/commit/?h=sdk-v1.4… arch/powerpc/cpu/mpc85xx/Kconfig | 8 ++++++++ arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 ++++ drivers/usb/common/fsl-errata.c | 28 +++++++++++++++++++++++++++ drivers/usb/host/ehci-fsl.c | 7 +++++++ drivers/usb/host/ehci-hcd.c | 12 +++++++++++- drivers/usb/host/ehci.h | 4 ++++ include/fsl_usb.h | 1 + 7 files changed, 63 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 7d139fffa24a..309ca294601b 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -659,6 +659,7 @@ config ARCH_P1010 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_A005275 select SYS_FSL_ERRATUM_A006261 select SYS_FSL_ERRATUM_A007075 select SYS_FSL_ERRATUM_ESDHC111 @@ -821,6 +822,7 @@ config ARCH_P2041 select FSL_LAW select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004849 + select SYS_FSL_ERRATUM_A005275 select SYS_FSL_ERRATUM_A006261 select SYS_FSL_ERRATUM_CPU_A003999 select SYS_FSL_ERRATUM_DDR_A003 @@ -845,6 +847,7 @@ config ARCH_P3041 select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004849 + select SYS_FSL_ERRATUM_A005275 select SYS_FSL_ERRATUM_A005812 select SYS_FSL_ERRATUM_A006261 select SYS_FSL_ERRATUM_CPU_A003999 @@ -910,6 +913,7 @@ config ARCH_P5020 select FSL_LAW select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004510 + select SYS_FSL_ERRATUM_A005275 select SYS_FSL_ERRATUM_A006261 select SYS_FSL_ERRATUM_DDR_A003 select SYS_FSL_ERRATUM_DDR_A003474 @@ -935,6 +939,7 @@ config ARCH_P5040 select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004699 + select SYS_FSL_ERRATUM_A005275 select SYS_FSL_ERRATUM_A005812 select SYS_FSL_ERRATUM_A006261 select SYS_FSL_ERRATUM_DDR_A003 @@ -1303,6 +1308,9 @@ config SYS_FSL_ERRATUM_A005812 config SYS_FSL_ERRATUM_A005871 bool +config SYS_FSL_ERRATUM_A005275 + bool + config SYS_FSL_ERRATUM_A006261 bool diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index eda2e7e63d76..e455d8baf584 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -307,6 +307,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) puts("Work-around for Erratum I2C-A004447 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005275 + if (has_erratum_a005275()) + puts("Work-around for Erratum A005275 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 if (has_erratum_a006261()) puts("Work-around for Erratum A006261 enabled\n"); diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c index 386130d7a1f6..9eb1d2306725 100644 --- a/drivers/usb/common/fsl-errata.c +++ b/drivers/usb/common/fsl-errata.c @@ -6,6 +6,7 @@ */ #include <common.h> +#include <hwconfig.h> #include <fsl_errata.h> #include<fsl_usb.h> #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \ @@ -44,6 +45,33 @@ bool has_dual_phy(void) return false; } +bool has_erratum_a005275(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + if (hwconfig("no_erratum_a005275")) + return false; + + switch (soc) { +#ifdef CONFIG_PPC + case SVR_P3041: + case SVR_P2041: + case SVR_P2040: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); + case SVR_P5010: + case SVR_P5020: + case SVR_P5021: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_P5040: + case SVR_P1010: + return IS_SVR_REV(svr, 1, 0); +#endif + } + + return false; +} + bool has_erratum_a006261(void) { u32 svr = get_svr(); diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index a04f6a31c8e4..71e4ded53100 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -93,6 +93,7 @@ static int ehci_fsl_probe(struct udevice *dev) struct usb_ehci *ehci = NULL; struct ehci_hccr *hccr; struct ehci_hcor *hcor; + struct ehci_ctrl *echi_ctrl = &priv->echi; /* * Get the base address for EHCI controller from the device node @@ -107,6 +108,8 @@ static int ehci_fsl_probe(struct udevice *dev) hcor = (struct ehci_hcor *) ((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275(); + if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0) return -ENXIO; @@ -145,6 +148,8 @@ U_BOOT_DRIVER(ehci_fsl) = { int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { + struct ehci_ctrl *ehci_ctrl = container_of(hccr, + struct ehci_ctrl, hccr); struct usb_ehci *ehci = NULL; switch (index) { @@ -163,6 +168,8 @@ int ehci_hcd_init(int index, enum usb_init_type init, *hcor = (struct ehci_hcor *)((uint32_t) *hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275(); + return ehci_fsl_init(index, ehci, *hccr, *hcor); } diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 199b3a8b264d..d1d8f08d9867 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -409,9 +409,15 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) | QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) | QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) | - QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) | QH_ENDPT1_DEVADDR(usb_pipedevice(pipe)); + + /* Force FS for fsl HS quirk */ + if (!ctrl->has_fsl_erratum_a005275) + endpt |= QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)); + else + endpt |= QH_ENDPT1_EPS(ehci_encode_speed(QH_FULL_SPEED)); + qh->qh_endpt1 = cpu_to_hc32(endpt); endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0); qh->qh_endpt2 = cpu_to_hc32(endpt); @@ -832,6 +838,10 @@ static int ehci_submit_root(struct usb_device *dev, unsigned long pipe, } else { int ret; + /* Disable chirp for HS erratum */ + if (ctrl->has_fsl_erratum_a005275) + reg |= PORTSC_FSL_PFSC; + reg |= EHCI_PS_PR; reg &= ~EHCI_PS_PE; ehci_writel(status_reg, reg); diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 7945016624da..6c359af90c94 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -8,6 +8,7 @@ #ifndef USB_EHCI_H #define USB_EHCI_H +#include <stdbool.h> #include <usb.h> #include <generic-phy.h> @@ -66,6 +67,8 @@ struct ehci_hcor { #define PORTSC_PSPD_FS 0x0 #define PORTSC_PSPD_LS 0x1 #define PORTSC_PSPD_HS 0x2 +#define PORTSC_FSL_PFSC BIT(24) /* PFSC bit to disable HS chirping */ + uint32_t or_systune; } __attribute__ ((packed, aligned(4))); @@ -251,6 +254,7 @@ struct ehci_ctrl { uint32_t *periodic_list; int periodic_schedules; int ntds; + bool has_fsl_erratum_a005275; /* Freescale HS silicon quirk */ struct ehci_ops ops; void *priv; /* client's private data */ }; diff --git a/include/fsl_usb.h b/include/fsl_usb.h index e9e1dd69053e..c0f076b06daf 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -87,6 +87,7 @@ struct ccsr_usb_phy { /* USB Erratum Checking code */ #if defined(CONFIG_PPC) || defined(CONFIG_ARM) bool has_dual_phy(void); +bool has_erratum_a005275(void); bool has_erratum_a006261(void); bool has_erratum_a007075(void); bool has_erratum_a007798(void); -- 2.19.0

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[U-Boot] [PATCH 00/20] Add support for MediaTek SoCs - MT7623n / MT7629
by Ryder Lee 11 Oct '18

11 Oct '18

Hello, This is first round (time) to add U-boot support for MediaTek SoCs (MT7623n and MT7629), and the most of the drivers are based on mainline Linux, like clock, timer, mmc, pinctrl, watchdog, power domain and DTS. The following are the major differences between Linux and U-boot: - modify the driver interface to adapt the U-boot DM framework. - remove unneeded DT nodes as they don't have proper drivers in U-boot yet. - just add the basic functions (step-by-step) so that we can monitor the size. - reuse ns16550.c but add a highspeed register for MediaTek UARTs. - add a whole new SNOR driver mtk_qspi.c which is based on SPI master-slave hierarchy. Our current progress: The MT7623n (BananaPi R2) which has already supported in mainline Linux. - We can choice to boot from eMMC or SD card. (ROM -> MediaTek preloder -> U-boot ...) - MT7623n has an open development board called BananaPi R2 [1]. The MT7629 which has NOT supported in mainline Linux yet, but we will do it soon. - Boot from SNOR. (ROM -> (boot header parsing sequence) -> SPL -> U-boot ...) [1] http://wiki.banana-pi.org/Banana_Pi_BPI-R2 Thanks, Ryder Guochun Mao (1): spi: mtk_qspi: add qspi driver for MT7629 SoC Ryder Lee (16): tools: MediaTek: add MTK boot header generation to mkimage arm: MediaTek: add basic support for MT7629 boards arm: dts: MediaTek: add MT7629 reference board support arm: dts: MediaTek: add MT7623 Bananapi R2 board support configs: MediaTek: add MT7629 reference board support clk: MediaTek: add clock driver for MT7629 SoC. clk: MediaTek: add clock driver for MT7623 SoC. timer: MediaTek: add timer driver for MediaTek SoCs watchdog: MediaTek: add watchdog driver for MediaTek SoCs pinctrl: MediaTek: add pinctrl driver for MT7629 SoC pinctrl: MediaTek: add pinctrl driver for MT7623 SoC power domain: MediaTek: add power domain driver for MT7629 SoC power domain: MediaTek: add power domain driver for MT7623 SoC serial: 16550: allow the driver to support MediaTek serial ram: MediaTek: add DDR3 driver for MT7629 SoC MAINTAINERS: add an entry for MediaTek Weijie Gao (3): arm: MediaTek: add basic support for MT7623 boards configs: MediaTek: add MT7623 Bananapi R2 board support mmc: mtk-sd: add SD/MMC host controller driver for MT7623 SoC MAINTAINERS | 18 + Makefile | 20 + arch/arm/Kconfig | 14 + arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 4 + arch/arm/dts/mt7623.dtsi | 258 +++++ arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 207 ++++ arch/arm/dts/mt7629-rfb.dts | 71 ++ arch/arm/dts/mt7629.dtsi | 232 +++++ arch/arm/include/asm/arch-mediatek/gpio.h | 9 + arch/arm/mach-mediatek/Kconfig | 32 + arch/arm/mach-mediatek/Makefile | 7 + arch/arm/mach-mediatek/cpu.c | 34 + arch/arm/mach-mediatek/include/mach/chipid.h | 17 + arch/arm/mach-mediatek/include/mach/gpio.h | 9 + arch/arm/mach-mediatek/init.h | 11 + arch/arm/mach-mediatek/mt7623/Makefile | 4 + arch/arm/mach-mediatek/mt7623/init.c | 53 + arch/arm/mach-mediatek/mt7623/lowlevel_init.S | 22 + arch/arm/mach-mediatek/mt7623/preloader.h | 99 ++ arch/arm/mach-mediatek/mt7629/Makefile | 4 + arch/arm/mach-mediatek/mt7629/init.c | 142 +++ arch/arm/mach-mediatek/mt7629/lowlevel_init.S | 50 + arch/arm/mach-mediatek/spl.c | 43 + board/mediatek/mt7623/Kconfig | 13 + board/mediatek/mt7623/MAINTAINERS | 7 + board/mediatek/mt7623/Makefile | 4 + board/mediatek/mt7623/mt7623_rfb.c | 16 + board/mediatek/mt7629/Kconfig | 17 + board/mediatek/mt7629/MAINTAINERS | 7 + board/mediatek/mt7629/Makefile | 4 + board/mediatek/mt7629/mt7629_rfb.c | 16 + common/image.c | 1 + configs/mt7623n_bpir2_defconfig | 53 + configs/mt7629_rfb_defconfig | 73 ++ drivers/clk/Makefile | 1 + drivers/clk/mediatek/Makefile | 7 + drivers/clk/mediatek/clk-mt7623.c | 867 +++++++++++++++++ drivers/clk/mediatek/clk-mt7629.c | 666 +++++++++++++ drivers/clk/mediatek/clk-mtk.c | 494 ++++++++++ drivers/clk/mediatek/clk-mtk.h | 151 +++ drivers/mmc/Kconfig | 9 + drivers/mmc/Makefile | 1 + drivers/mmc/mtk-sd.c | 1286 +++++++++++++++++++++++++ drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/mediatek/Kconfig | 15 + drivers/pinctrl/mediatek/Makefile | 7 + drivers/pinctrl/mediatek/pinctrl-mt7623.c | 1280 ++++++++++++++++++++++++ drivers/pinctrl/mediatek/pinctrl-mt7629.c | 489 ++++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 558 +++++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 186 ++++ drivers/power/domain/Kconfig | 7 + drivers/power/domain/Makefile | 1 + drivers/power/domain/mtk-power-domain.c | 406 ++++++++ drivers/ram/Makefile | 1 + drivers/ram/mediatek/Makefile | 7 + drivers/ram/mediatek/ddr3-mt7629.c | 766 +++++++++++++++ drivers/serial/ns16550.c | 10 + drivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/mtk_qspi.c | 406 ++++++++ drivers/timer/Kconfig | 7 + drivers/timer/Makefile | 1 + drivers/timer/mtk_timer.c | 85 ++ drivers/watchdog/Kconfig | 8 + drivers/watchdog/Makefile | 1 + drivers/watchdog/mtk_wdt.c | 135 +++ include/configs/mt7623.h | 66 ++ include/configs/mt7629.h | 70 ++ include/dt-bindings/clock/mt7623-clk.h | 429 +++++++++ include/dt-bindings/clock/mt7629-clk.h | 217 +++++ include/dt-bindings/power/mt7623-power.h | 19 + include/dt-bindings/power/mt7629-power.h | 13 + include/dt-bindings/reset/mt7623-resets.h | 85 ++ include/image.h | 1 + scripts/Makefile.spl | 11 + tools/Makefile | 1 + tools/mtkimage.c | 748 ++++++++++++++ tools/mtkimage.h | 199 ++++ 80 files changed, 11299 insertions(+) create mode 100644 arch/arm/dts/mt7623.dtsi create mode 100644 arch/arm/dts/mt7623n-bananapi-bpi-r2.dts create mode 100644 arch/arm/dts/mt7629-rfb.dts create mode 100644 arch/arm/dts/mt7629.dtsi create mode 100644 arch/arm/include/asm/arch-mediatek/gpio.h create mode 100644 arch/arm/mach-mediatek/Kconfig create mode 100644 arch/arm/mach-mediatek/Makefile create mode 100644 arch/arm/mach-mediatek/cpu.c create mode 100644 arch/arm/mach-mediatek/include/mach/chipid.h create mode 100644 arch/arm/mach-mediatek/include/mach/gpio.h create mode 100644 arch/arm/mach-mediatek/init.h create mode 100644 arch/arm/mach-mediatek/mt7623/Makefile create mode 100644 arch/arm/mach-mediatek/mt7623/init.c create mode 100644 arch/arm/mach-mediatek/mt7623/lowlevel_init.S create mode 100644 arch/arm/mach-mediatek/mt7623/preloader.h create mode 100644 arch/arm/mach-mediatek/mt7629/Makefile create mode 100644 arch/arm/mach-mediatek/mt7629/init.c create mode 100644 arch/arm/mach-mediatek/mt7629/lowlevel_init.S create mode 100644 arch/arm/mach-mediatek/spl.c create mode 100644 board/mediatek/mt7623/Kconfig create mode 100644 board/mediatek/mt7623/MAINTAINERS create mode 100644 board/mediatek/mt7623/Makefile create mode 100644 board/mediatek/mt7623/mt7623_rfb.c create mode 100644 board/mediatek/mt7629/Kconfig create mode 100644 board/mediatek/mt7629/MAINTAINERS create mode 100644 board/mediatek/mt7629/Makefile create mode 100644 board/mediatek/mt7629/mt7629_rfb.c create mode 100644 configs/mt7623n_bpir2_defconfig create mode 100644 configs/mt7629_rfb_defconfig create mode 100644 drivers/clk/mediatek/Makefile create mode 100644 drivers/clk/mediatek/clk-mt7623.c create mode 100644 drivers/clk/mediatek/clk-mt7629.c create mode 100644 drivers/clk/mediatek/clk-mtk.c create mode 100644 drivers/clk/mediatek/clk-mtk.h create mode 100644 drivers/mmc/mtk-sd.c create mode 100644 drivers/pinctrl/mediatek/Kconfig create mode 100644 drivers/pinctrl/mediatek/Makefile create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7623.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7629.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h create mode 100644 drivers/power/domain/mtk-power-domain.c create mode 100644 drivers/ram/mediatek/Makefile create mode 100644 drivers/ram/mediatek/ddr3-mt7629.c create mode 100644 drivers/spi/mtk_qspi.c create mode 100644 drivers/timer/mtk_timer.c create mode 100644 drivers/watchdog/mtk_wdt.c create mode 100644 include/configs/mt7623.h create mode 100644 include/configs/mt7629.h create mode 100644 include/dt-bindings/clock/mt7623-clk.h create mode 100644 include/dt-bindings/clock/mt7629-clk.h create mode 100644 include/dt-bindings/power/mt7623-power.h create mode 100644 include/dt-bindings/power/mt7629-power.h create mode 100644 include/dt-bindings/reset/mt7623-resets.h create mode 100644 tools/mtkimage.c create mode 100644 tools/mtkimage.h -- 1.9.1

4 33

[U-Boot] [PATCH][v2] armv8: lx2160a: Add LX2160A SoC Support
by Priyanka Jain 11 Oct '18

11 Oct '18

LX2160A Soc is based on Layerscape Chassis Generation 3.2 Architecture. Features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, two 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao(a)nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal(a)nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma(a)nxp.com> Signed-off-by: Sriram Dash <sriram.dash(a)nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- Changes for v2: Add CCN508 define Rebased on TF-A Boot support for NXP Chassis 2 platforms Removed eSDHC nodes from dts, will be send in separate patch. Add reset related changes arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 52 +++++++- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 6 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 15 ++- arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 57 +++++++++ .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 36 ++++++ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 +- arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 132 +++++++++++++++++++++ arch/arm/dts/fsl-lx2160a.dtsi | 118 ++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 56 +++++++++ .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 28 +++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 22 ++++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 6 + .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 9 +- drivers/ddr/fsl/Kconfig | 1 + drivers/net/ldpaa_eth/Makefile | 3 +- drivers/net/ldpaa_eth/lx2160a.c | 107 +++++++++++++++++ 16 files changed, 640 insertions(+), 10 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c create mode 100644 arch/arm/dts/fsl-lx2160a.dtsi create mode 100644 drivers/net/ldpaa_eth/lx2160a.c diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 650ac94..2b086da 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -170,6 +170,42 @@ config ARCH_LS2080A imply DISTRO_DEFAULTS imply PANIC_HANG +config ARCH_LX2160A + bool + select ARMV8_SET_SMPEN + select FSL_LSCH3 + select NXP_LSCH3_2 + select SYS_HAS_SERDES + select SYS_FSL_SRDS_1 + select SYS_FSL_SRDS_2 + select SYS_NXP_SRDS_3 + select SYS_FSL_DDR + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_EC1 + select SYS_FSL_EC2 + select SYS_FSL_HAS_RGMII + select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_CCN508 + select SYS_FSL_HAS_DDR4 + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 + select SYS_I2C_MXC_I2C5 + select SYS_I2C_MXC_I2C6 + select SYS_I2C_MXC_I2C7 + select SYS_I2C_MXC_I2C8 + imply DISTRO_DEFAULTS + imply PANIC_HANG + imply SCSI + imply SCSI_AHCI + config FSL_LSCH2 bool select SYS_FSL_HAS_CCI400 @@ -185,7 +221,7 @@ config NXP_LSCH3_2 config FSL_MC_ENET bool "Management Complex network" - depends on ARCH_LS2080A || ARCH_LS1088A + depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A default y select RESV_RAM help @@ -202,6 +238,7 @@ config FSL_PCIE_COMPAT default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A default "fsl,ls1088a-pcie" if ARCH_LS1088A + default "fsl,lx2160a-pcie" if ARCH_LX2160A help This compatible is used to find pci controller node in Kernel DT to complete fixup. @@ -300,6 +337,7 @@ config MAX_CPUS default 4 if ARCH_LS1046A default 16 if ARCH_LS2080A default 8 if ARCH_LS1088A + default 16 if ARCH_LX2160A default 1 help Set this number to the maximum number of possible CPUs in the SoC. @@ -342,6 +380,9 @@ config SYS_FSL_HAS_CCI400 config SYS_FSL_HAS_CCN504 bool +config SYS_FSL_HAS_CCN508 + bool + config SYS_FSL_HAS_DP_DDR bool @@ -404,6 +445,7 @@ config SYS_FSL_DSPI_CLK_DIV config SYS_FSL_DUART_CLK_DIV int "DUART clock divider" default 1 if ARCH_LS1043A + default 4 if ARCH_LX2160A default 2 help This is the divider that is used to derive DUART clock from Platform @@ -464,13 +506,15 @@ config RESV_RAM config SYS_FSL_EC1 bool help - Ethernet controller 1, this is connected to MAC3. + Ethernet controller 1, this is connected to + MAC17 for LX2160A or to MAC3 for other SoCs Provides DPAA2 capabilities config SYS_FSL_EC2 bool help - Ethernet controller 2, this is connected to MAC4. + Ethernet controller 2, this is connected to + MAC18 for LX2160A or to MAC4 for other SoCs Provides DPAA2 capabilities config SYS_FSL_ERRATUM_A008336 @@ -506,7 +550,7 @@ config SYS_FSL_HAS_RGMII config SYS_MC_RSV_MEM_ALIGN hex "Management Complex reserved memory alignment" depends on RESV_RAM - default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A + default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A help Reserved memory needs to be aligned for MC to use. Default value is 512MB. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 5d6f68a..3710ad6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# +# Copyright 2016-2018 NXP # Copyright 2014-2015, Freescale Semiconductor obj-y += cpu.o @@ -22,6 +22,10 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o endif endif +ifneq ($(CONFIG_ARCH_LX2160A),) +obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o +endif + ifneq ($(CONFIG_ARCH_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 8dbcab7..8f357b0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -60,6 +60,9 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), CPU_TYPE_ENTRY(LS1048A, LS1048A, 4), CPU_TYPE_ENTRY(LS1044A, LS1044A, 4), + CPU_TYPE_ENTRY(LX2160A, LX2160A, 16), + CPU_TYPE_ENTRY(LX2120A, LX2120A, 12), + CPU_TYPE_ENTRY(LX2080A, LX2080A, 8), }; #define EARLY_PGTABLE_SIZE 0x5000 @@ -246,7 +249,7 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#ifdef CONFIG_ARCH_LS2080A +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | @@ -366,6 +369,10 @@ void cpu_name(char *name) for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { strcpy(name, cpu_type_list[i].name); +#ifdef CONFIG_ARCH_LX2160A + if (IS_C_PROCESSOR(svr)) + strcat(name, "C"); +#endif if (IS_E_PROCESSOR(svr)) strcat(name, "E"); @@ -1165,10 +1172,16 @@ void __efi_runtime reset_cpu(ulong addr) { u32 val; +#ifdef CONFIG_ARCH_LX2160A + val = in_le32(rstcr); + val |= 0x01; + out_le32(rstcr, val); +#else /* Raise RESET_REQ_B */ val = scfg_in32(rstcr); val |= 0x02; scfg_out32(rstcr, val); +#endif } #ifdef CONFIG_EFI_LOADER diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index 276ab90..a0e2621 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -7,6 +7,7 @@ SoC overview 5. LS1046A 6. LS2088A 7. LS2081A + 8. LX2160A LS1043A --------- @@ -271,3 +272,59 @@ Refer to LS2084A(LS2088A) section above for details. It has one more similar SoC personality 1)LS2041A, few difference w.r.t. LS2081A: a) Four 64-bit ARM v8 Cortex-A72 CPUs + +LX2160A +-------- +The QorIQ LX2160A processor is built in the 16FFC process on +the Layerscape architecture combining sixteen ARM A72 processor +cores with advanced, high-performance datapath acceleration and +network, peripheral interfaces required for networking, wireless +infrastructure, storage, and general-purpose embedded applications. + +LX2160A is compliant with the Layerscape Chassis Generation 3.2. + +The LX2160A SoC includes the following function and features: + Sixteen 32-bit / 64-bit ARM v8 A72 CPUs + Cache Coherent Interconnect Fabric (CCN508 aka “Eliot”) + Two 64-bit 3.2GT/s DDR4 SDRAM memory controllers with ECC. + Data path acceleration architecture (DPAA2) + 24 Serdes lanes at up to 25 GHz + Ethernet interfaces + Single WRIOP tile supporting 130Gbps using 18 MACs + Support for 10G-SXGMII (aka USXGMII). + Support for SGMII (and 1000Base-KX) + Support for XFI (and 10GBase-KR) + Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G). + Support for XLAUI (and 40GBase-KR4) for 40G. + Support for two RGMII parallel interfaces. + Energy efficient Ethernet support (802.3az) + IEEE 1588 support. + High-speed peripheral interfaces + Two PCIe Gen 4.0 8-lane controllers supporting SR-IOV, + Four PCIe Gen 4.0 4-lane controllers. + Four serial ATA (SATA 3.0) controllers. + Two USB 3.0 controllers with integrated PHY + Two Enhanced secure digital host controllers + Two Controller Area Network (CAN) modules + Flexible Serial peripheral interface (FlexSPI) controller. + Three Serial peripheral interface (SPI) controllers. + Eight I2C Controllers. + Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports. + General Purpose IO (GPIO) + Support for hardware virtualization and partitioning (ARM MMU-500) + Support for GIC (ARM GIC-500) + QorIQ platform Trust Architecture 3.0 + One Secure WatchDog timer and one Non-Secure Watchdog timer. + ARM Generic Timer + Two Flextimers + Debug supporting run control, data acquisition, high-speed trace, + performance/event monitoring + Thermal Monitor Unit (TMU) with +/- 2C accuracy + Support for Voltage ID (VID) for yield improvement + +LX2160A SoC has 2 more similar SoC personalities +1)LX2120A, few difference w.r.t. LX2160A: + a) Twelve 64-bit ARM v8 Cortex-A72 CPUs + +2)LX2080A, few difference w.r.t. LX2160A: + a) Eight 64-bit ARM v8 Cortex-A72 CPUs diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index bb50e3d..ab1be3f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -22,9 +22,18 @@ static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT]; #endif #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_ARCH_LX2160A +int xfi_dpmac[XFI14 + 1]; +int sgmii_dpmac[SGMII18 + 1]; +int a25gaui_dpmac[_25GE10 + 1]; +int xlaui_dpmac[_40GE2 + 1]; +int caui2_dpmac[_50GE2 + 1]; +int caui4_dpmac[_100GE2 + 1]; +#else int xfi_dpmac[XFI8 + 1]; int sgmii_dpmac[SGMII16 + 1]; #endif +#endif __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) { @@ -146,6 +155,32 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, else { serdes_prtcl_map[lane_prtcl] = 1; #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_ARCH_LX2160A + if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14) + wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18) + wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10) + wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2) + wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2) + wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2) + wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl], + (int)lane_prtcl); + +#else switch (lane_prtcl) { case QSGMII_A: case QSGMII_B: @@ -167,6 +202,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, break; } #endif +#endif } } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index cbc9112..6721a57 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -354,7 +354,7 @@ get_svr: ret #endif -#ifdef CONFIG_SYS_FSL_HAS_CCN504 +#if defined(CONFIG_SYS_FSL_HAS_CCN504) || defined(CONFIG_SYS_FSL_HAS_CCN508) hnf_pstate_poll: /* x0 has the desired status, return 0 for success, 1 for timeout * clobber x1, x2, x3, x4, x6, x7 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c new file mode 100644 index 0000000..a04a370 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <asm/arch/fsl_serdes.h> + +struct serdes_config { + u8 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x02, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII6, SGMII5, SGMII4, SGMII3 } }, + {0x03, {PCIE2, PCIE2, PCIE2, PCIE2, XFI6, XFI5, XFI4, + XFI3 } }, + {0x04, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, + SGMII3 } }, + {0x05, {XFI10, XFI9, XFI8, XFI7, PCIE1, PCIE1, PCIE1, + PCIE1 } }, + {0x06, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, XFI4, + XFI3 } }, + {0x07, {SGMII10, SGMII9, SGMII8, SGMII7, XFI6, XFI5, XFI4, + XFI3 } }, + {0x08, {XFI10, XFI9, XFI8, XFI7, XFI6, XFI5, XFI4, XFI3 } }, + {0x09, {SGMII10, SGMII9, SGMII8, PCIE2, SGMII6, SGMII5, SGMII4, + PCIE1 } }, + {0x0A, {XFI10, XFI9, XFI8, PCIE2, XFI6, XFI5, XFI4, PCIE1 } }, + {0x0B, {SGMII10, SGMII9, PCIE2, PCIE2, SGMII6, SGMII5, PCIE1, PCIE1 } }, + {0x0C, {SGMII10, SGMII9, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x0D, {_100GE2, _100GE2, _100GE2, _100GE2, _100GE1, _100GE1, _100GE1, + _100GE1 } }, + {0x0E, {PCIE2, PCIE2, PCIE2, PCIE2, _100GE1, _100GE1, _100GE1, + _100GE1 } }, + {0x0F, {PCIE2, PCIE2, PCIE2, PCIE2, _50GE2, _50GE2, _50GE1, _50GE1 } }, + {0x10, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _50GE1, _50GE1 } }, + {0x11, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, _25GE3 } }, + {0x12, {XFI10, XFI9, XFI8, XFI7, _25GE6, _25GE5, XFI4, + XFI3 } }, + {0x13, {_40GE2, _40GE2, _40GE2, _40GE2, _25GE6, _25GE5, XFI4, XFI3 } }, + {0x14, {_40GE2, _40GE2, _40GE2, _40GE2, _40GE1, _40GE1, _40GE1, + _40GE1 } }, + {0x15, {_25GE10, _25GE9, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, + _25GE3 } }, + {0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } }, + {} +}; + +static struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {0x01, {PCIE3, PCIE3, SATA1, SATA2, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x02, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, + {0x03, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x04, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, + {0x05, {PCIE3, PCIE3, PCIE3, PCIE3, SATA3, SATA4, SATA1, SATA2 } }, + {0x06, {PCIE3, PCIE3, PCIE3, PCIE3, SGMII15, SGMII16, XFI13, + XFI14 } }, + {0x07, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, XFI13, + XFI14 } }, + {0x08, {NONE, NONE, SATA1, SATA2, SATA3, SATA4, XFI13, XFI14 } }, + {0x09, {SGMII11, SGMII12, SGMII17, SGMII18, SGMII15, SGMII16, SGMII13, + SGMII14} }, + {0x0A, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, PCIE4, + PCIE4 } }, + {0x0B, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, SGMII13, + SGMII14 } }, + {0x0C, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, SATA1, + SATA2 } }, + {0x0D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII13, SGMII14 } }, + {0x0E, {PCIE3, PCIE3, SGMII17, SGMII18, PCIE4, PCIE4, SGMII13, + SGMII14 } }, + {} +}; + +static struct serdes_config serdes3_cfg_tbl[] = { + /* SerDes 3 */ + {0x02, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5 } }, + {0x03, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE6, PCIE6, PCIE6, PCIE6 } }, + {} +}; + +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, + serdes2_cfg_tbl, + serdes3_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi new file mode 100644 index 0000000..b407dc6 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP lx2160a SOC common device tree source + * + * Copyright 2018 NXP + * + */ + +/ { + compatible = "fsl,lx2160a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>; + /* DRAM space - 1, size : 2 GB DRAM */ + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + clockgen: clocking@1300000 { + compatible = "fsl,ls2080a-clockgen"; + reg = <0 0x1300000 0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + gic: interrupt-controller@6000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + <0x0 0x06200000 0 0x100000>; /* GICR */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <1 9 0x4>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ + <1 14 0x8>, /* Physical NS PPI, active-low */ + <1 11 0x8>, /* Virtual PPI, active-low */ + <1 10 0x8>; /* Hypervisor PPI, active-low */ + }; + + uart0: serial@21c0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21c0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + }; + + uart1: serial@21d0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21d0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + }; + + uart2: serial@21e0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21e0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + uart3: serial@21f0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21f0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 26 0x4>; /* Level high type */ + num-cs = <6>; + }; + + dspi1: dspi@2110000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <0 240 0x4>; /* Level high type */ + num-cs = <6>; + }; + + dspi2: dspi@2120000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2120000 0x0 0x10000>; + interrupts = <0 241 0x4>; /* Level high type */ + num-cs = <6>; + }; + + usb0: usb3@3100000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; /* Level high type */ + dr_mode = "host"; + }; + + usb1: usb3@3110000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; /* Level high type */ + dr_mode = "host"; + }; +}; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 8a05148..c2abc7a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright 2016-2018 NXP * Copyright 2015, Freescale Semiconductor */ @@ -176,6 +177,61 @@ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ +/* LX2160A Soc Support */ +#elif defined(CONFIG_ARCH_LX2160A) +#define TZPC_BASE 0x02200000 +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_EARLY_INIT +#define SRDS_MAX_LANES 8 +#ifndef L1_CACHE_BYTES +#define L1_CACHE_SHIFT 6 +#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) +#endif +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 } +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 + +#define CONFIG_SYS_PAGE_SIZE 0x10000 + +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ + +/* DDR */ +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE + +#define CONFIG_SYS_FSL_CCSR_GUR_LE +#define CONFIG_SYS_FSL_CCSR_SCFG_LE +#define CONFIG_SYS_FSL_ESDHC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE + +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06200000 + +/* SMMU Definitions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */ + +/* SFP */ +#define CONFIG_SYS_FSL_SFP_VER_3_4 +#define CONFIG_SYS_FSL_SFP_LE +#define CONFIG_SYS_FSL_SRK_LE + +/* Security Monitor */ +#define CONFIG_SYS_FSL_SEC_MON_LE + +/* Secure Boot */ +#define CONFIG_ESBC_HDR_LS + +/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE + +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + #elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index c041a31..68354ff 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -20,8 +20,12 @@ enum srds_prtcl { PCIE2, PCIE3, PCIE4, + PCIE5, + PCIE6, SATA1, SATA2, + SATA3, + SATA4, XAUI1, XAUI2, XFI1, @@ -32,6 +36,12 @@ enum srds_prtcl { XFI6, XFI7, XFI8, + XFI9, + XFI10, + XFI11, + XFI12, + XFI13, + XFI14, SGMII1, SGMII2, SGMII3, @@ -48,10 +58,28 @@ enum srds_prtcl { SGMII14, SGMII15, SGMII16, + SGMII17, + SGMII18, QSGMII_A, QSGMII_B, QSGMII_C, QSGMII_D, + _25GE1, + _25GE2, + _25GE3, + _25GE4, + _25GE5, + _25GE6, + _25GE7, + _25GE8, + _25GE9, + _25GE10, + _40GE1, + _40GE2, + _50GE1, + _50GE2, + _100GE1, + _100GE2, SERDES_PRCTL_COUNT }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 7fb24c0..2ed6b99 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -328,6 +328,28 @@ struct ccsr_gur { #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT #define FSL_CHASSIS3_SRDS1_REGSR 29 #define FSL_CHASSIS3_SRDS2_REGSR 29 +#elif defined(CONFIG_ARCH_LX2160A) +#define FSL_CHASSIS3_EC1_REGSR 27 +#define FSL_CHASSIS3_EC2_REGSR 27 +#define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003 +#define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT 0 +#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x00000007 +#define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT 2 +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000 +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0x03E00000 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 21 +#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK 0x7C000000 +#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT 26 +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK +#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS3_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK +#define FSL_CHASSIS3_SRDS3_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS1_REGSR 29 +#define FSL_CHASSIS3_SRDS2_REGSR 29 +#define FSL_CHASSIS3_SRDS3_REGSR 29 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_CHASSIS3_EC1_REGSR 26 #define FSL_CHASSIS3_EC2_REGSR 26 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index daa1c70..f5bef6d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -96,12 +96,18 @@ enum boot_src get_boot_src(void); #define SVR_LS2044A 0x870930 #define SVR_LS2081A 0x870918 #define SVR_LS2041A 0x870914 +#define SVR_LX2160A 0x873601 +#define SVR_LX2120A 0x873621 +#define SVR_LX2080A 0x873603 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_REV(svr) (((svr) >> 0) & 0xff) #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) +#ifdef CONFIG_ARCH_LX2160A +#define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1)) +#endif #define IS_SVR_REV(svr, maj, min) \ ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) #define SVR_DEV(svr) ((svr) >> 8) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index afea9b8..ca273f0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright 2015-2018 NXP * Copyright 2014 Freescale Semiconductor, Inc. * */ @@ -66,11 +67,11 @@ #define FSL_SDMMC_STREAM_ID 3 #define FSL_SATA1_STREAM_ID 4 -#if defined(CONFIG_ARCH_LS2080A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) #define FSL_SATA2_STREAM_ID 5 #endif -#if defined(CONFIG_ARCH_LS2080A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) #define FSL_DMA_STREAM_ID 6 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_DMA_STREAM_ID 5 @@ -79,6 +80,10 @@ /* PCI - programmed in PEXn_LUT */ #define FSL_PEX_STREAM_ID_START 7 +#ifdef CONFIG_ARCH_LX2160A +#define FSL_PEX_STREAM_ID_NUM (0x100) +#endif + #if defined(CONFIG_ARCH_LS2080A) #define FSL_PEX_STREAM_ID_END 22 #elif defined(CONFIG_ARCH_LS1088A) diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index a3d2bd5..c5bd8a8 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -34,6 +34,7 @@ config SYS_NUM_DDR_CTLRS ARCH_P4080 || \ ARCH_P5020 || \ ARCH_P5040 || \ + ARCH_LX2160A || \ ARCH_T4160 default 1 diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile index 477ee4f..1d85b2c 100644 --- a/drivers/net/ldpaa_eth/Makefile +++ b/drivers/net/ldpaa_eth/Makefile @@ -1,8 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ -# +# Copyright 2015-2018 NXP # Copyright 2014 Freescale Semiconductor, Inc. obj-y += ldpaa_wriop.o obj-y += ldpaa_eth.o obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o +obj-$(CONFIG_ARCH_LX2160A) += lx2160a.o diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c new file mode 100644 index 0000000..7dd46c0 --- /dev/null +++ b/drivers/net/ldpaa_eth/lx2160a.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ +#include <common.h> +#include <phy.h> +#include <fsl-mc/ldpaa_wriop.h> +#include <asm/io.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> + +u32 dpmac_to_devdisr[] = { + [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1, + [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2, + [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3, + [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4, + [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5, + [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6, + [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7, + [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8, + [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9, + [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10, + [WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11, + [WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12, + [WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13, + [WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14, + [WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15, + [WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16, + [WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17, + [WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18, +}; + +static int is_device_disabled(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 devdisr2 = in_le32(&gur->devdisr2); + + return dpmac_to_devdisr[dpmac_id] & devdisr2; +} + +void wriop_dpmac_disable(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); +} + +void wriop_dpmac_enable(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); +} + +phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl) +{ + enum srds_prtcl; + + if (is_device_disabled(dpmac_id + 1)) + return PHY_INTERFACE_MODE_NONE; + + if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18) + return PHY_INTERFACE_MODE_SGMII; + + if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14) + return PHY_INTERFACE_MODE_XGMII; + + if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10) + return PHY_INTERFACE_MODE_25G_AUI; + + if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2) + return PHY_INTERFACE_MODE_XLAUI; + + if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2) + return PHY_INTERFACE_MODE_CAUI2; + + if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2) + return PHY_INTERFACE_MODE_CAUI4; + + return PHY_INTERFACE_MODE_NONE; +} + +#ifdef CONFIG_SYS_FSL_HAS_RGMII +void fsl_rgmii_init(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 ec; + +#ifdef CONFIG_SYS_FSL_EC1 + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1]) + & FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK; + ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT; + + if (!ec) + wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID); +#endif + +#ifdef CONFIG_SYS_FSL_EC2 + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1]) + & FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK; + ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT; + + if (!ec) + wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID); +#endif +} +#endif -- 2.7.4

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[U-Boot] [PATCH] image-fdt: reserve lmb for fdt
by Andy Yan 11 Oct '18

11 Oct '18

Memory region for fdt should be reserved, or they may be allocated by other module via lmb_alloc. Then the fdt data will be destroy. We found a case on a board with 64MB DRAM like bellow: No ethernet found. Hit any key to stop autoboot: 0 ANDROID: reboot reason: "recovery" FDT load addr 0x10f00000 size 41 KiB Booting kernel at 0x2008000 with fdt at 2c8ac00... lmb_add base:0x58000 size:0x3fa8000 lmb_add base:0x0 size:0x0 lmb_reserve base:0x34ca2a0 size:0xb35d60 Booting Android Image at 0x02008000 ... Kernel load addr 0x02008800 size 3808 KiB RAM disk load addr 0x11000000 size 9000 KiB * fdt: cmdline image address = 0x02c8ac00 Checking for 'FDT'/'FDT Image' at 02c8ac00 * fdt: raw FDT blob Flattened Device Tree blob at 02c8ac00 Booting using the fdt blob at 0x2c8ac00 of_flat_tree at 0x02c8ac00 size 0x00009d6d XIP Kernel Image ... OK do_bootm_states reserve: 0x2008800 -- 0x3b7c30 lmb_reserve base:0x2008800 size:0x3b7c30 no initrd_high env_get_bootm_size size:66748416(0x3fa8000) tmp:360448(0x58000) start:360448(0x58000) initrd_high = 0x03fa8000, copy_to_ram = 1 Loading Ramdisk to 02c00000, end 034c9d09 ... OK ERROR: image is not a fdt - must RESET the board to recover. FDT creation failed! hanging...### ERROR ### Please RESET the board ### Signed-off-by: Andy Yan <andy.yan(a)rock-chips.com> --- common/image-fdt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/common/image-fdt.c b/common/image-fdt.c index 9b41f16248..56f6d7e26b 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -422,6 +422,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, *of_flat_tree = fdt_blob; *of_size = fdt_totalsize(fdt_blob); + lmb_reserve(&images->lmb, (ulong)*of_flat_tree, *of_size); debug(" of_flat_tree at 0x%08lx size 0x%08lx\n", (ulong)*of_flat_tree, *of_size); -- 2.17.1

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[U-Boot] 4 failures with 'ut dm'
by Bin Meng 11 Oct '18

11 Oct '18

Hi Simon, With current u-boot/master, there are 4 failures with 'ut dm'. I was wondering is this not covered by travis-ci? Test: dm_test_bus_children: bus.c test/dm/bus.c:112, dm_test_bus_children(): num_devices == list_count_items(&uc->dev_head): Expected 7, got 6 Test: dm_test_fdt: test-fdt.c test/dm/test-fdt.c:184, dm_test_fdt(): num_devices == list_count_items(&uc->dev_head): Expected 7, got 6 Test: dm_test_spmi_access: spmi.c test/dm/spmi.c:55, dm_test_spmi_access(): 0 == device_get_child(bus, 0, &pmic): Expected 0, got -22 Test: dm_test_spmi_access_peripheral: spmi.c test/dm/spmi.c:82, dm_test_spmi_access_peripheral(): 0 == gpio_lookup_name("spmi1", &dev, &offset, &gpio): Expected 0, got -22 Regards, Bin

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