October 2018 - U-Boot

[U-Boot] [PATCH] armv8: lx2160ardb : Add support for LX2160ARDB platform
by Priyanka Jain 15 Oct '18

15 Oct '18

LX2160ARDB is an evaluation board that supports LX2160A family SoCs. This patch add base support for this board. Signed-off-by: Wasim Khan <wasim.khan(a)nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur(a)nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal(a)nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma(a)nxp.com> Signed-off-by: Sriram Dash <sriram.dash(a)nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat(a)nxp.com> Signed-off-by: Pankit Garg <pankit.garg(a)nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- Depends on https://patchwork.ozlabs.org/project/uboot/list/?series=70506 TF-A Boot support for NXP Chassis 2 platforms https://patchwork.ozlabs.org/patch/982274/ Add LX2160A SoC Support arch/arm/Kconfig | 14 ++ arch/arm/cpu/armv8/Kconfig | 2 +- arch/arm/dts/Makefile | 3 +- arch/arm/dts/fsl-lx2160a-rdb.dts | 20 +++ board/freescale/common/qixis.c | 4 + board/freescale/lx2160a/Kconfig | 16 ++ board/freescale/lx2160a/MAINTAINERS | 8 + board/freescale/lx2160a/Makefile | 9 + board/freescale/lx2160a/README | 79 +++++++++ board/freescale/lx2160a/ddr.c | 20 +++ board/freescale/lx2160a/eth_lx2160ardb.c | 210 +++++++++++++++++++++++ board/freescale/lx2160a/lx2160a.c | 279 +++++++++++++++++++++++++++++++ configs/lx2160ardb_tfa_defconfig | 74 ++++++++ include/configs/lx2160a_common.h | 214 ++++++++++++++++++++++++ include/configs/lx2160ardb.h | 102 +++++++++++ 15 files changed, 1052 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/fsl-lx2160a-rdb.dts create mode 100644 board/freescale/lx2160a/Kconfig create mode 100644 board/freescale/lx2160a/MAINTAINERS create mode 100644 board/freescale/lx2160a/Makefile create mode 100644 board/freescale/lx2160a/README create mode 100644 board/freescale/lx2160a/ddr.c create mode 100644 board/freescale/lx2160a/eth_lx2160ardb.c create mode 100644 board/freescale/lx2160a/lx2160a.c create mode 100644 configs/lx2160ardb_tfa_defconfig create mode 100644 include/configs/lx2160a_common.h create mode 100644 include/configs/lx2160ardb.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9f5eaf8..8ef72f5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1018,6 +1018,19 @@ config TARGET_LS2081ARDB development platform that supports the QorIQ LS2081A/LS2041A Layerscape Architecture processor. +config TARGET_LX2160ARDB + bool "Support lx2160ardb" + select ARCH_LX2160A + select ARCH_MISC_INIT + select ARM64 + select ARMV8_MULTIENTRY + select BOARD_LATE_INIT + help + Support for NXP LX2160ARDB platform. + The lx2160ardb (LX2160A Reference design board (RDB) + is a high-performance development platform that supports the + QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor. + config TARGET_HIKEY bool "Support HiKey 96boards Consumer Edition Platform" select ARM64 @@ -1478,6 +1491,7 @@ source "board/freescale/ls1046ardb/Kconfig" source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/ls1012afrdm/Kconfig" +source "board/freescale/lx2160a/Kconfig" source "board/freescale/mx35pdk/Kconfig" source "board/freescale/s32v234evb/Kconfig" source "board/grinn/chiliboard/Kconfig" diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index c8bebab..aac3aeb 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -105,7 +105,7 @@ config PSCI_RESET !TARGET_LS1012AFRWY && \ !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ - !TARGET_LS2081ARDB && \ + !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ !ARCH_UNIPHIER && !TARGET_S32V234EVB help Most armv8 systems have PSCI support enabled in EL3, either through diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ebfa227..0c3c396 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -226,7 +226,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2081a-rdb.dtb \ fsl-ls2088a-rdb-qspi.dtb \ fsl-ls1088a-rdb.dtb \ - fsl-ls1088a-qds.dtb + fsl-ls1088a-qds.dtb \ + fsl-lx2160a-rdb.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts new file mode 100644 index 0000000..08201b5 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-rdb.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160ARDB device tree source + * + * Author: Priyanka Jain <priyanka.jain(a)nxp.com> + * Sriram Dash <sriram.dash(a)nxp.com> + * + * Copyright 2018 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a.dtsi" + +/ { + model = "NXP Layerscape LX2160ARDB Board"; + compatible = "fsl,lx2160ardb", "fsl,lx2160a"; + +}; diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index af3dc59..f1b98bc 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -227,8 +227,12 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar #ifdef QIXIS_LBMAP_SD QIXIS_WRITE(rst_ctl, 0x30); QIXIS_WRITE(rcfg_ctl, 0); +#ifdef NON_EXTENDED_DUTCFG + QIXIS_WRITE(dutcfg[0], QIXIS_RCW_SRC_SD); +#else set_lbmap(QIXIS_LBMAP_SD); set_rcw_src(QIXIS_RCW_SRC_SD); +#endif QIXIS_WRITE(rcfg_ctl, 0x20); QIXIS_WRITE(rcfg_ctl, 0x21); #else diff --git a/board/freescale/lx2160a/Kconfig b/board/freescale/lx2160a/Kconfig new file mode 100644 index 0000000..5562c3e --- /dev/null +++ b/board/freescale/lx2160a/Kconfig @@ -0,0 +1,16 @@ +if TARGET_LX2160ARDB + +config SYS_BOARD + default "lx2160a" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "lx2160ardb" + +source "board/freescale/common/Kconfig" +endif diff --git a/board/freescale/lx2160a/MAINTAINERS b/board/freescale/lx2160a/MAINTAINERS new file mode 100644 index 0000000..b4dd842 --- /dev/null +++ b/board/freescale/lx2160a/MAINTAINERS @@ -0,0 +1,8 @@ +LX2160ARDB BOARD +M: Priyanka Jain <priyanka.jain(a)nxp.com> +S: Maintained +F: board/freescale/lx2160a/ +F: include/configs/lx2160a_common.h +F: include/configs/lx2160ardb.h +F: configs/lx2160ardb_defconfig +F: arch/arm/dts/fsl-lx2160a-rdb.dts diff --git a/board/freescale/lx2160a/Makefile b/board/freescale/lx2160a/Makefile new file mode 100644 index 0000000..be3709d --- /dev/null +++ b/board/freescale/lx2160a/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2018 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += lx2160a.o +obj-y += ddr.o +obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o diff --git a/board/freescale/lx2160a/README b/board/freescale/lx2160a/README new file mode 100644 index 0000000..5b99de8 --- /dev/null +++ b/board/freescale/lx2160a/README @@ -0,0 +1,79 @@ +Overview +-------- +The LX2160A Reference Design (RDB) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LX2160A +Layerscape Architecture processor and its personalities. + +LX2160A SoC Overview +-------------------------------------- +For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc + +LX2160ARDB board Overview +---------------------- +DDR Memory + Two ports of 72-bits (8-bits ECC) DDR4. + Each port supports four chip-selects and two DIMM + connectors. Data rate upto 3.2 GT/s. + +SERDES ports + Thress serdes controllers (24 lanes) + Serdes1: Supports two USXGMII connectors, each connected through + Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi + IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi + CS4223 phy. + + Serdes2: Supports one PCIe x4 (Gen1/2/3/4) connector, four SATA 3.0 + connectors + + Serdes3: Supports one PCIe x8 (Gen1/2/3/4) connector + +eSDHC + eSDHC1: Supports a SD connector for connecting SD cards + eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC + +Octal SPI (XSPI) + Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator + for off-board emulation + +I2C All system devices on I2C1 multiplexed using PCA9547 multiplexer + Serial Ports + +USB 3.0 + Two high speed USB 3.0 ports. First USB 3.0 port configured as + Host with Type-A connector, second USB 3.0 port configured as OTG + with micro-AB connector + +Serial Ports Two UART ports +Ethernet Two RGMII interfaces +Debug ARM JTAG support + +Booting Options +--------------- +a) Flexspi boot +b) SD boot + +Memory map for Flexspi flash +---------------------------- +Image Flash Offset +bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl) 0x00000000 +fip.bin (bl31 + bl33(u-boot) + + header for Secure-boot(secure-boot only)) 0x00100000 +Boot firmware Environment 0x00500000 +DDR PHY Firmware (fip_ddr_all.bin) 0x00800000 +DPAA2 MC Firmware 0x00A00000 +DPAA2 DPL 0x00D00000 +DPAA2 DPC 0x00E00000 +Kernel.itb 0x01000000 + +Memory map for sd card +---------------------------- +Image SD card Offset +bl2_sd.pbl (RCW+PBI+bl2.pbl) 0x00008 +fip.bin (bl31 + bl33(u-boot) + + header for Secure-boot(secure-boot only)) 0x00800 +Boot firmware Environment 0x02800 +DDR PHY Firmware (fip_ddr_all.bin) 0x04000 +DPAA2 MC Firmware 0x05000 +DPAA2 DPL 0x06800 +DPAA2 DPC 0x07000 +Kernel.itb 0x08000 diff --git a/board/freescale/lx2160a/ddr.c b/board/freescale/lx2160a/ddr.c new file mode 100644 index 0000000..cd422bf --- /dev/null +++ b/board/freescale/lx2160a/ddr.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> + +DECLARE_GLOBAL_DATA_PTR; + +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} diff --git a/board/freescale/lx2160a/eth_lx2160ardb.c b/board/freescale/lx2160a/eth_lx2160ardb.c new file mode 100644 index 0000000..ab75582 --- /dev/null +++ b/board/freescale/lx2160a/eth_lx2160ardb.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <malloc.h> +#include <fsl_mdio.h> +#include <miiphy.h> +#include <phy.h> +#include <fm_eth.h> +#include <asm/io.h> +#include <exports.h> +#include <asm/arch/fsl_serdes.h> +#include <fsl-mc/fsl_mc.h> +#include <fsl-mc/ldpaa_wriop.h> + +DECLARE_GLOBAL_DATA_PTR; + +static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad) +{ + int phy_reg; + u32 phy_id; + + phy_reg = bus->read(bus, addr, devad, MII_PHYSID1); + phy_id = (phy_reg & 0xffff) << 16; + + phy_reg = bus->read(bus, addr, devad, MII_PHYSID2); + phy_id |= (phy_reg & 0xffff); + + if (phy_id == PHY_UID_IN112525_S03) + return true; + else + return false; +} + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FSL_MC_ENET) + struct memac_mdio_info mdio_info; + struct memac_mdio_controller *reg; + int i, interface; + struct mii_dev *dev; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_le32(&gur->rcwsr[28]) & + FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; + mdio_info.regs = reg; + mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; + + /* Register the EMI 1 */ + fm_memac_mdio_init(bis, &mdio_info); + + reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; + mdio_info.regs = reg; + mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; + + /* Register the EMI 2 */ + fm_memac_mdio_init(bis, &mdio_info); + + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); + switch (srds_s1) { + case 19: + wriop_set_phy_address(WRIOP1_DPMAC2, + CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC3, + AQR107_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC4, + AQR107_PHY_ADDR2); + if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) { + wriop_set_phy_address(WRIOP1_DPMAC5, + INPHI_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC6, + INPHI_PHY_ADDR1); + } + wriop_set_phy_address(WRIOP1_DPMAC17, + RGMII_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC18, + RGMII_PHY_ADDR2); + break; + + case 18: + wriop_set_phy_address(WRIOP1_DPMAC7, + CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC8, + CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC9, + CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC10, + CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC3, + AQR107_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC4, + AQR107_PHY_ADDR2); + if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) { + wriop_set_phy_address(WRIOP1_DPMAC5, + INPHI_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC6, + INPHI_PHY_ADDR1); + } + wriop_set_phy_address(WRIOP1_DPMAC17, + RGMII_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC18, + RGMII_PHY_ADDR2); + break; + + default: + printf("SerDes1 protocol 0x%x is not supported on LX2160ARDB\n", + srds_s1); + goto next; + } + + for (i = WRIOP1_DPMAC2; i <= WRIOP1_DPMAC10; i++) { + interface = wriop_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); + wriop_set_mdio(i, dev); + break; + case PHY_INTERFACE_MODE_25G_AUI: + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); + wriop_set_mdio(i, dev); + break; + case PHY_INTERFACE_MODE_XLAUI: + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); + wriop_set_mdio(i, dev); + break; + default: + break; + } + } + for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) { + interface = wriop_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); + wriop_set_mdio(i, dev); + break; + default: + break; + } + } + +next: + cpu_eth_init(bis); +#endif /* CONFIG_FSL_MC_ENET */ + +#ifdef CONFIG_PHY_AQUANTIA + /* + * Export functions to be used by AQ firmware + * upload application + */ + gd->jt->strcpy = strcpy; + gd->jt->mdelay = mdelay; + gd->jt->mdio_get_current_dev = mdio_get_current_dev; + gd->jt->phy_find_by_mask = phy_find_by_mask; + gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; + gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; +#endif + return pci_eth_init(bis); +} + +#if defined(CONFIG_RESET_PHY_R) +void reset_phy(void) +{ +#if defined(CONFIG_FSL_MC_ENET) + mc_env_boot(); +#endif +} +#endif /* CONFIG_RESET_PHY_R */ + +int fdt_fixup_board_phy(void *fdt) +{ + int mdio_offset; + int ret; + struct mii_dev *dev; + + ret = 0; + + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); + if (!get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) { + mdio_offset = fdt_path_offset(fdt, "/soc/mdio@0x8B97000"); + + if (mdio_offset < 0) + mdio_offset = fdt_path_offset(fdt, "/mdio@0x8B97000"); + + if (mdio_offset < 0) { + printf("mdio@0x8B9700 node not found in dts\n"); + return mdio_offset; + } + + ret = fdt_setprop_string(fdt, mdio_offset, "status", + "disabled"); + if (ret) { + printf("Could not set disable mdio@0x8B97000 %s\n", + fdt_strerror(ret)); + return ret; + } + } + + return ret; +} diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c new file mode 100644 index 0000000..0214c57 --- /dev/null +++ b/board/freescale/lx2160a/lx2160a.c @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <dm.h> +#include <dm/platform_data/serial_pl01x.h> +#include <i2c.h> +#include <malloc.h> +#include <errno.h> +#include <netdev.h> +#include <fsl_ddr.h> +#include <fsl_sec.h> +#include <asm/io.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <fsl-mc/fsl_mc.h> +#include <environment.h> +#include <efi_loader.h> +#include <asm/arch/mmu.h> +#include <hwconfig.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> +#include "../common/qixis.h" +#include "../common/vid.h" +#include <fsl_immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct pl01x_serial_platdata serial0 = { +#if CONFIG_CONS_INDEX == 0 + .base = CONFIG_SYS_SERIAL0, +#elif CONFIG_CONS_INDEX == 1 + .base = CONFIG_SYS_SERIAL1, +#else +#error "Unsupported console index value." +#endif + .type = TYPE_PL011, +}; + +U_BOOT_DEVICE(nxp_serial0) = { + .name = "serial_pl01x", + .platdata = &serial0, +}; + +static struct pl01x_serial_platdata serial1 = { + .base = CONFIG_SYS_SERIAL1, + .type = TYPE_PL011, +}; + +U_BOOT_DEVICE(nxp_serial1) = { + .name = "serial_pl01x", + .platdata = &serial1, +}; + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +static void uart_get_clock(void) +{ + serial0.clock = get_serial_clock(); + serial0.clock = get_serial_clock(); +} + +int board_early_init_f(void) +{ +#ifdef CONFIG_SYS_I2C_EARLY_INIT + i2c_early_init_f(); +#endif + /* get required clock for UART IP */ + uart_get_clock(); + + fsl_lsch3_early_init_f(); + return 0; +} + +int esdhc_status_fixup(void *blob, const char *compat) +{ + /* Enable both esdhc DT nodes for LX2160ARDB */ + do_fixup_by_compat(blob, compat, "status", "okay", + sizeof("okay"), 1); + + return 0; +} + +#if defined(CONFIG_VID) +int i2c_multiplexer_select_vid_channel(u8 channel) +{ + return select_i2c_ch_pca9547(channel); +} + +#endif + +int checkboard(void) +{ + enum boot_src src = get_boot_src(); + char buf[64]; + u8 sw; + + cpu_name(buf); + printf("Board: %s-RDB, ", buf); + + sw = QIXIS_READ(arch); + printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A'); + + if (src == BOOT_SOURCE_SD_MMC) { + puts("SD\n"); + } else { + sw = QIXIS_READ(brdcfg[0]); + sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK; + switch (sw) { + case 0: + case 4: + puts("FlexSPI DEV#0\n"); + break; + case 1: + puts("FlexSPI DEV#1\n"); + break; + case 2: + case 3: + puts("FlexSPI EMU\n"); + break; + default: + printf("invalid setting, xmap: %d\n", sw); + break; + } + } + printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); + + puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n"); + puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); + puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n"); + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + return 100000000; +} + +unsigned long get_board_ddr_clk(void) +{ + return 100000000; +} + +int board_init(void) +{ +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + + return 0; +} + +void detail_board_ddr_info(void) +{ + int i; + u64 ddr_size = 0; + + puts("\nDDR "); + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + ddr_size += gd->bd->bi_dram[i].size; + print_size(ddr_size, ""); + print_ddr_info(0); +} + +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + return 0; +} +#endif + +#ifdef CONFIG_FSL_MC_ENET +extern int fdt_fixup_board_phy(void *fdt); + +void fdt_fixup_board_enet(void *fdt) +{ + int offset; + + offset = fdt_path_offset(fdt, "/soc/fsl-mc"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/fsl-mc"); + + if (offset < 0) { + printf("%s: fsl-mc node not found in device tree (error %d)\n", + __func__, offset); + return; + } + + if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) { + fdt_status_okay(fdt, offset); + fdt_fixup_board_phy(fdt); + } else { + fdt_status_fail(fdt, offset); + } +} + +void board_quiesce_devices(void) +{ + fsl_mc_ldpaa_exit(gd->bd); +} +#endif + +#ifdef CONFIG_OF_BOARD_SETUP + +int ft_board_setup(void *blob, bd_t *bd) +{ + int i; + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + ft_cpu_setup(blob, bd); + + /* fixup DT for the three GPP DDR banks */ + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + base[i] = gd->bd->bi_dram[i].start; + size[i] = gd->bd->bi_dram[i].size; + } + +#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; + else if (gd->arch.resv_ram >= base[2] && + gd->arch.resv_ram < base[2] + size[2]) + size[2] = gd->arch.resv_ram - base[2]; +#endif + + fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); + +#ifdef CONFIG_USB + fsl_fdt_fixup_dr_usb(blob, bd); +#endif + +#ifdef CONFIG_FSL_MC_ENET + fdt_fsl_mc_fixup_iommu_map_entry(blob); + fdt_fixup_board_enet(blob); +#endif + + return 0; +} +#endif + +void qixis_dump_switch(void) +{ + int i, nr_of_cfgsw; + + QIXIS_WRITE(cms[0], 0x00); + nr_of_cfgsw = QIXIS_READ(cms[1]); + + puts("DIP switch settings dump:\n"); + for (i = 1; i <= nr_of_cfgsw; i++) { + QIXIS_WRITE(cms[0], i); + printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); + } +} diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig new file mode 100644 index 0000000..fb1102e --- /dev/null +++ b/configs/lx2160ardb_tfa_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_TARGET_LX2160ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" +CONFIG_NR_DRAM_BANKS=3 +CONFIG_DM=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_TFABOOT=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_SERIAL=y +CONFIG_CONS_INDEX=0 +CONFIG_FSL_CAAM=y +CONFIG_FSL_ESDHC=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_USE_4K_SECTORS=n +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_NXP_FSPI=y +CONFIG_FSPI_AHB_EN_4BYTE=y +CONFIG_SYS_FSPI_AHB_INIT=y +CONFIG_PHYLIB=y +CONFIG_NETDEVICES=y +CONFIG_PHY_GIGE=y +CONFIG_CMD_NET=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_FAT=y +CONFIG_CMD_EXT2=y +CONFIG_NET=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +# CONFIG_SYS_FSL_DDR_PHY is not set +CONFIG_SYS_GEN2_DDR_PHY=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_PHYLIB_10G=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_CORTINA=y +CONFIG_PHY_ATHEROS=y +CONFIG_PHY_INPHI=y +CONFIG_INPHI_25G=y +CONFIG_HUSH_PARSER=y +CONFIG_EMC2305=y diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h new file mode 100644 index 0000000..5c08c87 --- /dev/null +++ b/include/configs/lx2160a_common.h @@ -0,0 +1,214 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __LX2_COMMON_H +#define __LX2_COMMON_H + +#include <asm/arch/stream_id_lsch3.h> +#include <asm/arch/config.h> +#include <asm/arch/soc.h> + +#define CONFIG_REMAKE_ELF +#define CONFIG_FSL_LAYERSCAPE +#define CONFIG_GICV3 +#define CONFIG_FSL_TZPC_BP147 +#define CONFIG_FSL_MEMAC + +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_FLASH_BASE 0x20000000 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F 1 + +/* DDR */ +#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 +#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL +#define CONFIG_DDR_SPD +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS3 0x53 +#define SPD_EEPROM_ADDRESS4 0x54 +#define SPD_EEPROM_ADDRESS5 0x55 +#define SPD_EEPROM_ADDRESS6 0x56 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 +#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ +#define CONFIG_SYS_MONITOR_LEN (936 * 1024) + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Generic Timer Definitions */ +/* + * This is not an accurate number. It is used in start.S. The frequency + * will be udpated later when get_bus_freq(0) is available. + */ + +#define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) + +/* Serial Port */ +#define CONFIG_PL01X_SERIAL +#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4) +#define CONFIG_SYS_SERIAL0 0x21c0000 +#define CONFIG_SYS_SERIAL1 0x21d0000 +#define CONFIG_SYS_SERIAL2 0x21e0000 +#define CONFIG_SYS_SERIAL3 0x21f0000 +/*below might needs to be removed*/ +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1, \ + (void *)CONFIG_SYS_SERIAL2, \ + (void *)CONFIG_SYS_SERIAL3 } +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* MC firmware */ +#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 + +/* Define phy_reset function to boot the MC based on mcinitcmd. + * This happens late enough to properly fixup u-boot env MAC addresses. + */ +#define CONFIG_RESET_PHY_R + +/* + * Carve out a DDR region which will not be used by u-boot/Linux + * + * It will be used by MC and Debug Server. The MC region must be + * 512MB aligned, so the min size to hide is 512MB. + */ +#ifdef CONFIG_FSL_MC_ENET +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) +#endif + +/* I2C bus multiplexer */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ +#define I2C_MUX_CH_DEFAULT 0x8 + +/* RTC */ +#define RTC +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* Qixis */ +#define CONFIG_FSL_QIXIS +#define CONFIG_QIXIS_I2C_ACCESS +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 + +/* PCI */ +#ifdef CONFIG_PCI +#define CONFIG_SYS_PCI_64BIT +#define CONFIG_PCI_SCAN_SHOW +#endif + +/* MMC */ +#ifdef CONFIG_MMC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#endif + +/* SATA */ + +#ifdef CONFIG_SCSI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 +#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#endif + +/* USB */ +#ifdef CONFIG_USB +#define CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +/* FlexSPI */ +#ifdef CONFIG_NXP_FSPI +#define NXP_FSPI_FLASH_SIZE SZ_64M +#define NXP_FSPI_FLASH_NUM 1 +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_OFFSET 0x50000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ + CONFIG_ENV_OFFSET) + +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +/* Initial environment variables */ +#define XSPI_NOR_BOOTCOMMAND "fsl_mc apply dpl 0x20d00000;" \ + "sf probe 0:0;" \ + "sf read 0xa0000000 0x1000000 0x3000000;" \ + "bootm 0xa0000000" + +#define SD_BOOTCOMMAND "mmc read 0xa0000000 0x6800 0xA0;" \ + "fsl_mc apply dpl 0xa0000000;" \ + "mmc read 0xb0000000 0x8000 0x1d000;" \ + "bootm 0xb0000000" + +#define XSPI_MC_INIT_CMD \ + "fsl_mc start mc 0x20a00000 0x20e00000\0" + +#define SD_MC_INIT_CMD \ + "mmc read 0x80000000 0x5000 0x800;" \ + "mmc read 0x80100000 0x7000 0x800;" \ + "fsl_mc start mc 0x80000000 0x80100000\0" + +#endif /* __LX2_COMMON_H */ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h new file mode 100644 index 0000000..67d214d --- /dev/null +++ b/include/configs/lx2160ardb.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __LX2_RDB_H +#define __LX2_RDB_H + +#include "lx2160a_common.h" + +/* Qixis */ +#define QIXIS_XMAP_MASK 0x07 +#define QIXIS_XMAP_SHIFT 5 +#define QIXIS_RST_CTL_RESET_EN 0x30 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x20 +#define QIXIS_LBMAP_QSPI 0x00 +#define QIXIS_RCW_SRC_QSPI 0xff +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SD +#define QIXIS_RCW_SRC_SD 0x08 +#define NON_EXTENDED_DUTCFG + +/* VID */ + +#define I2C_MUX_CH_VOL_MONITOR 0xA +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x63 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 +#define CONFIG_VID_FLS_ENV "lx2160ardb_vdd_mv" +#define CONFIG_VID + +/* The lowest and highest voltage allowed*/ +#define VDD_MV_MIN 775 +#define VDD_MV_MAX 855 + +/* PM Bus commands code for LTC3882*/ +#define PMBUS_CMD_PAGE 0x0 +#define PMBUS_CMD_READ_VOUT 0x8B +#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 +#define PMBUS_CMD_VOUT_COMMAND 0x21 +#define PWM_CHANNEL0 0x0 + +#define CONFIG_VOL_MONITOR_LTC3882_SET +#define CONFIG_VOL_MONITOR_LTC3882_READ + +/* RTC */ +#define CONFIG_SYS_RTC_BUS_NUM 4 + +/* MAC/PHY configuration */ +#if defined(CONFIG_FSL_MC_ENET) +#define CONFIG_MII +#define CONFIG_ETHPRIME "DPMAC1@xgmii" + +#define AQR107_PHY_ADDR1 0x04 +#define AQR107_PHY_ADDR2 0x05 + +#define CORTINA_NO_FW_UPLOAD +#define CORTINA_PHY_ADDR1 0x0 +#define INPHI_PHY_ADDR1 0x0 + +#define RGMII_PHY_ADDR1 0x01 +#define RGMII_PHY_ADDR2 0x02 + +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "scriptaddr=0x80800000\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x81000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "ramdisk_addr_r=0x89000000\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x21000000\0" \ + "lx2160ardb_vdd_mv=800\0" \ + "mcmemsize=0x40000000\0" + +#include <asm/fsl_secure_boot.h> + +#endif /* __LX2_RDB_H */ -- 2.7.4

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[U-Boot] [PATCH v10 01/16] test: regmap: Increase size of syscon0 memory
by Mario Six 15 Oct '18

15 Oct '18

The upcoming changes to the regmap interface will contain a proper check for plausibility when reading/writing from/to a register map. To still have the current tests pass, increase the size of the memory region for the syscon0 device, since one of the tests reads and writes beyond this range. Reviewed-by: Anatolij Gustschin <agust(a)denx.de> Reviewed-by: Simon Glass <sjg(a)chromium.org> Signed-off-by: Mario Six <mario.six(a)gdsys.cc> --- v9 -> v10: No changes v8 -> v9: No changes v7 -> v8: No changes v6 -> v7: No changes v5 -> v6: * Fix the test that checks the changed size v4 -> v5: No changes v3 -> v4: No changes v2 -> v3: New in v3 --- arch/sandbox/dts/test.dts | 2 +- test/dm/regmap.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 491f889f3b..a14ddea54c 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -474,7 +474,7 @@ syscon@0 { compatible = "sandbox,syscon0"; - reg = <0x10 4>; + reg = <0x10 16>; }; syscon@1 { diff --git a/test/dm/regmap.c b/test/dm/regmap.c index d4b86b3b03..b28d6a6cd1 100644 --- a/test/dm/regmap.c +++ b/test/dm/regmap.c @@ -25,7 +25,7 @@ static int dm_test_regmap_base(struct unit_test_state *uts) ut_assertok_ptr(map); ut_asserteq(1, map->range_count); ut_asserteq(0x10, map->ranges[0].start); - ut_asserteq(4, map->ranges[0].size); + ut_asserteq(16, map->ranges[0].size); ut_asserteq(0x10, map_to_sysmem(regmap_get_range(map, 0))); ut_assertok(uclass_get_device(UCLASS_SYSCON, 1, &dev)); -- 2.11.0

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[U-Boot] [PATCH] ARM: omap3_logic: Add NOR Flash Support for SOM-LV
by Adam Ford 14 Oct '18

14 Oct '18

The DM37 and OMAP35 SOM-LV SOM-LV products both support a NOR flash part connected to CS2 in addition to the NAND part on CS0. This patch setups the GPMC timings for the MT28 NOR Flash and enables the CFI-Flash driver now that the CFI stuff is in Kconfig Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 4507b1ed99..c3ff8a990c 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -40,6 +40,22 @@ DECLARE_GLOBAL_DATA_PTR; +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1 0x00011203 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2 0x000A1302 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3 0x000F1302 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4 0x0A021303 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5 0x00120F18 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6 0x0A030000 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 0x00000C50 + +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1 0x00011203 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2 0x00091102 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3 0x000D1102 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4 0x09021103 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5 0x00100D15 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50 + /* This is only needed until SPL gets OF support */ #ifdef CONFIG_SPL_BUILD static const struct ns16550_platdata omap3logic_serial = { @@ -208,6 +224,16 @@ int misc_init_r(void) return 0; } +static const u32 gpmc_dm37_c2nor_config[] = { + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 +}; + /* * Routine: board_init * Description: Early hardware init. @@ -219,6 +245,10 @@ int board_init(void) /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + /* Enable CS2 for NOR Flash */ + enable_gpmc_cs_config(gpmc_dm37_c2nor_config, &gpmc_cfg->cs[2], + 0x10000000, GPMC_SIZE_64M); + return 0; } diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index 4521aedb2a..de47aad69b 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -24,8 +24,8 @@ CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_CACHE=y -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)" +CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y @@ -39,6 +39,11 @@ CONFIG_FASTBOOT_BUF_ADDR=0x82000000 CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_PROTECTION=y +CONFIG_SYS_FLASH_CFI=y CONFIG_NAND=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index d29621d8ce..16351ba41c 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -20,12 +20,11 @@ CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x240000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 # CONFIG_CMD_EEPROM is not set -# CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_CACHE=y -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)" +CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y @@ -40,6 +39,12 @@ CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_MMC_OMAP36XX_PINS=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_PROTECTION=y +CONFIG_SYS_FLASH_CFI=y CONFIG_NAND=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 8644e16830..fe557f91ca 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -183,9 +183,14 @@ /* **** PISMO SUPPORT *** */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE +#define CONFIG_SYS_FLASH_BASE 0x10000000 #endif +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_SIZE 0x4000000 + /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -- 2.17.1

1 0

[U-Boot] [PATCH v2 00/31] virtio: Introduce VirtIO driver support
by Bin Meng 14 Oct '18

14 Oct '18

This series brings in VirtIO driver support in U-Boot. The work is based on Tuomas's virtio support on QEMU ARM targets. VirtIO is a virtualization standard for network and disk device drivers where just the guest's device driver "knows" it is running in a virtual environment, and cooperates with the hypervisor. This enables guests to get high performance network and disk operations, and gives most of the performance benefits of paravirtualization. In the U-Boot case, the guest is U-Boot itself, while the virtual environment are normally QEMU targets like ARM, RISC-V and x86. Both VirtIO MMIO and PCI transport options are supported. Only VirtIO network and block device drivers are supported for now. The following QEMU targets are supported. - qemu_arm_defconfig - qemu_arm64_defconfig - qemu-riscv32_defconfig - qemu-riscv64_defconfig - qemu-x86_defconfig - qemu-x86_64_defconfig A new child_post_probe() uclass driver method is introduced to better support virtio device driver. This also changes BLK uclass driver to supply a post_probe() method which calls part_init(), so that we can avoid duplicating such call in every BLK driver. Not every checkpatch warning reported was fixed, but I tried to fix as many as possible which makes sense. This series is available at u-boot-x86/virtio-working for testing. Changes in v2: - new patch to add test case for uclass driver's child_post_probe() - new patch to add dm_remove_devices_flags() call to do_bootm_linux() for riscv bootm - Added virtio spec link and a short statement of what virtio is in the header and source files - Changed to use 'transport' over 'bus' in drivers/virtio/Kconfig - Added UCLASS_VIRTIO ID in alphabetical order - Moved the header file inclusion from virtio.h to C file - Fixed code styling issue (blank line before return) in virtio_xxx() APIs - Changed virtio_init() to return int if there is an error - Added virtio_uclass_pre_probe() to check virtio transport driver ops here so that we don't need check these ops each time when the virtio_xxx APIs are called - Implemented child_post_remove() method to reset the virtio device - Changed virtio_driver_features_init() parameter 'feature' and 'feature_legacy' to const, and adjust member of 'struct virtio_dev_priv' accordingly - Initialize uc_priv->vqs in virtio_uclass_post_probe() - Changed virtio net driver feature table to const - Correct desc->vendor for PCI transport - imply VIRTIO_PCI for qemu-arm too - use an internal function _dm_pci_find_next_capability() for dm_pci_find_capability() and dm_pci_find_next_capability() - adjust swap_case driver to handle request from _dm_pci_find_next_capability() - fix compiler warnings in 64-bit build - adjust virtio_pci_find_capability() to avoid walking through capability list to find next one by ourselves - new patch to add a Sandbox transport driver - new patch to add test cases for virtio uclass - Added driver remove and flags description in the documentation Bin Meng (26): dm: core: Allow uclass to set up a device's child after it is probed test: dm: core: Add test case for uclass driver's child_post_probe() riscv: bootm: Add dm_remove_devices_flags() call to do_bootm_linux() dm: Add a new uclass driver for VirtIO transport devices virtio: Add virtio over mmio transport driver test: dm: blk: Correct blk_base test case sandbox: blk: Switch to use platdata_auto_alloc_size for the driver data efi_driver: blk: Switch to use platdata_auto_alloc_size for the driver data blk: Call part_init() in the post_probe() method blk: Drop blk_prepare_device() blk: Make blk_next_free_devnum() public riscv: qemu: Enumerate virtio bus during early boot riscv: qemu: Include some useful commands kconfig: Introduce HAVE_ARCH_IOMAP x86: Implement arch-specific io accessor routines virtio: Add virtio over pci transport driver arm: qemu: Add a Kconfig in the board directory arm: qemu: Enumerate virtio bus during early boot x86: qemu: Imply virtio PCI transport and device drivers dm: pci: Add APIs to find next capability and extended capability test: dm: pci: Add cases for finding next PCI capability APIs virtio: pci: Support non-legacy PCI transport device virtio: net: Support non-legacy device virtio: Add a Sandbox transport driver test: dm: virtio: Add test cases for virtio uclass doc: Document virtio support Tuomas Tynkkynen (5): virtio: Add codes for virtual queue/ring management virtio: Add net driver support blk: Introduce IF_TYPE_VIRTIO virtio: Add block driver support virtio: cmd: Add virtio command for virtio devices arch/Kconfig | 6 + arch/arm/Kconfig | 1 + arch/riscv/lib/bootm.c | 11 +- arch/sandbox/dts/test.dts | 8 + arch/x86/include/asm/io.h | 66 +++ board/emulation/qemu-arm/Kconfig | 13 + board/emulation/qemu-arm/qemu-arm.c | 10 + board/emulation/qemu-riscv/Kconfig | 11 + board/emulation/qemu-riscv/qemu-riscv.c | 9 + board/emulation/qemu-x86/Kconfig | 3 + cmd/Kconfig | 7 + cmd/Makefile | 1 + cmd/sata.c | 9 - cmd/virtio.c | 38 ++ common/usb_storage.c | 4 +- configs/qemu_arm64_defconfig | 1 - configs/qemu_arm_defconfig | 1 - disk/part.c | 6 + doc/README.virtio | 253 ++++++++++++ drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/block/blk-uclass.c | 25 +- drivers/block/ide.c | 2 - drivers/block/sandbox.c | 17 +- drivers/core/uclass.c | 13 +- drivers/misc/swap_case.c | 9 + drivers/mmc/mmc.c | 3 - drivers/nvme/nvme.c | 1 - drivers/pci/pci-uclass.c | 51 ++- drivers/scsi/scsi.c | 1 - drivers/virtio/Kconfig | 62 +++ drivers/virtio/Makefile | 11 + drivers/virtio/virtio-uclass.c | 369 +++++++++++++++++ drivers/virtio/virtio_blk.c | 137 +++++++ drivers/virtio/virtio_blk.h | 129 ++++++ drivers/virtio/virtio_mmio.c | 413 +++++++++++++++++++ drivers/virtio/virtio_mmio.h | 129 ++++++ drivers/virtio/virtio_net.c | 239 +++++++++++ drivers/virtio/virtio_net.h | 268 ++++++++++++ drivers/virtio/virtio_pci.h | 173 ++++++++ drivers/virtio/virtio_pci_legacy.c | 421 +++++++++++++++++++ drivers/virtio/virtio_pci_modern.c | 609 +++++++++++++++++++++++++++ drivers/virtio/virtio_ring.c | 358 ++++++++++++++++ drivers/virtio/virtio_sandbox.c | 233 +++++++++++ include/blk.h | 22 +- include/dm/test.h | 1 + include/dm/uclass-id.h | 1 + include/dm/uclass.h | 4 +- include/linux/io.h | 4 + include/pci.h | 48 +++ include/virtio.h | 707 ++++++++++++++++++++++++++++++++ include/virtio_ring.h | 320 +++++++++++++++ include/virtio_types.h | 24 ++ lib/Kconfig | 6 + lib/efi_driver/efi_block_device.c | 26 +- test/dm/Makefile | 1 + test/dm/blk.c | 27 +- test/dm/bus.c | 45 ++ test/dm/pci.c | 20 + test/dm/test-fdt.c | 7 +- test/dm/virtio.c | 122 ++++++ 61 files changed, 5420 insertions(+), 99 deletions(-) create mode 100644 board/emulation/qemu-arm/Kconfig create mode 100644 cmd/virtio.c create mode 100644 doc/README.virtio create mode 100644 drivers/virtio/Kconfig create mode 100644 drivers/virtio/Makefile create mode 100644 drivers/virtio/virtio-uclass.c create mode 100644 drivers/virtio/virtio_blk.c create mode 100644 drivers/virtio/virtio_blk.h create mode 100644 drivers/virtio/virtio_mmio.c create mode 100644 drivers/virtio/virtio_mmio.h create mode 100644 drivers/virtio/virtio_net.c create mode 100644 drivers/virtio/virtio_net.h create mode 100644 drivers/virtio/virtio_pci.h create mode 100644 drivers/virtio/virtio_pci_legacy.c create mode 100644 drivers/virtio/virtio_pci_modern.c create mode 100644 drivers/virtio/virtio_ring.c create mode 100644 drivers/virtio/virtio_sandbox.c create mode 100644 include/virtio.h create mode 100644 include/virtio_ring.h create mode 100644 include/virtio_types.h create mode 100644 test/dm/virtio.c -- 2.7.4

1 31

[U-Boot] [PATCH V5 00/32] i.MX: Add i.MX8QXP support
by Peng Fan 14 Oct '18

14 Oct '18

This patchset is to upstream i.MX8QXP and mek board support, with some drivers update to support i.MX8QXP. The information about the processor could be found https://www.nxp.com/products/processors-and-microcontrollers/applications-p… The architecture of i.MX8QXP is different from i.MX6/7/8M, inside i.MX8QXP, there is a dedicated processor(SCU) used for power/clock/pin/ pad/resource management/thermal and etc. V5: Addressed Lothar Waßmann's comments for patch 24 and 32. Rebased on master. V4: Add reviewed tag from Anatolij Gustschin Addressed comments from Anatolig for patch "misc: add i.MX8 misc driver" Addressed comments from Anatolig for patch "misc: imx8: add scfw api impementation" Merged the files into one Moved one error handle to patch 4 Moved patch "arm: global_data: add scu_dev for i.MX8" to patch 7 For Fabio's comments to imx-mkimage, I'll start the porting work, but needs more time, it will be not be in this patchset. V3: patch 7: use CONFIG_IMX8 patch 29: use CONFIG_IMX8 patch 32: Added README with scfw_tcm.bin link added misc: remove sc_rpc_msg_t typedef, use struct sc_rpc_msg_s in patchset. V2: In this V2 patchset, the SCFW API is replaced by uclass driver implementation, but the api name is not changed from scfw api. The related macro definitions are kept in different api.h file following SCFW API file structure. Impelemnted scu misc driver to handle the low level communication between Acore and SCU. Implemented rm/pm/pad/misc protocol code to invoke misc_call for different functionality. The dm clk/pinctrl/power and others will invokde the protocol api to communicate with SCU. The arch/arm/mach-imx/imx8/clock.c currently is only a dummy file to avoid build break for mxc_get_clock. The i2c patch and common power domain patches are removed from this patchset. The imx8 name still kept, this is because NXP marketing requires to use this name for i.MX branding. Peng Fan (30): dt-bindings: pinctrl: add i.MX8QXP pads definition dt-bindings: clock: dt-bindings: pinctrl: add i.MX8QXP clocks definition dt-bindings: soc: add i.MX8QXP pm and rsrc definition imx8: add scfw macro definition imx: add Kconfig entry for i.MX8QXP arm: build mach-imx for i.MX8 arm: global_data: add scu_dev for i.MX8 misc: add i.MX8 misc driver misc: imx8: add scfw api impementation imx: boot_mode: Add FLEXSPI boot entry imx8: add imx-regs header file imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP defined imx: add i.MX8 cpu type armv8: add cpu core helper functions imx8: add basic cpu support imx8: add boot device detection imx8: implement mmc_get_env_dev imx8: add mmu and dram related functiions imx8: add arch_cpu_init arch_cpu_init_dm imx8: add iomux configuration api imx8: add dummy clock gpio: mxc_gpio: add support for i.MX8 pinctrl: Add pinctrl driver for i.MX8 power: Add power domain driver for i.MX8 clk: imx: add clk driver for i.MX8QXP serial_lpuart: Update lpuart driver to support i.MX8 serial: lpuart: support uclass clk api mmc: fsl_esdhc: add uclass clk support arm: dts: introduce dtsi for i.MX8QXP imx: add i.MX8QXP MEK board support Ye Li (2): serial: lpuart: Enable RX and TX FIFO fsl_esdhc: Update usdhc driver to support i.MX8 arch/arm/Kconfig | 8 + arch/arm/Makefile | 2 +- arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-imx8-ca35.dtsi | 66 ++ arch/arm/dts/fsl-imx8dx.dtsi | 452 +++++++++++++ arch/arm/dts/fsl-imx8dxp.dtsi | 11 + arch/arm/dts/fsl-imx8qxp-mek.dts | 136 ++++ arch/arm/dts/fsl-imx8qxp.dtsi | 51 ++ arch/arm/include/asm/arch-imx/cpu.h | 5 + arch/arm/include/asm/arch-imx8/clock.h | 27 + arch/arm/include/asm/arch-imx8/gpio.h | 21 + arch/arm/include/asm/arch-imx8/imx-regs.h | 46 ++ arch/arm/include/asm/arch-imx8/imx8-pins.h | 15 + arch/arm/include/asm/arch-imx8/iomux.h | 40 ++ arch/arm/include/asm/arch-imx8/power-domain.h | 15 + arch/arm/include/asm/arch-imx8/sci/rpc.h | 158 +++++ arch/arm/include/asm/arch-imx8/sci/sci.h | 86 +++ arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h | 30 + arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h | 57 ++ arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h | 44 ++ arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h | 69 ++ arch/arm/include/asm/arch-imx8/sci/types.h | 220 +++++++ arch/arm/include/asm/arch-imx8/sys_proto.h | 19 + arch/arm/include/asm/armv8/cpu.h | 26 + arch/arm/include/asm/global_data.h | 4 + arch/arm/include/asm/mach-imx/boot_mode.h | 1 + arch/arm/include/asm/mach-imx/sys_proto.h | 3 + arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/imx8/Kconfig | 26 + arch/arm/mach-imx/imx8/Makefile | 7 + arch/arm/mach-imx/imx8/clock.c | 21 + arch/arm/mach-imx/imx8/cpu.c | 544 ++++++++++++++++ arch/arm/mach-imx/imx8/iomux.c | 43 ++ board/freescale/imx8qxp_mek/Kconfig | 14 + board/freescale/imx8qxp_mek/MAINTAINERS | 6 + board/freescale/imx8qxp_mek/Makefile | 7 + board/freescale/imx8qxp_mek/README | 72 ++ board/freescale/imx8qxp_mek/imx8qxp_mek.c | 152 +++++ board/freescale/mx8mq_evk/README | 81 +++ configs/imx8qxp_mek_defconfig | 38 ++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/imx/Kconfig | 6 + drivers/clk/imx/Makefile | 5 + drivers/clk/imx/clk-imx8.c | 212 ++++++ drivers/gpio/mxc_gpio.c | 30 +- drivers/misc/Makefile | 1 + drivers/misc/imx8/Makefile | 3 + drivers/misc/imx8/scu.c | 266 ++++++++ drivers/misc/imx8/scu_api.c | 316 +++++++++ drivers/mmc/fsl_esdhc.c | 30 +- drivers/pinctrl/nxp/Kconfig | 18 + drivers/pinctrl/nxp/Makefile | 2 + drivers/pinctrl/nxp/pinctrl-imx.c | 209 +++--- drivers/pinctrl/nxp/pinctrl-imx.h | 16 + drivers/pinctrl/nxp/pinctrl-imx8.c | 40 ++ drivers/pinctrl/nxp/pinctrl-scu.c | 66 ++ drivers/power/domain/Kconfig | 8 +- drivers/power/domain/Makefile | 1 + drivers/power/domain/imx8-power-domain.c | 315 +++++++++ drivers/serial/serial_lpuart.c | 126 +++- include/configs/imx8qxp_mek.h | 156 +++++ include/dt-bindings/clock/imx8qxp-clock.h | 583 +++++++++++++++++ include/dt-bindings/pinctrl/pads-imx8qxp.h | 757 ++++++++++++++++++++++ include/dt-bindings/soc/imx8_pd.h | 188 ++++++ include/dt-bindings/soc/imx_rsrc.h | 557 ++++++++++++++++ include/fsl_lpuart.h | 2 +- 67 files changed, 6399 insertions(+), 142 deletions(-) create mode 100644 arch/arm/dts/fsl-imx8-ca35.dtsi create mode 100644 arch/arm/dts/fsl-imx8dx.dtsi create mode 100644 arch/arm/dts/fsl-imx8dxp.dtsi create mode 100644 arch/arm/dts/fsl-imx8qxp-mek.dts create mode 100644 arch/arm/dts/fsl-imx8qxp.dtsi create mode 100644 arch/arm/include/asm/arch-imx8/clock.h create mode 100644 arch/arm/include/asm/arch-imx8/gpio.h create mode 100644 arch/arm/include/asm/arch-imx8/imx-regs.h create mode 100644 arch/arm/include/asm/arch-imx8/imx8-pins.h create mode 100644 arch/arm/include/asm/arch-imx8/iomux.h create mode 100644 arch/arm/include/asm/arch-imx8/power-domain.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/rpc.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/sci.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h create mode 100644 arch/arm/include/asm/arch-imx8/sci/types.h create mode 100644 arch/arm/include/asm/arch-imx8/sys_proto.h create mode 100644 arch/arm/include/asm/armv8/cpu.h create mode 100644 arch/arm/mach-imx/imx8/Kconfig create mode 100644 arch/arm/mach-imx/imx8/Makefile create mode 100644 arch/arm/mach-imx/imx8/clock.c create mode 100644 arch/arm/mach-imx/imx8/cpu.c create mode 100644 arch/arm/mach-imx/imx8/iomux.c create mode 100644 board/freescale/imx8qxp_mek/Kconfig create mode 100644 board/freescale/imx8qxp_mek/MAINTAINERS create mode 100644 board/freescale/imx8qxp_mek/Makefile create mode 100644 board/freescale/imx8qxp_mek/README create mode 100644 board/freescale/imx8qxp_mek/imx8qxp_mek.c create mode 100644 board/freescale/mx8mq_evk/README create mode 100644 configs/imx8qxp_mek_defconfig create mode 100644 drivers/clk/imx/Kconfig create mode 100644 drivers/clk/imx/Makefile create mode 100644 drivers/clk/imx/clk-imx8.c create mode 100644 drivers/misc/imx8/Makefile create mode 100644 drivers/misc/imx8/scu.c create mode 100644 drivers/misc/imx8/scu_api.c create mode 100644 drivers/pinctrl/nxp/pinctrl-imx8.c create mode 100644 drivers/pinctrl/nxp/pinctrl-scu.c create mode 100644 drivers/power/domain/imx8-power-domain.c create mode 100644 include/configs/imx8qxp_mek.h create mode 100644 include/dt-bindings/clock/imx8qxp-clock.h create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h create mode 100644 include/dt-bindings/soc/imx8_pd.h create mode 100644 include/dt-bindings/soc/imx_rsrc.h -- 2.14.1

3 38

[U-Boot] [PATCH 1/2] cpu: Add DM_FLAG_PRE_RELOC flag to various cpu drivers
by Bin Meng 14 Oct '18

14 Oct '18

It turns out commit c0434407b595 broke some boards which have DM CPU driver with CONFIG_DISPLAY_CPUINFO option on. These boards just fail to boot when print_cpuinfo() is called during boot. Fixes: c0434407b595 ("board_f: Use static print_cpuinfo if CONFIG_CPU is active") Reported-by: Stefan Roese <sr(a)denx.de> Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/baytrail/cpu.c | 1 + arch/x86/cpu/broadwell/cpu.c | 1 + arch/x86/cpu/cpu_x86.c | 1 + arch/x86/cpu/ivybridge/model_206ax.c | 1 + drivers/cpu/cpu_sandbox.c | 1 + 5 files changed, 5 insertions(+) diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c index 56e9813..2eb9172 100644 --- a/arch/x86/cpu/baytrail/cpu.c +++ b/arch/x86/cpu/baytrail/cpu.c @@ -203,4 +203,5 @@ U_BOOT_DRIVER(cpu_x86_baytrail_drv) = { .bind = cpu_x86_bind, .probe = cpu_x86_baytrail_probe, .ops = &cpu_x86_baytrail_ops, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index 02b3169..232fa40 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -764,4 +764,5 @@ U_BOOT_DRIVER(cpu_x86_broadwell_drv) = { .probe = cpu_x86_broadwell_probe, .ops = &cpu_x86_broadwell_ops, .priv_auto_alloc_size = sizeof(struct cpu_broadwell_priv), + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/arch/x86/cpu/cpu_x86.c b/arch/x86/cpu/cpu_x86.c index 2b6cc9f..1aaf851 100644 --- a/arch/x86/cpu/cpu_x86.c +++ b/arch/x86/cpu/cpu_x86.c @@ -94,4 +94,5 @@ U_BOOT_DRIVER(cpu_x86_drv) = { .of_match = cpu_x86_ids, .bind = cpu_x86_bind, .ops = &cpu_x86_ops, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index 33e5c62..6edc3e2 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -478,4 +478,5 @@ U_BOOT_DRIVER(cpu_x86_model_206ax_drv) = { .bind = cpu_x86_bind, .probe = cpu_x86_model_206ax_probe, .ops = &cpu_x86_model_206ax_ops, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/cpu/cpu_sandbox.c b/drivers/cpu/cpu_sandbox.c index ff87e8a..c1f60fd 100644 --- a/drivers/cpu/cpu_sandbox.c +++ b/drivers/cpu/cpu_sandbox.c @@ -58,4 +58,5 @@ U_BOOT_DRIVER(cpu_sandbox) = { .ops = &cpu_sandbox_ops, .of_match = cpu_sandbox_ids, .probe = cpu_sandbox_probe, + .flags = DM_FLAG_PRE_RELOC, }; -- 2.7.4

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[U-Boot] [PATCH v2 00/18] test: Various test refinements and improvements
by Simon Glass 13 Oct '18

13 Oct '18

This series includes a number of small changes designed to make tests run more smoothly. The overall goal is that 'make check' runs cleanly without unnecessary output and all temporary files aare cleaned up. Changes in v2: - Quote @$ correctly so that quoted arguments can be passed to run_test - Add new patch to reduce the number of tests run with sandbox_flattree - Add a patch to run binman tests concurrently Simon Glass (17): sandbox: Unprotect DATA regions in bus tests patman: Handle unicode in _ProjectConfigParser tests test/py: Fix unicode handling for log filtering buildman: Make the toolchain test more forgiving binman: Reorder tests to put helper functions first Makefile: Add a 'check' target for make test: Simplify the PATH setup test: Print the name of each test before running it test: Tidy up comments and variable name binman: Add a default path to libfdt.py binman: Fix up removal of temporary directories binman: Separate out testSplBssPad() buildman: dtoc: Suppress unwanted output from test tools: Set an initial value for indir patman: Don't clear progress in tout unless it was used test: Reduce the number of tests run with sandbox_flattree binman: Run tests concurrently Stephen Warren (1): test/py: ignore console read exceptions after test failure .travis.yml | 1 + Makefile | 6 +- arch/sandbox/cpu/os.c | 11 + include/os.h | 12 + test/dm/bus.c | 12 + test/py/README.md | 1 + test/py/multiplexed_log.py | 7 +- test/py/u_boot_console_base.py | 12 +- test/run | 57 +++-- tools/binman/binman.py | 28 ++- tools/binman/cmdline.py | 2 + tools/binman/elf_test.py | 5 + tools/binman/entry_test.py | 15 +- tools/binman/fdt_test.py | 4 + tools/binman/ftest.py | 289 ++++++++++++----------- tools/buildman/test.py | 8 +- tools/concurrencytest/.gitignore | 1 + tools/concurrencytest/README.md | 74 ++++++ tools/concurrencytest/concurrencytest.py | 144 +++++++++++ tools/dtoc/dtoc.py | 7 + tools/dtoc/test_dtoc.py | 6 +- tools/dtoc/test_fdt.py | 12 +- tools/patman/settings.py | 27 ++- tools/patman/test_util.py | 2 +- tools/patman/tools.py | 3 + tools/patman/tout.py | 8 +- 26 files changed, 560 insertions(+), 194 deletions(-) create mode 100644 tools/concurrencytest/.gitignore create mode 100644 tools/concurrencytest/README.md create mode 100644 tools/concurrencytest/concurrencytest.py -- 2.19.0.605.g01d371f741-goog

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[U-Boot] [PATCH v2 1/1] x86: put global data pointer into the .data section
by Heinrich Schuchardt 13 Oct '18

13 Oct '18

On x86_64 the field global_data_ptr is assigned before relocation. As sections for uninitialized global data (.bss) overlap with the relocation sections (.rela) this destroys the relocation table and leads to spurious errors. Initialization forces the global_data_ptr into a section for initialized global data (.data) which cannot overlap any .rela section. Fixes: a160092a610f ("x86: Support global_data on x86_64") Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- v2 Use .data instead of .text section --- arch/x86/cpu/x86_64/cpu.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index 18b3e94e12..a8097bc55d 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -7,8 +7,14 @@ #include <common.h> #include <debug_uart.h> -/* Global declaration of gd */ -struct global_data *global_data_ptr; +/* + * Global declaration of gd. + * + * As we write to it before relocation we have to make sure it is not put into + * a .bss section which may overlap a .rela section. Initialization forces it + * into a .data section which cannot overlap any .rela section. + */ +struct global_data *global_data_ptr = (struct global_data *)~0; void arch_setup_gd(gd_t *new_gd) { -- 2.19.1

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[U-Boot] [PATCH 1/1] efi_loader: fix relocation on x86_64
by Heinrich Schuchardt 13 Oct '18

13 Oct '18

Currently the relocation of the EFI runtime on x86_64 fails. This renders the EFI subsystem unusable. The ELF relocation records for x86_64 contain an addend field. Always write the function name into error messages related to the EFI runtime relocation. Break an excessively long line. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- lib/efi_loader/efi_runtime.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c index c5fbd91fa3..f059dc97fd 100644 --- a/lib/efi_loader/efi_runtime.c +++ b/lib/efi_loader/efi_runtime.c @@ -41,9 +41,13 @@ static efi_status_t __efi_runtime EFIAPI efi_invalid_parameter(void); #elif defined(__arm__) #define R_RELATIVE R_ARM_RELATIVE #define R_MASK 0xffULL -#elif defined(__x86_64__) || defined(__i386__) +#elif defined(__i386__) #define R_RELATIVE R_386_RELATIVE #define R_MASK 0xffULL +#elif defined(__x86_64__) +#define R_RELATIVE R_X86_64_RELATIVE +#define R_MASK 0xffffffffULL +#define IS_RELA 1 #elif defined(__riscv) #define R_RELATIVE R_RISCV_RELATIVE #define R_MASK 0xffULL @@ -358,7 +362,8 @@ void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map) p = (void*)((ulong)rel->offset - base) + gd->relocaddr; - debug("%s: rel->info=%#lx *p=%#lx rel->offset=%p\n", __func__, rel->info, *p, rel->offset); + debug("%s: rel->info=%#lx *p=%#lx rel->offset=%p\n", __func__, + rel->info, *p, rel->offset); switch (rel->info & R_MASK) { case R_RELATIVE: @@ -377,6 +382,9 @@ void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map) } #endif default: + if (!efi_runtime_tobedetached(p)) + printf("%s: Unknown relocation type %llx\n", + __func__, rel->info & R_MASK); continue; } @@ -385,8 +393,8 @@ void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map) newaddr > (map->virtual_start + (map->num_pages << EFI_PAGE_SHIFT)))) { if (!efi_runtime_tobedetached(p)) - printf("U-Boot EFI: Relocation at %p is out of " - "range (%lx)\n", p, newaddr); + printf("%s: Relocation at %p is out of " + "range (%lx)\n", __func__, p, newaddr); continue; } -- 2.19.1

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[U-Boot] [PATCH 1/1] x86: put global data pointer into the .text section
by Heinrich Schuchardt 13 Oct '18

13 Oct '18

On x86_64 the field global_data_ptr is assigned before relocation. As global data sections (.data and .bss) overlap with the relocation sections (.rela) this destroys the relocation table and leads to spurious errors. By moving the field to the .text section it will not overlap any relocation section anymore. Fixes: a160092a610f ("x86: Support global_data on x86_64") Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- arch/x86/cpu/x86_64/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index 18b3e94e12..676a789524 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -8,7 +8,7 @@ #include <debug_uart.h> /* Global declaration of gd */ -struct global_data *global_data_ptr; +struct global_data *global_data_ptr __attribute__((section(".text"))); void arch_setup_gd(gd_t *new_gd) { -- 2.19.1

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