October 2018 - U-Boot

[U-Boot] [PATCH v2] net: phy: add TSE PCS support to dwmac-socfpga
by Ooi, Joyce 22 Oct '18

22 Oct '18

This adds support for TSE PCS (Triple Speed Ethernet Physical Coding Sublayer) that uses SGMII adapter when the phy-mode in device tree is set to sgmii. Signed-off-by: Ooi, Joyce <joyce.ooi(a)intel.com> --- arch/arm/mach-socfpga/include/mach/misc.h | 1 + arch/arm/mach-socfpga/misc.c | 5 + arch/arm/mach-socfpga/misc_s10.c | 6 + drivers/net/Makefile | 3 +- drivers/net/designware.c | 5 + drivers/net/designware.h | 1 + drivers/net/dwmac_socfpga.c | 121 ++++++++++++++++++ drivers/net/phy/altr_tse_pcs.c | 197 ++++++++++++++++++++++++++++++ drivers/net/phy/altr_tse_pcs.h | 59 +++++++++ 9 files changed, 397 insertions(+), 1 deletion(-) create mode 100644 drivers/net/phy/altr_tse_pcs.c create mode 100644 drivers/net/phy/altr_tse_pcs.h --- v2: add a __weak function to make it compatible for all socfpga platforms diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 2660992..d1de5cf 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -39,6 +39,7 @@ void socfpga_init_security_policies(void); void socfpga_sdram_remap_zero(void); #endif +int socfpga_test_fpga_ready(void); void do_bridge_reset(int enable); #endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 350aad1..3a2a1a4 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -227,6 +227,11 @@ int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id, return 0; } + +__weak int socfpga_test_fpga_ready(void) +{ + return 0; +} #endif #ifndef CONFIG_SPL_BUILD diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c index e611d2c..3a8646f 100644 --- a/arch/arm/mach-socfpga/misc_s10.c +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -11,6 +11,7 @@ #include <miiphy.h> #include <netdev.h> #include <asm/io.h> +#include <asm/arch/mailbox_s10.h> #include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> #include <asm/arch/misc.h> @@ -91,6 +92,11 @@ static int socfpga_set_phymode(void) return 0; } + +int socfpga_test_fpga_ready(void) +{ + return mbox_get_fpga_config_status(MBOX_CONFIG_STATUS); +} #else static int socfpga_set_phymode(void) { diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 48a2878..c2333b5 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o obj-$(CONFIG_CS8900) += cs8900.o obj-$(CONFIG_TULIP) += dc2114x.o obj-$(CONFIG_ETH_DESIGNWARE) += designware.o -obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o +obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac-socfpga.o obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o obj-$(CONFIG_DNET) += dnet.o obj-$(CONFIG_E1000) += e1000.o @@ -73,3 +73,4 @@ obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_FSL_PFE) += pfe_eth/ obj-$(CONFIG_SNI_AVE) += sni_ave.o +dwmac-socfpga-objs := phy/altr_tse_pcs.o dwmac_socfpga.o diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 19db0a8..666cf41 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -235,6 +235,8 @@ static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, struct phy_device *phydev) { u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; + struct udevice *dev = priv->phydev->dev; + struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); if (!phydev->link) { printf("%s: No link.\n", phydev->dev->name); @@ -254,6 +256,9 @@ static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, writel(conf, &mac_p->conf); + if (dw_pdata->pcs_adjust_link) + dw_pdata->pcs_adjust_link(dev, phydev); + printf("Speed: %d, %s duplex%s\n", phydev->speed, (phydev->duplex) ? "full" : "half", (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); diff --git a/drivers/net/designware.h b/drivers/net/designware.h index dea12b7..3a5a93f 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -255,6 +255,7 @@ extern const struct eth_ops designware_eth_ops; struct dw_eth_pdata { struct eth_pdata eth_pdata; u32 reset_delays[3]; + void (*pcs_adjust_link)(struct udevice *dev, struct phy_device *phydev); }; int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr); diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c index 08fc967..70e95f8 100644 --- a/drivers/net/dwmac_socfpga.c +++ b/drivers/net/dwmac_socfpga.c @@ -9,12 +9,16 @@ #include <asm/io.h> #include <dm.h> #include <clk.h> +#include <fdt_support.h> #include <phy.h> #include <regmap.h> #include <reset.h> #include <syscon.h> #include "designware.h" +#include "phy/altr_tse_pcs.h" +#include <asm/arch/misc.h> +#include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> enum dwmac_type { @@ -27,8 +31,122 @@ struct dwmac_socfpga_platdata { struct dw_eth_pdata dw_eth_pdata; enum dwmac_type type; void *phy_intf; + struct tse_pcs pcs; }; +static void socfpga_tse_pcs_adjust_link(struct udevice *dev, + struct phy_device *phydev) +{ + struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev); + phys_addr_t tse_pcs_base = pdata->pcs.tse_pcs_base; + phys_addr_t sgmii_adapter_base = pdata->pcs.sgmii_adapter_base; + + if ((tse_pcs_base) && (sgmii_adapter_base)) + writew(SGMII_ADAPTER_DISABLE, + sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); + + if ((tse_pcs_base) && (sgmii_adapter_base)) + tse_pcs_fix_mac_speed(&pdata->pcs, phydev, phydev->speed); +} + +static int socfpga_dw_tse_pcs_init(struct udevice *dev) +{ + struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev); + struct dw_eth_pdata *dw_pdata = &pdata->dw_eth_pdata; + struct eth_pdata *eth_pdata = &pdata->dw_eth_pdata.eth_pdata; + phys_addr_t tse_pcs_base = pdata->pcs.tse_pcs_base; + phys_addr_t sgmii_adapter_base = pdata->pcs.sgmii_adapter_base; + const fdt32_t *reg; + int ret = 0; + int parent, index, na, ns, offset, len; + + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), + "altr,gmii-to-sgmii-converter"); + if (offset > 0) { + /* check FPGA status */ + ret = socfpga_test_fpga_ready(); + if (ret) { + debug("%s: FPGA status returns %d\n", __func__, ret); + return -EPERM; + } + + /* enable HPS bridge */ + do_bridge_reset(1); + + parent = fdt_parent_offset(gd->fdt_blob, offset); + if (parent < 0) { + debug("s10-hps-bridge DT not found\n"); + return -ENODEV; + } + + na = fdt_address_cells(gd->fdt_blob, parent); + if (na < 1) { + debug("bad #address-cells\n"); + return -EINVAL; + } + + ns = fdt_size_cells(gd->fdt_blob, parent); + if (ns < 1) { + debug("bad #size-cells\n"); + return -EINVAL; + } + + index = fdt_stringlist_search(gd->fdt_blob, offset, "reg-names", + "eth_tse_control_port"); + if (index < 0) { + debug("fail to find eth_tse_control_port: %s\n", + fdt_strerror(index)); + return -ENOENT; + } + + reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len); + if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns)))) + return -EINVAL; + + reg += index * (na + ns); + tse_pcs_base = fdt_translate_address((void *)gd->fdt_blob, + offset, reg); + if (tse_pcs_base == FDT_ADDR_T_NONE) { + debug("tse pcs address not found\n"); + return -EINVAL; + } + + index = fdt_stringlist_search(gd->fdt_blob, offset, "reg-names", + "gmii_to_sgmii_adapter_avalon_slave"); + if (index < 0) { + debug("fail to find gmii_to_sgmii_adapter_avalon_slave: %s\n", + fdt_strerror(index)); + return -EINVAL; + } + + reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len); + if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns)))) + return -EINVAL; + + reg += index * (na + ns); + sgmii_adapter_base = fdt_translate_address((void *)gd->fdt_blob, + offset, reg); + if (sgmii_adapter_base == FDT_ADDR_T_NONE) { + debug("gmii-to-sgmii adapter address not found\n"); + return -EINVAL; + } + + if (eth_pdata->phy_interface == PHY_INTERFACE_MODE_SGMII) { + if (tse_pcs_init(tse_pcs_base, &pdata->pcs) != 0) { + debug("Unable to intiialize TSE PCS\n"); + return -EINVAL; + } + } + /* Clear sgmii_adapter_base first */ + writel(0, sgmii_adapter_base); + + pdata->pcs.tse_pcs_base = tse_pcs_base; + pdata->pcs.sgmii_adapter_base = sgmii_adapter_base; + dw_pdata->pcs_adjust_link = socfpga_tse_pcs_adjust_link; + } + return ret; +} + static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev) { struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev); @@ -94,6 +212,7 @@ static int dwmac_socfpga_probe(struct udevice *dev) switch (edata->phy_interface) { case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: + case PHY_INTERFACE_MODE_SGMII: modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; break; case PHY_INTERFACE_MODE_RMII: @@ -122,6 +241,8 @@ static int dwmac_socfpga_probe(struct udevice *dev) reset_release_bulk(&reset_bulk); } + socfpga_dw_tse_pcs_init(dev); + return designware_eth_probe(dev); } diff --git a/drivers/net/phy/altr_tse_pcs.c b/drivers/net/phy/altr_tse_pcs.c new file mode 100644 index 0000000..459695c --- /dev/null +++ b/drivers/net/phy/altr_tse_pcs.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Intel Corporation <www.intel.com> + */ + +#include <asm/io.h> +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <net.h> +#include <linux/compat.h> +#include <phy.h> +#include <timer.h> +#include <linux/ethtool.h> + +#include <asm/omap_common.h> +#include <asm/omap_musb.h> + +#include "altr_tse_pcs.h" + +static int tse_pcs_reset(phys_addr_t base, struct tse_pcs *pcs) +{ + int counter = 0; + u16 val; + + val = readw(base + TSE_PCS_CONTROL_REG); + val |= TSE_PCS_SW_RST_MASK; + + writew(val, base + TSE_PCS_CONTROL_REG); + + while (counter < TSE_PCS_SW_RESET_TIMEOUT) { + val = readw(base + TSE_PCS_CONTROL_REG); + val &= TSE_PCS_SW_RST_MASK; + if (val == 0) + break; + counter++; + udelay(1); + } + + if (counter >= TSE_PCS_SW_RESET_TIMEOUT) { + debug("%s: PCS could not get out of sw reset\n", __func__); + return -ETIMEDOUT; + } + + return 0; +} + +int tse_pcs_init(phys_addr_t base, struct tse_pcs *pcs) +{ + int ret = 0; + + writew(TSE_PCS_USE_SGMII_ENA, base + TSE_PCS_IF_MODE_REG); + writew(TSE_PCS_SGMII_LINK_TIMER_0, base + TSE_PCS_LINK_TIMER_0_REG); + writew(TSE_PCS_SGMII_LINK_TIMER_1, base + TSE_PCS_LINK_TIMER_1_REG); + + ret = tse_pcs_reset(base, pcs); + if (ret == 0) + writew(SGMII_ADAPTER_ENABLE, + pcs->sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); + + return ret; +} + +static void pcs_link_timer_callback(struct tse_pcs *pcs) +{ + u16 val = 0; + phys_addr_t tse_pcs_base = pcs->tse_pcs_base; + phys_addr_t sgmii_adapter_base = pcs->sgmii_adapter_base; + + val = readw(tse_pcs_base + TSE_PCS_STATUS_REG); + val &= TSE_PCS_STATUS_LINK_MASK; + + if (val != 0) { + printf("Adapter: Link is established\n"); + writew(SGMII_ADAPTER_ENABLE, + sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); + } else { + printf("Adapter: Link fail to establish\n"); + } +} + +static void auto_nego_timer_callback(struct tse_pcs *pcs) +{ + u16 val = 0; + u16 speed = 0; + u16 duplex = 0; + phys_addr_t tse_pcs_base = pcs->tse_pcs_base; + phys_addr_t sgmii_adapter_base = pcs->sgmii_adapter_base; + + val = readw(tse_pcs_base + TSE_PCS_STATUS_REG); + val &= TSE_PCS_STATUS_AN_COMPLETED_MASK; + + if (val != 0) { + printf("Adapter: Auto Negotiation is completed\n"); + val = readw(tse_pcs_base + TSE_PCS_PARTNER_ABILITY_REG); + speed = val & TSE_PCS_PARTNER_SPEED_MASK; + duplex = val & TSE_PCS_PARTNER_DUPLEX_MASK; + + if (speed == TSE_PCS_PARTNER_SPEED_10 && + duplex == TSE_PCS_PARTNER_DUPLEX_FULL) + printf("Adapter: Link Partner is Up - 10/Full\n"); + else if (speed == TSE_PCS_PARTNER_SPEED_100 && + duplex == TSE_PCS_PARTNER_DUPLEX_FULL) + printf("Adapter: Link Partner is Up - 100/Full\n"); + else if (speed == TSE_PCS_PARTNER_SPEED_1000 && + duplex == TSE_PCS_PARTNER_DUPLEX_FULL) + printf("Adapter: Link Partner is Up - 1000/Full\n"); + else if (speed == TSE_PCS_PARTNER_SPEED_10 && + duplex == TSE_PCS_PARTNER_DUPLEX_HALF) + printf("Adapter does not support Half Duplex\n"); + else if (speed == TSE_PCS_PARTNER_SPEED_100 && + duplex == TSE_PCS_PARTNER_DUPLEX_HALF) + printf("Adapter does not support Half Duplex\n"); + else if (speed == TSE_PCS_PARTNER_SPEED_1000 && + duplex == TSE_PCS_PARTNER_DUPLEX_HALF) + printf("Adapter does not support Half Duplex\n"); + else + printf("Adapter: Invalid Partner Speed and Duplex\n"); + + if (duplex == TSE_PCS_PARTNER_DUPLEX_FULL && + (speed == TSE_PCS_PARTNER_SPEED_10 || + speed == TSE_PCS_PARTNER_SPEED_100 || + speed == TSE_PCS_PARTNER_SPEED_1000)) + writew(SGMII_ADAPTER_ENABLE, + sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); + } else { + printf("Auto-negotioation failed\n"); + } +} + +void tse_pcs_fix_mac_speed(struct tse_pcs *pcs, struct phy_device *phy_dev, + unsigned int speed) +{ + phys_addr_t tse_pcs_base = pcs->tse_pcs_base; + phys_addr_t sgmii_adapter_base = pcs->sgmii_adapter_base; + u32 val, start; + + writew(SGMII_ADAPTER_ENABLE, + sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG); + pcs->autoneg = phy_dev->autoneg; + + if (pcs->autoneg == AUTONEG_ENABLE) { + val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); + val |= TSE_PCS_CONTROL_AN_EN_MASK; + writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG); + + val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG); + val |= TSE_PCS_USE_SGMII_AN_MASK; + writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG); + + val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); + val |= TSE_PCS_CONTROL_RESTART_AN_MASK; + + tse_pcs_reset(tse_pcs_base, pcs); + + } else if (pcs->autoneg == AUTONEG_DISABLE) { + val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); + val &= ~TSE_PCS_CONTROL_AN_EN_MASK; + writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG); + + val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG); + val &= ~TSE_PCS_USE_SGMII_AN_MASK; + writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG); + + val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG); + val &= ~TSE_PCS_SGMII_SPEED_MASK; + + switch (speed) { + case 1000: + val |= TSE_PCS_SGMII_SPEED_1000; + break; + case 100: + val |= TSE_PCS_SGMII_SPEED_100; + break; + case 10: + val |= TSE_PCS_SGMII_SPEED_10; + break; + default: + return; + } + writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG); + + tse_pcs_reset(tse_pcs_base, pcs); + } + + start = get_timer(0); + while (1) { + if (get_timer(start) >= AUTONEGO_LINK_TIMER) { + if (pcs->autoneg == AUTONEG_ENABLE) + auto_nego_timer_callback(pcs); + else if (pcs->autoneg == AUTONEG_DISABLE) + pcs_link_timer_callback(pcs); + return; + } + udelay(100); + } +} diff --git a/drivers/net/phy/altr_tse_pcs.h b/drivers/net/phy/altr_tse_pcs.h new file mode 100644 index 0000000..e0c0c34 --- /dev/null +++ b/drivers/net/phy/altr_tse_pcs.h @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Intel Corporation <www.intel.com> + */ + +#ifndef __TSE_PCS_H__ +#define __TSE_PCS_H__ + +#define TSE_PCS_CONTROL_AN_EN_MASK BIT(12) +#define TSE_PCS_CONTROL_REG 0x00 +#define TSE_PCS_CONTROL_RESTART_AN_MASK BIT(9) +#define TSE_PCS_IF_MODE_REG 0x28 +#define TSE_PCS_LINK_TIMER_0_REG 0x24 +#define TSE_PCS_LINK_TIMER_1_REG 0x26 +#define TSE_PCS_SIZE 0x40 +#define TSE_PCS_STATUS_AN_COMPLETED_MASK BIT(5) +#define TSE_PCS_STATUS_LINK_MASK 0x0004 +#define TSE_PCS_STATUS_REG 0x02 +#define TSE_PCS_SGMII_SPEED_1000 BIT(3) +#define TSE_PCS_SGMII_SPEED_100 BIT(2) +#define TSE_PCS_SGMII_SPEED_10 0x0 +#define TSE_PCS_SW_RST_MASK 0x8000 +#define TSE_PCS_PARTNER_ABILITY_REG 0x0A +#define TSE_PCS_PARTNER_DUPLEX_FULL 0x1000 +#define TSE_PCS_PARTNER_DUPLEX_HALF 0x0000 +#define TSE_PCS_PARTNER_DUPLEX_MASK 0x1000 +#define TSE_PCS_PARTNER_SPEED_MASK GENMASK(11, 10) +#define TSE_PCS_PARTNER_SPEED_1000 BIT(11) +#define TSE_PCS_PARTNER_SPEED_100 BIT(10) +#define TSE_PCS_PARTNER_SPEED_10 0x0000 +#define TSE_PCS_PARTNER_SPEED_1000 BIT(11) +#define TSE_PCS_PARTNER_SPEED_100 BIT(10) +#define TSE_PCS_PARTNER_SPEED_10 0x0000 +#define TSE_PCS_SGMII_SPEED_MASK GENMASK(3, 2) +#define TSE_PCS_SGMII_LINK_TIMER_0 0x0D40 +#define TSE_PCS_SGMII_LINK_TIMER_1 0x0003 +#define TSE_PCS_SW_RESET_TIMEOUT 100 +#define TSE_PCS_USE_SGMII_AN_MASK BIT(1) +#define TSE_PCS_USE_SGMII_ENA BIT(0) + +#define SGMII_ADAPTER_CTRL_REG 0x00 +#define SGMII_ADAPTER_DISABLE 0x0001 +#define SGMII_ADAPTER_ENABLE 0x0000 + +#define AUTONEGO_LINK_TIMER 20 + +struct tse_pcs { + struct device *dev; + phys_addr_t tse_pcs_base; + phys_addr_t sgmii_adapter_base; + struct timer_list aneg_link_timer; + int autoneg; +}; + +int tse_pcs_init(phys_addr_t base, struct tse_pcs *pcs); +void tse_pcs_fix_mac_speed(struct tse_pcs *pcs, struct phy_device *phy_dev, + unsigned int speed); + +#endif /* __TSE_PCS_H__ */ -- 1.9.1

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[U-Boot] [PATCH v2] net: Add MT76xx ethernet driver
by Stefan Roese 22 Oct '18

22 Oct '18

This patch adds ethernet support for the Mediatek MT76xx SoC, including a minimum setup of the integrated switch. This driver is loosly based on the driver version included in this MediaTek github repository: https://github.com/MediaTek-Labs/linkit-smart-uboot.git Tested on the MT7688 LinkIt smart-gateway and on the Gardena-smart-gateway. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> --- v2: - Use wait_for_bit_le32() in more places - Use syscon / regmap to access the system-controller registers needed in this driver instead of finding and mapping this area drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/mt76xx-eth.c | 638 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 646 insertions(+) create mode 100644 drivers/net/mt76xx-eth.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 5441da47d1..ed73f21a59 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -227,6 +227,13 @@ config MACB_ZYNQ The Cadence MACB ethernet interface was used on Zynq platform. Say Y to enable support for the MACB/GEM in Zynq chip. +config MT76XX_ETH + bool "MediaTek MT76xx Ethernet Interface" + depends on ARCH_MT7620 + help + The MediaTek MT76xx ethernet interface is used on MT7688 + based boards. + config PCH_GBE bool "Intel Platform Controller Hub EG20T GMAC driver" depends on DM_ETH && DM_PCI diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 48a2878071..05189514b7 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o +obj-$(CONFIG_MT76XX_ETH) += mt76xx-eth.o obj-$(CONFIG_MVGBE) += mvgbe.o obj-$(CONFIG_MVNETA) += mvneta.o obj-$(CONFIG_MVPP2) += mvpp2.o diff --git a/drivers/net/mt76xx-eth.c b/drivers/net/mt76xx-eth.c new file mode 100644 index 0000000000..a623a475af --- /dev/null +++ b/drivers/net/mt76xx-eth.c @@ -0,0 +1,638 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * MediaTek ethernet IP driver for U-Boot + * + * Copyright (C) 2018 Stefan Roese <sr(a)denx.de> + * + * This code is mostly based on the code extracted from this MediaTek + * github repository: + * + * https://github.com/MediaTek-Labs/linkit-smart-uboot.git + * + * I was not able to find a specific license or other developers + * copyrights here, so I can't add them here. + */ + +#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <miiphy.h> +#include <net.h> +#include <regmap.h> +#include <syscon.h> +#include <wait_bit.h> +#include <asm/io.h> +#include <linux/err.h> + +/* System controller register */ +#define MT76XX_RSTCTRL_REG 0x34 +#define RSTCTRL_EPHY_RST BIT(24) + +#define MT76XX_AGPIO_CFG_REG 0x3c +#define MT7628_EPHY_GPIO_AIO_EN GENMASK(20, 17) +#define MT7628_EPHY_P0_DIS BIT(16) + +#define MT76XX_GPIO2_MODE_REG 0x64 + +/* Ethernet frame engine register */ +#define PDMA_RELATED 0x0800 + +#define TX_BASE_PTR0 (PDMA_RELATED + 0x000) +#define TX_MAX_CNT0 (PDMA_RELATED + 0x004) +#define TX_CTX_IDX0 (PDMA_RELATED + 0x008) +#define TX_DTX_IDX0 (PDMA_RELATED + 0x00c) + +#define RX_BASE_PTR0 (PDMA_RELATED + 0x100) +#define RX_MAX_CNT0 (PDMA_RELATED + 0x104) +#define RX_CALC_IDX0 (PDMA_RELATED + 0x108) + +#define PDMA_GLO_CFG (PDMA_RELATED + 0x204) +#define PDMA_RST_IDX (PDMA_RELATED + 0x208) +#define DLY_INT_CFG (PDMA_RELATED + 0x20c) + +#define SDM_RELATED 0x0c00 + +#define SDM_MAC_ADRL (SDM_RELATED + 0x0c) /* MAC address LSB */ +#define SDM_MAC_ADRH (SDM_RELATED + 0x10) /* MAC Address MSB */ + +#define RST_DTX_IDX0 BIT(0) +#define RST_DRX_IDX0 BIT(16) + +#define TX_DMA_EN BIT(0) +#define TX_DMA_BUSY BIT(1) +#define RX_DMA_EN BIT(2) +#define RX_DMA_BUSY BIT(3) +#define TX_WB_DDONE BIT(6) + +/* Ethernet switch register */ +#define MT76XX_SWITCH_FCT0 0x0008 +#define MT76XX_SWITCH_PFC1 0x0014 +#define MT76XX_SWITCH_FPA 0x0084 +#define MT76XX_SWITCH_SOCPC 0x008c +#define MT76XX_SWITCH_POC0 0x0090 +#define MT76XX_SWITCH_POC2 0x0098 +#define MT76XX_SWITCH_SGC 0x009c +#define MT76XX_SWITCH_PCR0 0x00c0 +#define MT76XX_SWITCH_PCR1 0x00c4 +#define MT76XX_SWITCH_FPA1 0x00c8 +#define MT76XX_SWITCH_FCT2 0x00cc +#define MT76XX_SWITCH_SGC2 0x00e4 +#define MT76XX_SWITCH_BMU_CTRL 0x0110 + +/* rxd2 */ +#define RX_DMA_DONE BIT(31) +#define RX_DMA_LSO BIT(30) +#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) +#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) +#define RX_DMA_TAG BIT(15) +/* rxd3 */ +#define RX_DMA_TPID(_x) (((_x) >> 16) & 0xffff) +#define RX_DMA_VID(_x) ((_x) & 0xffff) +/* rxd4 */ +#define RX_DMA_L4VALID BIT(30) + +struct fe_rx_dma { + unsigned int rxd1; + unsigned int rxd2; + unsigned int rxd3; + unsigned int rxd4; +} __packed __aligned(4); + +#define TX_DMA_BUF_LEN 0x3fff +#define TX_DMA_PLEN0_MASK (TX_DMA_BUF_LEN << 16) +#define TX_DMA_PLEN0(_x) (((_x) & TX_DMA_BUF_LEN) << 16) +#define TX_DMA_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN) +#define TX_DMA_GET_PLEN0(_x) (((_x) >> 16) & TX_DMA_BUF_LEN) +#define TX_DMA_GET_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN) +#define TX_DMA_LS1 BIT(14) +#define TX_DMA_LS0 BIT(30) +#define TX_DMA_DONE BIT(31) + +#define TX_DMA_INS_VLAN_MT7621 BIT(16) +#define TX_DMA_INS_VLAN BIT(7) +#define TX_DMA_INS_PPPOE BIT(12) +#define TX_DMA_QN(_x) ((_x) << 16) +#define TX_DMA_PN(_x) ((_x) << 24) +#define TX_DMA_QN_MASK TX_DMA_QN(0x7) +#define TX_DMA_PN_MASK TX_DMA_PN(0x7) +#define TX_DMA_UDF BIT(20) +#define TX_DMA_CHKSUM (0x7 << 29) +#define TX_DMA_TSO BIT(28) + +struct fe_tx_dma { + unsigned int txd1; + unsigned int txd2; + unsigned int txd3; + unsigned int txd4; +} __packed __aligned(4); + +#define NUM_RX_DESC 256 +#define NUM_TX_DESC 4 + +#define PADDING_LENGTH 60 + +#define MTK_QDMA_PAGE_SIZE 2048 + +#define CONFIG_MDIO_TIMEOUT 100 +#define CONFIG_DMA_STOP_TIMEOUT 100 +#define CONFIG_TX_DMA_TIMEOUT 100 + +#define LINK_DELAY_TIME 500 /* 500 ms */ +#define LINK_TIMEOUT 10000 /* 10 seconds */ + +struct mt76xx_eth_dev { + void __iomem *base; /* frame engine base address */ + void __iomem *eth_sw_base; /* switch base address */ + struct regmap *sysctrl_regmap; /* system-controller reg-map */ + + struct mii_dev *bus; + + struct fe_tx_dma *tx_ring; + struct fe_rx_dma *rx_ring; + + u8 *rx_buf[NUM_RX_DESC]; + + /* Point to the next RXD DMA wants to use in RXD Ring0 */ + int rx_dma_idx; + /* Point to the next TXD in TXD Ring0 CPU wants to use */ + int tx_dma_idx; +}; + +static int mdio_wait_read(struct mt76xx_eth_dev *priv, u32 mask, bool mask_set) +{ + void __iomem *base = priv->eth_sw_base; + int ret; + + ret = wait_for_bit_le32(base + MT76XX_SWITCH_PCR1, mask, mask_set, + CONFIG_MDIO_TIMEOUT, false); + if (ret) { + printf("MDIO operation timeout!\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int mii_mgr_read(struct mt76xx_eth_dev *priv, + u32 phy_addr, u32 phy_register, u32 *read_data) +{ + void __iomem *base = priv->eth_sw_base; + u32 status = 0; + u32 ret; + + *read_data = 0xffff; + /* Make sure previous read operation is complete */ + ret = mdio_wait_read(priv, BIT(1), false); + if (ret) + return ret; + + writel(BIT(14) | (phy_register << 8) | phy_addr, + base + MT76XX_SWITCH_PCR0); + + /* Make sure previous read operation is complete */ + ret = mdio_wait_read(priv, BIT(1), true); + if (ret) + return ret; + + status = readl(base + MT76XX_SWITCH_PCR1); + *read_data = (u32)(status >> 16); + + return 0; +} + +static int mii_mgr_write(struct mt76xx_eth_dev *priv, + u32 phy_addr, u32 phy_register, u32 write_data) +{ + void __iomem *base = priv->eth_sw_base; + u32 data; + int ret; + + /* Make sure previous write operation is complete */ + ret = mdio_wait_read(priv, BIT(0), false); + if (ret) + return ret; + + data = (write_data & 0xffff) << 16; + data |= (phy_register << 8) | phy_addr; + data |= BIT(13); + writel(data, base + MT76XX_SWITCH_PCR0); + + return mdio_wait_read(priv, BIT(0), true); +} + +static int mt76xx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + u32 val; + int ret; + + ret = mii_mgr_read(bus->priv, addr, reg, &val); + if (ret) + return ret; + + return val; +} + +static int mt76xx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value) +{ + return mii_mgr_write(bus->priv, addr, reg, value); +} + +static void mt7628_ephy_init(struct mt76xx_eth_dev *priv) +{ + int i; + + mii_mgr_write(priv, 0, 31, 0x2000); /* change G2 page */ + mii_mgr_write(priv, 0, 26, 0x0000); + + for (i = 0; i < 5; i++) { + mii_mgr_write(priv, i, 31, 0x8000); /* change L0 page */ + mii_mgr_write(priv, i, 0, 0x3100); + + /* EEE disable */ + mii_mgr_write(priv, i, 30, 0xa000); + mii_mgr_write(priv, i, 31, 0xa000); /* change L2 page */ + mii_mgr_write(priv, i, 16, 0x0606); + mii_mgr_write(priv, i, 23, 0x0f0e); + mii_mgr_write(priv, i, 24, 0x1610); + mii_mgr_write(priv, i, 30, 0x1f15); + mii_mgr_write(priv, i, 28, 0x6111); + } + + /* 100Base AOI setting */ + mii_mgr_write(priv, 0, 31, 0x5000); /* change G5 page */ + mii_mgr_write(priv, 0, 19, 0x004a); + mii_mgr_write(priv, 0, 20, 0x015a); + mii_mgr_write(priv, 0, 21, 0x00ee); + mii_mgr_write(priv, 0, 22, 0x0033); + mii_mgr_write(priv, 0, 23, 0x020a); + mii_mgr_write(priv, 0, 24, 0x0000); + mii_mgr_write(priv, 0, 25, 0x024a); + mii_mgr_write(priv, 0, 26, 0x035a); + mii_mgr_write(priv, 0, 27, 0x02ee); + mii_mgr_write(priv, 0, 28, 0x0233); + mii_mgr_write(priv, 0, 29, 0x000a); + mii_mgr_write(priv, 0, 30, 0x0000); + + /* Fix EPHY idle state abnormal behavior */ + mii_mgr_write(priv, 0, 31, 0x4000); /* change G4 page */ + mii_mgr_write(priv, 0, 29, 0x000d); + mii_mgr_write(priv, 0, 30, 0x0500); +} + +static void rt305x_esw_init(struct mt76xx_eth_dev *priv) +{ + void __iomem *base = priv->eth_sw_base; + + /* + * FC_RLS_TH=200, FC_SET_TH=160 + * DROP_RLS=120, DROP_SET_TH=80 + */ + writel(0xc8a07850, base + MT76XX_SWITCH_FCT0); + writel(0x00000000, base + MT76XX_SWITCH_SGC2); + writel(0x00405555, base + MT76XX_SWITCH_PFC1); + writel(0x00007f7f, base + MT76XX_SWITCH_POC0); + writel(0x00007f7f, base + MT76XX_SWITCH_POC2); /* disable VLAN */ + writel(0x0002500c, base + MT76XX_SWITCH_FCT2); + /* hashing algorithm=XOR48, aging interval=300sec */ + writel(0x0008a301, base + MT76XX_SWITCH_SGC); + writel(0x02404040, base + MT76XX_SWITCH_SOCPC); + + /* Ext PHY Addr=0x1f */ + writel(0x3f502b28, base + MT76XX_SWITCH_FPA1); + writel(0x00000000, base + MT76XX_SWITCH_FPA); + /* 1us cycle number=125 (FE's clock=125Mhz) */ + writel(0x7d000000, base + MT76XX_SWITCH_BMU_CTRL); + + /* Configure analog GPIO setup */ + regmap_update_bits(priv->sysctrl_regmap, MT76XX_AGPIO_CFG_REG, + MT7628_EPHY_P0_DIS, MT7628_EPHY_GPIO_AIO_EN); + + /* Reset PHY */ + regmap_update_bits(priv->sysctrl_regmap, MT76XX_RSTCTRL_REG, + 0, RSTCTRL_EPHY_RST); + regmap_update_bits(priv->sysctrl_regmap, MT76XX_RSTCTRL_REG, + RSTCTRL_EPHY_RST, 0); + mdelay(10); + + /* Set P0 EPHY LED mode */ + regmap_update_bits(priv->sysctrl_regmap, MT76XX_GPIO2_MODE_REG, + 0x0ffc0ffc, 0x05540554); + mdelay(10); + + mt7628_ephy_init(priv); +} + +static void eth_dma_start(struct mt76xx_eth_dev *priv) +{ + void __iomem *base = priv->base; + + setbits_le32(base + PDMA_GLO_CFG, TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); +} + +static void eth_dma_stop(struct mt76xx_eth_dev *priv) +{ + void __iomem *base = priv->base; + int ret; + + clrbits_le32(base + PDMA_GLO_CFG, TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); + + /* Wait for DMA to stop */ + ret = wait_for_bit_le32(base + PDMA_GLO_CFG, + RX_DMA_BUSY | TX_DMA_BUSY, false, + CONFIG_DMA_STOP_TIMEOUT, false); + if (ret) + printf("DMA stop timeout error!\n"); +} + +static int mt76xx_eth_write_hwaddr(struct udevice *dev) +{ + struct mt76xx_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + u8 *addr = ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr; + u32 val; + u16 tmp; + + /* Set MAC address. */ + tmp = (u16)addr[0]; + val = (tmp << 8) | addr[1]; + + writel(val, base + SDM_MAC_ADRH); + + tmp = (u16)addr[2]; + val = (tmp << 8) | addr[3]; + val = val << 16; + tmp = (u16)addr[4]; + val |= (tmp << 8) | addr[5]; + writel(val, base + SDM_MAC_ADRL); + + return 0; +} + +static int mt76xx_eth_send(struct udevice *dev, void *packet, int length) +{ + struct mt76xx_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + int ret; + int idx; + int i; + + idx = priv->tx_dma_idx; + + /* Pad message to a minimum length */ + if (length < PADDING_LENGTH) { + char *p = (char *)packet; + + for (i = 0; i < PADDING_LENGTH - length; i++) + p[length + i] = 0; + length = PADDING_LENGTH; + } + + /* Check if buffer is ready for next TX DMA */ + ret = wait_for_bit_le32(&priv->tx_ring[idx].txd2, TX_DMA_DONE, true, + CONFIG_TX_DMA_TIMEOUT, false); + if (ret) { + printf("TX: DMA still busy on buffer %d\n", idx); + return ret; + } + + flush_dcache_range((u32)packet, (u32)packet + length); + + priv->tx_ring[idx].txd1 = CPHYSADDR(packet); + priv->tx_ring[idx].txd2 |= TX_DMA_PLEN0(length); + priv->tx_ring[idx].txd2 &= ~TX_DMA_DONE; + + idx = (idx + 1) % NUM_TX_DESC; + + /* Make sure the writes exceuted at this place */ + wmb(); + writel(idx, base + TX_CTX_IDX0); + + priv->tx_dma_idx = idx; + + return 0; +} + +static int mt76xx_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct mt76xx_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + u32 rxd_info; + int length; + int idx; + + idx = priv->rx_dma_idx; + + rxd_info = priv->rx_ring[idx].rxd2; + if ((rxd_info & RX_DMA_DONE) == 0) + return -EAGAIN; + + length = RX_DMA_GET_PLEN0(priv->rx_ring[idx].rxd2); + if (length == 0 || length > MTK_QDMA_PAGE_SIZE) { + printf("%s: invalid length (%d bytes)\n", __func__, length); + return -EIO; + } + + *packetp = priv->rx_buf[idx]; + invalidate_dcache_range((u32)*packetp, (u32)*packetp + length); + + priv->rx_ring[idx].rxd4 = 0; + priv->rx_ring[idx].rxd2 = RX_DMA_LSO; + + /* Make sure the writes exceuted at this place */ + wmb(); + + /* Move point to next RXD which wants to alloc */ + writel(idx, base + RX_CALC_IDX0); + + /* Update to Next packet point that was received */ + idx = (idx + 1) % NUM_RX_DESC; + + priv->rx_dma_idx = idx; + + return length; +} + +static int phy_link_up(struct mt76xx_eth_dev *priv) +{ + u32 val; + + mii_mgr_read(priv, 0x00, MII_BMSR, &val); + return !!(val & BMSR_LSTATUS); +} + +static int mt76xx_eth_start(struct udevice *dev) +{ + struct mt76xx_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + uchar packet[MTK_QDMA_PAGE_SIZE]; + uchar *packetp; + int i; + + for (i = 0; i < NUM_RX_DESC; i++) { + memset((void *)&priv->rx_ring[i], 0, sizeof(priv->rx_ring[0])); + priv->rx_ring[i].rxd2 |= RX_DMA_LSO; + priv->rx_ring[i].rxd1 = CPHYSADDR(priv->rx_buf[i]); + } + + for (i = 0; i < NUM_TX_DESC; i++) { + memset((void *)&priv->tx_ring[i], 0, sizeof(priv->tx_ring[0])); + priv->tx_ring[i].txd2 = TX_DMA_LS0 | TX_DMA_DONE; + priv->tx_ring[i].txd4 = TX_DMA_PN(1); + } + + priv->rx_dma_idx = 0; + priv->tx_dma_idx = 0; + + /* Make sure the writes exceuted at this place */ + wmb(); + + /* disable delay interrupt */ + writel(0, base + DLY_INT_CFG); + + clrbits_le32(base + PDMA_GLO_CFG, 0xffff0000); + + /* Tell the adapter where the TX/RX rings are located. */ + writel(CPHYSADDR(&priv->rx_ring[0]), base + RX_BASE_PTR0); + writel(CPHYSADDR((u32)&priv->tx_ring[0]), base + TX_BASE_PTR0); + + writel(NUM_RX_DESC, base + RX_MAX_CNT0); + writel(NUM_TX_DESC, base + TX_MAX_CNT0); + + writel(priv->tx_dma_idx, base + TX_CTX_IDX0); + writel(RST_DTX_IDX0, base + PDMA_RST_IDX); + + writel(NUM_RX_DESC - 1, base + RX_CALC_IDX0); + writel(RST_DRX_IDX0, base + PDMA_RST_IDX); + + /* Make sure the writes exceuted at this place */ + wmb(); + eth_dma_start(priv); + + /* Check if link is not up yet */ + if (!phy_link_up(priv)) { + /* Wait for link to come up */ + + printf("Waiting for link to come up ."); + for (i = 0; i < (LINK_TIMEOUT / LINK_DELAY_TIME); i++) { + mdelay(LINK_DELAY_TIME); + if (phy_link_up(priv)) { + mdelay(100); /* Ensure all is ready */ + break; + } + + printf("."); + } + + if (phy_link_up(priv)) + printf(" done\n"); + else + printf(" timeout! Trying anyways\n"); + } + + /* + * The integrated switch seems to queue some received ethernet + * packets in some FIFO. Lets read the already queued packets + * out by using the reveice routine, so that these old messages + * are dropped before the new xfer starts. + */ + packetp = &packet[0]; + while (mt76xx_eth_recv(dev, 0, &packetp) != -EAGAIN) + ; + + return 0; +} + +static void mt76xx_eth_stop(struct udevice *dev) +{ + struct mt76xx_eth_dev *priv = dev_get_priv(dev); + + eth_dma_stop(priv); +} + +static int mt76xx_eth_probe(struct udevice *dev) +{ + struct mt76xx_eth_dev *priv = dev_get_priv(dev); + struct udevice *syscon; + struct mii_dev *bus; + int ret; + int i; + + /* Save frame-engine base address for later use */ + priv->base = dev_remap_addr_index(dev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + /* Save switch base address for later use */ + priv->eth_sw_base = dev_remap_addr_index(dev, 1); + if (IS_ERR(priv->eth_sw_base)) + return PTR_ERR(priv->eth_sw_base); + + /* Get system controller regmap */ + ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, + "syscon", &syscon); + if (ret) { + pr_err("unable to find syscon device\n"); + return ret; + } + + priv->sysctrl_regmap = syscon_get_regmap(syscon); + if (!priv->sysctrl_regmap) { + pr_err("unable to find regmap\n"); + return -ENODEV; + } + + /* Put rx and tx rings into KSEG1 area (uncached) */ + priv->tx_ring = (struct fe_tx_dma *) + KSEG1ADDR(memalign(ARCH_DMA_MINALIGN, + sizeof(*priv->tx_ring) * NUM_TX_DESC)); + priv->rx_ring = (struct fe_rx_dma *) + KSEG1ADDR(memalign(ARCH_DMA_MINALIGN, + sizeof(*priv->rx_ring) * NUM_RX_DESC)); + + for (i = 0; i < NUM_RX_DESC; i++) + priv->rx_buf[i] = memalign(PKTALIGN, MTK_QDMA_PAGE_SIZE); + + bus = mdio_alloc(); + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = mt76xx_mdio_read; + bus->write = mt76xx_mdio_write; + snprintf(bus->name, sizeof(bus->name), dev->name); + bus->priv = (void *)priv; + + ret = mdio_register(bus); + if (ret) + return ret; + + /* Switch configuration */ + rt305x_esw_init(priv); + + return 0; +} + +static const struct eth_ops mt76xx_eth_ops = { + .start = mt76xx_eth_start, + .send = mt76xx_eth_send, + .recv = mt76xx_eth_recv, + .stop = mt76xx_eth_stop, + .write_hwaddr = mt76xx_eth_write_hwaddr, +}; + +static const struct udevice_id mt76xx_eth_ids[] = { + { .compatible = "mediatek,mt7622-eth" }, + { } +}; + +U_BOOT_DRIVER(mt76xx_eth) = { + .name = "mt76xx_eth", + .id = UCLASS_ETH, + .of_match = mt76xx_eth_ids, + .probe = mt76xx_eth_probe, + .ops = &mt76xx_eth_ops, + .priv_auto_alloc_size = sizeof(struct mt76xx_eth_dev), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; -- 2.19.1

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[U-Boot] [PATCH 0/6] driver: net: fsl-mc: Add support of multiple phys for dpmac
by Pankaj Bansal 22 Oct '18

22 Oct '18

This patch set adds support of multiple phys for one dpmac Till now we have had cases where we had one phy device per dpmac. Now, with the upcoming products (LX2160AQDS), we have cases, where there are sometimes two phy devices for one dpmac. One phy for TX lanes and one phy for RX lanes. To handle such cases, add the support for multiple phys in ethernet driver. The ethernet link is up if all the phy devices connected to one dpmac report link up. also the link capabilities are limited by the weakest phy device. i.e. say if there are two phys for one dpmac. one operates at 10G without autoneg and other operate at 1G with autoneg. Then the ethernet interface will operate at 1G without autoneg. Pankaj Bansal (6): driver: net: fsl-mc: modify the label name driver: net: fsl-mc: remove unused strcture elements driver: net: fsl-mc: fix error handing in init_phy driver: net: fsl-mc: Modify the dpmac link detection method driver: net: fsl-mc: initialize dpmac irrespective of phy driver: net: fsl-mc: Add support of multiple phys for dpmac board/freescale/ls1088a/eth_ls1088aqds.c | 18 +-- board/freescale/ls1088a/eth_ls1088ardb.c | 21 +-- board/freescale/ls2080aqds/eth.c | 26 +-- board/freescale/ls2080ardb/eth_ls2080rdb.c | 24 +-- drivers/net/fsl-mc/mc.c | 6 +- drivers/net/ldpaa_eth/ldpaa_eth.c | 180 +++++++++++++-------- drivers/net/ldpaa_eth/ldpaa_eth.h | 1 - drivers/net/ldpaa_eth/ldpaa_wriop.c | 49 ++++-- include/fsl-mc/ldpaa_wriop.h | 22 +-- 9 files changed, 209 insertions(+), 138 deletions(-) -- 2.17.1

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[U-Boot] Pull request: u-boot-staging
by Anatolij Gustschin 22 Oct '18

22 Oct '18

Hi Tom, please pull some synxi PWM driver bugfixes: The following changes since commit e3beca3a2fe172ca707a0e70310f9f7ebd3b3f0f: Merge tag 'signed-efi-2018.11' of git://github.com/agraf/u-boot (2018-10-17 07:20:52 -0400) are available in the Git repository at: git://git.denx.de/u-boot-staging.git agust(a)denx.de for you to fetch changes up to a1f95bf1a87c5e4f9fe37b02bc1e34cccd3893b5: pwm: sunxi: choose best prescaler to improve PWM resolution (2018-10-18 23:05:00 +0200) ---------------------------------------------------------------- Vasily Khoruzhick (3): pwm: sunxi: fix off-by-one that prevented PWM to use prescaler bypass pwm: sunxi: use new prescaler when configuring PWM pwm: sunxi: choose best prescaler to improve PWM resolution drivers/pwm/sunxi_pwm.c | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) -- Anatolij

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[U-Boot] [PATCH v3 0/5] Add support for Pinebook
by Vasily Khoruzhick 22 Oct '18

22 Oct '18

This series adds support for the Pinebook, an allwinner A64 laptop produced by Pine64. It also syncs sun50i-a64.dtsi with linux, adds support for mmc delay calibration, R_I2C controller, and addresses the issue with activating video bridge when any of GPIOs is missing. v2: - sync sun50i-a64.dtsi with linux instead of adding missing nodes - take sun50i-a64-pinebook.dts from linux - don't introduce new Kconfig for A64 MMC calibration - improve code in video bridge uclass to check for presensce of GPIO instead of ingoring EINVAL errors v3: - enable calibration for H6 as well - init ret variable in video_bridge_set_active() - fix order of dts files Makefile - split anx6345 binding into sun50i-a64-pinebook-u-boot.dts - drop speaker_amp node from pinebook dts - drop unnecessary options from defconfig Vasily Khoruzhick (5): mmc: sunxi: add support for automatic delay calibration dm: video: bridge: don't fail to activate bridge if reset or sleep GPIO is missing sunxi: DT: A64: update device tree file for Allwinner A64 SoC sun50i: A64: add support for R_I2C controller sunxi: DT: add support for Pinebook arch/arm/dts/Makefile | 1 + arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi | 15 + arch/arm/dts/sun50i-a64-pinebook.dts | 294 +++++++++++++++++++ arch/arm/dts/sun50i-a64.dtsi | 122 ++++++-- arch/arm/include/asm/arch-sunxi/gpio.h | 1 + arch/arm/include/asm/arch-sunxi/mmc.h | 6 +- arch/arm/mach-sunxi/Kconfig | 1 + board/sunxi/board.c | 6 + configs/pinebook_defconfig | 22 ++ drivers/mmc/sunxi_mmc.c | 21 +- drivers/video/bridge/video-bridge-uclass.c | 16 +- 11 files changed, 479 insertions(+), 26 deletions(-) create mode 100644 arch/arm/dts/sun50i-a64-pinebook-u-boot.dtsi create mode 100644 arch/arm/dts/sun50i-a64-pinebook.dts create mode 100644 configs/pinebook_defconfig -- 2.19.0

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[U-Boot] [PATCH] syscon: reset node list syscon_list after relocation
by Patrick Delaunay 22 Oct '18

22 Oct '18

Reset the list head after the reallocation because the list syscon_list use allocated pointer and they are no more valid. This patch avoid issue (crash) when syscon_node_to_regmap() is called before and after reallocation. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)st.com> --- Hi This patch correct a crash see on v2018.11-rc1 with my board stm32mp1 for the command "reset". The crash is a side effect of 2 patches 1f6ca3f42f6edf143473159297f4c515b1cf36f6 sysreset: syscon: update regmap access to syscon 23471aed5c33e104d6fa64575932577618543bec board_f: Add reset status printing With the first patch the syscon_node_to_regmap() is called each time that the class sysreset_syscon is probed. => in v2018.09 probe is done only when reset is requested NB: for stm32mp1, the node rcc_reboot in tagged pre-relocated to support reset in pre-reloc phases (allow panic). With the second patch, U-Boot probes all the sysreset uclass in preloc phase to allow to print the reset status, and the list is initialized in board_f / pre-reloc: -> print_resetinfo --> uclass_first_device_err(UCLASS_SYSRESET, &dev); ---> syscon_reboot_probe() ----> syscon_node_to_regmap(node) -----> of_syscon_register() -------> list_add_tail(&syscon->list, &syscon_list); During relocation, the content of syscon_list (static) is updated but the list use pointers allocated by malloc in pre-reloc phasis And when I execute the reset command -> do_reset() --> reset_cpu() ---> sysreset_walk_halt(SYSRESET_COLD); ----> loop on device UCLASS_SYSRESET -----> syscon_reboot_probe() ------> syscon_node_to_regmap(node) -------> list_for_each_entry(entry, &syscon_list, list) I have a crash here because the pointer syscon_list.next is invalid. I solve the issue by resetting the list after reloc and it is working but I don't know if a more elegant solution exist (keep the list in .bss section to be set to 0). Regards Patrick drivers/core/syscon-uclass.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c index 303e166..aacb43a 100644 --- a/drivers/core/syscon-uclass.c +++ b/drivers/core/syscon-uclass.c @@ -156,8 +156,15 @@ static struct syscon *of_syscon_register(ofnode node) struct regmap *syscon_node_to_regmap(ofnode node) { + static int reloc_done; struct syscon *entry, *syscon = NULL; + /* content of list is not relocated (malloc): reinit when needed */ + if (!reloc_done && (gd->flags & GD_FLG_RELOC)) { + INIT_LIST_HEAD(&syscon_list); + reloc_done++; + } + list_for_each_entry(entry, &syscon_list, list) if (ofnode_equal(entry->node, node)) { syscon = entry; -- 2.7.4

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[U-Boot] [PATCH 0/4] Add adc uclass's channel mask and conversion helpers and enhance adc cmd
by Fabrice Gasnier 22 Oct '18

22 Oct '18

This series adds ADC uclass's helpers to - retrieve the ADC device available channels - ease conversions to standard unit (µV) - enhance 'adc' command to print information on available ADC channels - enhance 'adc' command to print conversion result both as raw and µV - enhance 'adc' command to scan once several or all channels Fabrice Gasnier (4): dm: adc: add uclass's mask and conversion helpers cmd: adc: add info on channel mask cmd: adc: print single conversion also in uV cmd: adc: add an option to scan some or all available channels cmd/adc.c | 70 +++++++++++++++++++++++++++++++++++++++++++++--- drivers/adc/adc-uclass.c | 37 +++++++++++++++++++++++++ include/adc.h | 21 +++++++++++++++ 3 files changed, 124 insertions(+), 4 deletions(-) -- 1.9.1

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[U-Boot] [PATCH] arm: ti: boot: Remove environment partition
by Sam Protsenko 22 Oct '18

22 Oct '18

Remove "environment" partition and do not read it when booting Android from eMMC. We don't use this partition anymore, so this is just an unintentional leftover. Earlier we were reading dtb file from "environment" partition to feed it further to kernel. Now we are using dtb from FIT image ("boot" partition contains boot_fit.img image), which can be seen from this command: bootm ${loadaddr}#${fdtfile} where "#" character means we have FIT image in ${loadaddr} RAM address. Signed-off-by: Sam Protsenko <semen.protsenko(a)linaro.org> --- include/environment/ti/boot.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h index 2893cd4287..560753ae4c 100644 --- a/include/environment/ti/boot.h +++ b/include/environment/ti/boot.h @@ -35,7 +35,6 @@ "uuid_disk=${uuid_gpt_disk};" \ "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \ "name=bootloader,size=1792K,uuid=${uuid_gpt_bootloader};" \ - "name=environment,size=128K,uuid=${uuid_gpt_environment};" \ "name=misc,size=128K,uuid=${uuid_gpt_misc};" \ "name=reserved,size=256K,uuid=${uuid_gpt_reserved};" \ "name=efs,size=16M,uuid=${uuid_gpt_efs};" \ @@ -92,8 +91,6 @@ "mmc dev $mmcdev; " \ "mmc rescan; " \ AVB_VERIFY_CHECK \ - "part start mmc ${mmcdev} environment fdt_start; " \ - "part size mmc ${mmcdev} environment fdt_size; " \ "part start mmc ${mmcdev} boot boot_start; " \ "part size mmc ${mmcdev} boot boot_size; " \ "mmc read ${fdtaddr} ${fdt_start} ${fdt_size}; " \ -- 2.19.1

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[U-Boot] [PATCH] watchdog: aspeed: restore default value of reset_mask
by Cédric Le Goater 22 Oct '18

22 Oct '18

This is required for the current Linux kernel to reboot. It should also probably be fixed in Linux. Signed-off-by: Cédric Le Goater <clg(a)kaod.org> --- arch/arm/include/asm/arch-aspeed/wdt.h | 9 +++++++++ drivers/watchdog/ast_wdt.c | 1 + 2 files changed, 10 insertions(+) diff --git a/arch/arm/include/asm/arch-aspeed/wdt.h b/arch/arm/include/asm/arch-aspeed/wdt.h index 8d6f292c8495..fb04d41d3cbf 100644 --- a/arch/arm/include/asm/arch-aspeed/wdt.h +++ b/arch/arm/include/asm/arch-aspeed/wdt.h @@ -57,6 +57,15 @@ #define WDT_RESET_SPI (1 << 24) #define WDT_RESET_MISC (1 << 25) +#define WDT_RESET_DEFAULT \ + (WDT_RESET_ARM | WDT_RESET_COPROC | WDT_RESET_I2C | \ + WDT_RESET_MAC1 | WDT_RESET_MAC2 | WDT_RESET_GCRT | \ + WDT_RESET_USB20 | WDT_RESET_USB11_HOST | WDT_RESET_USB11_EHCI2 | \ + WDT_RESET_VIDEO | WDT_RESET_HAC | WDT_RESET_LPC | \ + WDT_RESET_SDSDIO | WDT_RESET_MIC | WDT_RESET_CRT2C | \ + WDT_RESET_PWM | WDT_RESET_PECI | WDT_RESET_JTAG | \ + WDT_RESET_ADC | WDT_RESET_GPIO | WDT_RESET_MISC) + #ifndef __ASSEMBLY__ struct ast_wdt { u32 counter_status; diff --git a/drivers/watchdog/ast_wdt.c b/drivers/watchdog/ast_wdt.c index 477605e7222d..59afa21efa4b 100644 --- a/drivers/watchdog/ast_wdt.c +++ b/drivers/watchdog/ast_wdt.c @@ -50,6 +50,7 @@ static int ast_wdt_stop(struct udevice *dev) clrbits_le32(&priv->regs->ctrl, WDT_CTRL_EN); + writel(WDT_RESET_DEFAULT, &priv->regs->reset_mask); return 0; } -- 2.17.2

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[U-Boot] [PATCH] ARM: omap3_logic: Add NOR Flash Support for SOM-LV
by Adam Ford 22 Oct '18

22 Oct '18

The DM37 and OMAP35 SOM-LV SOM-LV products both support a NOR flash part connected to CS2 in addition to the NAND part on CS0. This patch setups the GPMC timings for the MT28 NOR Flash and enables the CFI-Flash driver now that the CFI stuff is in Kconfig Signed-off-by: Adam Ford <aford173(a)gmail.com> --- V2: Check for OMAP35 or DM37 and set GPMC CS2 accordingly diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 4507b1ed99..37e288c6e7 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -40,6 +40,22 @@ DECLARE_GLOBAL_DATA_PTR; +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1 0x00011203 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2 0x000A1302 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3 0x000F1302 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4 0x0A021303 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5 0x00120F18 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6 0x0A030000 +#define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 0x00000C50 + +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1 0x00011203 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2 0x00091102 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3 0x000D1102 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4 0x09021103 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5 0x00100D15 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000 +#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50 + /* This is only needed until SPL gets OF support */ #ifdef CONFIG_SPL_BUILD static const struct ns16550_platdata omap3logic_serial = { @@ -208,6 +224,28 @@ int misc_init_r(void) return 0; } +#if defined(CONFIG_FLASH_CFI_DRIVER) +static const u32 gpmc_dm37_c2nor_config[] = { + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6, + LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 +}; + +static const u32 gpmc_omap35_c2nor_config[] = { + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6, + LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 +}; +#endif + /* * Routine: board_init * Description: Early hardware init. @@ -218,7 +256,16 @@ int board_init(void) /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - +#if defined(CONFIG_FLASH_CFI_DRIVER) + if (get_cpu_family() == CPU_OMAP36XX) { + /* Enable CS2 for NOR Flash */ + enable_gpmc_cs_config(gpmc_dm37_c2nor_config, &gpmc_cfg->cs[2], + 0x10000000, GPMC_SIZE_64M); + } else { + enable_gpmc_cs_config(gpmc_omap35_c2nor_config, &gpmc_cfg->cs[2], + 0x10000000, GPMC_SIZE_64M); + } +#endif return 0; } diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index 4521aedb2a..2b7dececf7 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -24,8 +24,8 @@ CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_CACHE=y -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)" +CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y @@ -39,6 +39,12 @@ CONFIG_FASTBOOT_BUF_ADDR=0x82000000 CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_PROTECTION=y +CONFIG_SYS_FLASH_CFI=y CONFIG_NAND=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index d29621d8ce..16351ba41c 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -20,12 +20,11 @@ CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x240000 CONFIG_CMD_SPL_WRITE_SIZE=0x20000 # CONFIG_CMD_EEPROM is not set -# CONFIG_CMD_FLASH is not set CONFIG_CMD_NAND=y CONFIG_CMD_NAND_LOCK_UNLOCK=y CONFIG_CMD_CACHE=y -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)" +CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y @@ -40,6 +39,12 @@ CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_MMC_OMAP_HS=y CONFIG_MMC_OMAP36XX_PINS=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_PROTECTION=y +CONFIG_SYS_FLASH_CFI=y CONFIG_NAND=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 8644e16830..fe557f91ca 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -183,9 +183,14 @@ /* **** PISMO SUPPORT *** */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE +#define CONFIG_SYS_FLASH_BASE 0x10000000 #endif +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_SIZE 0x4000000 + /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -- 2.17.1

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