January 2018 - U-Boot

[U-Boot] [PATCH] doc: zynq: Describe status of zc770-xm011
by Michal Simek 15 Jan '18

15 Jan '18

zc770-xm011 is also added and supported. Reflect this in README. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- doc/README.zynq | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/doc/README.zynq b/doc/README.zynq index 451743f39eaa..cc5c0de21741 100644 --- a/doc/README.zynq +++ b/doc/README.zynq @@ -57,7 +57,7 @@ bootmode strings at runtime. - Added basic board configurations support. - Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq -- Added zynq boards named - zc70x, zed, microzed, zc770_xm010, zc770_xm012, zc770_xm013 +- Added zynq boards named - zc70x, zed, microzed, zc770_xm010/xm011/xm012/xm013 - Added zynq drivers: serial - drivers/serial/serial_zynq.c net - drivers/net/zynq_gem.c @@ -72,7 +72,6 @@ bootmode strings at runtime. 6. TODO -- Add zynq boards support - zc770_xm011 - Add FDT support on individual drivers [1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm -- 1.9.1

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[U-Boot] [PATCH] doc: Update the zynq u-boot status
by Ezequiel Garcia 15 Jan '18

15 Jan '18

NAND and QSPI devices are now supported, so mark them as such. Cc: Michal Simek <michal.simek(a)xilinx.com> Signed-off-by: Ezequiel Garcia <ezequiel(a)vanguardiasur.com.ar> --- doc/README.zynq | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/doc/README.zynq b/doc/README.zynq index b89c39edac18..451743f39eaa 100644 --- a/doc/README.zynq +++ b/doc/README.zynq @@ -62,9 +62,10 @@ bootmode strings at runtime. serial - drivers/serial/serial_zynq.c net - drivers/net/zynq_gem.c mmc - drivers/mmc/zynq_sdhci.c - mmc - drivers/mmc/zynq_sdhci.c - spi- drivers/spi/zynq_spi.c + spi - drivers/spi/zynq_spi.c + qspi - drivers/spi/zynq_qspi.c i2c - drivers/i2c/zynq_i2c.c + nand - drivers/mtd/nand/zynq_nand.c - Done proper cleanups on board configurations - Added basic FDT support for zynq boards - d-cache support for zynq_gem.c @@ -72,8 +73,6 @@ bootmode strings at runtime. 6. TODO - Add zynq boards support - zc770_xm011 -- Add zynq qspi controller driver -- Add zynq nand controller driver - Add FDT support on individual drivers [1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm -- 2.15.1

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[U-Boot] [PATCH] arm: zynq: Enable SPL_CLK only if SPL is enabled
by Ezequiel Garcia 15 Jan '18

15 Jan '18

Setup proper dependency in Kconfig for SPL_CLK. If SPL is not enabled, SPL_CLK shouldn't be selected. Cc: Michal Simek <michal.simek(a)xilinx.com> Signed-off-by: Ezequiel Garcia <ezequiel(a)vanguardiasur.com.ar> --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index de323bf4b96e..4ff369c32524 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -760,7 +760,7 @@ config ARCH_ZYNQ select DM_USB if USB select BLK select CLK - select SPL_CLK + select SPL_CLK if SPL select CLK_ZYNQ imply CMD_CLK imply FAT_WRITE -- 2.15.1

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[U-Boot] [PATCH v3] armv8: errata: Implement workaround for Cortex-A53 Erratum 855873
by Alison Wang 15 Jan '18

15 Jan '18

855873: An eviction might overtake a cache clean operation Workaround: The erratum can be avoided by upgrading cache clean by address operations to cache clean and invalidate operations. For Cortex-A53 r0p3 and later release, this can be achieved by setting CPUACTLR.ENDCCASCI to 1. This patch is to implement the workaround for this erratum. Signed-off-by: Alison Wang <alison.wang(a)nxp.com> --- Changes in v3: - Check the major revision of Cortex-A53. Changes in v2: - Check the revision of Cortex-A53 and apply the erratum to r0p3 and later release. - Fix the mistake in the commit description. arch/arm/Kconfig | 3 +++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 3 +++ arch/arm/cpu/armv8/start.S | 24 +++++++++++++++++++++++- 3 files changed, 29 insertions(+), 1 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f2c35e3..de323bf 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -122,6 +122,9 @@ config ARM_ERRATA_852421 config ARM_ERRATA_852423 bool +config ARM_ERRATA_855873 + bool + config CPU_ARM720T bool select SYS_CACHE_SHIFT_5 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 66bc32c..76a4d8b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -1,6 +1,7 @@ config ARCH_LS1012A bool select ARMV8_SET_SMPEN + select ARM_ERRATA_855873 select FSL_LSCH2 select SYS_FSL_DDR_BE select SYS_FSL_MMDC @@ -15,6 +16,7 @@ config ARCH_LS1012A config ARCH_LS1043A bool select ARMV8_SET_SMPEN + select ARM_ERRATA_855873 select FSL_LSCH2 select SYS_FSL_DDR select SYS_FSL_DDR_BE @@ -67,6 +69,7 @@ config ARCH_LS1046A config ARCH_LS1088A bool select ARMV8_SET_SMPEN + select ARM_ERRATA_855873 select FSL_LSCH3 select SYS_FSL_DDR select SYS_FSL_DDR_LE diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 03e744e..f385ed4 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -196,7 +196,10 @@ reset_sctrl: WEAK(apply_core_errata) mov x29, lr /* Save LR */ - /* For now, we support Cortex-A57 specific errata only */ + /* For now, we support Cortex-A53, Cortex-A57 specific errata */ + + /* Check if we are running on a Cortex-A53 core */ + branch_if_a53_core x0, apply_a53_core_errata /* Check if we are running on a Cortex-A57 core */ branch_if_a57_core x0, apply_a57_core_errata @@ -204,6 +207,25 @@ WEAK(apply_core_errata) mov lr, x29 /* Restore LR */ ret +apply_a53_core_errata: + +#ifdef CONFIG_ARM_ERRATA_855873 + mrs x0, midr_el1 + tst x0, #(0xf << 20) + b.ne 0b + + mrs x0, midr_el1 + and x0, x0, #0xf + cmp x0, #3 + b.lt 0b + + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ + /* Enable data cache clean as data cache clean/invalidate */ + orr x0, x0, #1 << 44 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ +#endif + b 0b + apply_a57_core_errata: #ifdef CONFIG_ARM_ERRATA_828024 -- 1.7.1

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[U-Boot] [PATCH v1] x86: Fix reference to QEMU variant of write_acpi_tables()
by Andy Shevchenko 15 Jan '18

15 Jan '18

The commit eece493a7ac1 ("cmd: qfw: bring ACPI generation code into qfw core") moves ACPI related code to another file and missed an update of references in acpi_table.c. Do it now. Fixes: eece493a7ac1 ("cmd: qfw: bring ACPI generation code into qfw core") Cc: Miao Yan <yanmiaobest(a)gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- arch/x86/lib/acpi_table.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 3eb101105b..7b33cd371e 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -357,8 +357,7 @@ void enter_acpi_mode(int pm1_cnt) } /* - * QEMU's version of write_acpi_tables is defined in - * arch/x86/cpu/qemu/acpi_table.c + * QEMU's version of write_acpi_tables is defined in drivers/misc/qfw.c */ ulong write_acpi_tables(ulong start) { -- 2.15.1

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[U-Boot] [PATCH v1] x86: tangier: Make _CRS for BTH0 Serialized to avoid warning
by Andy Shevchenko 15 Jan '18

15 Jan '18

ASL compiler warns: ASL board/intel/edison/dsdt.asl board/intel/edison/dsdt.asl.tmp 238: Method (_CRS, 0, NotSerialized) Remark 2120 - Control Method should be made Serialized ^ (due to creation of named objects within) Do as suggested by ASL compiler. Fixes: 5d8c4ebd95e2 ("x86: tangier: Add Bluetooth to ACPI table") Reported-by: Ferry Toth <fntoth(a)gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- arch/x86/include/asm/arch-tangier/acpi/southcluster.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl index 2b3b897c5b..5289b14957 100644 --- a/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl +++ b/arch/x86/include/asm/arch-tangier/acpi/southcluster.asl @@ -284,7 +284,7 @@ Device (PCI0) Return (STA_VISIBLE) } - Method (_CRS, 0, NotSerialized) + Method (_CRS, 0, Serialized) { Name (RBUF, ResourceTemplate () { -- 2.15.1

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[U-Boot] [PATCH 0/4] Add CONFIG_SPL_NAND_IDENT
by Jörg Krause 14 Jan '18

14 Jan '18

When adding SPL support to a custom i.MX6ULL board with Toshiba TC58NVG0S3 NAND chip the MXS NAND SPL loader failed with "Failed to identify". This reason is that the SPL MXS NAND driver only supports ONFi-compliant NAND chips and the mentioned Toshiba NAND chip is non-ONFi. This patch set makes `nand_get_flash_type()` from `nand_base.c` public, so it can be used by any SPL NAND driver, introduced a new config option `CONFIG_SPL_NAND_IDENT` to enable the lookup for supported NAND chips in the chip ID list. Finally, the MXS NAND SPL driver is refactored so that the original ONFi-only identification routine is enabled by default. For non-ONFi NAND chips the newly introduced config option can be used. In my setup the binary size of `u-boot-spl.bin` is increased by about 13 kB when `CONFIG_SPL_NAND_IDENT` is enabled. As the i.MX6, as well as the i.MX28, both have an OCRAM of 128 kB the increase in the binary size is reasonable. Jörg Krause (4): mtd: nand: export nand_get_flash_type function spl, nand: add option CONFIG_SPL_NAND_IDENT to lookup for supported NAND chips mtd: nand: mxs_nand_spl: refactor mxs_flash_ident mtd: nand: mxs_nand_spl: add mxs_flash_full_ident README | 4 ++++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/mxs_nand_spl.c | 37 ++++++++++++++++++++++++++++++++++++- drivers/mtd/nand/nand_base.c | 3 ++- include/linux/mtd/rawnand.h | 10 +++++++--- scripts/config_whitelist.txt | 1 + 6 files changed, 51 insertions(+), 5 deletions(-) -- 2.15.1

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[U-Boot] [PATCH 1/1] efi_loader: text output for device path end node
by Heinrich Schuchardt 14 Jan '18

14 Jan '18

Without the patch a device path consisting only of an end node is displayed as '/UNKNOWN(007f,00ff)'. It should be displayed as '/'. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- lib/efi_loader/efi_device_path_to_text.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/efi_loader/efi_device_path_to_text.c b/lib/efi_loader/efi_device_path_to_text.c index 40eae730ed..a79e60a4ee 100644 --- a/lib/efi_loader/efi_device_path_to_text.c +++ b/lib/efi_loader/efi_device_path_to_text.c @@ -245,6 +245,8 @@ static char *efi_convert_single_device_node_to_text( case DEVICE_PATH_TYPE_MEDIA_DEVICE: str = dp_media(str, dp); break; + case DEVICE_PATH_TYPE_END: + break; default: str = dp_unknown(str, dp); } -- 2.14.2

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[U-Boot] X86 Broadwell-DE override FSP configuration
by vnktux 14 Jan '18

14 Jan '18

Hi all, I managed to fully boot a bare metal U-Boot on the Intel Camelback Mountain CRB (Broadwell-DE). However I have a small problem, basically U-Boot does not override the FSP UPD data when the platform boot. For prototyping I am using a patched FSP binary I got in the company where I work. Now that it boot on the camelback mountain I need it to run on another platform (also broadwell-de) that has memory down installed on the motherboard. That should be easy, all I have to do is to enable memory down in the fsp_config.c file and provide the address of the SPD binary file. I have done that, but for some reason it doesn't work. During the booting process the platform give an error about the Dimm module not being supported. That make sense since the pached FSP binary I am using has memory down disabled. The part I don't understand is why U-Boot doesnt override the UPD settings specified in my fsp_config.c file. Below you will find my implementation, can somebody explain me what am I doing wrong? /* * Copyright (C) 2017, Vincenzo Bove < vincenzo.bove(a)prodrive-technologies.com > * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <fdtdec.h> #include <asm/fsp/fsp_support.h> #define CONFIG_FSP_MEMORY_DOWN 1 unsigned int px86a_c0_d0_spd[] = { 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x3a, 0x20, 0x32, 0x33, 0x20, 0x30, 0x30, 0x20, 0x30, 0x63, 0x20, 0x30, 0x33, 0x20, 0x38, 0x35, 0x20, .... }; unsigned int px86a_c0_d0_spd_len = 2400; DECLARE_GLOBAL_DATA_PTR; /** * Override the FSP's configuration data. * If the device tree does not specify an integer setting, use the default * provided by Prodrive BroadwellDE.rom */ void update_fsp_configs(struct fsp_config_data *config, struct fspinit_rtbuf *rt_buf) { struct upd_region *fsp_upd = &config->fsp_upd; const void *blob = gd->fdt_blob; int node; /* Initialize runtime buffer for fsp_init() */ rt_buf->common.stack_top = config->common.stack_top - 32; rt_buf->common.boot_mode = config->common.boot_mode; rt_buf->common.upd_data = &config->fsp_upd; node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BROADWELL_DE_FSP); if (node < 0) { debug("%s: Cannot find FSP node\n", __func__); return; } debug("%s: FSP node found!\n", __func__); fsp_upd->memEccSupport = fdtdec_get_int(blob, node, "fsp,memEccSupport", MEM_ECC_SUPPORT_AUTO); fsp_upd->memDdrMemoryType = fdtdec_get_int(blob, node, "fsp,memDdrMemoryType", MEM_DDR_MEMORY_TYPE_UDIMM_AND_RDIMM); fsp_upd->memRankMultiplication = fdtdec_get_int(blob, node, "fsp,memRankMultiplication", MEM_RANK_MULTIPLICATION_AUTO); fsp_upd->memRankMarginTool = fdtdec_get_int(blob, node, "fsp,memRankMarginTool", MEM_RANK_MARGIN_TOOL_AUTO); fsp_upd->memScrambling = fdtdec_get_int(blob, node, "fsp,memScrambling", MEM_SCRAMBLING_AUTO); fsp_upd->memRefreshMode = fdtdec_get_int(blob, node, "fsp,memRefreshMode", MEM_REFRESH_MODE_ACC_SELF_REFRESH); fsp_upd->memMcOdtOverride = fdtdec_get_int(blob, node, "fsp,memMcOdtOverride", MEM_MC0DT_OVERRIDE_AUTO); fsp_upd->memCAParity = fdtdec_get_int(blob, node, "fsp,memCAParity", MEM_CA_PARITY_AUTO); fsp_upd->memThermalThrottling = fdtdec_get_int(blob, node, "fsp,memThermalThrottling", MEM_THERMAL_THROTTLING_CLOSEDLOOP); fsp_upd->memPowerSavingsMode = fdtdec_get_int(blob, node, "fsp,memPowerSavingsMode", MEM_POWER_SAVINGS_MODE_AUTO); fsp_upd->memElectricalThrottling = fdtdec_get_int(blob, node, "fsp,memElectricalThrottling", MEM_ELECTRICAL_THROTTLING_DISABLED); fsp_upd->memPagePolicy = fdtdec_get_int(blob, node, "fsp,memPagePolicy", MEM_PAGE_POLICY_AUTO); fsp_upd->memSocketInterleaveBelow4G = fdtdec_get_int(blob, node, "fsp,memSocketInterleaveBelow4G", MEM_SOCKET_INTERLEAVE_BELOW_4G_DISABLED); fsp_upd->memChannelInterleave = fdtdec_get_int(blob, node, "fsp,memChannelInterleave", MEM_CHANNEL_INTERLEAVE_AUTO); fsp_upd->memRankInterleave = fdtdec_get_int(blob, node, "fsp,memRankInterleave", MEM_RANK_INTERLEAVE_AUTO); if(CONFIG_FSP_MEMORY_DOWN){ //memcpy ((int *)0xfffd0000, px86a_c0_d0_spd, sizeof (px86a_c0_d0_spd)); fsp_upd->memDownEnable = fdtdec_get_bool(blob, node, "fsp,memDownEnable"); fsp_upd->memDownCh0Dimm0SpdPtr = fdtdec_get_int(blob, node, "fsp,memDownCh0Dimm0SpdPtr", (int)px86a_c0_d0_spd); fsp_upd->memDownCh0Dimm1SpdPtr = fdtdec_get_int(blob, node, "fsp,memDownCh0Dimm1SpdPtr", 0x0); fsp_upd->memDownCh1Dimm0SpdPtr = fdtdec_get_int(blob, node, "fsp,memDownCh1Dimm0SpdPtr", 0x0); fsp_upd->memDownCh1Dimm1SpdPtr = fdtdec_get_int(blob, node, "fsp,memDownCh1Dimm1SpdPtr", 0x0); } #ifdef CONFIG_ENABLE_MRC_CACHE fsp_upd->memFastBoot = fdtdec_get_bool(blob, node, "fsp,mem-fast-boot"); #endif fsp_upd->pam0_hienable = fdtdec_get_int(blob, node, "fsp,pam0-hienable", PAM_RW_DRAM_ONLY); fsp_upd->pam1_loenable = fdtdec_get_int(blob, node, "fsp,pam1-loenable", PAM_RW_DRAM_ONLY); fsp_upd->pam1_hienable = fdtdec_get_int(blob, node, "fsp,pam1-hienable", PAM_RW_DRAM_ONLY); fsp_upd->pam2_loenable = fdtdec_get_int(blob, node, "fsp,pam2-loenable", PAM_RW_DRAM_ONLY); fsp_upd->pam2_hienable = fdtdec_get_int(blob, node, "fsp,pam2-hienable", PAM_RW_DRAM_ONLY); fsp_upd->pam3_loenable = fdtdec_get_int(blob, node, "fsp,pam3-loenable", PAM_RW_DRAM_ONLY); fsp_upd->pam3_hienable = fdtdec_get_int(blob, node, "fsp,pam3-hienable", PAM_RW_DRAM_ONLY); fsp_upd->pam4_loenable = fdtdec_get_int(blob, node, "fsp,pam4-loenable", PAM_RW_DRAM_ONLY); fsp_upd->pam4_hienable = fdtdec_get_int(blob, node, "fsp,pam4-hienable", PAM_RW_DRAM_ONLY); fsp_upd->pam5_loenable = fdtdec_get_int(blob, node, "fsp,pam5-loenable", PAM_RW_DRAM_ONLY); fsp_upd->pam5_hienable = fdtdec_get_int(blob, node, "fsp,pam5-hienable", PAM_RW_DRAM_ONLY); fsp_upd->pam6_loenable = fdtdec_get_int(blob, node, "fsp,pam6-loenable", PAM_RW_DRAM_ONLY); fsp_upd->pam6_hienable = fdtdec_get_int(blob, node, "fsp,pam6-hienable", PAM_RW_DRAM_ONLY); fsp_upd->memAdr = fdtdec_get_int(blob, node, "fsp,memAdr", MEM_ADR_DISABLED); fsp_upd->serialPortType = fdtdec_get_int(blob, node, "fsp,serial-port-type", SERIAL_PORT_TYPE_IO); fsp_upd->serialPortAddress = fdtdec_get_int(blob, node, "fsp,serial-port-address", 0x3f8); fsp_upd->serialPortConfigure = fdtdec_get_bool(blob, node, "fsp,serial-port-configure"); fsp_upd->serialPortBaudRate = fdtdec_get_int(blob, node, "fsp,serial-port-baudrate", SERIAL_PORT_BAUDRATE_115200); fsp_upd->serialPortControllerInit0 = fdtdec_get_bool(blob, node, "fsp,serial-port-controller-init0"); fsp_upd->serialPortControllerInit1 = fdtdec_get_bool(blob, node, "fsp,serial-port-controller-init1"); fsp_upd->configIOU1_PciPort3 = fdtdec_get_int(blob, node, "fsp,config-iou1-pci-port3", CONFIG_IOU1_PCI_PORT3_X4X4X4X4); fsp_upd->configIOU2_PciPort1 = fdtdec_get_int(blob, node, "fsp,config-iou2-pci-port1", CONFIG_IOU2_PCI_PORT1_XXX8); fsp_upd->pchPciPort1 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port1"); fsp_upd->pchPciPort2 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port2"); fsp_upd->pchPciPort3 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port3"); fsp_upd->pchPciPort4 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port4"); fsp_upd->pchPciPort5 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port5"); fsp_upd->pchPciPort6 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port6"); fsp_upd->pchPciPort7 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port7"); fsp_upd->pchPciPort8 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port8"); fsp_upd->ehci1Enable = fdtdec_get_bool(blob, node, "fsp,ehci1-enable"); fsp_upd->hyperThreading = fdtdec_get_bool(blob, node, "fsp,hyper-threading"); fsp_upd->debugOutputLevel = fdtdec_get_int(blob, node, "fsp,debug-output-level", DEBUG_OUTPUT_LEVEL_NORMAL); fsp_upd->tcoTimerHaltLock = fdtdec_get_bool(blob, node, "fsp,tco-timer-halt-lock"); fsp_upd->turboMode = fdtdec_get_bool(blob, node, "fsp,turbo-mode"); fsp_upd->bootPerfMode = fdtdec_get_bool(blob, node, "fsp,boot-perf-mode"); fsp_upd->pciePort1aAspm = fdtdec_get_int(blob, node, "fsp,pcie-port1a-aspm", PCIE_ASPM_DISABLED); fsp_upd->pciePort1bAspm = fdtdec_get_int(blob, node, "fsp,pcie-port1b-aspm", PCIE_ASPM_DISABLED); fsp_upd->pciePort3aAspm = fdtdec_get_int(blob, node, "fsp,pcie-port3a-aspm", PCIE_ASPM_DISABLED); fsp_upd->pciePort3bAspm = fdtdec_get_int(blob, node, "fsp,pcie-port3b-aspm", PCIE_ASPM_DISABLED); fsp_upd->pciePort3cAspm = fdtdec_get_int(blob, node, "fsp,pcie-port3c-aspm", PCIE_ASPM_DISABLED); fsp_upd->pciePort3dAspm = fdtdec_get_int(blob, node, "fsp,pcie-port3d-aspm", PCIE_ASPM_DISABLED); fsp_upd->pchPciePort1Aspm = fdtdec_get_int(blob, node, "fsp,pch-pcie-port1-aspm", PCH_PCI_ASPM_DISABLED); fsp_upd->pchPciePort2Aspm = fdtdec_get_int(blob, node, "fsp,pch-pcie-port2-aspm", PCH_PCI_ASPM_DISABLED); fsp_upd->pchPciePort3Aspm = fdtdec_get_int(blob, node, "fsp,pch-pcie-port3-aspm", PCH_PCI_ASPM_DISABLED); fsp_upd->pchPciePort4Aspm = fdtdec_get_int(blob, node, "fsp,pch-pcie-port4-aspm", PCH_PCI_ASPM_DISABLED); fsp_upd->pchPciePort5Aspm = fdtdec_get_int(blob, node, "fsp,pch-pcie-port5-aspm", PCH_PCI_ASPM_DISABLED); fsp_upd->pchPciePort6Aspm = fdtdec_get_int(blob, node, "fsp,pch-pcie-port6-aspm", PCH_PCI_ASPM_DISABLED); fsp_upd->pchPciePort7Aspm = fdtdec_get_int(blob, node, "fsp,pch-pcie-port7-aspm", PCH_PCI_ASPM_DISABLED); fsp_upd->pchPciePort8Aspm = fdtdec_get_int(blob, node, "fsp,pch-pcie-port8-aspm", PCH_PCI_ASPM_DISABLED); fsp_upd->thermalDeviceEnable = fdtdec_get_bool(blob, node, "fsp,thermal-device-enable"); Sent with [ProtonMail](https://protonmail.com) Secure Email.

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[U-Boot] [PATCH] mtd: zynq: nand: Move board_nand_init() function to board.c
by Wilson Lee 13 Jan '18

13 Jan '18

Putting board_nand_init() function inside NAND driver was not appropriate due to it doesn't allow board vendor to customise their NAND initialization code such as adding NAND lock/unlock code. This commit was to move the board_nand_init() function from NAND driver to board.c file. This allow customization of board_nand_init() function. Signed-off-by: Wilson Lee <wilson.lee(a)ni.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Keng Soon Cheah <keng.soon.cheah(a)ni.com> Cc: Chen Yee Chew <chen.yee.chew(a)ni.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Michal Simek <michal.simek(a)xilinx.com> Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Cc: Scott Wood <oss(a)buserror.net> --- arch/arm/mach-zynq/include/mach/nand.h | 9 +++++++++ board/xilinx/zynq/board.c | 10 ++++++++++ drivers/mtd/nand/zynq_nand.c | 12 +----------- 3 files changed, 20 insertions(+), 11 deletions(-) create mode 100644 arch/arm/mach-zynq/include/mach/nand.h diff --git a/arch/arm/mach-zynq/include/mach/nand.h b/arch/arm/mach-zynq/include/mach/nand.h new file mode 100644 index 0000000..61ef45f --- /dev/null +++ b/arch/arm/mach-zynq/include/mach/nand.h @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2017 National Instruments Corp. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <nand.h> + +void zynq_nand_init(void); diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 90ef542..8bcb830 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -9,6 +9,7 @@ #include <fpga.h> #include <mmc.h> #include <zynqpl.h> +#include <asm/arch/nand.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> @@ -156,3 +157,12 @@ int dram_init(void) return 0; } #endif + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; +void board_nand_init(void) +{ + struct nand_chip *nand = &nand_chip[0]; + + if (zynq_nand_init(nand, 0)) + puts("ZYNQ NAND init failed\n"); +} diff --git a/drivers/mtd/nand/zynq_nand.c b/drivers/mtd/nand/zynq_nand.c index dec2c41..9be6856 100644 --- a/drivers/mtd/nand/zynq_nand.c +++ b/drivers/mtd/nand/zynq_nand.c @@ -1006,7 +1006,7 @@ static int zynq_nand_device_ready(struct mtd_info *mtd) return 0; } -static int zynq_nand_init(struct nand_chip *nand_chip, int devnum) +int zynq_nand_init(struct nand_chip *nand_chip, int devnum) { struct zynq_nand_info *xnand; struct mtd_info *mtd; @@ -1191,13 +1191,3 @@ fail: free(xnand); return err; } - -static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; - -void board_nand_init(void) -{ - struct nand_chip *nand = &nand_chip[0]; - - if (zynq_nand_init(nand, 0)) - puts("ZYNQ NAND init failed\n"); -} -- 2.7.4

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