January 2018 - U-Boot

[U-Boot] UDP packet sender
by Gaëtan Carlier 06 Feb '18

06 Feb '18

Hi, I would like to implement a new command and submit it to the mailing list. The command will have the following format: udpsend <destination/broadcast ip> <destination port> <source port> <text to send> udpsend 255.255.255.255 4040 0 hello world If source port is 0, a random port will be used (11000 + (get_timer(0) % 4096)) Where do I have to place my code : cmd or net directory ? For me cmd will be the better directory to keep it away from all more complex stuff like DHCP, TFTP, ... Thank you for these informations. Regards, Gaëtan.

3 8

[U-Boot] [PATCH] arm64 :show_regs: show the address before relocation
by Peng Fan 06 Feb '18

06 Feb '18

After relocation, when error happends, it is hard to track ELR and LR with asm file objdumped from elf file. So subtract the gd->reloc_off the reflect the compliation address. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- arch/arm/lib/interrupts_64.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/lib/interrupts_64.c b/arch/arm/lib/interrupts_64.c index 7c9cfce69f..cbcfeec2b0 100644 --- a/arch/arm/lib/interrupts_64.c +++ b/arch/arm/lib/interrupts_64.c @@ -9,6 +9,7 @@ #include <linux/compiler.h> #include <efi_loader.h> +DECLARE_GLOBAL_DATA_PTR; int interrupt_init(void) { @@ -29,8 +30,13 @@ void show_regs(struct pt_regs *regs) { int i; - printf("ELR: %lx\n", regs->elr); - printf("LR: %lx\n", regs->regs[30]); + if (gd->flags & GD_FLG_RELOC) { + printf("ELR: %lx\n", regs->elr - gd->reloc_off); + printf("LR: %lx\n", regs->regs[30] - gd->reloc_off); + } else { + printf("ELR: %lx\n", regs->elr); + printf("LR: %lx\n", regs->regs[30]); + } for (i = 0; i < 29; i += 2) printf("x%-2d: %016lx x%-2d: %016lx\n", i, regs->regs[i], i+1, regs->regs[i+1]); -- 2.14.1

4 6

[U-Boot] [PATCH] usb: ulpi: kconfig: Remove meaningless choice default
by Ulf Magnusson 06 Feb '18

06 Feb '18

'default' on a choice refers to the symbol selected by default, not to the choice mode, so 'default n' is meaningless. No functional changes. Optional choices implicitly default to n mode (and there is no way to make them default to another mode). Discovered in Kconfiglib (https://github.com/ulfalizer/Kconfiglib), which prints the following warning: warning: the default selection n (undefined) of <choice> (defined at drivers/usb/ulpi/Kconfig:3) is not contained in the choice I've added a corresponding warning to the C tools too, which is currently in linux-next: https://patchwork.kernel.org/patch/9983667/ Signed-off-by: Ulf Magnusson <ulfalizer(a)gmail.com> --- drivers/usb/ulpi/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/usb/ulpi/Kconfig b/drivers/usb/ulpi/Kconfig index 329d2df3ed..001564d40c 100644 --- a/drivers/usb/ulpi/Kconfig +++ b/drivers/usb/ulpi/Kconfig @@ -3,7 +3,6 @@ comment "ULPI drivers" choice prompt "ULPI Viewport type" optional - default n help Select ULPI viewport (SoC-side interface to ULPI) implementation appropriate for the device if you want to communicate with -- 2.14.1

2 1

[U-Boot] [PATCH] am335x, shc: kconfig: Fix misspelled choice default
by Ulf Magnusson 06 Feb '18

06 Feb '18

There is no EMMC symbol in the "enable different boot versions for the shc board" choice. SHC_EMMC was probably intended. No functional changes. Kconfig choices fall back on using the first (visible) symbol in the choice as the default if the default symbol is not visible. Discovered in Kconfiglib (https://github.com/ulfalizer/Kconfiglib), which prints the following warning: warning: the default selection EMMC (undefined) of <choice> (defined at board/bosch/shc/Kconfig:15) is not contained in the choice I've added a corresponding warning to the C tools too, which is currently in linux-next: https://patchwork.kernel.org/patch/9983667/ Signed-off-by: Ulf Magnusson <ulfalizer(a)gmail.com> --- board/bosch/shc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/bosch/shc/Kconfig b/board/bosch/shc/Kconfig index c71af11c1c..e0e56e6bfd 100644 --- a/board/bosch/shc/Kconfig +++ b/board/bosch/shc/Kconfig @@ -14,7 +14,7 @@ config SYS_CONFIG_NAME choice prompt "enable different boot versions for the shc board" - default EMMC + default SHC_EMMC help Select the boot version of the shc board. -- 2.14.1

2 1

[U-Boot] [PATCH] Fix FreeBSD endian checks
by Justin Hibbits 06 Feb '18

06 Feb '18

FreeBSD, like OpenBSD, uses BIG_ENDIAN, LITTLE_ENDIAN, and BYTE_ORDER, whereas Linux and compatibles use __-prefixed names. Define the names the same as the OpenBSD block below it. --- include/compiler.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/compiler.h b/include/compiler.h index a43fb6a738..957f4b5d49 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -50,6 +50,9 @@ typedef unsigned long ulong; #endif #ifdef __FreeBSD__ # include <sys/endian.h> /* htole32 and friends */ +# define __BYTE_ORDER BYTE_ORDER +# define __LITTLE_ENDIAN LITTLE_ENDIAN +# define __BIG_ENDIAN BIG_ENDIAN #elif defined(__OpenBSD__) # include <endian.h> # define __BYTE_ORDER BYTE_ORDER -- 2.15.1

2 1

[U-Boot] [PATCH 1/2] fpga: Resync various CONFIG_FPGA_* symbols
by Tuomas Tynkkynen 06 Feb '18

06 Feb '18

These are declared in Kconfig, but some #defines have crept in. CONFIG_FPGA CONFIG_FPGA_ALTERA CONFIG_FPGA_CYCLON2 CONFIG_FPGA_SOCFPGA CONFIG_FPGA_XILINX CONFIG_FPGA_ZYNQMPPL Signed-off-by: Tuomas Tynkkynen <tuomas(a)tuxera.com> --- configs/apf27_defconfig | 1 + configs/astro_mcf5373l_defconfig | 2 ++ configs/mt_ventoux_defconfig | 1 + configs/x600_defconfig | 1 + include/configs/M54455EVB.h | 1 - include/configs/apf27.h | 4 ---- include/configs/astro_mcf5373l.h | 2 -- include/configs/mt_ventoux.h | 2 -- include/configs/x600.h | 2 -- 9 files changed, 5 insertions(+), 11 deletions(-) diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig index f09c5a828b..6949b711fd 100644 --- a/configs/apf27_defconfig +++ b/configs/apf27_defconfig @@ -31,6 +31,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand.0:1M(u-boot)ro,512K(env),512K(env2),512K(firmware),512K(dtb),5M(kernel),-(rootfs)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_FPGA_XILINX=y CONFIG_MMC_MXC=y CONFIG_NAND=y CONFIG_NAND_MXC=y diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig index cababcf990..1e3708fcb5 100644 --- a/configs/astro_mcf5373l_defconfig +++ b/configs/astro_mcf5373l_defconfig @@ -16,4 +16,6 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_CMD_JFFS2=y CONFIG_FPGA_ALTERA=y +CONFIG_FPGA_CYCLON2=y +CONFIG_FPGA_XILINX=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig index 3dd8adb5ce..c059a49576 100644 --- a/configs/mt_ventoux_defconfig +++ b/configs/mt_ventoux_defconfig @@ -31,6 +31,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1m(u-boot),256k(env1),256k(env2),8m(ubisystem),-(rootfs)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_FPGA_XILINX=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/x600_defconfig b/configs/x600_defconfig index 4658f977a4..18720daafc 100644 --- a/configs/x600_defconfig +++ b/configs/x600_defconfig @@ -37,6 +37,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:64M(ubi0),64M(ubi1)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_FLASH=y +CONFIG_FPGA_XILINX=y CONFIG_SYS_I2C_DW=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index a709fbbf63..c5a0a0371d 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -182,7 +182,6 @@ /* FPGA - Spartan 2 */ /* experiment -#define CONFIG_FPGA #define CONFIG_FPGA_COUNT 1 #define CONFIG_SYS_FPGA_PROG_FEEDBACK #define CONFIG_SYS_FPGA_CHECK_CTRLC diff --git a/include/configs/apf27.h b/include/configs/apf27.h index 24afc84a02..16345ca2b5 100644 --- a/include/configs/apf27.h +++ b/include/configs/apf27.h @@ -215,11 +215,7 @@ /* * FPGA */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_FPGA -#endif #define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA_XILINX #define CONFIG_FPGA_SPARTAN3 #define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */ #define CONFIG_SYS_FPGA_PROG_FEEDBACK diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 540db79a27..c8d5c1bd3d 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -177,9 +177,7 @@ #define CONFIG_SYS_LONGHELP #define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA_XILINX #define CONFIG_FPGA_SPARTAN3 -#define CONFIG_FPGA_CYCLON2 #define CONFIG_SYS_FPGA_PROG_FEEDBACK #define CONFIG_SYS_FPGA_WAIT 1000 diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h index 11ba3e752a..bee8ddd4f2 100644 --- a/include/configs/mt_ventoux.h +++ b/include/configs/mt_ventoux.h @@ -33,8 +33,6 @@ /* * FPGA */ -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX #define CONFIG_FPGA_SPARTAN3 #define CONFIG_SYS_FPGA_PROG_FEEDBACK #define CONFIG_SYS_FPGA_WAIT 10000 diff --git a/include/configs/x600.h b/include/configs/x600.h index 4aa5a2a924..cd3bd94efb 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -87,8 +87,6 @@ #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* FPGA config options */ -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX #define CONFIG_FPGA_SPARTAN3 #define CONFIG_FPGA_COUNT 1 -- 2.16.1

2 3

[U-Boot] [PATCH v2 0/4] Add support for treating compiler warnings as errors
by Daniel Schwierzeck 05 Feb '18

05 Feb '18

To enforce a zero-warnings policy (e.g. in CI builds), all compiler warnings have to be treated as errors. Extend Kbuild and buildman with according options to achieve this. Enable these new options in all Travis CI builds. All builds with compiler warnings will now fail. Only DTC warnings are still being ignored. Example build which failed due to a compiler warning: https://travis-ci.org/danielschwierzeck/u-boot/jobs/333349371#L936 The patch which fixes the warning above: https://patchwork.ozlabs.org/patch/866009/ Changes in v2: - new patch - replace 'W=err' with 'KCFLAGS=-Werror' Daniel Schwierzeck (4): README: add doc for how to supply user specific compiler flags to Kbuild buildman: add option -E for treating compiler warnings as errors travis.yml: fix 'set +e' in build script travis.yml: run buildman with option -E .travis.yml | 5 ++--- README | 5 +++++ tools/buildman/builder.py | 5 ++++- tools/buildman/builderthread.py | 2 ++ tools/buildman/cmdline.py | 2 ++ tools/buildman/control.py | 3 ++- 6 files changed, 17 insertions(+), 5 deletions(-) -- 2.16.1

2 9

[U-Boot] [PATCH 1/1] Broadwell-DE Implementation
by vnktux 05 Feb '18

05 Feb '18

Hi all, This patch contain a working implementation of Broadwell-DE for U-Boot, and support memory down with external SPD binary file. However there is only one issue that I couldn't solve, the booting process takes 1 hour. When the FSP reach "DDRIO Initialization" it take a lot before the memory is initialized and you can reach the U-Boot shell. I would like a review of my implementation since I am out of options. I tried to Enable/Disable MRC Cache and ACPI Resume but the problem is still there. Best regards, Vincenzo Bove Signed-off-by: Vincenzo Bove <vnktux(a)protonmail.com> --- arch/x86/Kconfig | 29 + arch/x86/cpu/Makefile | 1 + arch/x86/cpu/broadwell-de/Kconfig | 70 + arch/x86/cpu/broadwell-de/Makefile | 10 + arch/x86/cpu/broadwell-de/acpi.c | 234 +++ arch/x86/cpu/broadwell-de/broadwell_de.c | 38 + arch/x86/cpu/broadwell-de/cpu.c | 98 + arch/x86/cpu/broadwell-de/fsp_configs.c | 292 +++ arch/x86/dts/Makefile | 1 + arch/x86/dts/poseidon.dts | 210 ++ arch/x86/dts/u-boot.dtsi | 6 + .../asm/arch-broadwell-de/acpi/global_nvs.asl | 15 + .../asm/arch-broadwell-de/acpi/irq_helper.h | 36 + .../asm/arch-broadwell-de/acpi/irqlinks.asl | 454 +++++ .../asm/arch-broadwell-de/acpi/irqroute.asl | 29 + .../include/asm/arch-broadwell-de/acpi/irqroute.h | 31 + .../x86/include/asm/arch-broadwell-de/acpi/lpc.asl | 81 + .../include/asm/arch-broadwell-de/acpi/pcie1.asl | 455 +++++ .../asm/arch-broadwell-de/acpi/platform.asl | 61 + .../asm/arch-broadwell-de/acpi/southcluster.asl | 339 ++++ arch/x86/include/asm/arch-broadwell-de/device.h | 116 ++ .../asm/arch-broadwell-de/fsp/fsp_configs.h | 134 ++ .../include/asm/arch-broadwell-de/fsp/fsp_vpd.h | 116 ++ .../x86/include/asm/arch-broadwell-de/global_nvs.h | 21 + arch/x86/include/asm/arch-broadwell-de/iomap.h | 58 + arch/x86/include/asm/arch-broadwell-de/irq.h | 88 + board/prodrive/Kconfig | 23 + board/prodrive/poseidon/.gitignore | 5 + board/prodrive/poseidon/Kconfig | 45 + board/prodrive/poseidon/MAINTAINERS | 6 + board/prodrive/poseidon/Makefile | 8 + board/prodrive/poseidon/acpi/mainboard.asl | 11 + board/prodrive/poseidon/dsdt.asl | 187 ++ board/prodrive/poseidon/poseidon.c | 18 + configs/poseidon_defconfig | 70 + include/configs/poseidon.h | 29 + include/configs/x86-common.h | 17 +- include/fdtdec.h | 1 + lib/fdtdec.c | 1 + tools/binman/etype/intel_spd.py | 14 + 49 files changed, 10260 insertions(+), 1 deletion(-) create mode 100644 arch/x86/cpu/broadwell-de/Kconfig create mode 100644 arch/x86/cpu/broadwell-de/Makefile create mode 100644 arch/x86/cpu/broadwell-de/acpi.c create mode 100644 arch/x86/cpu/broadwell-de/broadwell_de.c create mode 100644 arch/x86/cpu/broadwell-de/cpu.c create mode 100644 arch/x86/cpu/broadwell-de/fsp_configs.c create mode 100644 arch/x86/dts/poseidon.dts create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/global_nvs.asl create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/irq_helper.h create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/irqlinks.asl create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.asl create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.h create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/lpc.asl create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/pcie1.asl create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/platform.asl create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/southcluster.asl create mode 100644 arch/x86/include/asm/arch-broadwell-de/device.h create mode 100644 arch/x86/include/asm/arch-broadwell-de/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-broadwell-de/fsp/fsp_vpd.h create mode 100644 arch/x86/include/asm/arch-broadwell-de/global_nvs.h create mode 100644 arch/x86/include/asm/arch-broadwell-de/iomap.h create mode 100644 arch/x86/include/asm/arch-broadwell-de/irq.h create mode 100644 board/prodrive/Kconfig create mode 100644 board/prodrive/poseidon/.gitignore create mode 100644 board/prodrive/poseidon/Kconfig create mode 100644 board/prodrive/poseidon/MAINTAINERS create mode 100644 board/prodrive/poseidon/Makefile create mode 100644 board/prodrive/poseidon/acpi/mainboard.asl create mode 100644 board/prodrive/poseidon/dsdt.asl create mode 100644 board/prodrive/poseidon/poseidon.c create mode 100644 configs/poseidon_defconfig create mode 100644 include/configs/poseidon.h create mode 100644 tools/binman/etype/intel_spd.py diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 5c23b2c..57fdcd7 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -78,6 +78,9 @@ config VENDOR_GOOGLE config VENDOR_INTEL bool "Intel" +config VENDOR_PRODRIVE + bool "Prodrive" + endchoice # subarchitectures-specific options below @@ -105,11 +108,13 @@ source "board/efi/Kconfig" source "board/emulation/Kconfig" source "board/google/Kconfig" source "board/intel/Kconfig" +source "board/prodrive/Kconfig" # platform-specific options below source "arch/x86/cpu/baytrail/Kconfig" source "arch/x86/cpu/braswell/Kconfig" source "arch/x86/cpu/broadwell/Kconfig" +source "arch/x86/cpu/broadwell-de/Kconfig" source "arch/x86/cpu/coreboot/Kconfig" source "arch/x86/cpu/ivybridge/Kconfig" source "arch/x86/cpu/qemu/Kconfig" @@ -766,6 +771,30 @@ config HIGH_TABLE_SIZE Increse it if the default size does not fit the board's needs. This is most likely due to a large ACPI DSDT table is used. +config FSP_MEMORY_DOWN + bool "Platform has memory down" + help + Select this option if your platform has memory soldered on the motherboard and FSP need SPD file. + +config HAVE_SPD + bool "Add SPD file" + help + Select this option if you have a SPD binary file for your memorydown. + +config SPD_FILE + string "SPD image filename" + depends on HAVE_SPD + default "spd_ch0_dimm0.bin" + help + The filename of the ram SPD binary. + +config SPD_ADDR + hex "SPD image location" + depends on HAVE_SPD + default 0xffcb0000 + help + The location of the SPD binary file. + source "arch/x86/lib/efi/Kconfig" endmenu diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 94cdff1..1fb1c40 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -29,6 +29,7 @@ obj-y += intel_common/ obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/ obj-$(CONFIG_INTEL_BRASWELL) += braswell/ obj-$(CONFIG_INTEL_BROADWELL) += broadwell/ +obj-$(CONFIG_INTEL_BROADWELL_DE) += broadwell-de/ obj-$(CONFIG_SYS_COREBOOT) += coreboot/ obj-$(CONFIG_EFI_APP) += efi/ obj-$(CONFIG_QEMU) += qemu/ diff --git a/arch/x86/cpu/broadwell-de/Kconfig b/arch/x86/cpu/broadwell-de/Kconfig new file mode 100644 index 0000000..a42821d --- /dev/null +++ b/arch/x86/cpu/broadwell-de/Kconfig @@ -0,0 +1,70 @@ +# +# Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +config INTEL_BROADWELL_DE + bool + select HAVE_FSP + select ARCH_MISC_INIT + select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED + imply HAVE_INTEL_ME + imply ENABLE_MRC_CACHE + imply AHCI_PCI + imply ICH_SPI + imply INTEL_ICH6_GPIO + imply SCSI + imply SPI_FLASH + imply SYS_NS16550 + imply USB + imply USB_EHCI_HCD + imply USB_XHCI_HCD + #imply VIDEO_VESA + +if INTEL_BROADWELL_DE + +config FSP_ADDR + hex + default 0xffeb0000 + +config FSP_BROKEN_HOB + bool + default y + +#config DCACHE_RAM_BASE +# default 0xfef00000 + +#config DCACHE_RAM_SIZE +# default 0x4000 + +config CPU_SPECIFIC_OPTIONS + def_bool y + select SMM_TSEG + #select X86_RAMTEST + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config INTERNAL_UART + bool + default y + +config MAX_CPUS + int + default 16 + +config MAX_PIRQ_LINKS + int + default 4 + +config IRQ_SLOT_COUNT + int + default 18 + +config XIP_ROM_SIZE + hex + default 0x10000 + +endif diff --git a/arch/x86/cpu/broadwell-de/Makefile b/arch/x86/cpu/broadwell-de/Makefile new file mode 100644 index 0000000..0fa427e --- /dev/null +++ b/arch/x86/cpu/broadwell-de/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpu.o +obj-y += fsp_configs.o +obj-y += broadwell_de.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o diff --git a/arch/x86/cpu/broadwell-de/acpi.c b/arch/x86/cpu/broadwell-de/acpi.c new file mode 100644 index 0000000..2e00562 --- /dev/null +++ b/arch/x86/cpu/broadwell-de/acpi.c @@ -0,0 +1,234 @@ +/* + * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <cpu.h> +#include <dm.h> +#include <dm/uclass-internal.h> +#include <asm/acpi_s3.h> +#include <asm/acpi_table.h> +#include <asm/io.h> +#include <asm/tables.h> +#include <asm/arch/global_nvs.h> +#include <asm/arch/iomap.h> + +#define PM1_STS 0x00 +#define PM1_CNT 0x04 +#define GEN_PMCON1 0xA0 +#define WAK_STS (1 << 15) +#define PWR_FLR (1 << 1) +#define SUS_PWR_FLR (1 << 14) + +#define PMC_BASE_ADDRESS 0xfed03000 +#define PMC_BASE_SIZE 0x400 + +void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, + void *dsdt) +{ + struct acpi_table_header *header = &(fadt->header); + u16 pmbase = ACPI_BASE_ADDRESS; + + memset((void *)fadt, 0, sizeof(struct acpi_fadt)); + + /* + * Reference section 5.2.9 Fixed ACPI Description Table (FADT) + * in the ACPI 3.0b specification. + */ + + /* FADT Header Structure */ + acpi_fill_header(header, "FACP"); + header->length = sizeof(struct acpi_fadt); + header->revision = 4; + + /* ACPI Pointers */ + fadt->firmware_ctrl = (u32)facs; + fadt->dsdt = (u32)dsdt; + + fadt->preferred_pm_profile = ACPI_PM_MOBILE; + fadt->sci_int = 9; + + /* System Management */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0; + fadt->acpi_disable = 0; + + /* Power Control */ + fadt->s4bios_req = 0; + fadt->pstate_cnt = 0; + + /* Control Registers - Base Address */ + fadt->pm1a_evt_blk = pmbase + 0x00; //PM1_STS + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x04; //PM1_CNT + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; //PM2A_CNT_BLK + fadt->pm_tmr_blk = pmbase + 0x8; //PM1_TMR + fadt->gpe0_blk = pmbase + 0x20; //GPE0_STS + fadt->gpe1_blk = 0; + + /* Control Registers - Length */ + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 0; + + /* RTC Registers */ + fadt->day_alrm = 0x0d; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PLATFORM_CLOCK; + + /* Reset Register */ + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = IO_PORT_RESET; + fadt->reset_reg.addrh = 0; + fadt->reset_value = 6; //SYS_RST | RST_CPU | FULL_RST + + /* Extended ACPI Pointers */ + fadt->x_firmware_ctl_l = (u32)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32)dsdt; + fadt->x_dsdt_h = 0; + + /* PM1 Status & PM1 Enable */ + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + /* PM1 Control Registers */ + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + /* PM2 Control Registers */ + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + /* PM1 Timer Register */ + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x0; + + /* General-Purpose Event Registers */ + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = table_compute_checksum(fadt, header->length); +} + +void acpi_create_gnvs(struct acpi_global_nvs *gnvs) +{ + struct udevice *dev; + int ret; + + /* at least we have one processor */ + gnvs->pcnt = 1; + /* override the processor count with actual number */ + ret = uclass_find_first_device(UCLASS_CPU, &dev); + if (ret == 0 && dev != NULL) { + ret = cpu_get_count(dev); + if (ret > 0) + gnvs->pcnt = ret; + } + + /* determine whether internal uart is on */ + if (IS_ENABLED(CONFIG_INTERNAL_UART)) + gnvs->iuart_en = 1; + else + gnvs->iuart_en = 0; +} + +#ifdef CONFIG_HAVE_ACPI_RESUME + +enum acpi_sleep_state chipset_prev_sleep_state(void) +{ + u32 pm1_sts; + u32 pm1_cnt; + u32 gen_pmcon1; + enum acpi_sleep_state prev_sleep_state = ACPI_S0; + + /* Read Power State */ + pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + gen_pmcon1 = readl(PMC_BASE_ADDRESS + GEN_PMCON1); + + debug("PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n", + pm1_sts, pm1_cnt, gen_pmcon1); + + if (pm1_sts & WAK_STS) + prev_sleep_state = acpi_sleep_from_pm1(pm1_cnt); + + if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) + prev_sleep_state = ACPI_S5; + + return prev_sleep_state; +} + +void chipset_clear_sleep_state(void) +{ + u32 pm1_cnt; + + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); +} + +#endif diff --git a/arch/x86/cpu/broadwell-de/broadwell_de.c b/arch/x86/cpu/broadwell-de/broadwell_de.c new file mode 100644 index 0000000..54afde7 --- /dev/null +++ b/arch/x86/cpu/broadwell-de/broadwell_de.c @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/mrccache.h> +#include <asm/post.h> + +int arch_cpu_init(void) +{ + post_code(POST_CPU_INIT); + + return x86_cpu_init_f(); +} + +int arch_misc_init(void) +{ +#ifdef CONFIG_ENABLE_MRC_CACHE + /* + * We intend not to check any return value here, as even MRC cache + * is not saved successfully, it is not a severe error that will + * prevent system from continuing to boot. + */ + mrccache_save(); +#endif + + return 0; +} + + + +void reset_cpu(ulong addr) +{ + /* cold reset */ + x86_full_reset(); +} diff --git a/arch/x86/cpu/broadwell-de/cpu.c b/arch/x86/cpu/broadwell-de/cpu.c new file mode 100644 index 0000000..71377fa --- /dev/null +++ b/arch/x86/cpu/broadwell-de/cpu.c @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <cpu.h> +#include <pci.h> +#include <asm/cpu.h> +#include <asm/cpu_x86.h> +#include <asm/cpu_common.h> +#include <asm/intel_regs.h> +#include <asm/io.h> +#include <asm/msr.h> +#include <asm/post.h> +#include <asm/turbo.h> +#include <asm/mrccache.h> +#include <asm/lapic.h> + +#define MSR_CORE_THREAD_COUNT 0x35 + +static void configure_mca(void) +{ + msr_t msr; + const unsigned int mcg_cap_msr = 0x179; + int i; + int num_banks; + + msr = msr_read(mcg_cap_msr); + num_banks = msr.lo & 0xff; + msr.lo = 0; + msr.hi = 0; + /* + * TODO(adurbin): This should only be done on a cold boot. Also, some + * of these banks are core vs package scope. For now every CPU clears + * every bank + */ + for (i = 0; i < num_banks; i++) { + msr_write(MSR_IA32_MC0_STATUS + (i * 4) + 1, msr); + msr_write(MSR_IA32_MC0_STATUS + (i * 4) + 2, msr); + msr_write(MSR_IA32_MC0_STATUS + (i * 4) + 3, msr); + + } + + msr.lo = 0xffffffff; + msr.hi = 0xffffffff; + + for (i = 0; i < num_banks; i++) { + msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr); + } +} + +static int cpu_x86_broadwell_de_probe(struct udevice *dev) +{ + debug("Init Broadwell-DE core\n"); + + /* Clear out pending MCEs */ + configure_mca(); + + return 0; +} + + +static int broadwell_de_get_info(struct udevice *dev, struct cpu_info *info) +{ + //TBD + + return 0; +} + +static int broadwell_de_get_count(struct udevice *dev) +{ + msr_t core_thread_count = msr_read(MSR_CORE_THREAD_COUNT); + return core_thread_count.lo & 0xffff; +} + +static const struct cpu_ops cpu_x86_broadwell_de_ops = { + .get_desc = cpu_x86_get_desc, + .get_info = broadwell_de_get_info, + .get_count = broadwell_de_get_count, + .get_vendor = cpu_x86_get_vendor, +}; + +static const struct udevice_id cpu_x86_broadwell_de_ids[] = { + { .compatible = "intel,broadwell-de-cpu" }, + { } +}; + +U_BOOT_DRIVER(cpu_x86_broadwell_de_drv) = { + .name = "cpu_x86_broadwell_de", + .id = UCLASS_CPU, + .of_match = cpu_x86_broadwell_de_ids, + .bind = cpu_x86_bind, + .probe = cpu_x86_broadwell_de_probe, + .ops = &cpu_x86_broadwell_de_ops, +}; diff --git a/arch/x86/cpu/broadwell-de/fsp_configs.c b/arch/x86/cpu/broadwell-de/fsp_configs.c new file mode 100644 index 0000000..b2ccbdb --- /dev/null +++ b/arch/x86/cpu/broadwell-de/fsp_configs.c @@ -0,0 +1,292 @@ +/* + * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <asm/fsp/fsp_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +/** + * Override the FSP's configuration data. + * If the device tree does not specify an integer setting, use the default + * provided by Prodrive BroadwellDE.rom + */ +void update_fsp_configs(struct fsp_config_data *config, + struct fspinit_rtbuf *rt_buf) +{ + struct upd_region *fsp_upd = &config->fsp_upd; + const void *blob = gd->fdt_blob; + int node; + + /* Initialize runtime buffer for fsp_init() */ + rt_buf->common.stack_top = config->common.stack_top - 32; + rt_buf->common.boot_mode = config->common.boot_mode; + rt_buf->common.upd_data = &config->fsp_upd; + + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BROADWELL_DE_FSP); + if (node < 0) { + debug("%s: Cannot find FSP node\n", __func__); + return; + } + + fsp_upd->memEccSupport = fdtdec_get_int(blob, node, + "fsp,memEccSupport", + MEM_ECC_SUPPORT_AUTO); + + fsp_upd->memDdrMemoryType = fdtdec_get_int(blob, node, + "fsp,memDdrMemoryType", + MEM_DDR_MEMORY_TYPE_UDIMM_AND_RDIMM); + + fsp_upd->memRankMultiplication = fdtdec_get_int(blob, node, + "fsp,memRankMultiplication", + MEM_RANK_MULTIPLICATION_AUTO); + + fsp_upd->memRankMarginTool = fdtdec_get_int(blob, node, + "fsp,memRankMarginTool", + MEM_RANK_MARGIN_TOOL_AUTO); + + fsp_upd->memScrambling = fdtdec_get_int(blob, node, + "fsp,memScrambling", + MEM_SCRAMBLING_AUTO); + + fsp_upd->memRefreshMode = fdtdec_get_int(blob, node, + "fsp,memRefreshMode", + MEM_REFRESH_MODE_ACC_SELF_REFRESH); + + fsp_upd->memMcOdtOverride = fdtdec_get_int(blob, node, + "fsp,memMcOdtOverride", + MEM_MC0DT_OVERRIDE_AUTO); + + fsp_upd->memCAParity = fdtdec_get_int(blob, node, + "fsp,memCAParity", + MEM_CA_PARITY_AUTO); + + fsp_upd->memThermalThrottling = fdtdec_get_int(blob, node, + "fsp,memThermalThrottling", + MEM_THERMAL_THROTTLING_CLOSEDLOOP); + + fsp_upd->memPowerSavingsMode = fdtdec_get_int(blob, node, + "fsp,memPowerSavingsMode", + MEM_POWER_SAVINGS_MODE_AUTO); + + fsp_upd->memElectricalThrottling = fdtdec_get_int(blob, node, + "fsp,memElectricalThrottling", + MEM_ELECTRICAL_THROTTLING_DISABLED); + + fsp_upd->memPagePolicy = fdtdec_get_int(blob, node, + "fsp,memPagePolicy", + MEM_PAGE_POLICY_AUTO); + + fsp_upd->memSocketInterleaveBelow4G = fdtdec_get_int(blob, node, + "fsp,memSocketInterleaveBelow4G", + MEM_SOCKET_INTERLEAVE_BELOW_4G_DISABLED); + + fsp_upd->memChannelInterleave = fdtdec_get_int(blob, node, + "fsp,memChannelInterleave", + MEM_CHANNEL_INTERLEAVE_AUTO); + + fsp_upd->memRankInterleave = fdtdec_get_int(blob, node, + "fsp,memRankInterleave", + MEM_RANK_INTERLEAVE_AUTO); + + #ifdef CONFIG_FSP_MEMORY_DOWN + fsp_upd->memDownEnable = fdtdec_get_bool(blob, node, "fsp,memDownEnable"); + + fsp_upd->memDownCh0Dimm0SpdPtr = fdtdec_get_int(blob, node, + "fsp,memDownCh0Dimm0SpdPtr", + CONFIG_SPD_ADDR); + + fsp_upd->memDownCh0Dimm1SpdPtr = fdtdec_get_int(blob, node, + "fsp,memDownCh0Dimm1SpdPtr", + 0x0); + + fsp_upd->memDownCh1Dimm0SpdPtr = fdtdec_get_int(blob, node, + "fsp,memDownCh1Dimm0SpdPtr", + 0x0); + + fsp_upd->memDownCh1Dimm1SpdPtr = fdtdec_get_int(blob, node, + "fsp,memDownCh1Dimm1SpdPtr", + 0x0); + #endif + + //#ifdef CONFIG_ENABLE_MRC_CACHE + //fsp_upd->memFastBoot = fdtdec_get_int(blob, node, "fsp,mem-fast-boot", MEM_FAST_BOOT_ENABLE); + //#else + //fsp_upd->memFastBoot = fdtdec_get_int(blob, node, "fsp,mem-fast-boot", MEM_FAST_BOOT_DISABLE); + //#endif + fsp_upd->memFastBoot = fdtdec_get_int(blob, node, "fsp,mem-fast-boot", MEM_FAST_BOOT_DISABLE); + + fsp_upd->pam0_hienable = fdtdec_get_int(blob, node, + "fsp,pam0-hienable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam1_loenable = fdtdec_get_int(blob, node, + "fsp,pam1-loenable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam1_hienable = fdtdec_get_int(blob, node, + "fsp,pam1-hienable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam2_loenable = fdtdec_get_int(blob, node, + "fsp,pam2-loenable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam2_hienable = fdtdec_get_int(blob, node, + "fsp,pam2-hienable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam3_loenable = fdtdec_get_int(blob, node, + "fsp,pam3-loenable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam3_hienable = fdtdec_get_int(blob, node, + "fsp,pam3-hienable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam4_loenable = fdtdec_get_int(blob, node, + "fsp,pam4-loenable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam4_hienable = fdtdec_get_int(blob, node, + "fsp,pam4-hienable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam5_loenable = fdtdec_get_int(blob, node, + "fsp,pam5-loenable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam5_hienable = fdtdec_get_int(blob, node, + "fsp,pam5-hienable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam6_loenable = fdtdec_get_int(blob, node, + "fsp,pam6-loenable", + PAM_RW_DRAM_ONLY); + + fsp_upd->pam6_hienable = fdtdec_get_int(blob, node, + "fsp,pam6-hienable", + PAM_RW_DRAM_ONLY); + + fsp_upd->memAdr = fdtdec_get_int(blob, node, + "fsp,memAdr", + MEM_ADR_DISABLED); + + fsp_upd->serialPortType = fdtdec_get_int(blob, node, + "fsp,serial-port-type", + SERIAL_PORT_TYPE_IO); + + fsp_upd->serialPortAddress = fdtdec_get_int(blob, node, + "fsp,serial-port-address", + 0x3f8); + + fsp_upd->serialPortConfigure = fdtdec_get_bool(blob, node, "fsp,serial-port-configure"); + + fsp_upd->serialPortBaudRate = fdtdec_get_int(blob, node, + "fsp,serial-port-baudrate", + SERIAL_PORT_BAUDRATE_115200); + + fsp_upd->serialPortControllerInit0 = fdtdec_get_bool(blob, node, "fsp,serial-port-controller-init0"); + + fsp_upd->serialPortControllerInit1 = fdtdec_get_bool(blob, node, "fsp,serial-port-controller-init1"); + + fsp_upd->configIOU1_PciPort3 = fdtdec_get_int(blob, node, + "fsp,config-iou1-pci-port3", + CONFIG_IOU1_PCI_PORT3_X4X4X4X4); + + fsp_upd->configIOU2_PciPort1 = fdtdec_get_int(blob, node, + "fsp,config-iou2-pci-port1", + CONFIG_IOU2_PCI_PORT1_XXX8); + + fsp_upd->pchPciPort1 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port1"); + + fsp_upd->pchPciPort2 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port2"); + + fsp_upd->pchPciPort3 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port3"); + + fsp_upd->pchPciPort4 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port4"); + + fsp_upd->pchPciPort5 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port5"); + + fsp_upd->pchPciPort6 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port6"); + + fsp_upd->pchPciPort7 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port7"); + + fsp_upd->pchPciPort8 = fdtdec_get_bool(blob, node, "fsp,pch-pci-port8"); + + fsp_upd->ehci1Enable = fdtdec_get_bool(blob, node, "fsp,ehci1-enable"); + + fsp_upd->hyperThreading = fdtdec_get_bool(blob, node, "fsp,hyper-threading"); + + fsp_upd->debugOutputLevel = fdtdec_get_int(blob, node, + "fsp,debug-output-level", + DEBUG_OUTPUT_LEVEL_NORMAL); + + fsp_upd->tcoTimerHaltLock = fdtdec_get_bool(blob, node, "fsp,tco-timer-halt-lock"); + + fsp_upd->turboMode = fdtdec_get_bool(blob, node, "fsp,turbo-mode"); + + fsp_upd->bootPerfMode = fdtdec_get_bool(blob, node, "fsp,boot-perf-mode"); + + fsp_upd->pciePort1aAspm = fdtdec_get_int(blob, node, + "fsp,pcie-port1a-aspm", + PCIE_ASPM_DISABLED); + + fsp_upd->pciePort1bAspm = fdtdec_get_int(blob, node, + "fsp,pcie-port1b-aspm", + PCIE_ASPM_DISABLED); + + fsp_upd->pciePort3aAspm = fdtdec_get_int(blob, node, + "fsp,pcie-port3a-aspm", + PCIE_ASPM_DISABLED); + + fsp_upd->pciePort3bAspm = fdtdec_get_int(blob, node, + "fsp,pcie-port3b-aspm", + PCIE_ASPM_DISABLED); + + fsp_upd->pciePort3cAspm = fdtdec_get_int(blob, node, + "fsp,pcie-port3c-aspm", + PCIE_ASPM_DISABLED); + + fsp_upd->pciePort3dAspm = fdtdec_get_int(blob, node, + "fsp,pcie-port3d-aspm", + PCIE_ASPM_DISABLED); + + fsp_upd->pchPciePort1Aspm = fdtdec_get_int(blob, node, + "fsp,pch-pcie-port1-aspm", + PCH_PCI_ASPM_DISABLED); + + fsp_upd->pchPciePort2Aspm = fdtdec_get_int(blob, node, + "fsp,pch-pcie-port2-aspm", + PCH_PCI_ASPM_DISABLED); + + fsp_upd->pchPciePort3Aspm = fdtdec_get_int(blob, node, + "fsp,pch-pcie-port3-aspm", + PCH_PCI_ASPM_DISABLED); + + fsp_upd->pchPciePort4Aspm = fdtdec_get_int(blob, node, + "fsp,pch-pcie-port4-aspm", + PCH_PCI_ASPM_DISABLED); + + fsp_upd->pchPciePort5Aspm = fdtdec_get_int(blob, node, + "fsp,pch-pcie-port5-aspm", + PCH_PCI_ASPM_DISABLED); + + fsp_upd->pchPciePort6Aspm = fdtdec_get_int(blob, node, + "fsp,pch-pcie-port6-aspm", + PCH_PCI_ASPM_DISABLED); + + fsp_upd->pchPciePort7Aspm = fdtdec_get_int(blob, node, + "fsp,pch-pcie-port7-aspm", + PCH_PCI_ASPM_DISABLED); + + fsp_upd->pchPciePort8Aspm = fdtdec_get_int(blob, node, + "fsp,pch-pcie-port8-aspm", + PCH_PCI_ASPM_DISABLED); + + fsp_upd->thermalDeviceEnable = fdtdec_get_bool(blob, node, "fsp,thermal-device-enable"); +} diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 6d0c4b6..e59f192 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -15,6 +15,7 @@ dtb-y += bayleybay.dtb \ efi.dtb \ galileo.dtb \ minnowmax.dtb \ + poseidon.dtb \ qemu-x86_i440fx.dtb \ qemu-x86_q35.dtb \ theadorable-x86-dfi-bt700.dtb \ diff --git a/arch/x86/dts/poseidon.dts b/arch/x86/dts/poseidon.dts new file mode 100644 index 0000000..40894b9 --- /dev/null +++ b/arch/x86/dts/poseidon.dts @@ -0,0 +1,210 @@ +/* + * Copyright (C) 2014, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include <asm/arch-broadwell-de/fsp/fsp_configs.h> +#include <dt-bindings/gpio/x86-gpio.h> +#include <dt-bindings/interrupt-router/intel-irq.h> + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" +/include/ "coreboot_fb.dtsi" + +/ { + model = "Intel Broadwell-DE"; + compatible = "x86", "intel,poseidon", "intel,broadwell-de"; + + chosen { + stdout-path = "/serial"; + }; + + /*cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <1>; + intel,apic-id = <1>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <2>; + intel,apic-id = <2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <3>; + intel,apic-id = <3>; + }; + };*/ + + tsc-timer { + clock-frequency = <1000000000>; + }; + + pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 + 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + + pch@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,pch9"; + #address-cells = <1>; + #size-cells = <1>; + + irq-router { + compatible = "intel,irq-router"; + intel,pirq-config = "ibase"; + intel,ibase-offset = <0x50>; + intel,pirq-link = <8 8>; + intel,pirq-mask = <0xdee0>; + intel,pirq-routing = < + /*PCI_BDF(0, 31, 0) LPC Controller does not generate an interrupt */ + PCI_BDF(0, 31, 2) INTB PIRQB /* SATA Controller #1 */ + PCI_BDF(0, 31, 3) INTC PIRQC /* SMBus Controller */ + PCI_BDF(0, 31, 5) INTB PIRQB /* SATA Controller #2 */ + PCI_BDF(0, 31, 6) INTC PIRQC /* Thermal Subsystem */ + PCI_BDF(0, 29, 0) INTA PIRQA /* USB EHCI Controller #1 */ + PCI_BDF(0, 28, 0) INTA PIRQA /* PCI Express Port 1 */ + PCI_BDF(0, 28, 1) INTB PIRQB /* PCI Express Port 2 */ + PCI_BDF(0, 28, 2) INTC PIRQC /* PCI Express Port 3 */ + PCI_BDF(0, 28, 3) INTD PIRQD /* PCI Express Port 4 */ + PCI_BDF(0, 28, 4) INTA PIRQA /* PCI Express Port 5 */ + PCI_BDF(0, 28, 5) INTB PIRQB /* PCI Express Port 6 */ + PCI_BDF(0, 28, 6) INTC PIRQC /* PCI Express Port 7 */ + PCI_BDF(0, 28, 7) INTD PIRQD /* PCI Express Port 8 */ + PCI_BDF(0, 25, 0) INTA PIRQA /* Gigabit Ethernet Controller*/ + PCI_BDF(0, 22, 0) INTA PIRQA /* Intel Management Engine Interface #1 */ + PCI_BDF(0, 22, 1) INTB PIRQB /* Intel Management Engine Interface #2*/ + PCI_BDF(0, 22, 2) INTC PIRQC /* IDE-R*/ + PCI_BDF(0, 22, 3) INTD PIRQD /* KT*/ + PCI_BDF(0, 20, 0) INTA PIRQA /* xHCI Controller */ + >; + }; + + }; + }; + + fsp { + compatible = "intel,broadwell-de-fsp"; + fsp,memEccSupport = <MEM_ECC_SUPPORT_AUTO>; + fsp,memDdrMemoryType = <MEM_DDR_MEMORY_TYPE_UDIMM_AND_RDIMM>; + fsp,memRankMultiplication = <MEM_RANK_MULTIPLICATION_AUTO>; + fsp,memRankMarginTool = <MEM_RANK_MARGIN_TOOL_AUTO>; + fsp,memScrambling = <MEM_SCRAMBLING_AUTO>; + fsp,memRefreshMode = <MEM_REFRESH_MODE_ACC_SELF_REFRESH>; + fsp,memMcOdtOverride = <MEM_MC0DT_OVERRIDE_AUTO>; + fsp,memCAParity = <MEM_CA_PARITY_AUTO>; + fsp,memThermalThrottling = <MEM_THERMAL_THROTTLING_CLOSEDLOOP>; + fsp,memPowerSavingsMode = <MEM_POWER_SAVINGS_MODE_AUTO>; + fsp,memElectricalThrottling = <MEM_ELECTRICAL_THROTTLING_DISABLED>; + fsp,memPagePolicy = <MEM_PAGE_POLICY_AUTO>; + fsp,memSocketInterleaveBelow4G = <MEM_SOCKET_INTERLEAVE_BELOW_4G_DISABLED>; + fsp,memChannelInterleave = <MEM_CHANNEL_INTERLEAVE_AUTO>; + fsp,memRankInterleave = <MEM_RANK_INTERLEAVE_AUTO>; + + #ifdef CONFIG_FSP_MEMORY_DOWN + fsp,memDownEnable; + fsp,memDownCh0Dimm0SpdPtr = <CONFIG_SPD_ADDR>; + fsp,memDownCh0Dimm1SpdPtr = <0x0>; + fsp,memDownCh1Dimm0SpdPtr = <0x0>; + fsp,memDownCh1Dimm1SpdPtr = <0x0>; + #endif + + /*#ifdef CONFIG_ENABLE_MRC_CACHE + fsp,mem-fast-boot = <MEM_FAST_BOOT_ENABLE>; + #else + fsp,mem-fast-boot = <MEM_FAST_BOOT_DISABLE>; + #endif*/ + fsp,mem-fast-boot = <MEM_FAST_BOOT_DISABLE>; + + fsp,pam0-hienable = <PAM_RW_DRAM_ONLY>; + fsp,pam1-loenable = <PAM_RW_DRAM_ONLY>; + fsp,pam1-hienable = <PAM_RW_DRAM_ONLY>; + fsp,pam2-loenable = <PAM_RW_DRAM_ONLY>; + fsp,pam2-hienable = <PAM_RW_DRAM_ONLY>; + fsp,pam3-loenable = <PAM_RW_DRAM_ONLY>; + fsp,pam3-hienable = <PAM_RW_DRAM_ONLY>; + fsp,pam4-loenable = <PAM_RW_DRAM_ONLY>; + fsp,pam4-hienable = <PAM_RW_DRAM_ONLY>; + fsp,pam5-loenable = <PAM_RW_DRAM_ONLY>; + fsp,pam5-hienable = <PAM_RW_DRAM_ONLY>; + fsp,pam6-loenable = <PAM_RW_DRAM_ONLY>; + fsp,pam6-hienable = <PAM_RW_DRAM_ONLY>; + fsp,memAdr = <MEM_ADR_DISABLED>; + fsp,serial-port-type = <SERIAL_PORT_TYPE_IO>; + fsp,serial-port-address = <0x3f8>; + fsp,serial-port-configure; + fsp,serial-port-baudrate = <SERIAL_PORT_BAUDRATE_115200>; + fsp,serial-port-controller-init0; + fsp,serial-port-controller-init1; + fsp,config-iou1-pci-port3 = <CONFIG_IOU1_PCI_PORT3_X4X4X4X4>; + fsp,config-iou2-pci-port1 = <CONFIG_IOU2_PCI_PORT1_XXX8>; + fsp,pch-pci-port1; + fsp,pch-pci-port2; + fsp,pch-pci-port3; + fsp,pch-pci-port4; + fsp,pch-pci-port5; + fsp,pch-pci-port6; + fsp,pch-pci-port7; + fsp,pch-pci-port8; + fsp,ehci1-enable; + fsp,hyper-threading; + fsp,debug-output-level = <DEBUG_OUTPUT_LEVEL_NORMAL>; + fsp,tco-timer-halt-lock; + fsp,turbo-mode; + fsp,boot-perf-mode; + fsp,pcie-port1a-aspm = <PCIE_ASPM_DISABLED>; + fsp,pcie-port1b-aspm = <PCIE_ASPM_DISABLED>; + fsp,pcie-port3a-aspm = <PCIE_ASPM_DISABLED>; + fsp,pcie-port3b-aspm = <PCIE_ASPM_DISABLED>; + fsp,pcie-port3c-aspm = <PCIE_ASPM_DISABLED>; + fsp,pcie-port3d-aspm = <PCIE_ASPM_DISABLED>; + fsp,pch-pcie-port1-aspm = <PCH_PCI_ASPM_DISABLED>; + fsp,pch-pcie-port2-aspm = <PCH_PCI_ASPM_DISABLED>; + fsp,pch-pcie-port3-aspm = <PCH_PCI_ASPM_DISABLED>; + fsp,pch-pcie-port4-aspm = <PCH_PCI_ASPM_DISABLED>; + fsp,pch-pcie-port5-aspm = <PCH_PCI_ASPM_DISABLED>; + fsp,pch-pcie-port6-aspm = <PCH_PCI_ASPM_DISABLED>; + fsp,pch-pcie-port7-aspm = <PCH_PCI_ASPM_DISABLED>; + fsp,pch-pcie-port8-aspm = <PCH_PCI_ASPM_DISABLED>; + fsp,thermal-device-enable; + }; + + microcode { + update@0 { +#include "microcode/broadwell_de_microcode/m1050663_0700000e.dtsi" + }; + update@1 { +#include "microcode/broadwell_de_microcode/m1050662_00000011.dtsi" + }; + update@2 { +#include "microcode/broadwell_de_microcode/mff50661_f1000008.dtsi" + }; + }; + +}; diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 7e37d4f..486abe3 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -67,6 +67,12 @@ pos = <CONFIG_VGA_BIOS_ADDR>; }; #endif +#ifdef CONFIG_HAVE_SPD + intel-spd { + filename = CONFIG_SPD_FILE; + pos = <CONFIG_SPD_ADDR>; + }; +#endif #ifdef CONFIG_HAVE_VBT intel-vbt { filename = CONFIG_VBT_FILE; diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/global_nvs.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/global_nvs.asl new file mode 100644 index 0000000..a28d4df --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/acpi/global_nvs.asl @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2016 Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/acpi/global_nvs.h> + +OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE) +Field(GNVS, ByteAcc, NoLock, Preserve) +{ + Offset (0x00), + PCNT, 8, /* processor count */ + IURE, 8, /* internal UART enabled */ +} diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/irq_helper.h b/arch/x86/include/asm/arch-broadwell-de/acpi/irq_helper.h new file mode 100644 index 0000000..5bdddd7 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/acpi/irq_helper.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#undef PCI_DEV_PIRQ_ROUTES +#undef ACPI_DEV_IRQ +#undef PCI_DEV_PIRQ_ROUTE +#undef PIRQ_PIC_ROUTES +#undef PIRQ_PIC +#undef IRQROUTE_H + +#if defined(PIC_MODE) + +#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ + { Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 } } + +#else /* defined(PIC_MODE) */ + +#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ + { Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ } } + +#endif + +#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ + { ACPI_DEV_IRQ(dev_, 0, a_), \ + ACPI_DEV_IRQ(dev_, 1, b_), \ + ACPI_DEV_IRQ(dev_, 2, c_), \ + ACPI_DEV_IRQ(dev_, 3, d_) } + +/* Empty PIRQ_PIC definition. */ +#define PIRQ_PIC(pirq_, pic_irq_) + +///* Include the mainboard irq route definition */ +#include "irqroute.h" diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/irqlinks.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/irqlinks.asl new file mode 100644 index 0000000..3694298 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/acpi/irqlinks.asl @@ -0,0 +1,454 @@ +/* + * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OperationRegion (PRR0, PCI_Config, 0x00, 0x100) +Field (PRR0, AnyAcc, NoLock, Preserve) { + Offset(0x60), + PIRA, 8, + PIRB, 8, + PIRC, 8, + PIRD, 8, + Offset(0x68), + PIRE, 8, + PIRF, 8, + PIRG, 8, + PIRH, 8 +} + +Device (LNKA) { // PCI IRQ link A + Name (_HID,EISAID("PNP0C0F")) + //Name(_UID, 1) + Method (_STA,0,NotSerialized) { + If(And(PIRA, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRA, 0x80, PIRA) + } + + Method (_CRS,0,Serialized) { + Name (BUF0, ResourceTemplate() {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And(PIRA, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And (PIRA,0x0F),IRQW) // Save in buffer + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)){ + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRA) + } // End of _SRS Method +} + +Device(LNKB) { // PCI IRQ link B + Name (_HID,EISAID("PNP0C0F")) + //Name(_UID, 2) + Method (_STA,0,NotSerialized) { + If (And (PIRB, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRB, 0x80,PIRB) + } + + Method (_CRS,0,Serialized) { + Name(BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRB, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And (PIRB,0x0F),IRQW) // Save in buffer + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name (_PRS, + ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual(IRQW,Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store (Local0, PIRB) + } // End of _SRS Method +} + +Device(LNKC) { // PCI IRQ link C + Name(_HID, EISAID("PNP0C0F")) + //Name(_UID, 3) + + Method (_STA,0,NotSerialized) { + If (And (PIRC, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS, 0, NotSerialized) { + Or (PIRC, 0x80, PIRC) + } + + Method (_CRS, 0, Serialized) { + Name (BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRC, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And (PIRC,0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRC) + } // End of _SRS Method +} + +Device (LNKD) { // PCI IRQ link D + Name (_HID,EISAID ("PNP0C0F")) + + //Name(_UID, 4) + + Method (_STA, 0, NotSerialized) { + If (And (PIRD, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS, 0, NotSerialized) { + Or(PIRD, 0x80,PIRD) + } + + Method (_CRS,0,Serialized) { + Name (BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRD, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0, And (PIRD,0x0F), IRQW) + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW, Local0)// Set IRQ + If (LNotEqual (IRQW, Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store(Local0, PIRD) + } // End of _SRS Method +} + +Device(LNKE) { // PCI IRQ link E + Name(_HID,EISAID("PNP0C0F")) + + //Name(_UID, 5) + + Method (_STA,0,NotSerialized) { + If (And (PIRE, 0x80)) { + Return(0x9) + } Else { + Return(0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRE, 0x80, PIRE) + } + + Method (_CRS, 0, Serialized) { + Name (BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRE, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One, Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0, And (PIRE,0x0F), IRQW) + Return (BUF0) // Return Buf0 + } // End of _CRS method + + Name(_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW, Local0) // Set IRQ + If (LNotEqual (IRQW, Zero)) { + And (Local0, 0x7F, Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store (Local0, PIRE) + } // End of _SRS Method +} + +Device(LNKF) { // PCI IRQ link F + Name (_HID,EISAID("PNP0C0F")) + + //Name(_UID, 6) + + Method (_STA,0,NotSerialized) { + If (And (PIRF, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or (PIRB, 0x80, PIRF) + } + + Method (_CRS,0,Serialized) { + Name(BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRF, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One, Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0, And (PIRF, 0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name(_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80, Local0) + } + Store (Local0, PIRF) + } // End of _SRS Method +} + +Device(LNKG) { // PCI IRQ link G + Name(_HID,EISAID("PNP0C0F")) + //Name(_UID, 7) + Method(_STA,0,NotSerialized) { + If (And (PIRG, 0x80)) { + Return (0x9) + } Else { + Return (0xB) + } // Don't display + } + + Method (_DIS, 0, NotSerialized) { + Or(PIRG, 0x80,PIRG) + } + + Method (_CRS,0,Serialized){ + Name(BUF0,ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And(PIRG, 0x80)) { + Store(Zero, Local0) + } Else { + Store(One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And(PIRG,0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name (_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit(IRQW,Local0) // Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRG) + } // End of _SRS Method +} + +Device(LNKH) { // PCI IRQ link H + Name (_HID,EISAID("PNP0C0F")) + + //Name(_UID, 8) + + Method (_STA,0,NotSerialized) { + If (And(PIRH, 0x80)) { + Return(0x9) + } Else { + Return(0xB) + } // Don't display + } + + Method (_DIS,0,NotSerialized) { + Or(PIRH, 0x80,PIRH) + } + + Method (_CRS,0,Serialized) { + Name(BUF0, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){0}}) + // + // Define references to buffer elements + // + CreateWordField (BUF0, 0x01, IRQW) // IRQ low + // + // Write current settings into IRQ descriptor + // + If (And (PIRH, 0x80)) { + Store (Zero, Local0) + } Else { + Store (One,Local0) + } + // + // Shift 1 by value in register 70, Save in buffer + // + ShiftLeft (Local0,And(PIRH,0x0F),IRQW) + Return (BUF0) + } // End of _CRS method + + Name(_PRS, ResourceTemplate() + {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}}) + + Method (_SRS,1,NotSerialized) { + CreateWordField (ARG0, 0x01, IRQW) // IRQ low + FindSetRightBit (IRQW,Local0)// Set IRQ + If (LNotEqual (IRQW,Zero)) { + And (Local0, 0x7F,Local0) + Decrement (Local0) + } Else { + Or (Local0, 0x80,Local0) + } + Store (Local0, PIRH) + } +} diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.asl new file mode 100644 index 0000000..39c7a19 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.asl @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* PCI Interrupt Routing */ +Method(_PRT) +{ + /* + * PICM comes from _PIC, which returns the following: + * 0 - PIC mode + * 1 - APIC mode + * 2 - SAPIC mode + */ + If (PICM) { + Return (Package() { + #undef PIC_MODE + #include "irq_helper.h" + PCI_DEV_PIRQ_ROUTES + }) + } Else { + Return (Package() { + #define PIC_MODE + #include "irq_helper.h" + PCI_DEV_PIRQ_ROUTES + }) + } +} diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.h b/arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.h new file mode 100644 index 0000000..27701db --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/device.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(ME_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(GBE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(EHCI1_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D) + +/* +* Route each PIRQ[A-H] to a PIC IRQ[0-15] +* Reserved: 0, 1, 2, 8, 13 +* ACPI/SCI: 9 +*/ +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 5), \ + PIRQ_PIC(B, 6), \ + PIRQ_PIC(C, 7), \ + PIRQ_PIC(D, 10), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 12), \ + PIRQ_PIC(G, 14), \ + PIRQ_PIC(H, 15) diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/lpc.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/lpc.asl new file mode 100644 index 0000000..c1a9e2f --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/acpi/lpc.asl @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Intel LPC Bus Device - 0:1f.0 */ + +Device (LPC0) +{ + Name(_ADR, 0x001f0000) + + #include "irqlinks.asl" + + Device (FWH) // Firmware Hub + { + Name (_HID, EISAID("INT0800")) + Name (_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + }) + } + + Device (HPET) + { + Name (_HID, EISAID("PNP0103")) + Name (_CID, 0x010CD041) + + Method (_STA, 0) // Device Status + { + Return (0xf) // Enable and show device + } + + Name(_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xfed00000, 0x400) + }) + } + + Device(LDRC) // LPC device: Resource consumption + { + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 2) + + Name (RBUF, ResourceTemplate() + { + IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status + IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post + IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI + }) + + Method (_CRS, 0, NotSerialized) + { + Return (RBUF) + } + } + + Device (RTC) // Real Time Clock + { + Name (_HID, EISAID("PNP0B00")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x70, 0x70, 1, 8) + }) + } + + Device (TIMR) // Intel 8254 timer + { + Name(_HID, EISAID("PNP0100")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x40, 0x40, 0x01, 0x04) + IO (Decode16, 0x50, 0x50, 0x10, 0x04) + IRQNoFlags() {0} + }) + } +} diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/pcie1.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/pcie1.asl new file mode 100644 index 0000000..4c0cd37 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/acpi/pcie1.asl @@ -0,0 +1,455 @@ +/* + * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +Name (PR01, Package() { + // [SL01]: PCI Express Slot 1 on 1A on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR01, Package() { + // [SL01]: PCI Express Slot 1 on 1A on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH01, Package() { + // [SL01]: PCI Express Slot 1 on 1A on PCI0 + Package() { 0x0000FFFF, 0, 0, 26 }, + Package() { 0x0000FFFF, 1, 0, 28 }, + Package() { 0x0000FFFF, 2, 0, 29 }, + Package() { 0x0000FFFF, 3, 0, 30 }, +}) + +Name (PR02, Package() { + // [SL02]: PCI Express Slot 2 on 1B on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR02, Package() { + // [SL02]: PCI Express Slot 2 on 1B on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH02, Package() { + // [SL02]: PCI Express Slot 2 on 1B on PCI0 + Package() { 0x0000FFFF, 0, 0, 27 }, + Package() { 0x0000FFFF, 1, 0, 30 }, + Package() { 0x0000FFFF, 2, 0, 28 }, + Package() { 0x0000FFFF, 3, 0, 29 }, +}) + +Name (PR03, Package() { + // [CB0I]: CB3DMA on IOSF + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [CB0J]: CB3DMA on IOSF + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + // [CB0K]: CB3DMA on IOSF + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + // [CB0L]: CB3DMA on IOSF + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR03, Package() { + // [CB0I]: CB3DMA on IOSF + Package() { 0x0000FFFF, 0, 0, 16 }, + // [CB0J]: CB3DMA on IOSF + Package() { 0x0000FFFF, 1, 0, 17 }, + // [CB0K]: CB3DMA on IOSF + Package() { 0x0000FFFF, 2, 0, 18 }, + // [CB0L]: CB3DMA on IOSF + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH03, Package() { + // [CB0I]: CB3DMA on IOSF + Package() { 0x0000FFFF, 0, 0, 32 }, + // [CB0J]: CB3DMA on IOSF + Package() { 0x0000FFFF, 1, 0, 36 }, + // [CB0K]: CB3DMA on IOSF + Package() { 0x0000FFFF, 2, 0, 37 }, + // [CB0L]: CB3DMA on IOSF + Package() { 0x0000FFFF, 3, 0, 38 }, +}) + +Name (PR04, Package() { + // [SL04]: PCI Express Slot 4 on 2B on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR04, Package() { + // [SL04]: PCI Express Slot 4 on 2B on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH04, Package() { + // [SL04]: PCI Express Slot 4 on 2B on PCI0 + Package() { 0x0000FFFF, 0, 0, 33 }, + Package() { 0x0000FFFF, 1, 0, 37 }, + Package() { 0x0000FFFF, 2, 0, 38 }, + Package() { 0x0000FFFF, 3, 0, 36 }, +}) + +Name (PR05, Package() { + // [SL05]: PCI Express Slot 5 on 2C on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR05, Package() { + // [SL05]: PCI Express Slot 5 on 2C on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH05, Package() { + // [SL05]: PCI Express Slot 5 on 2C on PCI0 + Package() { 0x0000FFFF, 0, 0, 34 }, + Package() { 0x0000FFFF, 1, 0, 37 }, + Package() { 0x0000FFFF, 2, 0, 36 }, + Package() { 0x0000FFFF, 3, 0, 38 }, +}) + +Name (PR06, Package() { + // [SL06]: PCI Express Slot 6 on 2D on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR06, Package() { + // [SL06]: PCI Express Slot 6 on 2D on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH06, Package() { + // [SL06]: PCI Express Slot 6 on 2D on PCI0 + Package() { 0x0000FFFF, 0, 0, 35 }, + Package() { 0x0000FFFF, 1, 0, 36 }, + Package() { 0x0000FFFF, 2, 0, 38 }, + Package() { 0x0000FFFF, 3, 0, 37 }, +}) + +Name (PR07, Package() { + // [SL07]: PCI Express Slot 7 on 3A on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR07, Package() { + // [SL07]: PCI Express Slot 7 on 3A on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH07, Package() { + // [SL07]: PCI Express Slot 7 on 3A on PCI0 + Package() { 0x0000FFFF, 0, 0, 40 }, + Package() { 0x0000FFFF, 1, 0, 44 }, + Package() { 0x0000FFFF, 2, 0, 45 }, + Package() { 0x0000FFFF, 3, 0, 46 }, +}) + +Name (PR08, Package() { + // [SL08]: PCI Express Slot 8 on 3B on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR08, Package() { + // [SL08]: PCI Express Slot 8 on 3B on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH08, Package() { + // [SL08]: PCI Express Slot 8 on 3B on PCI0 + Package() { 0x0000FFFF, 0, 0, 41 }, + Package() { 0x0000FFFF, 1, 0, 45 }, + Package() { 0x0000FFFF, 2, 0, 46 }, + Package() { 0x0000FFFF, 3, 0, 44 }, +}) + +Name (PR09, Package() { + // [SL09]: PCI Express Slot 9 on 3C on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR09, Package() { + // [SL09]: PCI Express Slot 9 on 3C on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH09, Package() { + // [SL09]: PCI Express Slot 9 on 3C on PCI0 + Package() { 0x0000FFFF, 0, 0, 42 }, + Package() { 0x0000FFFF, 1, 0, 45 }, + Package() { 0x0000FFFF, 2, 0, 44 }, + Package() { 0x0000FFFF, 3, 0, 46 }, +}) + +Name (PR0A, Package() { + // [SL0A]: PCI Express Slot 10 on 3D on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, +}) + +Name (AR0A, Package() { + // [SL0A]: PCI Express Slot 10 on 3D on PCI0 + Package() { 0x0000FFFF, 0, 0, 16 }, + Package() { 0x0000FFFF, 1, 0, 17 }, + Package() { 0x0000FFFF, 2, 0, 18 }, + Package() { 0x0000FFFF, 3, 0, 19 }, +}) + +Name (AH0A, Package() { + // [SL0A]: PCI Express Slot 10 on 3D on PCI0 + Package() { 0x0000FFFF, 0, 0, 43 }, + Package() { 0x0000FFFF, 1, 0, 44 }, + Package() { 0x0000FFFF, 2, 0, 46 }, + Package() { 0x0000FFFF, 3, 0, 45 }, +}) + + + // PCI Express Port 1A on PCI0 +Device (BR1A) { + Name (_ADR, 0x00010000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR01) + } + If (LEqual(APC1, One)) { + Return (AH01) + } + Return (AR01) + } + +} + +// PCI Express Port 1B on PCI0 +Device (BR1B) { + Name (_ADR, 0x00010001) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR02) + } + If (LEqual(APC1, One)) { + Return (AH02) + } + Return (AR02) + } + +} + +// PCI Express Port 2A on PCI0 +Device (BR2A) { + Name (_ADR, 0x00020000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR03) + } + If (LEqual(APC1, One)) { + Return (AH03) + } + Return (AR03) + } + + + // CB3DMA on IOSF + Device (CB0I) { + Name (_ADR, 0x00000000) + } + + // CB3DMA on IOSF + Device (CB0J) { + Name (_ADR, 0x00000001) + } + + // CB3DMA on IOSF + Device (CB0K) { + Name (_ADR, 0x00000002) + } + + // CB3DMA on IOSF + Device (CB0L) { + Name (_ADR, 0x00000003) + } +} + +// PCI Express Port 2B on PCI0 +Device (BR2B) { + Name (_ADR, 0x00020001) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR04) + } + If (LEqual(APC1, One)) { + Return (AH04) + } + Return (AR04) + } + +} + +// PCI Express Port 2C on PCI0 +Device (BR2C) { + Name (_ADR, 0x00020002) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR05) + } + If (LEqual(APC1, One)) { + Return (AH05) + } + Return (AR05) + } + +} + +// PCI Express Port 2D on PCI0 +Device (BR2D) { + Name (_ADR, 0x00020003) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR06) + } + If (LEqual(APC1, One)) { + Return (AH06) + } + Return (AR06) + } + +} + +// PCI Express Port 3A on PCI0 +Device (BR3A) { + Name (_ADR, 0x00030000) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR07) + } + If (LEqual(APC1, One)) { + Return (AH07) + } + Return (AR07) + } + +} + +// PCI Express Port 3B on PCI0 +Device (BR3B) { + Name (_ADR, 0x00030001) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR08) + } + If (LEqual(APC1, One)) { + Return (AH08) + } + Return (AR08) + } + +} + +// PCI Express Port 3C on PCI0 +Device (BR3C) { + Name (_ADR, 0x00030002) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR09) + } + If (LEqual(APC1, One)) { + Return (AH09) + } + Return (AR09) + } + +} + +// PCI Express Port 3D on PCI0 +Device (BR3D) { + Name (_ADR, 0x00030003) + Method (_PRW, 0) { + Return (Package (0x02) {0x09, 0x04}) + } + Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR0A) + } + If (LEqual(APC1, One)) { + Return (AH0A) + } + Return (AR0A) + } + +} diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/platform.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/platform.asl new file mode 100644 index 0000000..cefe4f7 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/acpi/platform.asl @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/acpi/statdef.asl> +#include <asm/arch/iomap.h> +#include <asm/arch/irq.h> + + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +Name(\APC1, Zero) // IIO IOAPIC + +Name(\PICM, Zero) // IOAPIC/8259 + +Method(_PIC, 1) +{ + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +/* ACPI global NVS */ +//#include "irqlinks.asl" + +Scope (\_SB) +{ + #include "southcluster.asl" + + #include "pcie1.asl" +} diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/southcluster.asl b/arch/x86/include/asm/arch-broadwell-de/acpi/southcluster.asl new file mode 100644 index 0000000..d2b0ba9 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/acpi/southcluster.asl @@ -0,0 +1,339 @@ +/* + * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/iomap.h> +#include <asm/arch/irq.h> + +Name(_HID,EISAID("PNP0A08")) // PCIe +Name(_CID,EISAID("PNP0A03")) // PCI + +Name(_ADR, 0) +Name(_BBN, 0) + +Name (MCRS, ResourceTemplate() { + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00fe, 0x0000, 0xff,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xefff, 0x0000, 0xE300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xc0000-0xc3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xc4000-0xc7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xc8000-0xcbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xcc000-0xcffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-0xfeafffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x90000000, 0xFEAFFFFF, 0x00000000, + 0x6EB00000,,, PMEM) + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfec00000, 0xfecfffff, 0x00000000, + 0x00100000,,, APIC) + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed00000, 0xfedfffff, 0x00000000, + 0x00100000,,, PCHR) + + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000380000000000, // Range Minimum + 0x0000383FFFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000004000000000, // Length + ,,, AddressRangeMemory, TypeStatic) +}) + +Method (_CRS, 0, Serialized) { + Return (MCRS) +} + +/* Device Resource Consumption */ +Device (PDRC) { + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 1) + + Name (PDRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) + Memory32Fixed(ReadWrite, PSEG_BASE_ADDRESS, PSEG_BASE_SIZE) + Memory32Fixed(ReadWrite, IOXAPIC1_BASE_ADDRESS, IOXAPIC1_BASE_SIZE) + Memory32Fixed(ReadWrite, IOXAPIC2_BASE_ADDRESS, IOXAPIC2_BASE_SIZE) + Memory32Fixed(ReadWrite, PCH_BASE_ADDRESS, PCH_BASE_SIZE) + Memory32Fixed(ReadWrite, LXAPIC_BASE_ADDRESS, LXAPIC_BASE_SIZE) + Memory32Fixed(ReadWrite, FIRMWARE_BASE_ADDRESS, FIRMWARE_BASE_SIZE) + }) + + // Current Resource Settings + Method (_CRS, 0, Serialized) + { + Return(PDRS) + } +} + +Method (_OSC, 4) { + /* Check for proper GUID */ + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } + Else + { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } +} + +Name (PR00, Package() { + // [DMI0]: Legacy PCI Express Port 0 on PCI0 + Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [BR1A]: PCI Express Port 1A on PCI0 + // [BR1B]: PCI Express Port 1B on PCI0 + Package() { 0x0001FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [BR2A]: PCI Express Port 2A on PCI0 + // [BR2B]: PCI Express Port 2B on PCI0 + // [BR2C]: PCI Express Port 2C on PCI0 + // [BR2D]: PCI Express Port 2D on PCI0 + Package() { 0x0002FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [BR3A]: PCI Express Port 3A on PCI0 + // [BR3B]: PCI Express Port 3B on PCI0 + // [BR3C]: PCI Express Port 3C on PCI0 + // [BR3D]: PCI Express Port 3D on PCI0 + Package() { 0x0003FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [CB0A]: CB3DMA on PCI0 + // [CB0E]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [CB0B]: CB3DMA on PCI0 + // [CB0F]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + // [CB0C]: CB3DMA on PCI0 + // [CB0G]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + // [CB0D]: CB3DMA on PCI0 + // [CB0H]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + // [IIM0]: IIOMISC on PCI0 + Package() { 0x0005FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0005FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0005FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0005FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + // [IID0]: IIODFX0 on PCI0 + Package() { 0x0006FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0006FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0006FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0006FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + // [XHCI]: xHCI controller 1 on PCH + Package() { 0x0014FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + // [HECI]: ME HECI on PCH + // [IDER]: ME IDE redirect on PCH + Package() { 0x0016FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [HEC2]: ME HECI2 on PCH + // [MEKT]: MEKT on PCH + Package() { 0x0016FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + // [GBEM]: GbE Controller VPRO + Package() { 0x0019FFFF, 0, \_SB.PCI0.LPC0.LNKE, 0 }, + // [EHC2]: EHCI controller #2 on PCH + Package() { 0x001AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + // [ALZA]: High definition Audio Controller + Package() { 0x001BFFFF, 0, \_SB.PCI0.LPC0.LNKG, 0 }, + // [RP01]: Pci Express Port 1 on PCH + // [RP05]: Pci Express Port 5 on PCH + Package() { 0x001CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [RP02]: Pci Express Port 2 on PCH + // [RP06]: Pci Express Port 6 on PCH + Package() { 0x001CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + // [RP03]: Pci Express Port 3 on PCH + // [RP07]: Pci Express Port 7 on PCH + Package() { 0x001CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + // [RP04]: Pci Express Port 4 on PCH + // [RP08]: Pci Express Port 8 on ICH + Package() { 0x001CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + // [EHC1]: EHCI controller #1 on PCH + Package() { 0x001DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + // [SAT1]: SATA controller 1 on PCH + // [SAT2]: SATA Host controller 2 on PCH + Package() { 0x001FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + // [SMBS]: SMBus controller on PCH + // [TERM]: Thermal Subsystem on ICH + Package() { 0x001FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, +}) + +Name (AR00, Package() { + // [DMI0]: Legacy PCI Express Port 0 on PCI0 + Package() { 0x0000FFFF, 0, 0, 47 }, + // [BR1A]: PCI Express Port 1A on PCI0 + // [BR1B]: PCI Express Port 1B on PCI0 + Package() { 0x0001FFFF, 0, 0, 47 }, + // [BR2A]: PCI Express Port 2A on PCI0 + // [BR2B]: PCI Express Port 2B on PCI0 + // [BR2C]: PCI Express Port 2C on PCI0 + // [BR2D]: PCI Express Port 2D on PCI0 + Package() { 0x0002FFFF, 0, 0, 47 }, + // [BR3A]: PCI Express Port 3A on PCI0 + // [BR3B]: PCI Express Port 3B on PCI0 + // [BR3C]: PCI Express Port 3C on PCI0 + // [BR3D]: PCI Express Port 3D on PCI0 + Package() { 0x0003FFFF, 0, 0, 47 }, + // [CB0A]: CB3DMA on PCI0 + // [CB0E]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 0, 0, 31 }, + // [CB0B]: CB3DMA on PCI0 + // [CB0F]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 1, 0, 39 }, + // [CB0C]: CB3DMA on PCI0 + // [CB0G]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 2, 0, 31 }, + // [CB0D]: CB3DMA on PCI0 + // [CB0H]: CB3DMA on PCI0 + Package() { 0x0004FFFF, 3, 0, 39 }, + // [IIM0]: IIOMISC on PCI0 + Package() { 0x0005FFFF, 0, 0, 16 }, + Package() { 0x0005FFFF, 1, 0, 17 }, + Package() { 0x0005FFFF, 2, 0, 18 }, + Package() { 0x0005FFFF, 3, 0, 19 }, + // [IID0]: IIODFX0 on PCI0 + Package() { 0x0006FFFF, 0, 0, 16 }, + Package() { 0x0006FFFF, 1, 0, 17 }, + Package() { 0x0006FFFF, 2, 0, 18 }, + Package() { 0x0006FFFF, 3, 0, 19 }, + // [XHCI]: xHCI controller 1 on PCH + Package() { 0x0014FFFF, 3, 0, 19 }, + // [HECI]: ME HECI on PCH + // [IDER]: ME IDE redirect on PCH + Package() { 0x0016FFFF, 0, 0, 16 }, + // [HEC2]: ME HECI2 on PCH + // [MEKT]: MEKT on PCH + Package() { 0x0016FFFF, 1, 0, 17 }, + // [GBEM]: GbE Controller VPRO + Package() { 0x0019FFFF, 0, 0, 20 }, + // [EHC2]: EHCI controller #2 on PCH + Package() { 0x001AFFFF, 2, 0, 18 }, + // [ALZA]: High definition Audio Controller + Package() { 0x001BFFFF, 0, 0, 22 }, + // [RP01]: Pci Express Port 1 on PCH + // [RP05]: Pci Express Port 5 on PCH + Package() { 0x001CFFFF, 0, 0, 16 }, + // [RP02]: Pci Express Port 2 on PCH + // [RP06]: Pci Express Port 6 on PCH + Package() { 0x001CFFFF, 1, 0, 17 }, + // [RP03]: Pci Express Port 3 on PCH + // [RP07]: Pci Express Port 7 on PCH + Package() { 0x001CFFFF, 2, 0, 18 }, + // [RP04]: Pci Express Port 4 on PCH + // [RP08]: Pci Express Port 8 on ICH + Package() { 0x001CFFFF, 3, 0, 19 }, + // [EHC1]: EHCI controller #1 on PCH + Package() { 0x001DFFFF, 2, 0, 18 }, + // [SAT1]: SATA controller 1 on PCH + // [SAT2]: SATA Host controller 2 on PCH + Package() { 0x001FFFFF, 0, 0, 16 }, + // [SMBS]: SMBus controller on PCH + // [TERM]: Thermal Subsystem on ICH + Package() { 0x001FFFFF, 2, 0, 18 }, +}) + +// Socket 0 Root bridge +Method (_PRT, 0) { + If (LEqual(PICM, Zero)) { + Return (PR00) + } + Return (AR00) // If you disable the IOxAPIC in IIO, you should return AR00 +} + +#include "lpc.asl" diff --git a/arch/x86/include/asm/arch-broadwell-de/device.h b/arch/x86/include/asm/arch-broadwell-de/device.h new file mode 100644 index 0000000..be6df7c --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/device.h @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BROADWELL_DE_DEVICE_H_ +#define _BROADWELL_DE_DEVICE_H_ + +#define BUS0 0 + +#define SOC_DEV 0 +#define SOC_FUNC 0 +#define SOC_DEVID 0x2F00 +#define SOC_DEVID_ES2 0x6F00 +#define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV, SOC_FUNC) + +#define VTD_DEV 5 +#define VTD_FUNC 0 +#define VTD_DEVID 0x6f28 +#define VTD_DEV_FUNC PCI_DEVFN(VTD_DEV, VTD_FUNC) + +#define LPC_DEV 31 +#define LPC_FUNC 0 +#define LPC_DEVID 0x8C42 +#define LPC_DEVID_ES2 0x8C54 +#define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV, LPC_FUNC) + +#define SATA_DEV 31 +#define SATA_FUNC 2 +#define AHCI_DEVID 0x8C02 +#define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV, SATA_FUNC) + +#define SMBUS_DEV 31 +#define SMBUS_FUNC 3 +#define SMBUS_DEVID 0x8C22 +#define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) + +#define SATA2_DEV 31 +#define SATA2_FUNC 5 +#define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV, SATA2_FUNC) + +#define EHCI1_DEV 29 +#define EHCI1_FUNC 0 +#define EHCI1_DEVID 0x8C26 +#define EHCI1_DEV_FUNC PCI_DEVFN(EHCI_DEV1, EHCI_FUNC1) + +#define EHCI2_DEV 26 +#define EHCI2_FUNC 0 +#define EHCI2_DEVID 0x8C2D +#define EHCI2_DEV_FUNC PCI_DEVFN(EHCI_DEV2, EHCI_FUNC2) + +#define XHCI_DEV 20 +#define XHCI_FUNC 0 +#define XHCI_DEVID 0x8C31 +#define XHCI_FUS_REG 0xE0 +#define XHCI_FUNC_DISABLE (1 << 0) +#define XHCI_USB2PR_REG 0xD0 +#define XHCI_DEV_FUNC PCI_DEVFN(XHCI_DEV, XHCI_FUNC) + +#define GBE_DEV 25 +#define GBE_FUNC 0 +#define GBE_DEVID 0x8C33 +#define GBE_DEV_FUNC PCI_DEVFN(GBE_DEV, GBE_FUNC) + +#define ME_DEV 22 +#define ME_FUNC 0 +#define ME_DEVID 0x8C3A +#define ME_DEV_FUNC PCI_DEVFN(ME_DEV, ME_FUNC) + +#define HDA_DEV 27 +#define HDA_FUNC 0 +#define HDA_DEVID 0x8C20 +#define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV, HDA_FUNC) + +#define PCIE_DEV 28 +#define PCIE_PORT1_DEV PCIE_DEV +#define PCIE_PORT1_FUNC 0 +#define PCIE_PORT1_DEVID 0x8C10 +#define PCIE_PORT2_DEV PCIE_DEV +#define PCIE_PORT2_FUNC 1 +#define PCIE_PORT2_DEVID 0x8C12 +#define PCIE_PORT3_DEV PCIE_DEV +#define PCIE_PORT3_FUNC 2 +#define PCIE_PORT3_DEVID 0x8C14 +#define PCIE_PORT4_DEV PCIE_DEV +#define PCIE_PORT4_FUNC 3 +#define PCIE_PORT4_DEVID 0x8C16 +#define PCIE_PORT5_DEV PCIE_DEV +#define PCIE_PORT5_FUNC 4 +#define PCIE_PORT5_DEVID 0x8C18 +#define PCIE_PORT6_DEV PCIE_DEV +#define PCIE_PORT6_FUNC 5 +#define PCIE_PORT6_DEVID 0x8C1A +#define PCIE_PORT7_DEV PCIE_DEV +#define PCIE_PORT7_FUNC 6 +#define PCIE_PORT7_DEVID 0x8C1C +#define PCIE_PORT8_DEV PCIE_DEV +#define PCIE_PORT8_FUNC 7 +#define PCIE_PORT8_DEVID 0x8C1E +#define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT1_FUNC) +#define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT2_FUNC) +#define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT3_FUNC) +#define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT4_FUNC) +#define PCIE_PORT5_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT5_FUNC) +#define PCIE_PORT6_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT6_FUNC) +#define PCIE_PORT7_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT7_FUNC) +#define PCIE_PORT8_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT8_FUNC) + +/* The SMM device is located on bus 0xff (QPI) */ +#define QPI_BUS 0xff +#define SMM_DEV 0x10 +#define SMM_FUNC 0x06 +#define SMM_DEV_FUNC PCI_DEVFN(SMM_DEV, SMM_FUNC) + +#endif /* _BROADWELL_DE_DEVICE_H_ */ diff --git a/arch/x86/include/asm/arch-broadwell-de/fsp/fsp_configs.h b/arch/x86/include/asm/arch-broadwell-de/fsp/fsp_configs.h new file mode 100644 index 0000000..139f8b5 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/fsp/fsp_configs.h @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSP_CONFIGS_H__ +#define __FSP_CONFIGS_H__ + +#ifndef __ASSEMBLY__ +struct fsp_config_data { + struct fsp_cfg_common common; + struct upd_region fsp_upd; +}; + +struct fspinit_rtbuf { + struct common_buf common; /* FSP common runtime data structure */ +}; +#endif + +/* FSP user configuration settings */ + +#define PAM_RW_DMI_ONLY 0 +#define PAM_R_DRAM_W_DMI 1 +#define PAM_R_DMI_W_DRAM 2 +#define PAM_RW_DRAM_ONLY 3 + +#define PCH_PCI_ASPM_DISABLED 0 +#define PCH_PCI_ASPM_L0S 1 +#define PCH_PCI_ASPM_L1_ONLY 2 +#define PCH_PCI_ASPM_L0SL1 3 +#define PCH_PCI_ASPM_AUTO 4 + +#define PCIE_ASPM_DISABLED 0 +#define PCIE_ASPM_L1ONLY 2 +#define PCIE_ASPM_AUTO 7 + +#define MEM_CHANNEL_INTERLEAVE_AUTO 0 +#define MEM_CHANNEL_INTERLEAVE_1WAY 1 +#define MEM_CHANNEL_INTERLEAVE_2WAY 2 +#define MEM_CHANNEL_INTERLEAVE_3WAY 3 +#define MEM_CHANNEL_INTERLEAVE_4WAY 4 + +#define MEM_SCRAMBLING_DISABLED 0 +#define MEM_SCRAMBLING_ENABLED 1 +#define MEM_SCRAMBLING_AUTO 2 + +#define MEM_ECC_SUPPORT_DISABLED 0 +#define MEM_ECC_SUPPORT_ENABLED 1 +#define MEM_ECC_SUPPORT_AUTO 2 + +#define MEM_CA_PARITY_DISABLED 0 +#define MEM_CA_PARITY_ENABLED 1 +#define MEM_CA_PARITY_AUTO 2 + +#define MEM_POWER_SAVINGS_MODE_DISABLED 0 +#define MEM_POWER_SAVINGS_MODE_SLOW 1 +#define MEM_POWER_SAVINGS_MODE_FAST 2 +#define MEM_POWER_SAVINGS_MODE_APD 3 +#define MEM_POWER_SAVINGS_MODE_USER 4 +#define MEM_POWER_SAVINGS_MODE_AUTO 5 + +#define MEM_RANK_MARGIN_TOOL_DISABLED 0 +#define MEM_RANK_MARGIN_TOOL_ENABLED 1 +#define MEM_RANK_MARGIN_TOOL_AUTO 2 + +#define MEM_RANK_MULTIPLICATION_AUTO 0 +#define MEM_RANK_MULTIPLICATION_ENABLED 1 + +#define MEM_THERMAL_THROTTLING_DISABLED 0 +#define MEM_THERMAL_THROTTLING_OPENLOOP 1 +#define MEM_THERMAL_THROTTLING_CLOSEDLOOP 2 + +#define MEM_ELECTRICAL_THROTTLING_DISABLED 0 +#define MEM_ELECTRICAL_THROTTLING_ENABLED 1 +#define MEM_ELECTRICAL_THROTTLING_AUTO 2 + +#define MEM_DDR_MEMORY_TYPE_RDIMM_ONLY 0 +#define MEM_DDR_MEMORY_TYPE_UDIMM_ONLY 1 +#define MEM_DDR_MEMORY_TYPE_UDIMM_AND_RDIMM 2 + +#define MEM_MC0DT_OVERRIDE_50OHM 0 +#define MEM_MC0DT_OVERRIDE_100OHM 1 +#define MEM_MC0DT_OVERRIDE_AUTO 2 + +#define MEM_ADR_DISABLED 0 +#define MEM_ADR_ENABLED 1 +#define MEM_ADR_ENABLED_NVDIMM 2 + +#define MEM_RANK_INTERLEAVE_AUTO 0 +#define MEM_RANK_INTERLEAVE_1WAY 1 +#define MEM_RANK_INTERLEAVE_2WAY 2 +#define MEM_RANK_INTERLEAVE_4WAY 4 +#define MEM_RANK_INTERLEAVE_8WAY 8 + +#define MEM_PAGE_POLICY_OPEN 0 +#define MEM_PAGE_POLICY_CLOSED 1 +#define MEM_PAGE_POLICY_ADAPTIVE 2 +#define MEM_PAGE_POLICY_AUTO 3 + +#define MEM_REFRESH_MODE_ACC_SELF_REFRESH 0 +#define MEM_REFRESH_MODE_2X_REFRESH 1 + +#define MEM_SOCKET_INTERLEAVE_BELOW_4G_DISABLED 0 +#define MEM_SOCKET_INTERLEAVE_BELOW_4G_ENABLED 1 + +#define CONFIG_IOU1_PCI_PORT3_X4X4X4X4 0 +#define CONFIG_IOU1_PCI_PORT3_X4X4XXX8 1 +#define CONFIG_IOU1_PCI_PORT3_XXX8X4X4 2 +#define CONFIG_IOU1_PCI_PORT3_XXX8XXX8 3 +#define CONFIG_IOU1_PCI_PORT3_XXXXXX16 4 + +#define CONFIG_IOU2_PCI_PORT1_X4X4 0 +#define CONFIG_IOU2_PCI_PORT1_XXX8 1 + +#define SERIAL_PORT_BAUDRATE_9600 8 +#define SERIAL_PORT_BAUDRATE_19200 9 +#define SERIAL_PORT_BAUDRATE_38400 10 +#define SERIAL_PORT_BAUDRATE_57600 11 +#define SERIAL_PORT_BAUDRATE_115200 12 + +#define SERIAL_PORT_TYPE_NONE 0 +#define SERIAL_PORT_TYPE_IO 1 +#define SERIAL_PORT_TYPE_MMIO 2 + +#define DEBUG_OUTPUT_LEVEL_DISABLED 0 +#define DEBUG_OUTPUT_LEVEL_MINIMUM 1 +#define DEBUG_OUTPUT_LEVEL_NORMAL 2 +#define DEBUG_OUTPUT_LEVEL_MAXIMUM 3 + +#define MEM_FAST_BOOT_DISABLE 0 +#define MEM_FAST_BOOT_ENABLE 1 + +#endif /* __FSP_CONFIGS_H__ */ diff --git a/arch/x86/include/asm/arch-broadwell-de/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-broadwell-de/fsp/fsp_vpd.h new file mode 100644 index 0000000..048c528 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/fsp/fsp_vpd.h @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSP_VPD_H +#define __FSP_VPD_H + +struct __packed upd_region { + uint64_t signature; /**Offset 0x0000 **/ + uint64_t reserved; /**Offset 0x0008 **/ + uint8_t unusedUpdSpace0[16]; /**Offset 0x0010 **/ + uint8_t serialPortType; /**Offset 0x0020 **/ + uint32_t serialPortAddress; /**Offset 0x0021 **/ + uint8_t serialPortConfigure; /**Offset 0x0025 **/ + uint8_t serialPortBaudRate; /**Offset 0x0026 **/ + uint8_t serialPortControllerInit0; /**Offset 0x0027 **/ + uint8_t serialPortControllerInit1; /**Offset 0x0028 **/ + uint8_t configIOU1_PciPort3; /**Offset 0x0029 **/ + uint8_t configIOU2_PciPort1; /**Offset 0x002A **/ + uint8_t powerStateAfterG3; /**Offset 0x002B **/ + uint8_t pchPciPort1; /**Offset 0x002C **/ + uint8_t pchPciPort2; /**Offset 0x002D **/ + uint8_t pchPciPort3; /**Offset 0x002E **/ + uint8_t pchPciPort4; /**Offset 0x002F **/ + uint8_t pchPciPort5; /**Offset 0x0030 **/ + uint8_t pchPciPort6; /**Offset 0x0031 **/ + uint8_t pchPciPort7; /**Offset 0x0032 **/ + uint8_t pchPciPort8; /**Offset 0x0033 **/ + uint8_t hotPlug_PchPciPort1; /**Offset 0x0034 **/ + uint8_t hotPlug_PchPciPort2; /**Offset 0x0035 **/ + uint8_t hotPlug_PchPciPort3; /**Offset 0x0036 **/ + uint8_t hotPlug_PchPciPort4; /**Offset 0x0037 **/ + uint8_t hotPlug_PchPciPort5; /**Offset 0x0038 **/ + uint8_t hotPlug_PchPciPort6; /**Offset 0x0039 **/ + uint8_t hotPlug_PchPciPort7; /**Offset 0x003A **/ + uint8_t hotPlug_PchPciPort8; /**Offset 0x003B **/ + uint8_t ehci1Enable; /**Offset 0x003C **/ + uint8_t ehci2Enable; /**Offset 0x003D **/ + uint8_t hyperThreading; /**Offset 0x003E **/ + uint8_t debugOutputLevel; /**Offset 0x003F **/ + uint8_t tcoTimerHaltLock; /**Offset 0x0040 **/ + uint8_t turboMode; /**Offset 0x0041 **/ + uint8_t bootPerfMode; /**Offset 0x0042 **/ + uint8_t pciePort1aAspm; /**Offset 0x0043 **/ + uint8_t pciePort1bAspm; /**Offset 0x0044 **/ + uint8_t pciePort3aAspm; /**Offset 0x0045 **/ + uint8_t pciePort3bAspm; /**Offset 0x0046 **/ + uint8_t pciePort3cAspm; /**Offset 0x0047 **/ + uint8_t pciePort3dAspm; /**Offset 0x0048 **/ + uint8_t pchPciePort1Aspm; /**Offset 0x0049 **/ + uint8_t pchPciePort2Aspm; /**Offset 0x004A **/ + uint8_t pchPciePort3Aspm; /**Offset 0x004B **/ + uint8_t pchPciePort4Aspm; /**Offset 0x004C **/ + uint8_t pchPciePort5Aspm; /**Offset 0x004D **/ + uint8_t pchPciePort6Aspm; /**Offset 0x004E **/ + uint8_t pchPciePort7Aspm; /**Offset 0x004F **/ + uint8_t pchPciePort8Aspm; /**Offset 0x0050 **/ + uint8_t dFXEnable; /**Offset 0x0051 **/ + uint8_t thermalDeviceEnable; /**Offset 0x0052 **/ + uint8_t unusedUpdSpace1[88]; /**Offset 0x0053 **/ + uint8_t memEccSupport; /**Offset 0x00AB **/ + uint8_t memDdrMemoryType; /**Offset 0x00AC **/ + uint8_t memRankMultiplication; /**Offset 0x00AD **/ + uint8_t memRankMarginTool; /**Offset 0x00AE **/ + uint8_t memScrambling; /**Offset 0x00AF **/ + uint8_t memRefreshMode; /**Offset 0x00B0 **/ + uint8_t memMcOdtOverride; /**Offset 0x00B1 **/ + uint8_t memCAParity; /**Offset 0x00B2 **/ + uint8_t memThermalThrottling; /**Offset 0x00B3 **/ + uint8_t memPowerSavingsMode; /**Offset 0x00B4 **/ + uint8_t memElectricalThrottling; /**Offset 0x00B5 **/ + uint8_t memPagePolicy; /**Offset 0x00B6 **/ + uint8_t memSocketInterleaveBelow4G; /**Offset 0x00B7 **/ + uint8_t memChannelInterleave; /**Offset 0x00B8 **/ + uint8_t memRankInterleave; /**Offset 0x00B9 **/ + uint8_t memDownEnable; /**Offset 0x00BA **/ + uint32_t memDownCh0Dimm0SpdPtr; /**Offset 0x00BB **/ + uint32_t memDownCh0Dimm1SpdPtr; /**Offset 0x00BF **/ + uint32_t memDownCh1Dimm0SpdPtr; /**Offset 0x00C3 **/ + uint32_t memDownCh1Dimm1SpdPtr; /**Offset 0x00C7 **/ + uint8_t memFastBoot; /**Offset 0x00CB **/ + uint8_t pam0_hienable; /**Offset 0x00CC **/ + uint8_t pam1_loenable; /**Offset 0x00CD **/ + uint8_t pam1_hienable; /**Offset 0x00CE **/ + uint8_t pam2_loenable; /**Offset 0x00CF **/ + uint8_t pam2_hienable; /**Offset 0x00D0 **/ + uint8_t pam3_loenable; /**Offset 0x00D1 **/ + uint8_t pam3_hienable; /**Offset 0x00D2 **/ + uint8_t pam4_loenable; /**Offset 0x00D3 **/ + uint8_t pam4_hienable; /**Offset 0x00D4 **/ + uint8_t pam5_loenable; /**Offset 0x00D5 **/ + uint8_t pam5_hienable; /**Offset 0x00D6 **/ + uint8_t pam6_loenable; /**Offset 0x00D7 **/ + uint8_t pam6_hienable; /**Offset 0x00D8 **/ + uint8_t memAdr; /**Offset 0x00D9 **/ + uint8_t memAdrResumePath; /**Offset 0x00DA **/ + uint8_t memBlockScTrafficOnAdr; /**Offset 0x00DB **/ + uint16_t memPlatformReleaseAdrClampsPort;/**Offset 0x00DC **/ + uint32_t memPlatformReleaseAdrClampsAnd; /**Offset 0x00DE **/ + uint32_t memPlatformReleaseAdrClampsOr; /**Offset 0x00E2 **/ + uint8_t unusedUpdSpace2[24]; /**Offset 0x00E6 **/ + uint16_t terminator; /**Offset 0x00FE **/ +}; + +#define VPD_IMAGE_ID 0x5F45442D5844425F /* '_BDX-DE_' */ + +struct __packed vpd_region { + uint64_t sign; /* Offset 0x0000 */ + uint32_t img_rev; /* Offset 0x0008 */ + uint32_t upd_offset; /* Offset 0x000c */ + uint8_t unused[16]; /* Offset 0x0010 */ + uint32_t fsp_res_memlen; /* Offset 0x0020 */ +}; +#endif diff --git a/arch/x86/include/asm/arch-broadwell-de/global_nvs.h b/arch/x86/include/asm/arch-broadwell-de/global_nvs.h new file mode 100644 index 0000000..5097cc1 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/global_nvs.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BROADWELL_DE_GLOBAL_NVS_H_ +#define _BROADWELL_DE_GLOBAL_NVS_H_ + +struct __packed acpi_global_nvs { + u8 pcnt; /* processor count */ + u8 iuart_en; /* internal UART enabled */ + + /* + * Add padding so sizeof(struct acpi_global_nvs) == 0x100. + * This must match the size defined in the global_nvs.asl. + */ + u8 rsvd[254]; +}; + +#endif /* _BROADWELL_DE_GLOBAL_NVS_H_ */ diff --git a/arch/x86/include/asm/arch-broadwell-de/iomap.h b/arch/x86/include/asm/arch-broadwell-de/iomap.h new file mode 100644 index 0000000..80f2b9d --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/iomap.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BROADWELL_DE_IOMAP_H_ +#define _BROADWELL_DE_IOMAP_H_ + +/* Memory Mapped IO bases */ + +/* PCI Configuration Space */ +#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE //CONFIG_MMCONF_BASE_ADDRESS in Coreboot +#define MCFG_BASE_SIZE 0x10000000 + +/* Transactions in this range will abort */ +#define ABORT_BASE_ADDRESS 0xfeb00000 +#define ABORT_BASE_SIZE 0x00010000 + +/* PSEG */ +#define PSEG_BASE_ADDRESS 0xfeb80000 +#define PSEG_BASE_SIZE 0x00080000 + +/* IOxAPIC */ +#define IOXAPIC1_BASE_ADDRESS 0xfec00000 +#define IOXAPIC1_BASE_SIZE 0x00100000 +#define IOXAPIC2_BASE_ADDRESS 0xfec01000 +#define IOXAPIC2_BASE_SIZE 0x00100000 + +/* PCH (HPET/LT/TPM/Others) */ +#define PCH_BASE_ADDRESS 0xfed00000 +#define PCH_BASE_SIZE 0x00100000 + +/* Local XAPIC */ +#define LXAPIC_BASE_ADDRESS 0xfee00000 +#define LXAPIC_BASE_SIZE 0x00100000 + +/* High Performance Event Timer */ +#define HPET_BASE_ADDRESS 0xfed00000 +#define HPET_BASE_SIZE 0x400 + +/* Firmware */ +#define FIRMWARE_BASE_ADDRESS 0xff000000 +#define FIRMWARE_BASE_SIZE 0x01000000 + +/* + * IO Port bases. + */ + +/* ACPI Base Address */ +#define ACPI_BASE_ADDRESS 0x400 +#define ACPI_BASE_SIZE 0x80 + +/* GPIO Base Address */ +#define GPIO_BASE_ADDRESS 0x500 +#define GPIO_BASE_SIZE 0x80 + +#endif /* _BROADWELL_DE_IOMAP_H_ */ diff --git a/arch/x86/include/asm/arch-broadwell-de/irq.h b/arch/x86/include/asm/arch-broadwell-de/irq.h new file mode 100644 index 0000000..ac6f689 --- /dev/null +++ b/arch/x86/include/asm/arch-broadwell-de/irq.h @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BROADWELL_DE_IRQ_H_ +#define _BROADWELL_DE_IRQ_H_ + +#define PIRQA_APIC_IRQ 16 +#define PIRQB_APIC_IRQ 17 +#define PIRQC_APIC_IRQ 18 +#define PIRQD_APIC_IRQ 19 +#define PIRQE_APIC_IRQ 20 +#define PIRQF_APIC_IRQ 21 +#define PIRQG_APIC_IRQ 22 +#define PIRQH_APIC_IRQ 23 + +/* PIC IRQ settings. */ +#define PIRQ_PIC_IRQ3 0x3 +#define PIRQ_PIC_IRQ4 0x4 +#define PIRQ_PIC_IRQ5 0x5 +#define PIRQ_PIC_IRQ6 0x6 +#define PIRQ_PIC_IRQ7 0x7 +#define PIRQ_PIC_IRQ9 0x9 +#define PIRQ_PIC_IRQ10 0xa +#define PIRQ_PIC_IRQ11 0xb +#define PIRQ_PIC_IRQ12 0xc +#define PIRQ_PIC_IRQ14 0xe +#define PIRQ_PIC_IRQ15 0xf +#define PIRQ_PIC_IRQDISABLE 0x80 +#define PIRQ_PIC_UNKNOWN_UNUSED 0xff + +/* Overloaded term, but these values determine the per device route. */ +#define PIRQA 0 +#define PIRQB 1 +#define PIRQC 2 +#define PIRQD 3 +#define PIRQE 4 +#define PIRQF 5 +#define PIRQG 6 +#define PIRQH 7 + +#define ACPI_CNTL_OFFSET 0x44 +#define SCIS_MASK 0x07 +#define SCIS_IRQ9 0x00 +#define SCIS_IRQ10 0x01 +#define SCIS_IRQ11 0x02 +#define SCIS_IRQ20 0x04 +#define SCIS_IRQ21 0x05 +#define SCIS_IRQ22 0x06 +#define SCIS_IRQ23 0x07 + +/* In each mainboard directory there should exist a header file irqroute.h that + * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which + * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ + +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) +#include <stdint.h> + +#define NUM_OF_PCI_DEVS 32 +#define NUM_PIRQS 8 + +struct broadwell_de_irq_route { + /* Per device configuration. */ + uint16_t pcidev[NUM_OF_PCI_DEVS]; + /* Route path for each internal PIRQx in PIC mode. */ + uint8_t pic[NUM_PIRQS]; +}; + +extern const struct broadwell_de_irq_route global_broadwell_de_irq_route; + +#define DEFINE_IRQ_ROUTES \ + const struct broadwell_de_irq_route global_broadwell_de_irq_route = { \ + .pcidev = { PCI_DEV_PIRQ_ROUTES, }, \ + .pic = { PIRQ_PIC_ROUTES, }, \ + } + +#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ + [dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ + ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0) + +#define PIRQ_PIC(pirq_, pic_irq_) \ + [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_ + +#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ + +#endif /* _BROADWELL_DE_IRQ_H_ */ diff --git a/board/prodrive/Kconfig b/board/prodrive/Kconfig new file mode 100644 index 0000000..4828b65 --- /dev/null +++ b/board/prodrive/Kconfig @@ -0,0 +1,23 @@ +# +# Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +if VENDOR_PRODRIVE + +choice + prompt "Mainboard model" + optional + +config TARGET_POSEIDON + bool "Poseidon" + help + This target is for Prodrive Poseidon. + Embedded board hosting x86 Broadwell-DE Xeon processor. + +endchoice + +source "board/prodrive/poseidon/Kconfig" + +endif diff --git a/board/prodrive/poseidon/.gitignore b/board/prodrive/poseidon/.gitignore new file mode 100644 index 0000000..c782010 --- /dev/null +++ b/board/prodrive/poseidon/.gitignore @@ -0,0 +1,5 @@ +dsdt.aml +dsdt.asl.tmp +dsdt.c + +!*.bin \ No newline at end of file diff --git a/board/prodrive/poseidon/Kconfig b/board/prodrive/poseidon/Kconfig new file mode 100644 index 0000000..4fa9fef --- /dev/null +++ b/board/prodrive/poseidon/Kconfig @@ -0,0 +1,45 @@ +# +# Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> +# +# SPDX-License-Identifier: GPL-2.0+ + +if TARGET_POSEIDON + +config SYS_BOARD + default "poseidon" + +config SYS_VENDOR + default "prodrive" + +config SYS_SOC + default "broadwell-de" + +config SYS_CONFIG_NAME + default "poseidon" + +config SYS_TEXT_BASE + default 0xffdb0000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select INTEL_BROADWELL_DE + select BOARD_ROMSIZE_KB_16384 + select SPI_FLASH_MACRONIX + +config PCIE_ECAM_BASE + default 0x80000000 + +config SYS_CAR_ADDR + hex + default 0xfef00000 + +config SYS_CAR_SIZE + hex + default 0x40000 + +config SYS_PROMPT + string + default "Poseidon => " + +endif diff --git a/board/prodrive/poseidon/MAINTAINERS b/board/prodrive/poseidon/MAINTAINERS new file mode 100644 index 0000000..c21f2e6 --- /dev/null +++ b/board/prodrive/poseidon/MAINTAINERS @@ -0,0 +1,6 @@ +Prodrive Poseidon x86 Broadwell-DE +M: Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> +S: Maintained +F: board/prodrive/poseidon +F: include/configs/poseidon.h +F: configs/poseidon_defconfig diff --git a/board/prodrive/poseidon/Makefile b/board/prodrive/poseidon/Makefile new file mode 100644 index 0000000..83fd499 --- /dev/null +++ b/board/prodrive/poseidon/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += poseidon.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/prodrive/poseidon/acpi/mainboard.asl b/board/prodrive/poseidon/acpi/mainboard.asl new file mode 100644 index 0000000..4cc8ad3 --- /dev/null +++ b/board/prodrive/poseidon/acpi/mainboard.asl @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} diff --git a/board/prodrive/poseidon/dsdt.asl b/board/prodrive/poseidon/dsdt.asl new file mode 100644 index 0000000..951f320 --- /dev/null +++ b/board/prodrive/poseidon/dsdt.asl @@ -0,0 +1,187 @@ +/* + * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x20110725) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) + Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) + + Scope (\_SB) + { + Device (PCI0) + { + #include <asm/arch/acpi/southcluster.asl> + #include <asm/arch/acpi/pcie1.asl> + } + + Name (PRUN, Package() { + Package() { 0x0008FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0009FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000AFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000BFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0010FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0011FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0011FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0011FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0011FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0012FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0012FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0012FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0012FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0013FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0013FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0013FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0013FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + }) + + Name (ARUN, Package() { + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + + Package() { 0x000CFFFF, 0, 0, 16 }, + Package() { 0x000CFFFF, 1, 0, 17 }, + Package() { 0x000CFFFF, 2, 0, 18 }, + Package() { 0x000CFFFF, 3, 0, 19 }, + + Package() { 0x000DFFFF, 0, 0, 16 }, + Package() { 0x000DFFFF, 1, 0, 17 }, + Package() { 0x000DFFFF, 2, 0, 18 }, + Package() { 0x000DFFFF, 3, 0, 19 }, + + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + + Package() { 0x0011FFFF, 0, 0, 16 }, + Package() { 0x0011FFFF, 1, 0, 17 }, + Package() { 0x0011FFFF, 2, 0, 18 }, + Package() { 0x0011FFFF, 3, 0, 19 }, + + Package() { 0x0012FFFF, 0, 0, 16 }, + Package() { 0x0012FFFF, 1, 0, 17 }, + Package() { 0x0012FFFF, 2, 0, 18 }, + Package() { 0x0012FFFF, 3, 0, 19 }, + + Package() { 0x0013FFFF, 0, 0, 16 }, + Package() { 0x0013FFFF, 1, 0, 17 }, + Package() { 0x0013FFFF, 2, 0, 18 }, + Package() { 0x0013FFFF, 3, 0, 19 }, + }) + + Device (UNC0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_UID, 0x3F) + Method (_BBN, 0, NotSerialized) + { + Return (0xff) + } + + Name (_ADR, 0x00) + Method (_STA, 0, NotSerialized) + { + Return (0xf) + } + + Name (_CRS, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x00FF, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + + Method (_PRT, 0, NotSerialized) + { + If (LEqual (PICM, Zero)) + { + Return (PRUN) + } + + Return (ARUN) + } + } + } + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/configs/poseidon_defconfig b/configs/poseidon_defconfig new file mode 100644 index 0000000..accf0a1 --- /dev/null +++ b/configs/poseidon_defconfig @@ -0,0 +1,70 @@ +CONFIG_X86=y +CONFIG_SYS_CONFIG_NAME="poseidon" +CONFIG_VENDOR_PRODRIVE=y +CONFIG_DEFAULT_DEVICE_TREE="poseidon" +CONFIG_TARGET_POSEIDON=y +CONFIG_FSP_MEMORY_DOWN=y +CONFIG_HAVE_SPD=y +CONFIG_INTERNAL_UART=y +CONFIG_SMP=y +#CONFIG_HAVE_VGA_BIOS=y +#CONFIG_VGA_BIOS_ADDR=0xfffd0001 +#CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +#CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_GENERATE_PIRQ_TABLE=y +#CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_ACPI_TABLE=y +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_SEABIOS=y +CONFIG_FIT=y +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +#CONFIG_USE_BOOTARGS=y +#CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/sdb3 init=/sbin/init rootwait ro" +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_PART=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CPU=y +CONFIG_USB_STORAGE=y +CONFIG_USB_KEYBOARD=y +CONFIG_CONSOLE_SCROLL_LINES=5 +#CONFIG_CMD_IMLS=n +CONFIG_SYS_NS16550=y +#CONFIG_CMD_TPM=y +#CONFIG_CMD_TPM_TEST=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_DM_PCI=y +#CONFIG_DM_RTC=y +CONFIG_TIMER=y +#CONFIG_TPM_TIS_LPC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_UHCI_HCD=y +#CONFIG_DM_VIDEO=y +CONFIG_USE_PRIVATE_LIBGCC=y +#CONFIG_TPM=y +CONFIG_OF_CONTROL=y +CONFIG_I8259_PIC=y +CONFIG_I8254_TIMER=y diff --git a/include/configs/poseidon.h b/include/configs/poseidon.h new file mode 100644 index 0000000..739ca8e --- /dev/null +++ b/include/configs/poseidon.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2017, Vincenzo Bove <vincenzo.bove(a)prodrive-technologies.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#define CONFIG_USB_ETHER_ASIX88179 + +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, 0x8c02} + +#undef CONFIG_ENV_IS_IN_SPI_FLASH + +#define DEBUG + +#endif /* __CONFIG_H */ diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 994214e..e415f36 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -19,16 +19,20 @@ #define CONFIG_PHYSMEM #define CONFIG_DISPLAY_BOARDINFO_LATE #define CONFIG_LAST_STAGE_INIT -#define CONFIG_NR_DRAM_BANKS 8 +#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_LMB +#define CONFIG_LZO #undef CONFIG_ZLIB #undef CONFIG_GZIP #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* SATA AHCI storage */ + +#define CONFIG_SCSI_AHCI #ifdef CONFIG_SCSI_AHCI +#define CONFIG_LIBATA #define CONFIG_LBA48 #define CONFIG_SYS_64BIT_LBA @@ -58,6 +62,8 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_AUTO_COMPLETE +#define CONFIG_SUPPORT_VFAT + /*----------------------------------------------------------------------- * Command line configuration. */ @@ -74,11 +80,19 @@ */ #define CONFIG_SYS_LONGHELP #define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + \ + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_MEMTEST_START 0x00100000 #define CONFIG_SYS_MEMTEST_END 0x01000000 #define CONFIG_SYS_LOAD_ADDR 0x20000000 +/* Fat write configuration */ +#define CONFIG_FAT_WRITE + /*----------------------------------------------------------------------- * CPU Features */ @@ -98,6 +112,7 @@ /*----------------------------------------------------------------------- * Environment configuration */ +#define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SIZE 0x01000 /*----------------------------------------------------------------------- diff --git a/include/fdtdec.h b/include/fdtdec.h index 4afb9ac..ea8bff4 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -150,6 +150,7 @@ enum fdt_compat_id { COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */ COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */ COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */ + COMPAT_INTEL_BROADWELL_DE_FSP, /* Intel Broadwell-DE FSP */ COMPAT_SUNXI_NAND, /* SUNXI NAND controller */ COMPAT_ALTERA_SOCFPGA_CLK, /* SoCFPGA Clock initialization */ COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE, /* SoCFPGA pinctrl-single */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index df9d9ae..e1a2f17 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -62,6 +62,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"), COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"), COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"), + COMPAT(INTEL_BROADWELL_DE_FSP, "intel,broadwell-de-fsp"), COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"), COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"), COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"), diff --git a/tools/binman/etype/intel_spd.py b/tools/binman/etype/intel_spd.py new file mode 100644 index 0000000..028c98f --- /dev/null +++ b/tools/binman/etype/intel_spd.py @@ -0,0 +1,14 @@ +# Copyright (c) 2016 Google, Inc +# Written by Simon Glass <sjg(a)chromium.org> +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Entry-type module for Intel Management Engine binary blob +# + +from entry import Entry +from blob import Entry_blob + +class Entry_intel_spd(Entry_blob): + def __init__(self, image, etype, node): + Entry_blob.__init__(self, image, etype, node) \ No newline at end of file -- 2.9.2.windows.1

3 3

[U-Boot] [PATCH] usb: dwc2: Rename CONFIG_DWC2_UTMI_PHY_WIDTH to CONFIG_DWC2_UTMI_WIDTH
by Alexey Brodkin 05 Feb '18

05 Feb '18

For some reason from day one we used to have both CONFIG_DWC2_UTMI_WIDTH mentioned in dwc2.h and in scripts/config_whitelist.txt but never really used and CONFIG_DWC2_UTMI_PHY_WIDTH used in real code in dwc2.c (but never defined). Moreover even though CONFIG_DWC2_UTMI_WIDTH might be either 8 or 16 depending on hardware (and the same is said in a comment for it in dwc2.h) but then 8 is hardcoded in the header leaving no ability to override this value in board's configuration. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> Cc: Marek Vasut <marex(a)denx.de> --- drivers/usb/host/dwc2.c | 2 +- drivers/usb/host/dwc2.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index 1293e18f75e7..784fcbdbd94f 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -375,7 +375,7 @@ static void dwc_otg_core_init(struct dwc2_priv *priv) usbcfg &= ~DWC2_GUSBCFG_DDRSEL; #endif } else { /* UTMI+ interface */ -#if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16) +#if (CONFIG_DWC2_UTMI_WIDTH == 16) usbcfg |= DWC2_GUSBCFG_PHYIF; #endif } diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h index 4482dc621d69..574607a2acbb 100644 --- a/drivers/usb/host/dwc2.h +++ b/drivers/usb/host/dwc2.h @@ -775,7 +775,9 @@ struct dwc2_core_regs { #define DWC2_PHY_TYPE_UTMI 1 #define DWC2_PHY_TYPE_ULPI 2 #define CONFIG_DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */ +#ifndef CONFIG_DWC2_UTMI_WIDTH #define CONFIG_DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */ +#endif #undef CONFIG_DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */ #define CONFIG_DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */ -- 2.14.3

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[U-Boot] [PATCH v4 2/2] imx: mx7: run sec_init for CAAM RNG
by Bryan O'Donoghue 05 Feb '18

05 Feb '18

This patch adds a sec_init call into arch_misc_init(). Doing so in conjunction with the patch "drivers/crypto/fsl: assign job-rings to non-TrustZone" enables use of the CAAM in Linux when OPTEE/TrustZone is active. u-boot will initialise the RNG and assign ownership of the job-ring registers to a non-TrustZone context. With recent changes by Lukas Auer to fully initialize the RNG in sec_init() this means that u-boot will hand-off the CAAM in a state that Linux then can use the CAAM without touching the reserved DECO registers. This change is safe both for the OPTEE/TrustZone boot path and the regular non-OPTEE/TrustZone boot path. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue(a)linaro.org> Cc: Fabio Estevam <fabio.estevam(a)nxp.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Marco Franchi <marco.franchi(a)nxp.com> Cc: Vanessa Maegima <vanessa.maegima(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Lukas Auer <lukas.auer(a)aisec.fraunhofer.de> --- arch/arm/mach-imx/mx7/soc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index d160e80..d444046 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -17,6 +17,7 @@ #include <asm/arch/crm_regs.h> #include <dm.h> #include <imx_thermal.h> +#include <fsl_sec.h> #if defined(CONFIG_IMX_THERMAL) static const struct imx_thermal_plat imx7_thermal_plat = { @@ -262,6 +263,10 @@ int arch_misc_init(void) env_set("soc", "imx7s"); #endif +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + return 0; } #endif -- 2.7.4

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