August 2017 - U-Boot

[U-Boot] [PATCH V2 1/5] mmc: uniphier-sd: Factor out register IO
by Marek Vasut 07 Aug '17

07 Aug '17

This patch prepares the driver to support controller(s) with registers at locations shifted by constant. Pull out the readl()/writel() from the driver into separate functions, where the adjustment of the register offset can be easily contained. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Masahiro Yamada <yamada.masahiro(a)socionext.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> --- V2: Use unsigned int for the reg argument --- drivers/mmc/uniphier-sd.c | 115 +++++++++++++++++++++++++--------------------- 1 file changed, 63 insertions(+), 52 deletions(-) diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c index e272b14153..b5c608d866 100644 --- a/drivers/mmc/uniphier-sd.c +++ b/drivers/mmc/uniphier-sd.c @@ -134,6 +134,17 @@ struct uniphier_sd_priv { #define UNIPHIER_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */ }; +static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, unsigned int reg) +{ + return readl(priv->regbase + reg); +} + +static void uniphier_sd_writel(struct uniphier_sd_priv *priv, + const u32 val, unsigned int reg) +{ + writel(val, priv->regbase + reg); +} + static dma_addr_t __dma_map_single(void *ptr, size_t size, enum dma_data_direction dir) { @@ -157,7 +168,7 @@ static void __dma_unmap_single(dma_addr_t addr, size_t size, static int uniphier_sd_check_error(struct udevice *dev) { struct uniphier_sd_priv *priv = dev_get_priv(dev); - u32 info2 = readl(priv->regbase + UNIPHIER_SD_INFO2); + u32 info2 = uniphier_sd_readl(priv, UNIPHIER_SD_INFO2); if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) { /* @@ -195,7 +206,7 @@ static int uniphier_sd_wait_for_irq(struct udevice *dev, unsigned int reg, long wait = 1000000; int ret; - while (!(readl(priv->regbase + reg) & flag)) { + while (!(uniphier_sd_readl(priv, reg) & flag)) { if (wait-- < 0) { dev_err(dev, "timeout\n"); return -ETIMEDOUT; @@ -227,14 +238,14 @@ static int uniphier_sd_pio_read_one_block(struct udevice *dev, u32 **pbuf, * Clear the status flag _before_ read the buffer out because * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered. */ - writel(0, priv->regbase + UNIPHIER_SD_INFO2); + uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2); if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) { for (i = 0; i < blocksize / 4; i++) - *(*pbuf)++ = readl(priv->regbase + UNIPHIER_SD_BUF); + *(*pbuf)++ = uniphier_sd_readl(priv, UNIPHIER_SD_BUF); } else { for (i = 0; i < blocksize / 4; i++) - put_unaligned(readl(priv->regbase + UNIPHIER_SD_BUF), + put_unaligned(uniphier_sd_readl(priv, UNIPHIER_SD_BUF), (*pbuf)++); } @@ -253,15 +264,15 @@ static int uniphier_sd_pio_write_one_block(struct udevice *dev, if (ret) return ret; - writel(0, priv->regbase + UNIPHIER_SD_INFO2); + uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2); if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) { for (i = 0; i < blocksize / 4; i++) - writel(*(*pbuf)++, priv->regbase + UNIPHIER_SD_BUF); + uniphier_sd_writel(priv, *(*pbuf)++, UNIPHIER_SD_BUF); } else { for (i = 0; i < blocksize / 4; i++) - writel(get_unaligned((*pbuf)++), - priv->regbase + UNIPHIER_SD_BUF); + uniphier_sd_writel(priv, get_unaligned((*pbuf)++), + UNIPHIER_SD_BUF); } return 0; @@ -292,22 +303,22 @@ static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv, { u32 tmp; - writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO1); - writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO2); + uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO1); + uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO2); /* enable DMA */ - tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE); + tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE); tmp |= UNIPHIER_SD_EXTMODE_DMA_EN; - writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE); - writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_L); + uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_L); /* suppress the warning "right shift count >= width of type" */ dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr)); - writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_H); + uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_H); - writel(UNIPHIER_SD_DMA_CTL_START, priv->regbase + UNIPHIER_SD_DMA_CTL); + uniphier_sd_writel(priv, UNIPHIER_SD_DMA_CTL_START, UNIPHIER_SD_DMA_CTL); } static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag, @@ -316,7 +327,7 @@ static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag, struct uniphier_sd_priv *priv = dev_get_priv(dev); long wait = 1000000 + 10 * blocks; - while (!(readl(priv->regbase + UNIPHIER_SD_DMA_INFO1) & flag)) { + while (!(uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO1) & flag)) { if (wait-- < 0) { dev_err(dev, "timeout during DMA\n"); return -ETIMEDOUT; @@ -325,7 +336,7 @@ static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag, udelay(10); } - if (readl(priv->regbase + UNIPHIER_SD_DMA_INFO2)) { + if (uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO2)) { dev_err(dev, "error during DMA\n"); return -EIO; } @@ -343,7 +354,7 @@ static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data) u32 poll_flag, tmp; int ret; - tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE); + tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE); if (data->flags & MMC_DATA_READ) { buf = data->dest; @@ -357,7 +368,7 @@ static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data) tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD; } - writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE); dma_addr = __dma_map_single(buf, len, dir); @@ -396,27 +407,27 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, int ret; u32 tmp; - if (readl(priv->regbase + UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) { + if (uniphier_sd_readl(priv, UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) { dev_err(dev, "command busy\n"); return -EBUSY; } /* clear all status flags */ - writel(0, priv->regbase + UNIPHIER_SD_INFO1); - writel(0, priv->regbase + UNIPHIER_SD_INFO2); + uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO1); + uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2); /* disable DMA once */ - tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE); + tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE); tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN; - writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE); - writel(cmd->cmdarg, priv->regbase + UNIPHIER_SD_ARG); + uniphier_sd_writel(priv, cmd->cmdarg, UNIPHIER_SD_ARG); tmp = cmd->cmdidx; if (data) { - writel(data->blocksize, priv->regbase + UNIPHIER_SD_SIZE); - writel(data->blocks, priv->regbase + UNIPHIER_SD_SECCNT); + uniphier_sd_writel(priv, data->blocksize, UNIPHIER_SD_SIZE); + uniphier_sd_writel(priv, data->blocks, UNIPHIER_SD_SECCNT); /* Do not send CMD12 automatically */ tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA; @@ -457,7 +468,7 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n", cmd->cmdidx, tmp, cmd->cmdarg); - writel(tmp, priv->regbase + UNIPHIER_SD_CMD); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CMD); ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1, UNIPHIER_SD_INFO1_RSP); @@ -465,10 +476,10 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, return ret; if (cmd->resp_type & MMC_RSP_136) { - u32 rsp_127_104 = readl(priv->regbase + UNIPHIER_SD_RSP76); - u32 rsp_103_72 = readl(priv->regbase + UNIPHIER_SD_RSP54); - u32 rsp_71_40 = readl(priv->regbase + UNIPHIER_SD_RSP32); - u32 rsp_39_8 = readl(priv->regbase + UNIPHIER_SD_RSP10); + u32 rsp_127_104 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP76); + u32 rsp_103_72 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP54); + u32 rsp_71_40 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP32); + u32 rsp_39_8 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10); cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) | ((rsp_103_72 & 0xff000000) >> 24); @@ -479,7 +490,7 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, cmd->response[3] = (rsp_39_8 & 0xffffff) << 8; } else { /* bit 39-8 */ - cmd->response[0] = readl(priv->regbase + UNIPHIER_SD_RSP10); + cmd->response[0] = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10); } if (data) { @@ -518,10 +529,10 @@ static int uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv, return -EINVAL; } - tmp = readl(priv->regbase + UNIPHIER_SD_OPTION); + tmp = uniphier_sd_readl(priv, UNIPHIER_SD_OPTION); tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK; tmp |= val; - writel(tmp, priv->regbase + UNIPHIER_SD_OPTION); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_OPTION); return 0; } @@ -531,12 +542,12 @@ static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv, { u32 tmp; - tmp = readl(priv->regbase + UNIPHIER_SD_IF_MODE); + tmp = uniphier_sd_readl(priv, UNIPHIER_SD_IF_MODE); if (mmc->ddr_mode) tmp |= UNIPHIER_SD_IF_MODE_DDR; else tmp &= ~UNIPHIER_SD_IF_MODE_DDR; - writel(tmp, priv->regbase + UNIPHIER_SD_IF_MODE); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_IF_MODE); } static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv, @@ -573,21 +584,21 @@ static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv, else val = UNIPHIER_SD_CLKCTL_DIV1024; - tmp = readl(priv->regbase + UNIPHIER_SD_CLKCTL); + tmp = uniphier_sd_readl(priv, UNIPHIER_SD_CLKCTL); if (tmp & UNIPHIER_SD_CLKCTL_SCLKEN && (tmp & UNIPHIER_SD_CLKCTL_DIV_MASK) == val) return; /* stop the clock before changing its rate to avoid a glitch signal */ tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN; - writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL); tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK; tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN; - writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL); tmp |= UNIPHIER_SD_CLKCTL_SCLKEN; - writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL); udelay(1000); } @@ -617,7 +628,7 @@ static int uniphier_sd_get_cd(struct udevice *dev) if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE) return 1; - return !!(readl(priv->regbase + UNIPHIER_SD_INFO1) & + return !!(uniphier_sd_readl(priv, UNIPHIER_SD_INFO1) & UNIPHIER_SD_INFO1_CD); } @@ -632,28 +643,28 @@ static void uniphier_sd_host_init(struct uniphier_sd_priv *priv) u32 tmp; /* soft reset of the host */ - tmp = readl(priv->regbase + UNIPHIER_SD_SOFT_RST); + tmp = uniphier_sd_readl(priv, UNIPHIER_SD_SOFT_RST); tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX; - writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST); tmp |= UNIPHIER_SD_SOFT_RST_RSTX; - writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST); /* FIXME: implement eMMC hw_reset */ - writel(UNIPHIER_SD_STOP_SEC, priv->regbase + UNIPHIER_SD_STOP); + uniphier_sd_writel(priv, UNIPHIER_SD_STOP_SEC, UNIPHIER_SD_STOP); /* * Connected to 32bit AXI. * This register dropped backward compatibility at version 0x10. * Write an appropriate value depending on the IP version. */ - writel(priv->version >= 0x10 ? 0x00000101 : 0x00000000, - priv->regbase + UNIPHIER_SD_HOST_MODE); + uniphier_sd_writel(priv, priv->version >= 0x10 ? 0x00000101 : 0x00000000, + UNIPHIER_SD_HOST_MODE); if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) { - tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE); + tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE); tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC; - writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE); } } @@ -724,7 +735,7 @@ static int uniphier_sd_probe(struct udevice *dev) NULL)) priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE; - priv->version = readl(priv->regbase + UNIPHIER_SD_VERSION) & + priv->version = uniphier_sd_readl(priv, UNIPHIER_SD_VERSION) & UNIPHIER_SD_VERSION_IP; dev_dbg(dev, "version %x\n", priv->version); if (priv->version >= 0x10) { -- 2.11.0

1 4

[U-Boot] [PATCH 0/5] Add intermediate driver(cff driver) between flash & FPGA
by tien.fong.chee＠intel.com 07 Aug '17

07 Aug '17

From: Tien Fong Chee <tien.fong.chee(a)intel.com> This patchset adding intermediate driver called cff driver to support all the FPGA program operations between FPGA manager and flash. Tien Fong Chee (5): arm: socfpga: Add checking function on searching boot device arm: socfpga: Add checking function on FPGA setting in FDT configs: socfpga: Add config for RBF loading from FAT fs arm: socfpga: Add intermediate driver between flash and FPGA manager arm: socfpga: Enable cff driver build arch/arm/mach-socfpga/Kconfig | 7 + arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/cff.c | 581 +++++++++++++++++++++++++++++ arch/arm/mach-socfpga/include/mach/cff.h | 40 ++ arch/arm/mach-socfpga/include/mach/misc.h | 20 + arch/arm/mach-socfpga/misc_arria10.c | 42 ++ include/configs/socfpga_arria10_socdk.h | 6 + 7 files changed, 697 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-socfpga/cff.c create mode 100644 arch/arm/mach-socfpga/include/mach/cff.h -- 1.7.7.4

3 19

[U-Boot] [PATCHv4 0/2] ARM: sunxi: Add support for OLinuXino Lime2 eMMC
by Olliver Schinagl 07 Aug '17

07 Aug '17

This patch series adds support for the Olimex OLinuXino Lime2 eMMC. This assembly variant uses eMMC flash instead of NAND (or no flash) on the other Lime2's. Additionally, we sync the dts with upstream as we now use this dts from the new defconfig. Changes since v3: * Added my signed-off-by to Emanuel's upstream kernel pach Changes since v2: * Converted these two patches into a patch-series Changes since v1: * Rebased with master Emmanuel Vadot (1): ARM: dts: sunxi: Change node name for pwrseq pin on Olinuxino-lime2-emmc Olliver Schinagl (1): sun7i: Add support for Olimex A20-OLinuXino-LIME2-eMMC arch/arm/dts/sun7i-a20-olinuxino-lime2-emmc.dts | 2 +- board/sunxi/MAINTAINERS | 5 ++++ configs/A20-OLinuXino-Lime2-eMMC_defconfig | 36 +++++++++++++++++++++++++ 3 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 configs/A20-OLinuXino-Lime2-eMMC_defconfig -- 2.11.0

3 6

[U-Boot] [PATCH v2 0/3] power: Add a driver to handle the PBIAS cell of the TI SOCs
by Jean-Jacques Hiblot 07 Aug '17

07 Aug '17

In the TI SOCs a PBIAS cell exists to provide a bias voltage to the MMC1 IO cells. Without this bias voltage these I/O cells can not function properly. This bias voltage is either 1.8v or 3.0v. The first patch adds 2 functions to the DM core: to count strings in a stringlist and get a string from a stringlist based on its position in the list. The second patch implements the support for this PBIAS cell as a regulator driver. The last patch is here to allow the binding of the driver. In the DTS of the dra7x and am57x platforms, the pbias entry is a child of a syscon. changes since v1: - add new functions to get strings from a stringlist in DM core - use the dev_read_*() API to access the DT - automatically select the PBIAS driver if DM_REGULATOR, DM_MMC and MMC_OMAP_HS are set. - removed the patch touching the DRA7 and AM57 config files. Jean-Jacques Hiblot (3): dm: core: Add functions to get strings and the string count from a stringlist regulator: pbias: Add PBIAS regulator for proper voltage switching on MMC1 dm: syscon: scan sub-nodes of the syscon node drivers/core/read.c | 11 ++ drivers/core/syscon-uclass.c | 1 + drivers/mmc/Kconfig | 1 + drivers/power/regulator/Kconfig | 10 + drivers/power/regulator/Makefile | 1 + drivers/power/regulator/pbias_regulator.c | 302 ++++++++++++++++++++++++++++++ include/dm/read.h | 36 ++++ 7 files changed, 362 insertions(+) create mode 100644 drivers/power/regulator/pbias_regulator.c -- 1.9.1

2 9

[U-Boot] [PATCH v2] m68k: add board stmark2, mcf5441x based
by Angelo Dureghello 07 Aug '17

07 Aug '17

Sysam stmark2 board is a generic and fully (hw and sw) open board, with a mcf54415 Coldfire CPU, 128MB of DDR2, 16MB of SPI flash and SD card as non volatile memories, and a wifi module included on-board. The board is actually used mainly for Coldfire custodian testing activity related to the mcf5441x Coldfire family. For further information please see: http://sysam.it/cff_stmark2.html Signed-off-by: Angelo Dureghello <angelo(a)sysam.it> --- Changes in v2: - remove CMD_REGINFO - add board information in commit message --- arch/m68k/Kconfig | 5 + board/sysam/stmark2/Kconfig | 15 +++ board/sysam/stmark2/MAINTAINERS | 6 ++ board/sysam/stmark2/Makefile | 8 ++ board/sysam/stmark2/sbf_dram_init.S | 119 +++++++++++++++++++++ board/sysam/stmark2/stmark2.c | 47 +++++++++ configs/stmark2_defconfig | 26 +++++ include/configs/stmark2.h | 199 ++++++++++++++++++++++++++++++++++++ scripts/config_whitelist.txt | 1 + 9 files changed, 426 insertions(+) create mode 100644 board/sysam/stmark2/Kconfig create mode 100644 board/sysam/stmark2/MAINTAINERS create mode 100644 board/sysam/stmark2/Makefile create mode 100644 board/sysam/stmark2/sbf_dram_init.S create mode 100644 board/sysam/stmark2/stmark2.c create mode 100644 configs/stmark2_defconfig create mode 100644 include/configs/stmark2.h diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 88e7d6a7b6..ce30e97935 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -208,6 +208,10 @@ config TARGET_AMCORE bool "Support AMCORE" select M5307 +config TARGET_STMARK2 + bool "Support stmark2" + select M54418 + endchoice source "board/BuS/eb_cpu5282/Kconfig" @@ -231,5 +235,6 @@ source "board/freescale/m54455evb/Kconfig" source "board/freescale/m547xevb/Kconfig" source "board/freescale/m548xevb/Kconfig" source "board/sysam/amcore/Kconfig" +source "board/sysam/stmark2/Kconfig" endmenu diff --git a/board/sysam/stmark2/Kconfig b/board/sysam/stmark2/Kconfig new file mode 100644 index 0000000000..87ab7ab7b5 --- /dev/null +++ b/board/sysam/stmark2/Kconfig @@ -0,0 +1,15 @@ +if TARGET_STMARK2 + +config SYS_CPU + default "mcf5445x" + +config SYS_BOARD + default "stmark2" + +config SYS_VENDOR + default "sysam" + +config SYS_CONFIG_NAME + default "stmark2" + +endif diff --git a/board/sysam/stmark2/MAINTAINERS b/board/sysam/stmark2/MAINTAINERS new file mode 100644 index 0000000000..b87f432bb3 --- /dev/null +++ b/board/sysam/stmark2/MAINTAINERS @@ -0,0 +1,6 @@ +STMARK2 BOARD +M: Angelo Dureghello <angelo(a)sysam.it> +S: Maintained +F: board/sysam/stmark2/ +F: include/configs/stmark2.h +F: configs/stmark2_defconfig diff --git a/board/sysam/stmark2/Makefile b/board/sysam/stmark2/Makefile new file mode 100644 index 0000000000..064a57ea05 --- /dev/null +++ b/board/sysam/stmark2/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2014 Angelo Dureghello <angelo(a)sysam.it> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = stmark2.o +extra-y += sbf_dram_init.o diff --git a/board/sysam/stmark2/sbf_dram_init.S b/board/sysam/stmark2/sbf_dram_init.S new file mode 100644 index 0000000000..52abda5c3c --- /dev/null +++ b/board/sysam/stmark2/sbf_dram_init.S @@ -0,0 +1,119 @@ +/* + * Board-specific early ddr/sdram init. + * + * (C) Copyright 2017 Angelo Dureghello <angelo(a)sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.equ PPMCR0, 0xfc04002d +.equ MSCR_SDRAMC, 0xec094060 +.equ MISCCR2, 0xec09001a +.equ DDR_RCR, 0xfc0b8180 +.equ DDR_PADCR, 0xfc0b81ac +.equ DDR_CR00, 0xfc0b8000 +.equ DDR_CR06, 0xfc0b8018 +.equ DDR_CR09, 0xfc0b8024 +.equ DDR_CR40, 0xfc0b80a0 +.equ DDR_CR45, 0xfc0b80b4 +.equ DDR_CR56, 0xfc0b80e0 + +.global sbf_dram_init +.text + +sbf_dram_init: + /* CD46 = DDR on */ + move.l #PPMCR0, %a1 + move.b #46, (%a1) + + /* stmark 2, max drive strength */ + move.l #MSCR_SDRAMC, %a1 + move.b #1, (%a1) + + /* + * use cpu clock, seems more realiable + * + * DDR2 clock is serviced from DDR controller as input clock / 2 + * so, if clock comes from + * vco, i.e. 480(vco) / 2, so ddr clock is 240 Mhz (measured) + * cpu, i.e. 250(cpu) / 2, so ddr clock is 125 Mhz (measured) + * + * . + * / \ DDR2 can't be clocked lower than 125Mhz + * / ! \ DDR2 init must pass further i/dcache enable test + * /_____\ + * WARNING + */ + + /* cpu / 2 = 125 Mhz for 480 Mhz pll */ + move.l #MISCCR2, %a1 + move.w #0xa01d, (%a1) + + /* DDR force sw reset settings */ + move.l #DDR_RCR, %a1 + move.l #0x00000000, (%a1) + move.l #0x40000000, (%a1) + + /* + * PAD_ODT_CS: for us seems both 1(75 ohm) and 2(150ohm) are good, + * 500/700 mV are ok + */ + move.l #DDR_PADCR, %a1 + move.l #0x01030203, (%a1) /* as freescale tower */ + + move.l #DDR_CR00, %a1 + move.l #0x01010101, (%a1)+ /* 0x00 */ + move.l #0x00000101, (%a1)+ /* 0x04 */ + move.l #0x01010100, (%a1)+ /* 0x08 */ + move.l #0x01010000, (%a1)+ /* 0x0C */ + move.l #0x00010101, (%a1)+ /* 0x10 */ + move.l #DDR_CR06, %a1 + move.l #0x00010100, (%a1)+ /* 0x18 */ + move.l #0x00000001, (%a1)+ /* 0x1C */ + move.l #0x01000001, (%a1)+ /* 0x20 */ + move.l #0x00000100, (%a1)+ /* 0x24 */ + move.l #0x00010001, (%a1)+ /* 0x28 */ + move.l #0x00000200, (%a1)+ /* 0x2C */ + move.l #0x01000002, (%a1)+ /* 0x30 */ + move.l #0x00000000, (%a1)+ /* 0x34 */ + move.l #0x00000100, (%a1)+ /* 0x38 */ + move.l #0x02000100, (%a1)+ /* 0x3C */ + move.l #0x02000407, (%a1)+ /* 0x40 */ + move.l #0x02030007, (%a1)+ /* 0x44 */ + move.l #0x02000100, (%a1)+ /* 0x48 */ + move.l #0x0A030203, (%a1)+ /* 0x4C */ + move.l #0x00020708, (%a1)+ /* 0x50 */ + move.l #0x00050008, (%a1)+ /* 0x54 */ + move.l #0x04030002, (%a1)+ /* 0x58 */ + move.l #0x00000004, (%a1)+ /* 0x5C */ + move.l #0x020A0000, (%a1)+ /* 0x60 */ + move.l #0x0C00000E, (%a1)+ /* 0x64 */ + move.l #0x00002004, (%a1)+ /* 0x68 */ + move.l #0x00000000, (%a1)+ /* 0x6C */ + move.l #0x00100010, (%a1)+ /* 0x70 */ + move.l #0x00100010, (%a1)+ /* 0x74 */ + move.l #0x00000000, (%a1)+ /* 0x78 */ + move.l #0x07990000, (%a1)+ /* 0x7C */ + move.l #DDR_CR40, %a1 + move.l #0x00000000, (%a1)+ /* 0xA0 */ + move.l #0x00C80064, (%a1)+ /* 0xA4 */ + move.l #0x44520002, (%a1)+ /* 0xA8 */ + move.l #0x00C80023, (%a1)+ /* 0xAC */ + move.l #DDR_CR45, %a1 + move.l #0x0000C350, (%a1) /* 0xB4 */ + move.l #DDR_CR56, %a1 + move.l #0x04000000, (%a1)+ /* 0xE0 */ + move.l #0x03000304, (%a1)+ /* 0xE4 */ + move.l #0x40040000, (%a1)+ /* 0xE8 */ + move.l #0xC0004004, (%a1)+ /* 0xEC */ + move.l #0x0642C000, (%a1)+ /* 0xF0 */ + move.l #0x00000642, (%a1)+ /* 0xF4 */ + move.l #DDR_CR09, %a1 + tpf + move.l #0x01000100, (%a1) /* 0x24 */ + + move.l #0x2000, %d1 + bsr asm_delay + + + rts diff --git a/board/sysam/stmark2/stmark2.c b/board/sysam/stmark2/stmark2.c new file mode 100644 index 0000000000..4f291ab6d6 --- /dev/null +++ b/board/sysam/stmark2/stmark2.c @@ -0,0 +1,47 @@ +/* + * Board-specific init. + * + * (C) Copyright 2017 Angelo Dureghello <angelo(a)sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spi.h> +#include <asm/io.h> +#include <asm/immap.h> +#include <mmc.h> +#include <fsl_esdhc.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + /* + * need to to: + * Check serial flash size. if 2mb evb, else 8mb demo + */ + puts("Board: "); + puts("Sysam stmark2\n"); + return 0; +} + +int dram_init(void) +{ + u32 dramsize; + + /* + * Serial Boot: The dram is already initialized in start.S + * only require to return DRAM size + */ + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + + gd->ram_size = dramsize; + + return 0; +} + +int testdram(void) +{ + return 0; +} diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig new file mode 100644 index 0000000000..cf3625c281 --- /dev/null +++ b/configs/stmark2_defconfig @@ -0,0 +1,26 @@ +CONFIG_M68K=y +CONFIG_SYS_TEXT_BASE=0x47E00000 +CONFIG_TARGET_STMARK2=y +CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=30000000" +# CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="stmark2 $ " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_LOADB=y +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_CACHE=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_REGEX=y diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h new file mode 100644 index 0000000000..5f711d03d8 --- /dev/null +++ b/include/configs/stmark2.h @@ -0,0 +1,199 @@ +/* + * Sysam stmark2 board configuration + * + * (C) Copyright 2017 Angelo Dureghello <angelo(a)sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __STMARK2_CONFIG_H +#define __STMARK2_CONFIG_H + +#define CONFIG_STMARK2 +#define CONFIG_HOSTNAME stmark2 + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT 0 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#define LDS_BOARD_TEXT \ + board/sysam/stmark2/sbf_dram_init.o (.text*) + +#define CONFIG_TIMESTAMP + +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 root=/dev/ram0 rw " \ + "rootfstype=ramfs " \ + "rdinit=/bin/init " \ + "devtmpfs.mount=1" + +#define CONFIG_BOOTCOMMAND \ + "sf probe 0:1 50000000; " \ + "sf read ${loadaddr} 0x100000 ${kern_size}; " \ + "bootm ${loadaddr}" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kern_size=0x700000\0" \ + "loadaddr=0x40001000\0" \ + "-(rootfs)\0" \ + "update_uboot=loady ${loadaddr}; " \ + "sf probe 0:1 50000000; " \ + "sf erase 0 0x80000; " \ + "sf write ${loadaddr} 0 ${filesize}\0" \ + "update_kernel=loady ${loadaddr}; " \ + "setenv kern_size ${filesize}; saveenv; " \ + "sf probe 0:1 50000000; " \ + "sf erase 0x100000 0x700000; " \ + "sf write ${loadaddr} 0x100000 ${filesize}\0" \ + "update_rootfs=loady ${loadaddr}; " \ + "sf probe 0:1 50000000; " \ + "sf erase 0x00800000 0x100000; " \ + "sf write ${loadaddr} 0x00800000 ${filesize}\0" \ + "" + +/* Realtime clock */ +#undef CONFIG_MCFRTC +#define CONFIG_RTC_MCFRRTC +#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 + +/* spi not partitions */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define MTDIDS_DEFAULT "nor0=spi-flash.0" +#define MTDPARTS_DEFAULT \ + "mtdparts=spi-flash.0:" \ + "1m(u-boot)," \ + "7m(kernel)," \ + "-(rootfs)" + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* DSPI and Serial Flash */ +#define CONFIG_CF_SPI +#define CONFIG_CF_DSPI +#define CONFIG_SF_DEFAULT_SPEED 50000000 +#define CONFIG_SERIAL_FLASH +#define CONFIG_HARD_SPI +#define CONFIG_SPI_FLASH_ISSI +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 1 + +#define CONFIG_SYS_SBFHDR_SIZE 0x7 + +#define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ + DSPI_CTAR_PCSSCK_1CLK | \ + DSPI_CTAR_PASC(0) | \ + DSPI_CTAR_PDT(0) | \ + DSPI_CTAR_CSSCK(0) | \ + DSPI_CTAR_ASC(0) | \ + DSPI_CTAR_DT(1) | \ + DSPI_CTAR_BR(6)) +#define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) +#define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) + +/* Input, PCI, Flexbus, and VCO */ +#define CONFIG_EXTRA_CLOCK + +#define CONFIG_PRAM 2048 /* 2048 KB */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) +#define CONFIG_SYS_MBAR 0xFC000000 + +/* + * Definitions for initial stack pointer and data area (in internal SRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +/* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) - 32) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ + +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) +#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) +#define CONFIG_SYS_DRAM_TEST + +#if defined(CONFIG_CF_SBF) +#define CONFIG_SERIAL_BOOT +#endif + +#if defined(CONFIG_SERIAL_BOOT) +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) +#else +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif + +#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) +/* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) +/* Reserve 256 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (256 << 10) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +/* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ + +#if defined(CONFIG_CF_SBF) +#define CONFIG_ENV_IS_IN_SPI_FLASH 1 +#define CONFIG_ENV_SPI_CS 1 +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#endif + +#undef CONFIG_ENV_OVERWRITE + +/* Cache Configuration */ +#define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ + CF_CACR_ICINVA | CF_CACR_EUSP) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + +#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 12) + +#endif /* __STMARK2_CONFIG_H */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 3b5c17a982..15b5099c12 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2340,6 +2340,7 @@ CONFIG_STM32_GPIO CONFIG_STM32_HSE_HZ CONFIG_STM32_HZ CONFIG_STM32_SERIAL +CONFIG_STMARK2 CONFIG_STRIDER CONFIG_STRIDER_CON CONFIG_STRIDER_CON_DP -- 2.13.3

1 0

[U-Boot] Remove STM32F1 support ?
by Patrice CHOTARD 07 Aug '17

07 Aug '17

Hi Matt, Kamil I currently doing some work on STM32 SoCs on U-boot, more precisely code factorization between STYM32F4, STM32F7 and STM32H7 I noticed you added STM32F1 SoCs support few years ago : 0144caf22ce6acd5c gpio: stm32: add stm32f1 support 2d18ef2364fd3561a ARMv7M: add STM32F1 support But neither STM32F1 dedicated defconfig nor board was associated to these commits. In order to facilitate the cleaning work i am currently doing, can i removed STM32F1 support ? (ie all files located in arch/arm/mach-stm32/stm32f1 and in arch/arm/include/asm/arch-stm32f1) Regards Patrice

3 2

[U-Boot] [PATCH 0/4] Fix compile failure encountered on u-boot-usb tree (2017-07-20)
by patrice.chotard＠st.com 06 Aug '17

06 Aug '17

From: Patrice Chotard <patrice.chotard(a)st.com> This series fixes : _ compilation issue reported by Ran Wang on u-boot-usb branch _ add last minute fixes for both generic-ehci and generic_ohci drivers which avoid to init a generic PHY if not found, reported by Patrick Delaunay This series need an additionnal patch from Jean-Jacques Hiblot : [PATCH v2] phy: add a NO-OP phy driver Patrice Chotard (4): dm: phy: add missing #ifdef CONFIG_PHY dm: usb: host: xhci-dwc3: add missing #ifdef CONFIG_DM_USB usb: host: ehci-generic: initialize PHY only when found usb: host: ohci-generic: initialize PHY only when found drivers/usb/host/ehci-generic.c | 11 ++++++----- drivers/usb/host/ohci-generic.c | 11 ++++++----- drivers/usb/host/xhci-dwc3.c | 2 ++ include/generic-phy.h | 42 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 56 insertions(+), 10 deletions(-) -- 1.9.1

5 16

[U-Boot] [PATCH] m68k: add board stmark2, mcf5441x based
by Angelo Dureghello 06 Aug '17

06 Aug '17

Signed-off-by: Angelo Dureghello <angelo(a)sysam.it> --- arch/m68k/Kconfig | 5 + board/sysam/stmark2/Kconfig | 15 +++ board/sysam/stmark2/MAINTAINERS | 6 ++ board/sysam/stmark2/Makefile | 8 ++ board/sysam/stmark2/sbf_dram_init.S | 119 +++++++++++++++++++++ board/sysam/stmark2/stmark2.c | 47 +++++++++ configs/stmark2_defconfig | 26 +++++ include/configs/stmark2.h | 202 ++++++++++++++++++++++++++++++++++++ scripts/config_whitelist.txt | 1 + 9 files changed, 429 insertions(+) create mode 100644 board/sysam/stmark2/Kconfig create mode 100644 board/sysam/stmark2/MAINTAINERS create mode 100644 board/sysam/stmark2/Makefile create mode 100644 board/sysam/stmark2/sbf_dram_init.S create mode 100644 board/sysam/stmark2/stmark2.c create mode 100644 configs/stmark2_defconfig create mode 100644 include/configs/stmark2.h diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 26509b73c6..42fb91539a 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -200,6 +200,10 @@ config TARGET_AMCORE bool "Support AMCORE" select M5307 +config TARGET_STMARK2 + bool "Support stmark2" + select M54418 + endchoice source "board/BuS/eb_cpu5282/Kconfig" @@ -223,5 +227,6 @@ source "board/freescale/m54455evb/Kconfig" source "board/freescale/m547xevb/Kconfig" source "board/freescale/m548xevb/Kconfig" source "board/sysam/amcore/Kconfig" +source "board/sysam/stmark2/Kconfig" endmenu diff --git a/board/sysam/stmark2/Kconfig b/board/sysam/stmark2/Kconfig new file mode 100644 index 0000000000..87ab7ab7b5 --- /dev/null +++ b/board/sysam/stmark2/Kconfig @@ -0,0 +1,15 @@ +if TARGET_STMARK2 + +config SYS_CPU + default "mcf5445x" + +config SYS_BOARD + default "stmark2" + +config SYS_VENDOR + default "sysam" + +config SYS_CONFIG_NAME + default "stmark2" + +endif diff --git a/board/sysam/stmark2/MAINTAINERS b/board/sysam/stmark2/MAINTAINERS new file mode 100644 index 0000000000..b87f432bb3 --- /dev/null +++ b/board/sysam/stmark2/MAINTAINERS @@ -0,0 +1,6 @@ +STMARK2 BOARD +M: Angelo Dureghello <angelo(a)sysam.it> +S: Maintained +F: board/sysam/stmark2/ +F: include/configs/stmark2.h +F: configs/stmark2_defconfig diff --git a/board/sysam/stmark2/Makefile b/board/sysam/stmark2/Makefile new file mode 100644 index 0000000000..064a57ea05 --- /dev/null +++ b/board/sysam/stmark2/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2014 Angelo Dureghello <angelo(a)sysam.it> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = stmark2.o +extra-y += sbf_dram_init.o diff --git a/board/sysam/stmark2/sbf_dram_init.S b/board/sysam/stmark2/sbf_dram_init.S new file mode 100644 index 0000000000..52abda5c3c --- /dev/null +++ b/board/sysam/stmark2/sbf_dram_init.S @@ -0,0 +1,119 @@ +/* + * Board-specific early ddr/sdram init. + * + * (C) Copyright 2017 Angelo Dureghello <angelo(a)sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.equ PPMCR0, 0xfc04002d +.equ MSCR_SDRAMC, 0xec094060 +.equ MISCCR2, 0xec09001a +.equ DDR_RCR, 0xfc0b8180 +.equ DDR_PADCR, 0xfc0b81ac +.equ DDR_CR00, 0xfc0b8000 +.equ DDR_CR06, 0xfc0b8018 +.equ DDR_CR09, 0xfc0b8024 +.equ DDR_CR40, 0xfc0b80a0 +.equ DDR_CR45, 0xfc0b80b4 +.equ DDR_CR56, 0xfc0b80e0 + +.global sbf_dram_init +.text + +sbf_dram_init: + /* CD46 = DDR on */ + move.l #PPMCR0, %a1 + move.b #46, (%a1) + + /* stmark 2, max drive strength */ + move.l #MSCR_SDRAMC, %a1 + move.b #1, (%a1) + + /* + * use cpu clock, seems more realiable + * + * DDR2 clock is serviced from DDR controller as input clock / 2 + * so, if clock comes from + * vco, i.e. 480(vco) / 2, so ddr clock is 240 Mhz (measured) + * cpu, i.e. 250(cpu) / 2, so ddr clock is 125 Mhz (measured) + * + * . + * / \ DDR2 can't be clocked lower than 125Mhz + * / ! \ DDR2 init must pass further i/dcache enable test + * /_____\ + * WARNING + */ + + /* cpu / 2 = 125 Mhz for 480 Mhz pll */ + move.l #MISCCR2, %a1 + move.w #0xa01d, (%a1) + + /* DDR force sw reset settings */ + move.l #DDR_RCR, %a1 + move.l #0x00000000, (%a1) + move.l #0x40000000, (%a1) + + /* + * PAD_ODT_CS: for us seems both 1(75 ohm) and 2(150ohm) are good, + * 500/700 mV are ok + */ + move.l #DDR_PADCR, %a1 + move.l #0x01030203, (%a1) /* as freescale tower */ + + move.l #DDR_CR00, %a1 + move.l #0x01010101, (%a1)+ /* 0x00 */ + move.l #0x00000101, (%a1)+ /* 0x04 */ + move.l #0x01010100, (%a1)+ /* 0x08 */ + move.l #0x01010000, (%a1)+ /* 0x0C */ + move.l #0x00010101, (%a1)+ /* 0x10 */ + move.l #DDR_CR06, %a1 + move.l #0x00010100, (%a1)+ /* 0x18 */ + move.l #0x00000001, (%a1)+ /* 0x1C */ + move.l #0x01000001, (%a1)+ /* 0x20 */ + move.l #0x00000100, (%a1)+ /* 0x24 */ + move.l #0x00010001, (%a1)+ /* 0x28 */ + move.l #0x00000200, (%a1)+ /* 0x2C */ + move.l #0x01000002, (%a1)+ /* 0x30 */ + move.l #0x00000000, (%a1)+ /* 0x34 */ + move.l #0x00000100, (%a1)+ /* 0x38 */ + move.l #0x02000100, (%a1)+ /* 0x3C */ + move.l #0x02000407, (%a1)+ /* 0x40 */ + move.l #0x02030007, (%a1)+ /* 0x44 */ + move.l #0x02000100, (%a1)+ /* 0x48 */ + move.l #0x0A030203, (%a1)+ /* 0x4C */ + move.l #0x00020708, (%a1)+ /* 0x50 */ + move.l #0x00050008, (%a1)+ /* 0x54 */ + move.l #0x04030002, (%a1)+ /* 0x58 */ + move.l #0x00000004, (%a1)+ /* 0x5C */ + move.l #0x020A0000, (%a1)+ /* 0x60 */ + move.l #0x0C00000E, (%a1)+ /* 0x64 */ + move.l #0x00002004, (%a1)+ /* 0x68 */ + move.l #0x00000000, (%a1)+ /* 0x6C */ + move.l #0x00100010, (%a1)+ /* 0x70 */ + move.l #0x00100010, (%a1)+ /* 0x74 */ + move.l #0x00000000, (%a1)+ /* 0x78 */ + move.l #0x07990000, (%a1)+ /* 0x7C */ + move.l #DDR_CR40, %a1 + move.l #0x00000000, (%a1)+ /* 0xA0 */ + move.l #0x00C80064, (%a1)+ /* 0xA4 */ + move.l #0x44520002, (%a1)+ /* 0xA8 */ + move.l #0x00C80023, (%a1)+ /* 0xAC */ + move.l #DDR_CR45, %a1 + move.l #0x0000C350, (%a1) /* 0xB4 */ + move.l #DDR_CR56, %a1 + move.l #0x04000000, (%a1)+ /* 0xE0 */ + move.l #0x03000304, (%a1)+ /* 0xE4 */ + move.l #0x40040000, (%a1)+ /* 0xE8 */ + move.l #0xC0004004, (%a1)+ /* 0xEC */ + move.l #0x0642C000, (%a1)+ /* 0xF0 */ + move.l #0x00000642, (%a1)+ /* 0xF4 */ + move.l #DDR_CR09, %a1 + tpf + move.l #0x01000100, (%a1) /* 0x24 */ + + move.l #0x2000, %d1 + bsr asm_delay + + + rts diff --git a/board/sysam/stmark2/stmark2.c b/board/sysam/stmark2/stmark2.c new file mode 100644 index 0000000000..4f291ab6d6 --- /dev/null +++ b/board/sysam/stmark2/stmark2.c @@ -0,0 +1,47 @@ +/* + * Board-specific init. + * + * (C) Copyright 2017 Angelo Dureghello <angelo(a)sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spi.h> +#include <asm/io.h> +#include <asm/immap.h> +#include <mmc.h> +#include <fsl_esdhc.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + /* + * need to to: + * Check serial flash size. if 2mb evb, else 8mb demo + */ + puts("Board: "); + puts("Sysam stmark2\n"); + return 0; +} + +int dram_init(void) +{ + u32 dramsize; + + /* + * Serial Boot: The dram is already initialized in start.S + * only require to return DRAM size + */ + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + + gd->ram_size = dramsize; + + return 0; +} + +int testdram(void) +{ + return 0; +} diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig new file mode 100644 index 0000000000..cf3625c281 --- /dev/null +++ b/configs/stmark2_defconfig @@ -0,0 +1,26 @@ +CONFIG_M68K=y +CONFIG_SYS_TEXT_BASE=0x47E00000 +CONFIG_TARGET_STMARK2=y +CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=30000000" +# CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="stmark2 $ " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_LOADB=y +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_CACHE=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_REGEX=y diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h new file mode 100644 index 0000000000..bd1f64bc8f --- /dev/null +++ b/include/configs/stmark2.h @@ -0,0 +1,202 @@ +/* + * Sysam stmark2 board configuration + * + * (C) Copyright 2016 Angelo Dureghello <angelo(a)sysam.it> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __STMARK2_CONFIG_H +#define __STMARK2_CONFIG_H + +#define CONFIG_STMARK2 +#define CONFIG_HOSTNAME stmark2 + +#define CONFIG_MCFUART +#define CONFIG_SYS_UART_PORT 0 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#define LDS_BOARD_TEXT \ + board/sysam/stmark2/sbf_dram_init.o (.text*) + +#define CONFIG_TIMESTAMP + +/* commands */ +#define CONFIG_CMD_REGINFO + +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 root=/dev/ram0 rw " \ + "rootfstype=ramfs " \ + "rdinit=/bin/init " \ + "devtmpfs.mount=1" + +#define CONFIG_BOOTCOMMAND \ + "sf probe 0:1 50000000; " \ + "sf read ${loadaddr} 0x100000 ${kern_size}; " \ + "bootm ${loadaddr}" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kern_size=0x700000\0" \ + "loadaddr=0x40001000\0" \ + "-(rootfs)\0" \ + "update_uboot=loady ${loadaddr}; " \ + "sf probe 0:1 50000000; " \ + "sf erase 0 0x80000; " \ + "sf write ${loadaddr} 0 ${filesize}\0" \ + "update_kernel=loady ${loadaddr}; " \ + "setenv kern_size ${filesize}; saveenv; " \ + "sf probe 0:1 50000000; " \ + "sf erase 0x100000 0x700000; " \ + "sf write ${loadaddr} 0x100000 ${filesize}\0" \ + "update_rootfs=loady ${loadaddr}; " \ + "sf probe 0:1 50000000; " \ + "sf erase 0x00800000 0x100000; " \ + "sf write ${loadaddr} 0x00800000 ${filesize}\0" \ + "" + +/* Realtime clock */ +#undef CONFIG_MCFRTC +#define CONFIG_RTC_MCFRRTC +#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 + +/* spi not partitions */ +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE +#define CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define MTDIDS_DEFAULT "nor0=spi-flash.0" +#define MTDPARTS_DEFAULT \ + "mtdparts=spi-flash.0:" \ + "1m(u-boot)," \ + "7m(kernel)," \ + "-(rootfs)" + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* DSPI and Serial Flash */ +#define CONFIG_CF_SPI +#define CONFIG_CF_DSPI +#define CONFIG_SF_DEFAULT_SPEED 50000000 +#define CONFIG_SERIAL_FLASH +#define CONFIG_HARD_SPI +#define CONFIG_SPI_FLASH_ISSI +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 1 + +#define CONFIG_SYS_SBFHDR_SIZE 0x7 + +#define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ + DSPI_CTAR_PCSSCK_1CLK | \ + DSPI_CTAR_PASC(0) | \ + DSPI_CTAR_PDT(0) | \ + DSPI_CTAR_CSSCK(0) | \ + DSPI_CTAR_ASC(0) | \ + DSPI_CTAR_DT(1) | \ + DSPI_CTAR_BR(6)) +#define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) +#define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) + +/* Input, PCI, Flexbus, and VCO */ +#define CONFIG_EXTRA_CLOCK + +#define CONFIG_PRAM 2048 /* 2048 KB */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) +#define CONFIG_SYS_MBAR 0xFC000000 + +/* + * Definitions for initial stack pointer and data area (in internal SRAM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +/* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) - 32) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ + +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) +#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) +#define CONFIG_SYS_DRAM_TEST + +#if defined(CONFIG_CF_SBF) +#define CONFIG_SERIAL_BOOT +#endif + +#if defined(CONFIG_SERIAL_BOOT) +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) +#else +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) +#endif + +#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) +/* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) +/* Reserve 256 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (256 << 10) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +/* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ + (CONFIG_SYS_SDRAM_SIZE << 20)) + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ + +#if defined(CONFIG_CF_SBF) +#define CONFIG_ENV_IS_IN_SPI_FLASH 1 +#define CONFIG_ENV_SPI_CS 1 +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#endif + +#undef CONFIG_ENV_OVERWRITE + +/* Cache Configuration */ +#define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ + CF_CACR_ICINVA | CF_CACR_EUSP) +#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ + CF_CACR_DEC | CF_CACR_DDCM_P | \ + CF_CACR_DCINVA) & ~CF_CACR_ICINVA) + +#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 12) + +#endif /* __STMARK2_CONFIG_H */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index e8f49ebe5d..e6faf3450e 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2696,6 +2696,7 @@ CONFIG_STM32_GPIO CONFIG_STM32_HSE_HZ CONFIG_STM32_HZ CONFIG_STM32_SERIAL +CONFIG_STMARK2 CONFIG_STRESS CONFIG_STRIDER CONFIG_STRIDER_CON -- 2.13.2

3 4

[U-Boot] [PATCH] efi_loader: LocateHandle should return EFI_NOT_FOUND if none found
by Rob Clark 06 Aug '17

06 Aug '17

Spotted this debugging OpenBSD's bootloader in qemu. (Wouldn't really fix anything, the problem was not having any disks, but we should probably return the correct error code.) Signed-off-by: Rob Clark <robdclark(a)gmail.com> --- lib/efi_loader/efi_boottime.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 5ff2d2d4b0..ada119325c 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -643,6 +643,9 @@ static efi_status_t EFIAPI efi_locate_handle( } *buffer_size = size; + if (size == 0) + return EFI_NOT_FOUND; + return EFI_SUCCESS; } -- 2.13.0

3 2

[U-Boot] [PATCH 0/3] rockchip: rk3368: spl: move SPL_LDSCRIPT from header-files to Kconfig
by Philipp Tomsich 06 Aug '17

06 Aug '17

After applying the SPL/TPL infrastructure changes for the RK3368, a number of unexpected failures occurred during the buildman validation run. For a some of platforms, SPL_LDSCRIPT was now defined multiple times: once from Kconfig and once from a header file. This is a hot fix (i.e. it's needed before I can send out our pull-request) that adjusts the everything else to work again with SPL_LDSCRIPT moved to Kconfig. Note that I marked this as 'rockchip: spl: rk3368', as it is a change from integration/merging the changes already queued for our tree. Philipp Tomsich (3): spl: add hierarchical defaults for SPL_LDSCRIPT spl: moveconfig: remove SPL_LDSCRIPT definitions for header-files rockchip: rk3368: spl: move SPL_LDSCRIPT to Kconfig arch/arm/Kconfig | 12 ++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 3 +++ arch/arm/mach-at91/Kconfig | 4 ++++ arch/arm/mach-davinci/Kconfig | 4 ++++ arch/arm/mach-exynos/Kconfig | 3 +++ arch/arm/mach-omap2/Kconfig | 3 +++ arch/arm/mach-orion5x/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3368/Kconfig | 3 +++ arch/arm/mach-sunxi/Kconfig | 3 +++ arch/arm/mach-zynq/Kconfig | 3 +++ arch/microblaze/Kconfig | 3 +++ board/armadeus/apf27/Kconfig | 3 +++ board/freescale/mx31pdk/Kconfig | 3 +++ board/spear/x600/Kconfig | 3 +++ include/configs/am335x_evm.h | 2 -- include/configs/am335x_igep003x.h | 1 - include/configs/am335x_shc.h | 2 -- include/configs/am335x_sl50.h | 2 -- include/configs/am3517_crane.h | 1 - include/configs/am3517_evm.h | 1 - include/configs/am43xx_evm.h | 2 -- include/configs/apf27.h | 1 - include/configs/at91sam9m10g45ek.h | 1 - include/configs/at91sam9n12ek.h | 1 - include/configs/at91sam9x5ek.h | 1 - include/configs/baltos.h | 2 -- include/configs/bav335x.h | 2 -- include/configs/bur_am335x_common.h | 1 - include/configs/chiliboard.h | 2 -- include/configs/cm_t335.h | 1 - include/configs/cm_t35.h | 1 - include/configs/cm_t43.h | 2 -- include/configs/da850evm.h | 1 - include/configs/edminiv2.h | 1 - include/configs/exynos5-common.h | 1 - include/configs/imx6_spl.h | 1 - include/configs/ipam390.h | 1 - include/configs/kc1.h | 2 -- include/configs/ls1021aiot.h | 1 - include/configs/ls1021aqds.h | 2 -- include/configs/ls1021atwr.h | 1 - include/configs/ls1043a_common.h | 2 -- include/configs/ls1046a_common.h | 2 -- include/configs/ls2080a_common.h | 1 - include/configs/ma5d4evk.h | 1 - include/configs/mcx.h | 1 - include/configs/microblaze-generic.h | 2 -- include/configs/mx31pdk.h | 1 - include/configs/mxs.h | 1 - include/configs/omap3_evm.h | 1 - include/configs/omapl138_lcdk.h | 1 - include/configs/origen.h | 1 - include/configs/pcm051.h | 2 -- include/configs/pengwyn.h | 2 -- include/configs/pepper.h | 1 - include/configs/picosam9g45.h | 1 - include/configs/sama5d2_xplained.h | 1 - include/configs/sama5d3_xplained.h | 1 - include/configs/sama5d3xek.h | 1 - include/configs/sama5d4_xplained.h | 1 - include/configs/sama5d4ek.h | 1 - include/configs/siemens-am33x-common.h | 2 -- include/configs/smartweb.h | 1 - include/configs/smdkv310.h | 1 - include/configs/sniper.h | 2 -- include/configs/sunxi-common.h | 4 ---- include/configs/tam3517-common.h | 1 - include/configs/tao3530.h | 1 - include/configs/ti814x_evm.h | 1 - include/configs/ti816x_evm.h | 2 -- include/configs/ti_omap3_common.h | 1 - include/configs/ti_omap4_common.h | 1 - include/configs/ti_omap5_common.h | 1 - include/configs/tricorder.h | 1 - include/configs/woodburn_sd.h | 1 - include/configs/x600.h | 1 - include/configs/zynq-common.h | 2 -- 77 files changed, 53 insertions(+), 85 deletions(-) -- 2.1.4

2 9