July 2017 - U-Boot

[U-Boot] [PATCH v2 0/6] sunxi: update sun8i-emac driver and A64 DTs
by Andre Przywara 25 Aug '17

25 Aug '17

This patch set updates the latest device trees for Allwinner A64 based boards from Linux. In contrast to v1 I now took the actual 4.13-rc1 DTs from Linux, which restructures the patch set a bit. The big advantage of having the very same DTs in U-Boot is that we can use UEFI boot much more easily, because U-Boot can just pass on its own DT, without having to find and load some external version. This makes UEFI based installers boot out of the box, which is a big relief. Linux 4.13-rc1 saw the addition of the sun8i-emac Ethernet driver, for which U-Boot has a driver for quite a while, but with a slightly different binding, so this series makes it compatible. Patch 1/6 adds some missing compatible strings, it was on the list before, but I add it to this series because it is a prerequisite for the following patches. Patches 2 till 4 add some code to be able to parse the new pinctrl bindings that newer Allwinner DTs use. Patch 5 extends U-Boot sun8i-emac driver to be able to properly parse the DT binding used by the new Linux driver as well. Patch 6 then actually replaces the DTs for A64 boards with the exact version as of the Linux tree (v4.13-rc1). This allows us to *almost* get rid of out *-u-boot.dtsi kludge, but we still need the alias, which the Linux version doesn't have, so this file still contains this one line, effectively. I am still not convinced that having a full featured pinctrl driver in U-Boot is the right thing, so I cheekily ignore this part of the comments. If people consider this a requirement, we can have a look at this, but I don't see any reply since the first patch was posted some months ago, so I guess this takes much more time. Also my apologies for not having looked at the syscon driver change Simon asked. It looks like a reasonable change, but I am about to leave for holidays and didn't want to postpone an updated version any longer. Cheers, Andre. Andre Przywara (6): sunxi: gpio: add missing compatible strings libfdt: add fdtdec_lookup_phandle_index() sunxi: GPIO: introduce sunxi_gpio_setup_dt_pins() net: sun8i-emac: use new, generic GPIO setup routine net: sun8i-emac: add support for new DT binding sunxi: A64: update Linux DTs arch/arm/dts/sun50i-a64-bananapi-m64-u-boot.dtsi | 5 + arch/arm/dts/sun50i-a64-bananapi-m64.dts | 16 ++- arch/arm/dts/sun50i-a64-orangepi-win.dts | 7 +- arch/arm/dts/sun50i-a64-pine64-plus-u-boot.dtsi | 45 ------- arch/arm/dts/sun50i-a64-pine64-plus.dts | 17 ++- arch/arm/dts/sun50i-a64-pine64.dts | 57 +++++++++ arch/arm/dts/sun50i-a64.dtsi | 142 ++++++++++++++++++++--- arch/arm/include/asm/arch-sunxi/gpio.h | 3 + arch/arm/mach-sunxi/pinmux.c | 79 +++++++++++++ drivers/gpio/sunxi_gpio.c | 4 + drivers/net/sun8i_emac.c | 105 +++++++++-------- include/dt-bindings/clock/sun8i-r-ccu.h | 59 ++++++++++ include/fdtdec.h | 12 ++ lib/fdtdec.c | 16 ++- 14 files changed, 441 insertions(+), 126 deletions(-) create mode 100644 arch/arm/dts/sun50i-a64-bananapi-m64-u-boot.dtsi create mode 100644 include/dt-bindings/clock/sun8i-r-ccu.h -- 2.8.2

2 7

[U-Boot] [PATCH 1/2] [rfc] parse the second area of android image
by Bin Chen 25 Aug '17

25 Aug '17

The second area of android image was intended to put a 2nd stage bootloader but in practice were rarely used (in my knowledge). An proposal was made to the AOSP to (re)use the second area as the dtb[1], This patch itself doesn't depend on that proposal being accepted but it won't be that helpful as well if that proposal won't be accepted. But don't do any harm as well. [1] https://android-review.googlesource.com/#/c/417447/ Signed-off-by: Bin Chen <bin.chen(a)linaro.org> --- common/image-android.c | 19 +++++++++++++++++++ include/image.h | 2 ++ 2 files changed, 21 insertions(+) diff --git a/common/image-android.c b/common/image-android.c index ee03b96..7daa5fa 100644 --- a/common/image-android.c +++ b/common/image-android.c @@ -146,6 +146,25 @@ int android_image_get_ramdisk(const struct andr_img_hdr *hdr, return 0; } +int android_image_get_second(const struct andr_img_hdr *hdr, + ulong *second_data, ulong *second_len) +{ + if (!hdr->second_size) { + *second_data = *second_len = 0; + return -1; + } + + *second_data = (unsigned long)hdr; + *second_data += hdr->page_size; + *second_data += ALIGN(hdr->kernel_size, hdr->page_size); + *second_data += ALIGN(hdr->ramdisk_size, hdr->page_size); + + printf("second address is 0x%lx\n",*second_data); + + *second_len = hdr->second_size; + return 0; +} + #if !defined(CONFIG_SPL_BUILD) /** * android_print_contents - prints out the contents of the Android format image diff --git a/include/image.h b/include/image.h index 3f26f9b..8264c52 100644 --- a/include/image.h +++ b/include/image.h @@ -1237,6 +1237,8 @@ int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify, ulong *os_data, ulong *os_len); int android_image_get_ramdisk(const struct andr_img_hdr *hdr, ulong *rd_data, ulong *rd_len); +int android_image_get_second(const struct andr_img_hdr *hdr, + ulong *second_data, ulong *second_len); ulong android_image_get_end(const struct andr_img_hdr *hdr); ulong android_image_get_kload(const struct andr_img_hdr *hdr); void android_print_contents(const struct andr_img_hdr *hdr); -- 1.9.1

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[U-Boot] [PATCH 00/14] dm: sata: mmc: Convert a sunxi board to driver model for MMC, SATA
by Simon Glass 22 Aug '17

22 Aug '17

At present SCSI support for driver model works only with PCI controllers. This series makes the following changes: - Adjusts SATA/AHCI support to work with non-PCI controllers - Allows driver model to be used for MMC in U-Boot proper without requiring it to be used in SPL - Adjusts sunxi MMC and SATA drivers to support driver model - Enables this on a single board (Linksprite_pcDuino3) Even with this series the AHCI uclass still does not have any operations. This will be needed for drivers which do not use SCSI. Further work is needed to complete this. Simon Glass (14): ahci: Support non-PCI controllers dm: mmc: Allow disabling driver model in SPL fdt: Correct fdt_get_base_address() dm: scsi: Drop duplicate SCSI and DM_SCSI options dm: ahci: Correct uclass private data dm: mmc: sunxi: Rename struct sunxi_mmc_host to sunxi_mmc_priv dm: mmc: sunxi: Rename mmchost to priv dm: mmc: sunxi: Pass private data around explicitly dm: mmc: sunxi: Drop mmc_clk_io_on() dm: mmc: sunxi: Add support for driver model dm: scsi: Don't scan the SCSI bus when probing dm: sunxi: sata: Don't build sata support into SPL dm: sata: sunxi: Add support for driver model dm: sunxi: Move Linksprite_pcDuino3 to use DM for MMC, SATA arch/arm/dts/sun7i-a20-pcduino3.dts | 1 - arch/x86/cpu/ivybridge/sata.c | 2 +- board/sunxi/Makefile | 2 + board/sunxi/ahci.c | 61 +++++- common/fdt_support.c | 7 +- common/spl/spl_mmc.c | 4 +- configs/Linksprite_pcDuino3_defconfig | 7 +- drivers/ata/Kconfig | 18 -- drivers/ata/ahci-uclass.c | 2 + drivers/ata/ahci.c | 33 ++-- drivers/block/Kconfig | 12 ++ drivers/block/Makefile | 4 +- drivers/mmc/Kconfig | 21 ++ drivers/mmc/Makefile | 4 +- drivers/mmc/mmc-uclass.c | 6 +- drivers/mmc/mmc.c | 28 +-- drivers/mmc/mmc_legacy.c | 2 +- drivers/mmc/mmc_private.h | 6 +- drivers/mmc/omap_hsmmc.c | 20 +- drivers/mmc/sunxi_mmc.c | 360 +++++++++++++++++++++++----------- drivers/scsi/scsi.c | 2 +- include/ahci.h | 14 +- include/blk.h | 4 +- include/mmc.h | 12 +- 24 files changed, 431 insertions(+), 201 deletions(-) -- 2.13.1.518.g3df882009-goog

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[U-Boot] [PATCH 1/5] mmc: uniphier-sd: Factor out register IO
by Marek Vasut 20 Aug '17

20 Aug '17

This patch prepares the driver to support controller(s) with registers at locations shifted by constant. Pull out the readl()/writel() from the driver into separate functions, where the adjustment of the register offset can be easily contained. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Masahiro Yamada <yamada.masahiro(a)socionext.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> --- drivers/mmc/uniphier-sd.c | 115 +++++++++++++++++++++++++--------------------- 1 file changed, 63 insertions(+), 52 deletions(-) diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c index e272b14153..70090522bd 100644 --- a/drivers/mmc/uniphier-sd.c +++ b/drivers/mmc/uniphier-sd.c @@ -134,6 +134,17 @@ struct uniphier_sd_priv { #define UNIPHIER_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */ }; +static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, const u32 reg) +{ + return readl(priv->regbase + reg); +} + +static void uniphier_sd_writel(struct uniphier_sd_priv *priv, + const u32 val, const u32 reg) +{ + writel(val, priv->regbase + reg); +} + static dma_addr_t __dma_map_single(void *ptr, size_t size, enum dma_data_direction dir) { @@ -157,7 +168,7 @@ static void __dma_unmap_single(dma_addr_t addr, size_t size, static int uniphier_sd_check_error(struct udevice *dev) { struct uniphier_sd_priv *priv = dev_get_priv(dev); - u32 info2 = readl(priv->regbase + UNIPHIER_SD_INFO2); + u32 info2 = uniphier_sd_readl(priv, UNIPHIER_SD_INFO2); if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) { /* @@ -195,7 +206,7 @@ static int uniphier_sd_wait_for_irq(struct udevice *dev, unsigned int reg, long wait = 1000000; int ret; - while (!(readl(priv->regbase + reg) & flag)) { + while (!(uniphier_sd_readl(priv, reg) & flag)) { if (wait-- < 0) { dev_err(dev, "timeout\n"); return -ETIMEDOUT; @@ -227,14 +238,14 @@ static int uniphier_sd_pio_read_one_block(struct udevice *dev, u32 **pbuf, * Clear the status flag _before_ read the buffer out because * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered. */ - writel(0, priv->regbase + UNIPHIER_SD_INFO2); + uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2); if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) { for (i = 0; i < blocksize / 4; i++) - *(*pbuf)++ = readl(priv->regbase + UNIPHIER_SD_BUF); + *(*pbuf)++ = uniphier_sd_readl(priv, UNIPHIER_SD_BUF); } else { for (i = 0; i < blocksize / 4; i++) - put_unaligned(readl(priv->regbase + UNIPHIER_SD_BUF), + put_unaligned(uniphier_sd_readl(priv, UNIPHIER_SD_BUF), (*pbuf)++); } @@ -253,15 +264,15 @@ static int uniphier_sd_pio_write_one_block(struct udevice *dev, if (ret) return ret; - writel(0, priv->regbase + UNIPHIER_SD_INFO2); + uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2); if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) { for (i = 0; i < blocksize / 4; i++) - writel(*(*pbuf)++, priv->regbase + UNIPHIER_SD_BUF); + uniphier_sd_writel(priv, *(*pbuf)++, UNIPHIER_SD_BUF); } else { for (i = 0; i < blocksize / 4; i++) - writel(get_unaligned((*pbuf)++), - priv->regbase + UNIPHIER_SD_BUF); + uniphier_sd_writel(priv, get_unaligned((*pbuf)++), + UNIPHIER_SD_BUF); } return 0; @@ -292,22 +303,22 @@ static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv, { u32 tmp; - writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO1); - writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO2); + uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO1); + uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO2); /* enable DMA */ - tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE); + tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE); tmp |= UNIPHIER_SD_EXTMODE_DMA_EN; - writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE); - writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_L); + uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_L); /* suppress the warning "right shift count >= width of type" */ dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr)); - writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_H); + uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_H); - writel(UNIPHIER_SD_DMA_CTL_START, priv->regbase + UNIPHIER_SD_DMA_CTL); + uniphier_sd_writel(priv, UNIPHIER_SD_DMA_CTL_START, UNIPHIER_SD_DMA_CTL); } static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag, @@ -316,7 +327,7 @@ static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag, struct uniphier_sd_priv *priv = dev_get_priv(dev); long wait = 1000000 + 10 * blocks; - while (!(readl(priv->regbase + UNIPHIER_SD_DMA_INFO1) & flag)) { + while (!(uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO1) & flag)) { if (wait-- < 0) { dev_err(dev, "timeout during DMA\n"); return -ETIMEDOUT; @@ -325,7 +336,7 @@ static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag, udelay(10); } - if (readl(priv->regbase + UNIPHIER_SD_DMA_INFO2)) { + if (uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO2)) { dev_err(dev, "error during DMA\n"); return -EIO; } @@ -343,7 +354,7 @@ static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data) u32 poll_flag, tmp; int ret; - tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE); + tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE); if (data->flags & MMC_DATA_READ) { buf = data->dest; @@ -357,7 +368,7 @@ static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data) tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD; } - writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE); dma_addr = __dma_map_single(buf, len, dir); @@ -396,27 +407,27 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, int ret; u32 tmp; - if (readl(priv->regbase + UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) { + if (uniphier_sd_readl(priv, UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) { dev_err(dev, "command busy\n"); return -EBUSY; } /* clear all status flags */ - writel(0, priv->regbase + UNIPHIER_SD_INFO1); - writel(0, priv->regbase + UNIPHIER_SD_INFO2); + uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO1); + uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2); /* disable DMA once */ - tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE); + tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE); tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN; - writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE); - writel(cmd->cmdarg, priv->regbase + UNIPHIER_SD_ARG); + uniphier_sd_writel(priv, cmd->cmdarg, UNIPHIER_SD_ARG); tmp = cmd->cmdidx; if (data) { - writel(data->blocksize, priv->regbase + UNIPHIER_SD_SIZE); - writel(data->blocks, priv->regbase + UNIPHIER_SD_SECCNT); + uniphier_sd_writel(priv, data->blocksize, UNIPHIER_SD_SIZE); + uniphier_sd_writel(priv, data->blocks, UNIPHIER_SD_SECCNT); /* Do not send CMD12 automatically */ tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA; @@ -457,7 +468,7 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n", cmd->cmdidx, tmp, cmd->cmdarg); - writel(tmp, priv->regbase + UNIPHIER_SD_CMD); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CMD); ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1, UNIPHIER_SD_INFO1_RSP); @@ -465,10 +476,10 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, return ret; if (cmd->resp_type & MMC_RSP_136) { - u32 rsp_127_104 = readl(priv->regbase + UNIPHIER_SD_RSP76); - u32 rsp_103_72 = readl(priv->regbase + UNIPHIER_SD_RSP54); - u32 rsp_71_40 = readl(priv->regbase + UNIPHIER_SD_RSP32); - u32 rsp_39_8 = readl(priv->regbase + UNIPHIER_SD_RSP10); + u32 rsp_127_104 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP76); + u32 rsp_103_72 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP54); + u32 rsp_71_40 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP32); + u32 rsp_39_8 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10); cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) | ((rsp_103_72 & 0xff000000) >> 24); @@ -479,7 +490,7 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, cmd->response[3] = (rsp_39_8 & 0xffffff) << 8; } else { /* bit 39-8 */ - cmd->response[0] = readl(priv->regbase + UNIPHIER_SD_RSP10); + cmd->response[0] = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10); } if (data) { @@ -518,10 +529,10 @@ static int uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv, return -EINVAL; } - tmp = readl(priv->regbase + UNIPHIER_SD_OPTION); + tmp = uniphier_sd_readl(priv, UNIPHIER_SD_OPTION); tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK; tmp |= val; - writel(tmp, priv->regbase + UNIPHIER_SD_OPTION); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_OPTION); return 0; } @@ -531,12 +542,12 @@ static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv, { u32 tmp; - tmp = readl(priv->regbase + UNIPHIER_SD_IF_MODE); + tmp = uniphier_sd_readl(priv, UNIPHIER_SD_IF_MODE); if (mmc->ddr_mode) tmp |= UNIPHIER_SD_IF_MODE_DDR; else tmp &= ~UNIPHIER_SD_IF_MODE_DDR; - writel(tmp, priv->regbase + UNIPHIER_SD_IF_MODE); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_IF_MODE); } static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv, @@ -573,21 +584,21 @@ static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv, else val = UNIPHIER_SD_CLKCTL_DIV1024; - tmp = readl(priv->regbase + UNIPHIER_SD_CLKCTL); + tmp = uniphier_sd_readl(priv, UNIPHIER_SD_CLKCTL); if (tmp & UNIPHIER_SD_CLKCTL_SCLKEN && (tmp & UNIPHIER_SD_CLKCTL_DIV_MASK) == val) return; /* stop the clock before changing its rate to avoid a glitch signal */ tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN; - writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL); tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK; tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN; - writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL); tmp |= UNIPHIER_SD_CLKCTL_SCLKEN; - writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL); udelay(1000); } @@ -617,7 +628,7 @@ static int uniphier_sd_get_cd(struct udevice *dev) if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE) return 1; - return !!(readl(priv->regbase + UNIPHIER_SD_INFO1) & + return !!(uniphier_sd_readl(priv, UNIPHIER_SD_INFO1) & UNIPHIER_SD_INFO1_CD); } @@ -632,28 +643,28 @@ static void uniphier_sd_host_init(struct uniphier_sd_priv *priv) u32 tmp; /* soft reset of the host */ - tmp = readl(priv->regbase + UNIPHIER_SD_SOFT_RST); + tmp = uniphier_sd_readl(priv, UNIPHIER_SD_SOFT_RST); tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX; - writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST); tmp |= UNIPHIER_SD_SOFT_RST_RSTX; - writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST); /* FIXME: implement eMMC hw_reset */ - writel(UNIPHIER_SD_STOP_SEC, priv->regbase + UNIPHIER_SD_STOP); + uniphier_sd_writel(priv, UNIPHIER_SD_STOP_SEC, UNIPHIER_SD_STOP); /* * Connected to 32bit AXI. * This register dropped backward compatibility at version 0x10. * Write an appropriate value depending on the IP version. */ - writel(priv->version >= 0x10 ? 0x00000101 : 0x00000000, - priv->regbase + UNIPHIER_SD_HOST_MODE); + uniphier_sd_writel(priv, priv->version >= 0x10 ? 0x00000101 : 0x00000000, + UNIPHIER_SD_HOST_MODE); if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) { - tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE); + tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE); tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC; - writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE); + uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE); } } @@ -724,7 +735,7 @@ static int uniphier_sd_probe(struct udevice *dev) NULL)) priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE; - priv->version = readl(priv->regbase + UNIPHIER_SD_VERSION) & + priv->version = uniphier_sd_readl(priv, UNIPHIER_SD_VERSION) & UNIPHIER_SD_VERSION_IP; dev_dbg(dev, "version %x\n", priv->version); if (priv->version >= 0x10) { -- 2.11.0

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[U-Boot] [PATCH v2 0/7] spl: add xip booting support
by Vikas Manocha 19 Aug '17

19 Aug '17

This patchset adds support for XIP (execute in place) of U-Boot or kernel image and enables it for stm32f7. Changed in v2: - added patch to move v7m thumb mode just before next image boot - removed extra blank line. Vikas Manocha (7): spl: armv7m: to keep ARM v7M in thumb mode before booting next image stm32f7: remove duplicate configs stm32: stm32f7: add spl build support SPL: Add XIP booting support serial: stm32f7: disable overrun spl: stm32f7: add kernel boot support spl: stm32f7: configure for xip booting arch/arm/include/asm/spl.h | 1 + arch/arm/mach-stm32/Kconfig | 1 + arch/arm/mach-stm32/stm32f7/Kconfig | 24 ++++++++++++++++++++ board/st/stm32f746-disco/stm32f746-disco.c | 36 +++++++++++++++++++++++++++++- common/spl/Kconfig | 9 ++++++++ common/spl/Makefile | 1 + common/spl/spl.c | 6 ++--- common/spl/spl_xip.c | 28 +++++++++++++++++++++++ configs/stm32f746-disco_defconfig | 5 ----- drivers/serial/serial_stm32x7.c | 3 +++ drivers/serial/serial_stm32x7.h | 2 ++ include/configs/stm32f746-disco.h | 31 ++++++++++++++++++++++--- 12 files changed, 135 insertions(+), 12 deletions(-) create mode 100644 common/spl/spl_xip.c -- 1.9.1

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[U-Boot] [PATCH 0/5] rockchip: rk3229: add sdram and sd support
by Kever Yang 18 Aug '17

18 Aug '17

Add sdram driver for rk3229 and other fix like pinctrl and sd node. Kever Yang (5): rockchip: rk322x: update dram bank size rockchip: rk322x: add sdram driver rockchip: dts: rk322x: add sdmmc device node rockchip: rk322x: pinctrl: using compatible name same with dts rockchip: dts: rk3229: remove dram channel info arch/arm/dts/rk3229-evb.dts | 13 +- arch/arm/dts/rk322x.dtsi | 62 ++ arch/arm/include/asm/arch-rockchip/sdram_rk322x.h | 581 +++++++++++++++ arch/arm/mach-rockchip/rk322x-board.c | 10 +- arch/arm/mach-rockchip/rk322x/Makefile | 1 + arch/arm/mach-rockchip/rk322x/sdram_rk322x.c | 855 ++++++++++++++++++++++ drivers/pinctrl/rockchip/pinctrl_rk322x.c | 8 +- 7 files changed, 1521 insertions(+), 9 deletions(-) create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk322x.h create mode 100644 arch/arm/mach-rockchip/rk322x/sdram_rk322x.c -- 1.9.1

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[U-Boot] [PATCH v1 1/1] net: phy: Add AFE settings to the Broadcom Cygnus phy
by Arun Parameswaran 18 Aug '17

18 Aug '17

Added the AFE (Analog Front End) settings for stability to the Broadcom Cygnus phy. This improves the time take to perform auto negotiation. Signed-off-by: Arun Parameswaran <arun.parameswaran(a)broadcom.com> --- drivers/net/phy/broadcom.c | 64 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c index 9871cc3..e4afa90 100644 --- a/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c @@ -30,6 +30,29 @@ #define MIIM_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */ #define MIIM_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */ +#define MIIM_BCM_AUXCNTL_SHDWSEL_MISC 0x0007 +#define MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN 0x0800 + +#define MIIM_BCM_CHANNEL_WIDTH 0x2000 + +static void bcm_phy_write_misc(struct phy_device *phydev, + u16 reg, u16 chl, u16 value) +{ + int reg_val; + + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, + MIIM_BCM_AUXCNTL_SHDWSEL_MISC); + + reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL); + reg_val |= MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN; + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg_val); + + reg_val = (chl * MIIM_BCM_CHANNEL_WIDTH) | reg; + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg_val); + + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, value); +} + /* Broadcom BCM5461S */ static int bcm5461_config(struct phy_device *phydev) { @@ -152,11 +175,50 @@ static int bcm_cygnus_startup(struct phy_device *phydev) return genphy_parse_link(phydev); } +static void bcm_cygnus_afe(struct phy_device *phydev) +{ + /* ensures smdspclk is enabled */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, 0x0c30); + + /* AFE_VDAC_ICTRL_0 bit 7:4 Iq=1100 for 1g 10bt, normal modes */ + bcm_phy_write_misc(phydev, 0x39, 0x01, 0xA7C8); + + /* AFE_HPF_TRIM_OTHERS bit11=1, short cascode for all modes*/ + bcm_phy_write_misc(phydev, 0x3A, 0x00, 0x0803); + + /* AFE_TX_CONFIG_1 bit 7:4 Iq=1100 for test modes */ + bcm_phy_write_misc(phydev, 0x3A, 0x01, 0xA740); + + /* AFE TEMPSEN_OTHERS rcal_HT, rcal_LT 10000 */ + bcm_phy_write_misc(phydev, 0x3A, 0x03, 0x8400); + + /* AFE_FUTURE_RSV bit 2:0 rccal <2:0>=100 */ + bcm_phy_write_misc(phydev, 0x3B, 0x00, 0x0004); + + /* Adjust bias current trim to overcome digital offSet */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x02); + + /* make rcal=100, since rdb default is 000 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B1); + phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0010); + + /* CORE_EXPB0, Reset R_CAL/RC_CAL Engine */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B0); + phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0010); + + /* CORE_EXPB0, Disable Reset R_CAL/RC_CAL Engine */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B0); + phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0000); +} + static int bcm_cygnus_config(struct phy_device *phydev) { genphy_config_aneg(phydev); - phy_reset(phydev); + /* AFE settings for PHY stability */ + bcm_cygnus_afe(phydev); + /* Forcing aneg after applying the AFE settings */ + genphy_restart_aneg(phydev); return 0; } -- 1.9.1

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[U-Boot] [PATCH v3 0/3] CMD_USB_MASS_STORAGE implies USB_FUNCTION_MASS_STORAGE
by Philipp Tomsich 17 Aug '17

17 Aug '17

Up to now, there's been some ugliness associated with the dependency from CMD_USB_MASS_STORAGE to USB_FUNCTION_MASS_STORAGE: if someone only defined CMD_USB_MASS_STORAGE, they'd meet a linker error due to missing symbols that came from USB_FUNCTION_MASS_STORAGE. Most platforms seem to have resorted to unconditionally enable USB_FUNCTION_MASS_STORAGE via their 'common' config-header... some tried to tie this to an #ifdef CMD_USB_MASS_STORAGE (in fact I had a patch for the RK3399 that did just that and rather decided to clean this up once and for all instead of contributing to the prolongation of the status quo). Neither is a good solution. So this series moves USB_FUNCTION_MASS_STORAGE to Kconfig and lets CMD_USB_MASS_STORAGE imply USB_FUNCTION_MASS_STORAGE. Finally, we run moveconfig to contain the damage. Changes in v3: - rebased onto u-boot-usb/master@d2f6f70 Changes in v2: - ran 'tabify' on newly added lines to fix a spaces vs. tabs issues Philipp Tomsich (3): usb: gadget: move USB_FUNCTION_MASS_STORAGE to Kconfig Kconfig: CMD_USB_MASS_STORAGE implies USB_FUNCTION_MASS_STORAGE config: move USB_FUNCTION_MASS_STORAGE cmd/Kconfig | 1 + configs/CHIP_pro_defconfig | 1 + configs/Nintendo_NES_Classic_Edition_defconfig | 1 + configs/Sinlinx_SinA33_defconfig | 1 + configs/fennec-rk3288_defconfig | 1 + configs/firefly-rk3288_defconfig | 1 + configs/kylin-rk3036_defconfig | 1 + configs/miqi-rk3288_defconfig | 1 + configs/parrot_r16_defconfig | 1 + configs/phycore-rk3288_defconfig | 2 +- configs/popmetal-rk3288_defconfig | 1 + configs/smdkv310_defconfig | 1 + configs/tinker-rk3288_defconfig | 1 + drivers/usb/gadget/Kconfig | 9 +++++++++ include/configs/advantech_dms-ba16.h | 1 - include/configs/apalis_imx6.h | 1 - include/configs/bav335x.h | 4 ---- include/configs/cgtqmx6eval.h | 2 -- include/configs/colibri_imx6.h | 1 - include/configs/colibri_imx7.h | 2 -- include/configs/colibri_vf.h | 1 - include/configs/exynos4-common.h | 2 -- include/configs/ge_bx50v3.h | 1 - include/configs/gw_ventana.h | 1 - include/configs/ma5d4evk.h | 1 - include/configs/mx6sabre_common.h | 2 -- include/configs/mx7dsabresd.h | 2 -- include/configs/nitrogen6x.h | 2 -- include/configs/odroid_xu3.h | 1 - include/configs/opos6uldev.h | 1 - include/configs/pico-imx6ul.h | 1 - include/configs/pico-imx7d.h | 2 -- include/configs/rk3036_common.h | 1 - include/configs/rk322x_common.h | 1 - include/configs/rk3288_common.h | 1 - include/configs/s5p_goni.h | 1 - include/configs/socfpga_common.h | 2 -- include/configs/sunxi-common.h | 1 - include/configs/tbs2910.h | 1 - include/configs/tegra-common-usb-gadget.h | 1 - include/configs/warp.h | 2 -- include/configs/warp7.h | 2 -- scripts/config_whitelist.txt | 1 - 43 files changed, 22 insertions(+), 43 deletions(-) -- 2.1.4

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[U-Boot] [PATCH] mmc: gen_atmel_mci: Fix wrong arguments used of bind()
by Wenyou Yang 17 Aug '17

17 Aug '17

The bind() method is called before the device is probed and so the device has no private data, should use the platform data, and set up a new struct to hold the mmc and cfg members. Signed-off-by: Wenyou Yang <wenyou.yang(a)microchip.com> --- drivers/mmc/gen_atmel_mci.c | 64 +++++++++++++++++++++++++++++---------------- 1 file changed, 42 insertions(+), 22 deletions(-) diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index e9f061e55d..22154d13d7 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -36,13 +36,22 @@ DECLARE_GLOBAL_DATA_PTR; # define MCI_BUS 0 #endif +#ifdef CONFIG_DM_MMC +struct atmel_mci_plat { + struct mmc mmc; + struct mmc_config cfg; + struct atmel_mci *mci; +}; +#endif + struct atmel_mci_priv { +#ifndef CONFIG_DM_MMC struct mmc_config cfg; struct atmel_mci *mci; +#endif unsigned int initialized:1; unsigned int curr_clk; #ifdef CONFIG_DM_MMC - struct mmc mmc; ulong bus_clk_rate; #endif }; @@ -67,18 +76,21 @@ static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg) /* Setup for MCI Clock and Block Size */ #ifdef CONFIG_DM_MMC -static void mci_set_mode(struct atmel_mci_priv *priv, u32 hz, u32 blklen) +static void mci_set_mode(struct udevice *dev, u32 hz, u32 blklen) { - struct mmc *mmc = &priv->mmc; + struct atmel_mci_plat *plat = dev_get_platdata(dev); + struct atmel_mci_priv *priv = dev_get_priv(dev); + struct mmc *mmc = &plat->mmc; u32 bus_hz = priv->bus_clk_rate; + atmel_mci_t *mci = plat->mci; #else static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) { struct atmel_mci_priv *priv = mmc->priv; u32 bus_hz = get_mci_clk_rate(); + atmel_mci_t *mci = priv->mci; #endif - atmel_mci_t *mci = priv->mci; u32 clkdiv = 255; unsigned int version = atmel_mci_get_version(mci); u32 clkodd = 0; @@ -222,15 +234,17 @@ io_fail: static int atmel_mci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data) { + struct atmel_mci_plat *plat = dev_get_platdata(dev); struct atmel_mci_priv *priv = dev_get_priv(dev); struct mmc *mmc = mmc_get_mmc_dev(dev); + atmel_mci_t *mci = plat->mci; #else static int mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { struct atmel_mci_priv *priv = mmc->priv; -#endif atmel_mci_t *mci = priv->mci; +#endif u32 cmdr; u32 error_flags = 0; u32 status; @@ -362,22 +376,23 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) #ifdef CONFIG_DM_MMC static int atmel_mci_set_ios(struct udevice *dev) { - struct atmel_mci_priv *priv = dev_get_priv(dev); + struct atmel_mci_plat *plat = dev_get_platdata(dev); struct mmc *mmc = mmc_get_mmc_dev(dev); + atmel_mci_t *mci = plat->mci; #else /* Entered into mmc structure during driver init */ static int mci_set_ios(struct mmc *mmc) { struct atmel_mci_priv *priv = mmc->priv; -#endif atmel_mci_t *mci = priv->mci; +#endif int bus_width = mmc->bus_width; unsigned int version = atmel_mci_get_version(mci); int busw; /* Set the clock speed */ #ifdef CONFIG_DM_MMC - mci_set_mode(priv, mmc->clock, MMC_DEFAULT_BLKLEN); + mci_set_mode(dev, mmc->clock, MMC_DEFAULT_BLKLEN); #else mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN); #endif @@ -410,15 +425,17 @@ static int mci_set_ios(struct mmc *mmc) } #ifdef CONFIG_DM_MMC -static int atmel_mci_hw_init(struct atmel_mci_priv *priv) +static int atmel_mci_hw_init(struct udevice *dev) { + struct atmel_mci_plat *plat = dev_get_platdata(dev); + atmel_mci_t *mci = plat->mci; #else /* Entered into mmc structure during driver init */ static int mci_init(struct mmc *mmc) { struct atmel_mci_priv *priv = mmc->priv; -#endif atmel_mci_t *mci = priv->mci; +#endif /* Initialize controller */ writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */ @@ -433,7 +450,7 @@ static int mci_init(struct mmc *mmc) /* Set default clocks and blocklen */ #ifdef CONFIG_DM_MMC - mci_set_mode(priv, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); + mci_set_mode(dev, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); #else mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); #endif @@ -509,12 +526,14 @@ static const struct dm_mmc_ops atmel_mci_mmc_ops = { .set_ios = atmel_mci_set_ios, }; -static void atmel_mci_setup_cfg(struct atmel_mci_priv *priv) +static void atmel_mci_setup_cfg(struct udevice *dev) { + struct atmel_mci_plat *plat = dev_get_platdata(dev); + struct atmel_mci_priv *priv = dev_get_priv(dev); struct mmc_config *cfg; u32 version; - cfg = &priv->cfg; + cfg = &plat->cfg; cfg->name = "Atmel mci"; cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; @@ -522,7 +541,7 @@ static void atmel_mci_setup_cfg(struct atmel_mci_priv *priv) * If the version is above 3.0, the capabilities of the 8-bit * bus width and high speed are supported. */ - version = atmel_mci_get_version(priv->mci); + version = atmel_mci_get_version(plat->mci); if ((version & 0xf00) >= 0x300) { cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz; @@ -568,7 +587,7 @@ failed: static int atmel_mci_probe(struct udevice *dev) { struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); - struct atmel_mci_priv *priv = dev_get_priv(dev); + struct atmel_mci_plat *plat = dev_get_platdata(dev); struct mmc *mmc; int ret; @@ -576,25 +595,25 @@ static int atmel_mci_probe(struct udevice *dev) if (ret) return ret; - priv->mci = (struct atmel_mci *)devfdt_get_addr_ptr(dev); + plat->mci = (struct atmel_mci *)devfdt_get_addr_ptr(dev); - atmel_mci_setup_cfg(priv); + atmel_mci_setup_cfg(dev); - mmc = &priv->mmc; - mmc->cfg = &priv->cfg; + mmc = &plat->mmc; + mmc->cfg = &plat->cfg; mmc->dev = dev; upriv->mmc = mmc; - atmel_mci_hw_init(priv); + atmel_mci_hw_init(dev); return 0; } static int atmel_mci_bind(struct udevice *dev) { - struct atmel_mci_priv *priv = dev_get_priv(dev); + struct atmel_mci_plat *plat = dev_get_platdata(dev); - return mmc_bind(dev, &priv->mmc, &priv->cfg); + return mmc_bind(dev, &plat->mmc, &plat->cfg); } static const struct udevice_id atmel_mci_ids[] = { @@ -608,6 +627,7 @@ U_BOOT_DRIVER(atmel_mci) = { .of_match = atmel_mci_ids, .bind = atmel_mci_bind, .probe = atmel_mci_probe, + .platdata_auto_alloc_size = sizeof(struct atmel_mci_plat), .priv_auto_alloc_size = sizeof(struct atmel_mci_priv), .ops = &atmel_mci_mmc_ops, }; -- 2.13.0

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[U-Boot] [PATCH 1/3] mmc: sh_sdhi: Add DM and DT probing support
by Marek Vasut 17 Aug '17

17 Aug '17

Add MMC DM and DT probing support into the SH SDHI driver. This patch abstracts out the common bits of the send command and set ios functions, so they can be used both by DM and non DM setups and adds the DM probe support. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx(a)renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> --- drivers/mmc/sh_sdhi.c | 165 ++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 145 insertions(+), 20 deletions(-) diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c index d181b63905..fd710399b6 100644 --- a/drivers/mmc/sh_sdhi.c +++ b/drivers/mmc/sh_sdhi.c @@ -13,15 +13,18 @@ #include <common.h> #include <malloc.h> #include <mmc.h> +#include <dm.h> #include <linux/errno.h> -#include <asm/io.h> +#include <linux/compat.h> +#include <linux/io.h> +#include <linux/sizes.h> #include <asm/arch/rmobile.h> #include <asm/arch/sh_sdhi.h> #define DRIVER_NAME "sh-sdhi" struct sh_sdhi_host { - unsigned long addr; + void __iomem *addr; int ch; int bus_shift; unsigned long quirks; @@ -50,11 +53,6 @@ static inline u16 sh_sdhi_readw(struct sh_sdhi_host *host, int reg) return readw(host->addr + (reg << host->bus_shift)); } -static void *mmc_priv(struct mmc *mmc) -{ - return (void *)mmc->priv; -} - static void sh_sdhi_detect(struct sh_sdhi_host *host) { sh_sdhi_writew(host, SDHI_OPTION, @@ -634,23 +632,17 @@ static int sh_sdhi_start_cmd(struct sh_sdhi_host *host, return ret; } -static int sh_sdhi_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, - struct mmc_data *data) +static int sh_sdhi_send_cmd_common(struct sh_sdhi_host *host, + struct mmc_cmd *cmd, struct mmc_data *data) { - struct sh_sdhi_host *host = mmc_priv(mmc); - int ret; - host->sd_error = 0; - ret = sh_sdhi_start_cmd(host, data, cmd); - - return ret; + return sh_sdhi_start_cmd(host, data, cmd); } -static int sh_sdhi_set_ios(struct mmc *mmc) +static int sh_sdhi_set_ios_common(struct sh_sdhi_host *host, struct mmc *mmc) { int ret; - struct sh_sdhi_host *host = mmc_priv(mmc); ret = sh_sdhi_clock_control(host, mmc->clock); if (ret) @@ -674,9 +666,8 @@ static int sh_sdhi_set_ios(struct mmc *mmc) return 0; } -static int sh_sdhi_initialize(struct mmc *mmc) +static int sh_sdhi_initialize_common(struct sh_sdhi_host *host) { - struct sh_sdhi_host *host = mmc_priv(mmc); int ret = sh_sdhi_sync_reset(host); sh_sdhi_writew(host, SDHI_PORTSEL, USE_1PORT); @@ -692,6 +683,34 @@ static int sh_sdhi_initialize(struct mmc *mmc) return ret; } +#ifndef CONFIG_DM_MMC +static void *mmc_priv(struct mmc *mmc) +{ + return (void *)mmc->priv; +} + +static int sh_sdhi_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct sh_sdhi_host *host = mmc_priv(mmc); + + return sh_sdhi_send_cmd_common(host, cmd, data); +} + +static int sh_sdhi_set_ios(struct mmc *mmc) +{ + struct sh_sdhi_host *host = mmc_priv(mmc); + + return sh_sdhi_set_ios_common(host, mmc); +} + +static int sh_sdhi_initialize(struct mmc *mmc) +{ + struct sh_sdhi_host *host = mmc_priv(mmc); + + return sh_sdhi_initialize_common(host); +} + static const struct mmc_ops sh_sdhi_ops = { .send_cmd = sh_sdhi_send_cmd, .set_ios = sh_sdhi_set_ios, @@ -743,7 +762,7 @@ int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks) } host->ch = ch; - host->addr = addr; + host->addr = (void __iomem *)addr; host->quirks = quirks; if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF) @@ -757,3 +776,109 @@ error: free(host); return ret; } + +#else + +struct sh_sdhi_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +int sh_sdhi_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct sh_sdhi_host *host = dev_get_priv(dev); + + return sh_sdhi_send_cmd_common(host, cmd, data); +} + +int sh_sdhi_dm_set_ios(struct udevice *dev) +{ + struct sh_sdhi_host *host = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); + + return sh_sdhi_set_ios_common(host, mmc); +} + +static const struct dm_mmc_ops sh_sdhi_dm_ops = { + .send_cmd = sh_sdhi_dm_send_cmd, + .set_ios = sh_sdhi_dm_set_ios, +}; + +static int sh_sdhi_dm_bind(struct udevice *dev) +{ + struct sh_sdhi_plat *plat = dev_get_platdata(dev); + + return mmc_bind(dev, &plat->mmc, &plat->cfg); +} + +static int sh_sdhi_dm_probe(struct udevice *dev) +{ + struct sh_sdhi_plat *plat = dev_get_platdata(dev); + struct sh_sdhi_host *host = dev_get_priv(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + const u32 quirks = dev_get_driver_data(dev); + fdt_addr_t base; + + base = devfdt_get_addr(dev); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + host->addr = devm_ioremap(dev, base, SZ_2K); + if (!host->addr) + return -ENOMEM; + + host->quirks = quirks; + + if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF) + host->bus_shift = 2; + else if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF) + host->bus_shift = 1; + + plat->cfg.name = dev->name; + plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; + + switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width", + 1)) { + case 8: + plat->cfg.host_caps |= MMC_MODE_8BIT; + break; + case 4: + plat->cfg.host_caps |= MMC_MODE_4BIT; + break; + case 1: + break; + default: + dev_err(dev, "Invalid \"bus-width\" value\n"); + return -EINVAL; + } + + sh_sdhi_initialize_common(host); + + plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; + plat->cfg.f_min = CLKDEV_INIT; + plat->cfg.f_max = CLKDEV_HS_DATA; + plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + upriv->mmc = &plat->mmc; + + return 0; +} + +static const struct udevice_id sh_sdhi_sd_match[] = { + { .compatible = "renesas,sdhi-r8a7795", .data = SH_SDHI_QUIRK_64BIT_BUF }, + { .compatible = "renesas,sdhi-r8a7796", .data = SH_SDHI_QUIRK_64BIT_BUF }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(sh_sdhi_mmc) = { + .name = "sh-sdhi-mmc", + .id = UCLASS_MMC, + .of_match = sh_sdhi_sd_match, + .bind = sh_sdhi_dm_bind, + .probe = sh_sdhi_dm_probe, + .priv_auto_alloc_size = sizeof(struct sh_sdhi_host), + .platdata_auto_alloc_size = sizeof(struct sh_sdhi_plat), + .ops = &sh_sdhi_dm_ops, +}; +#endif -- 2.11.0

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