May 2017 - U-Boot

[U-Boot] [PATCH] net: Add ag7xxx driver for Atheros MIPS
by Marek Vasut 09 Jun '17

09 Jun '17

Add ethernet driver for the AR933x and AR934x Atheros MIPS machines. The driver could be easily extended to other WiSoCs. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Wills Wang <wills.wang(a)live.com> --- V2: - Drop the printf() in case malloc fails, it's pointless to try and print something if we cannot allocate memory, since printf also allocates memory. V3: - Replace magic 0x11 with MII_MIPSCR register --- drivers/net/Kconfig | 9 + drivers/net/Makefile | 1 + drivers/net/ag7xxx.c | 980 +++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 990 insertions(+) create mode 100644 drivers/net/ag7xxx.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 91b7690..00f151f 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -46,6 +46,15 @@ menuconfig NETDEVICES if NETDEVICES +config AG7XXX + bool "Atheros AG7xxx Ethernet MAC support" + depends on DM_ETH + select PHYLIB + help + This driver supports the Atheros AG7xxx Ethernet MAC. This MAC is + present in the Atheros AR7xxx, AR9xxx and QCA9xxx MIPS chips. + + config ALTERA_TSE bool "Altera Triple-Speed Ethernet MAC support" depends on DM_ETH diff --git a/drivers/net/Makefile b/drivers/net/Makefile index fbedd04..55d56a0 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o obj-$(CONFIG_ALTERA_TSE) += altera_tse.o +obj-$(CONFIG_AG7XXX) += ag7xxx.o obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o obj-$(CONFIG_DRIVER_AX88180) += ax88180.o diff --git a/drivers/net/ag7xxx.c b/drivers/net/ag7xxx.c new file mode 100644 index 0000000..346f138 --- /dev/null +++ b/drivers/net/ag7xxx.c @@ -0,0 +1,980 @@ +/* + * Atheros AR71xx / AR9xxx GMAC driver + * + * Copyright (C) 2016 Marek Vasut <marex(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <miiphy.h> +#include <malloc.h> +#include <linux/compiler.h> +#include <linux/err.h> +#include <linux/mii.h> +#include <wait_bit.h> +#include <asm/io.h> + +#include <mach/ath79.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum ag7xxx_model { + AG7XXX_MODEL_AG933X, + AG7XXX_MODEL_AG934X, +}; + +#define AG7XXX_ETH_CFG1 0x00 +#define AG7XXX_ETH_CFG1_SOFT_RST BIT(31) +#define AG7XXX_ETH_CFG1_RX_RST BIT(19) +#define AG7XXX_ETH_CFG1_TX_RST BIT(18) +#define AG7XXX_ETH_CFG1_LOOPBACK BIT(8) +#define AG7XXX_ETH_CFG1_RX_EN BIT(2) +#define AG7XXX_ETH_CFG1_TX_EN BIT(0) + +#define AG7XXX_ETH_CFG2 0x04 +#define AG7XXX_ETH_CFG2_IF_1000 BIT(9) +#define AG7XXX_ETH_CFG2_IF_10_100 BIT(8) +#define AG7XXX_ETH_CFG2_IF_SPEED_MASK (3 << 8) +#define AG7XXX_ETH_CFG2_HUGE_FRAME_EN BIT(5) +#define AG7XXX_ETH_CFG2_LEN_CHECK BIT(4) +#define AG7XXX_ETH_CFG2_PAD_CRC_EN BIT(2) +#define AG7XXX_ETH_CFG2_FDX BIT(0) + +#define AG7XXX_ETH_MII_MGMT_CFG 0x20 +#define AG7XXX_ETH_MII_MGMT_CFG_RESET BIT(31) + +#define AG7XXX_ETH_MII_MGMT_CMD 0x24 +#define AG7XXX_ETH_MII_MGMT_CMD_READ 0x1 + +#define AG7XXX_ETH_MII_MGMT_ADDRESS 0x28 +#define AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT 8 + +#define AG7XXX_ETH_MII_MGMT_CTRL 0x2c + +#define AG7XXX_ETH_MII_MGMT_STATUS 0x30 + +#define AG7XXX_ETH_MII_MGMT_IND 0x34 +#define AG7XXX_ETH_MII_MGMT_IND_INVALID BIT(2) +#define AG7XXX_ETH_MII_MGMT_IND_BUSY BIT(0) + +#define AG7XXX_ETH_ADDR1 0x40 +#define AG7XXX_ETH_ADDR2 0x44 + +#define AG7XXX_ETH_FIFO_CFG_0 0x48 +#define AG7XXX_ETH_FIFO_CFG_1 0x4c +#define AG7XXX_ETH_FIFO_CFG_2 0x50 +#define AG7XXX_ETH_FIFO_CFG_3 0x54 +#define AG7XXX_ETH_FIFO_CFG_4 0x58 +#define AG7XXX_ETH_FIFO_CFG_5 0x5c + +#define AG7XXX_ETH_DMA_TX_CTRL 0x180 +#define AG7XXX_ETH_DMA_TX_CTRL_TXE BIT(0) + +#define AG7XXX_ETH_DMA_TX_DESC 0x184 + +#define AG7XXX_ETH_DMA_TX_STATUS 0x188 + +#define AG7XXX_ETH_DMA_RX_CTRL 0x18c +#define AG7XXX_ETH_DMA_RX_CTRL_RXE BIT(0) + +#define AG7XXX_ETH_DMA_RX_DESC 0x190 + +#define AG7XXX_ETH_DMA_RX_STATUS 0x194 + +/* Custom register at 0x18070000 */ +#define AG7XXX_GMAC_ETH_CFG 0x00 +#define AG7XXX_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) +#define AG7XXX_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AG7XXX_ETH_CFG_SW_ONLY_MODE BIT(6) +#define AG7XXX_ETH_CFG_GE0_ERR_EN BIT(5) +#define AG7XXX_ETH_CFG_MII_GE0_SLAVE BIT(4) +#define AG7XXX_ETH_CFG_MII_GE0_MASTER BIT(3) +#define AG7XXX_ETH_CFG_GMII_GE0 BIT(2) +#define AG7XXX_ETH_CFG_MII_GE0 BIT(1) +#define AG7XXX_ETH_CFG_RGMII_GE0 BIT(0) + +#define CONFIG_TX_DESCR_NUM 8 +#define CONFIG_RX_DESCR_NUM 8 +#define CONFIG_ETH_BUFSIZE 2048 +#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) +#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) + +/* DMA descriptor. */ +struct ag7xxx_dma_desc { + u32 data_addr; +#define AG7XXX_DMADESC_IS_EMPTY BIT(31) +#define AG7XXX_DMADESC_FTPP_OVERRIDE_OFFSET 16 +#define AG7XXX_DMADESC_PKT_SIZE_OFFSET 0 +#define AG7XXX_DMADESC_PKT_SIZE_MASK 0xfff + u32 config; + u32 next_desc; + u32 _pad[5]; +}; + +struct ar7xxx_eth_priv { + struct ag7xxx_dma_desc tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; + struct ag7xxx_dma_desc rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; + char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); + char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); + + void __iomem *regs; + void __iomem *phyregs; + + struct eth_device *dev; + struct phy_device *phydev; + struct mii_dev *bus; + + u32 interface; + u32 tx_currdescnum; + u32 rx_currdescnum; + enum ag7xxx_model model; +}; + +/* + * Switch and MDIO access + */ +static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val) +{ + struct ar7xxx_eth_priv *priv = bus->priv; + void __iomem *regs = priv->phyregs; + int ret; + + writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD); + writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg, + regs + AG7XXX_ETH_MII_MGMT_ADDRESS); + writel(AG7XXX_ETH_MII_MGMT_CMD_READ, + regs + AG7XXX_ETH_MII_MGMT_CMD); + + ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND, + AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0); + if (ret) + return ret; + + *val = readl(regs + AG7XXX_ETH_MII_MGMT_STATUS) & 0xffff; + writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD); + + return 0; +} + +static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val) +{ + struct ar7xxx_eth_priv *priv = bus->priv; + void __iomem *regs = priv->phyregs; + int ret; + + writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg, + regs + AG7XXX_ETH_MII_MGMT_ADDRESS); + writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL); + + ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND, + AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0); + + return ret; +} + +static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val) +{ + struct ar7xxx_eth_priv *priv = bus->priv; + u32 phy_addr; + u32 reg_addr; + u32 phy_temp; + u32 reg_temp; + u16 rv = 0; + int ret; + + if (priv->model == AG7XXX_MODEL_AG933X) { + phy_addr = 0x1f; + reg_addr = 0x10; + } else if (priv->model == AG7XXX_MODEL_AG934X) { + phy_addr = 0x18; + reg_addr = 0x00; + } else + return -EINVAL; + + ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9); + if (ret) + return ret; + + phy_temp = ((reg >> 6) & 0x7) | 0x10; + reg_temp = (reg >> 1) & 0x1e; + *val = 0; + + ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, &rv); + if (ret < 0) + return ret; + *val |= rv; + + ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv); + if (ret < 0) + return ret; + *val |= (rv << 16); + + return 0; +} + +static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val) +{ + struct ar7xxx_eth_priv *priv = bus->priv; + u32 phy_addr; + u32 reg_addr; + u32 phy_temp; + u32 reg_temp; + int ret; + + if (priv->model == AG7XXX_MODEL_AG933X) { + phy_addr = 0x1f; + reg_addr = 0x10; + } else if (priv->model == AG7XXX_MODEL_AG934X) { + phy_addr = 0x18; + reg_addr = 0x00; + } else + return -EINVAL; + + ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9); + if (ret) + return ret; + + phy_temp = ((reg >> 6) & 0x7) | 0x10; + reg_temp = (reg >> 1) & 0x1e; + + /* + * The switch on AR933x has some special register behavior, which + * expects particular write order of their nibbles: + * 0x40 ..... MSB first, LSB second + * 0x50 ..... MSB first, LSB second + * 0x98 ..... LSB first, MSB second + * others ... don't care + */ + if ((priv->model == AG7XXX_MODEL_AG933X) && (reg == 0x98)) { + ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff); + if (ret < 0) + return ret; + + ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16); + if (ret < 0) + return ret; + } else { + ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16); + if (ret < 0) + return ret; + + ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff); + if (ret < 0) + return ret; + } + + return 0; +} + +static u16 ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val) +{ + u32 data; + + /* Dummy read followed by PHY read/write command. */ + ag7xxx_switch_reg_read(bus, 0x98, &data); + data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31); + ag7xxx_switch_reg_write(bus, 0x98, data); + + /* Wait for operation to finish */ + do { + ag7xxx_switch_reg_read(bus, 0x98, &data); + } while (data & BIT(31)); + + return data & 0xffff; +} + +static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + return ag7xxx_mdio_rw(bus, addr, reg, BIT(27)); +} + +static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + ag7xxx_mdio_rw(bus, addr, reg, val); + return 0; +} + +/* + * DMA ring handlers + */ +static void ag7xxx_dma_clean_tx(struct udevice *dev) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + struct ag7xxx_dma_desc *curr, *next; + u32 start, end; + int i; + + for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) { + curr = &priv->tx_mac_descrtable[i]; + next = &priv->tx_mac_descrtable[(i + 1) % CONFIG_TX_DESCR_NUM]; + + curr->data_addr = virt_to_phys(&priv->txbuffs[i * CONFIG_ETH_BUFSIZE]); + curr->config = AG7XXX_DMADESC_IS_EMPTY; + curr->next_desc = virt_to_phys(next); + } + + priv->tx_currdescnum = 0; + + /* Cache: Flush descriptors, don't care about buffers. */ + start = (u32)(&priv->tx_mac_descrtable[0]); + end = start + sizeof(priv->tx_mac_descrtable); + flush_dcache_range(start, end); +} + +static void ag7xxx_dma_clean_rx(struct udevice *dev) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + struct ag7xxx_dma_desc *curr, *next; + u32 start, end; + int i; + + for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) { + curr = &priv->rx_mac_descrtable[i]; + next = &priv->rx_mac_descrtable[(i + 1) % CONFIG_RX_DESCR_NUM]; + + curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CONFIG_ETH_BUFSIZE]); + curr->config = AG7XXX_DMADESC_IS_EMPTY; + curr->next_desc = virt_to_phys(next); + } + + priv->rx_currdescnum = 0; + + /* Cache: Flush+Invalidate descriptors, Invalidate buffers. */ + start = (u32)(&priv->rx_mac_descrtable[0]); + end = start + sizeof(priv->rx_mac_descrtable); + flush_dcache_range(start, end); + invalidate_dcache_range(start, end); + + start = (u32)&priv->rxbuffs; + end = start + sizeof(priv->rxbuffs); + invalidate_dcache_range(start, end); +} + +/* + * Ethernet I/O + */ +static int ag7xxx_eth_send(struct udevice *dev, void *packet, int length) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + struct ag7xxx_dma_desc *curr; + u32 start, end; + + curr = &priv->tx_mac_descrtable[priv->tx_currdescnum]; + + /* Cache: Invalidate descriptor. */ + start = (u32)curr; + end = start + sizeof(*curr); + invalidate_dcache_range(start, end); + + if (!(curr->config & AG7XXX_DMADESC_IS_EMPTY)) { + printf("ag7xxx: Out of TX DMA descriptors!\n"); + return -EPERM; + } + + /* Copy the packet into the data buffer. */ + memcpy(phys_to_virt(curr->data_addr), packet, length); + curr->config = length & AG7XXX_DMADESC_PKT_SIZE_MASK; + + /* Cache: Flush descriptor, Flush buffer. */ + start = (u32)curr; + end = start + sizeof(*curr); + flush_dcache_range(start, end); + start = (u32)phys_to_virt(curr->data_addr); + end = start + length; + flush_dcache_range(start, end); + + /* Load the DMA descriptor and start TX DMA. */ + writel(AG7XXX_ETH_DMA_TX_CTRL_TXE, + priv->regs + AG7XXX_ETH_DMA_TX_CTRL); + + /* Switch to next TX descriptor. */ + priv->tx_currdescnum = (priv->tx_currdescnum + 1) % CONFIG_TX_DESCR_NUM; + + return 0; +} + +static int ag7xxx_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + struct ag7xxx_dma_desc *curr; + u32 start, end, length; + + curr = &priv->rx_mac_descrtable[priv->rx_currdescnum]; + + /* Cache: Invalidate descriptor. */ + start = (u32)curr; + end = start + sizeof(*curr); + invalidate_dcache_range(start, end); + + /* No packets received. */ + if (curr->config & AG7XXX_DMADESC_IS_EMPTY) + return -EAGAIN; + + length = curr->config & AG7XXX_DMADESC_PKT_SIZE_MASK; + + /* Cache: Invalidate buffer. */ + start = (u32)phys_to_virt(curr->data_addr); + end = start + length; + invalidate_dcache_range(start, end); + + /* Receive one packet and return length. */ + *packetp = phys_to_virt(curr->data_addr); + return length; +} + +static int ag7xxx_eth_free_pkt(struct udevice *dev, uchar *packet, + int length) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + struct ag7xxx_dma_desc *curr; + u32 start, end; + + curr = &priv->rx_mac_descrtable[priv->rx_currdescnum]; + + curr->config = AG7XXX_DMADESC_IS_EMPTY; + + /* Cache: Flush descriptor. */ + start = (u32)curr; + end = start + sizeof(*curr); + flush_dcache_range(start, end); + + /* Switch to next RX descriptor. */ + priv->rx_currdescnum = (priv->rx_currdescnum + 1) % CONFIG_RX_DESCR_NUM; + + return 0; +} + +static int ag7xxx_eth_start(struct udevice *dev) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + + /* FIXME: Check if link up */ + + /* Clear the DMA rings. */ + ag7xxx_dma_clean_tx(dev); + ag7xxx_dma_clean_rx(dev); + + /* Load DMA descriptors and start the RX DMA. */ + writel(virt_to_phys(&priv->tx_mac_descrtable[priv->tx_currdescnum]), + priv->regs + AG7XXX_ETH_DMA_TX_DESC); + writel(virt_to_phys(&priv->rx_mac_descrtable[priv->rx_currdescnum]), + priv->regs + AG7XXX_ETH_DMA_RX_DESC); + writel(AG7XXX_ETH_DMA_RX_CTRL_RXE, + priv->regs + AG7XXX_ETH_DMA_RX_CTRL); + + return 0; +} + +static void ag7xxx_eth_stop(struct udevice *dev) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + + /* Stop the TX DMA. */ + writel(0, priv->regs + AG7XXX_ETH_DMA_TX_CTRL); + wait_for_bit("ag7xxx", priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0, + 1000, 0); + + /* Stop the RX DMA. */ + writel(0, priv->regs + AG7XXX_ETH_DMA_RX_CTRL); + wait_for_bit("ag7xxx", priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0, + 1000, 0); +} + +/* + * Hardware setup + */ +static int ag7xxx_eth_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + unsigned char *mac = pdata->enetaddr; + u32 macid_lo, macid_hi; + + macid_hi = mac[3] | (mac[2] << 8) | (mac[1] << 16) | (mac[0] << 24); + macid_lo = (mac[5] << 16) | (mac[4] << 24); + + writel(macid_lo, priv->regs + AG7XXX_ETH_ADDR1); + writel(macid_hi, priv->regs + AG7XXX_ETH_ADDR2); + + return 0; +} + +static void ag7xxx_hw_setup(struct udevice *dev) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + u32 speed; + + setbits_be32(priv->regs + AG7XXX_ETH_CFG1, + AG7XXX_ETH_CFG1_RX_RST | AG7XXX_ETH_CFG1_TX_RST | + AG7XXX_ETH_CFG1_SOFT_RST); + + mdelay(10); + + writel(AG7XXX_ETH_CFG1_RX_EN | AG7XXX_ETH_CFG1_TX_EN, + priv->regs + AG7XXX_ETH_CFG1); + + if (priv->interface == PHY_INTERFACE_MODE_RMII) + speed = AG7XXX_ETH_CFG2_IF_10_100; + else + speed = AG7XXX_ETH_CFG2_IF_1000; + + clrsetbits_be32(priv->regs + AG7XXX_ETH_CFG2, + AG7XXX_ETH_CFG2_IF_SPEED_MASK, + speed | AG7XXX_ETH_CFG2_PAD_CRC_EN | + AG7XXX_ETH_CFG2_LEN_CHECK); + + writel(0xfff0000, priv->regs + AG7XXX_ETH_FIFO_CFG_1); + writel(0x1fff, priv->regs + AG7XXX_ETH_FIFO_CFG_2); + + writel(0x1f00, priv->regs + AG7XXX_ETH_FIFO_CFG_0); + setbits_be32(priv->regs + AG7XXX_ETH_FIFO_CFG_4, 0x3ffff); + writel(0x10ffff, priv->regs + AG7XXX_ETH_FIFO_CFG_1); + writel(0xaaa0555, priv->regs + AG7XXX_ETH_FIFO_CFG_2); + writel(0x7eccf, priv->regs + AG7XXX_ETH_FIFO_CFG_5); + writel(0x1f00140, priv->regs + AG7XXX_ETH_FIFO_CFG_3); +} + +static int ag7xxx_mii_get_div(void) +{ + ulong freq = get_bus_freq(0); + + switch (freq / 1000000) { + case 150: return 0x7; + case 175: return 0x5; + case 200: return 0x4; + case 210: return 0x9; + case 220: return 0x9; + default: return 0x7; + } +} + +static int ag7xxx_mii_setup(struct udevice *dev) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + int i, ret, div = ag7xxx_mii_get_div(); + u32 reg; + + if (priv->model == AG7XXX_MODEL_AG933X) { + /* Unit 0 is PHY-less on AR9331, see datasheet Figure 2-3 */ + if (priv->interface == PHY_INTERFACE_MODE_RMII) + return 0; + } + + if (priv->model == AG7XXX_MODEL_AG934X) { + writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | 0x4, + priv->regs + AG7XXX_ETH_MII_MGMT_CFG); + writel(0x4, priv->regs + AG7XXX_ETH_MII_MGMT_CFG); + return 0; + } + + for (i = 0; i < 10; i++) { + writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | div, + priv->regs + AG7XXX_ETH_MII_MGMT_CFG); + writel(div, priv->regs + AG7XXX_ETH_MII_MGMT_CFG); + + /* Check the switch */ + ret = ag7xxx_switch_reg_read(priv->bus, 0x10c, &reg); + if (ret) + continue; + + if (reg != 0x18007fff) + continue; + + return 0; + } + + return -EINVAL; +} + +static int ag933x_phy_setup_wan(struct udevice *dev) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + + /* Configure switch port 4 (GMAC0) */ + return ag7xxx_mdio_write(priv->bus, 4, 0, MII_BMCR, 0x9000); +} + +static int ag933x_phy_setup_lan(struct udevice *dev) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + int i, ret; + u32 reg; + + /* Reset the switch */ + ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg); + if (ret) + return ret; + reg |= BIT(31); + ret = ag7xxx_switch_reg_write(priv->bus, 0, reg); + if (ret) + return ret; + + do { + ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg); + if (ret) + return ret; + } while (reg & BIT(31)); + + /* Configure switch ports 0...3 (GMAC1) */ + for (i = 0; i < 4; i++) { + ret = ag7xxx_mdio_write(priv->bus, 0x4, 0, MII_BMCR, 0x9000); + if (ret) + return ret; + } + + /* Enable CPU port */ + ret = ag7xxx_switch_reg_write(priv->bus, 0x78, BIT(8)); + if (ret) + return ret; + + for (i = 0; i < 4; i++) { + ret = ag7xxx_switch_reg_write(priv->bus, i * 0x100, BIT(9)); + if (ret) + return ret; + } + + /* QM Control */ + ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e); + if (ret) + return ret; + + /* Disable Atheros header */ + ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004); + if (ret) + return ret; + + /* Tag priority mapping */ + ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50); + if (ret) + return ret; + + /* Enable ARP packets to the CPU */ + ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, &reg); + if (ret) + return ret; + reg |= 0x100000; + ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg); + if (ret) + return ret; + + return 0; +} + +static int ag933x_phy_setup_reset_set(struct udevice *dev, int port) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + int ret; + + ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_ADVERTISE, + ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | + ADVERTISE_PAUSE_ASYM); + if (ret) + return ret; + + if (priv->model == AG7XXX_MODEL_AG934X) { + ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_CTRL1000, + ADVERTISE_1000FULL); + if (ret) + return ret; + } + + return ag7xxx_mdio_write(priv->bus, port, 0, MII_BMCR, + BMCR_ANENABLE | BMCR_RESET); +} + +static int ag933x_phy_setup_reset_fin(struct udevice *dev, int port) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + int ret; + + do { + ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR); + if (ret < 0) + return ret; + mdelay(10); + } while (ret & BMCR_RESET); + + return 0; +} + +static int ag933x_phy_setup_common(struct udevice *dev) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + int i, ret, phymax; + + if (priv->model == AG7XXX_MODEL_AG933X) + phymax = 4; + else if (priv->model == AG7XXX_MODEL_AG934X) + phymax = 5; + else + return -EINVAL; + + if (priv->interface == PHY_INTERFACE_MODE_RMII) { + ret = ag933x_phy_setup_reset_set(dev, phymax); + if (ret) + return ret; + + ret = ag933x_phy_setup_reset_fin(dev, phymax); + if (ret) + return ret; + + /* Read out link status */ + ret = ag7xxx_mdio_read(priv->bus, phymax, 0, MII_MIPSCR); + if (ret < 0) + return ret; + + return 0; + } + + /* Switch ports */ + for (i = 0; i < phymax; i++) { + ret = ag933x_phy_setup_reset_set(dev, i); + if (ret) + return ret; + } + + for (i = 0; i < phymax; i++) { + ret = ag933x_phy_setup_reset_fin(dev, i); + if (ret) + return ret; + } + + for (i = 0; i < phymax; i++) { + /* Read out link status */ + ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR); + if (ret < 0) + return ret; + } + + return 0; +} + +static int ag934x_phy_setup(struct udevice *dev) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + int i, ret; + u32 reg; + + ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f); + if (ret) + return ret; + ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x40000000); + if (ret) + return ret; + ret = ag7xxx_switch_reg_write(priv->bus, 0x4, 0x07600000); + if (ret) + return ret; + ret = ag7xxx_switch_reg_write(priv->bus, 0xc, 0x01000000); + if (ret) + return ret; + ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e); + if (ret) + return ret; + + /* AR8327/AR8328 v1.0 fixup */ + ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg); + if (ret) + return ret; + if ((reg & 0xffff) == 0x1201) { + for (i = 0; i < 5; i++) { + ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x0); + if (ret) + return ret; + ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x02ea); + if (ret) + return ret; + ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x3d); + if (ret) + return ret; + ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x68a0); + if (ret) + return ret; + } + } + + ret = ag7xxx_switch_reg_read(priv->bus, 0x66c, &reg); + if (ret) + return ret; + reg &= ~0x70000; + ret = ag7xxx_switch_reg_write(priv->bus, 0x66c, reg); + if (ret) + return ret; + + return 0; +} + +static int ag7xxx_mac_probe(struct udevice *dev) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + int ret; + + ag7xxx_hw_setup(dev); + ret = ag7xxx_mii_setup(dev); + if (ret) + return ret; + + ag7xxx_eth_write_hwaddr(dev); + + if (priv->model == AG7XXX_MODEL_AG933X) { + if (priv->interface == PHY_INTERFACE_MODE_RMII) + ret = ag933x_phy_setup_wan(dev); + else + ret = ag933x_phy_setup_lan(dev); + } else if (priv->model == AG7XXX_MODEL_AG934X) { + ret = ag934x_phy_setup(dev); + } else { + return -EINVAL; + } + + if (ret) + return ret; + + return ag933x_phy_setup_common(dev); +} + +static int ag7xxx_mdio_probe(struct udevice *dev) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + struct mii_dev *bus = mdio_alloc(); + + if (!bus) + return -ENOMEM; + + bus->read = ag7xxx_mdio_read; + bus->write = ag7xxx_mdio_write; + snprintf(bus->name, sizeof(bus->name), dev->name); + + bus->priv = (void *)priv; + + return mdio_register(bus); +} + +static int ag7xxx_get_phy_iface_offset(struct udevice *dev) +{ + int offset; + + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, "phy"); + if (offset <= 0) { + debug("%s: PHY OF node not found (ret=%i)\n", __func__, offset); + return -EINVAL; + } + + offset = fdt_parent_offset(gd->fdt_blob, offset); + if (offset <= 0) { + debug("%s: PHY OF node parent MDIO bus not found (ret=%i)\n", + __func__, offset); + return -EINVAL; + } + + offset = fdt_parent_offset(gd->fdt_blob, offset); + if (offset <= 0) { + debug("%s: PHY MDIO OF node parent MAC not found (ret=%i)\n", + __func__, offset); + return -EINVAL; + } + + return offset; +} + +static int ag7xxx_eth_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + void __iomem *iobase, *phyiobase; + int ret, phyreg; + + /* Decoding of convoluted PHY wiring on Atheros MIPS. */ + ret = ag7xxx_get_phy_iface_offset(dev); + if (ret <= 0) + return ret; + phyreg = fdtdec_get_int(gd->fdt_blob, ret, "reg", -1); + + iobase = map_physmem(pdata->iobase, 0x200, MAP_NOCACHE); + phyiobase = map_physmem(phyreg, 0x200, MAP_NOCACHE); + + debug("%s, iobase=%p, phyiobase=%p, priv=%p\n", + __func__, iobase, phyiobase, priv); + priv->regs = iobase; + priv->phyregs = phyiobase; + priv->interface = pdata->phy_interface; + priv->model = dev_get_driver_data(dev); + + ret = ag7xxx_mdio_probe(dev); + if (ret) + return ret; + + priv->bus = miiphy_get_dev_by_name(dev->name); + + ret = ag7xxx_mac_probe(dev); + debug("%s, ret=%d\n", __func__, ret); + + return ret; +} + +static int ag7xxx_eth_remove(struct udevice *dev) +{ + struct ar7xxx_eth_priv *priv = dev_get_priv(dev); + + free(priv->phydev); + mdio_unregister(priv->bus); + mdio_free(priv->bus); + + return 0; +} + +static const struct eth_ops ag7xxx_eth_ops = { + .start = ag7xxx_eth_start, + .send = ag7xxx_eth_send, + .recv = ag7xxx_eth_recv, + .free_pkt = ag7xxx_eth_free_pkt, + .stop = ag7xxx_eth_stop, + .write_hwaddr = ag7xxx_eth_write_hwaddr, +}; + +static int ag7xxx_eth_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + const char *phy_mode; + int ret; + + pdata->iobase = dev_get_addr(dev); + pdata->phy_interface = -1; + + /* Decoding of convoluted PHY wiring on Atheros MIPS. */ + ret = ag7xxx_get_phy_iface_offset(dev); + if (ret <= 0) + return ret; + + phy_mode = fdt_getprop(gd->fdt_blob, ret, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + + return 0; +} + +static const struct udevice_id ag7xxx_eth_ids[] = { + { .compatible = "qca,ag933x-mac", .data = AG7XXX_MODEL_AG933X }, + { .compatible = "qca,ag934x-mac", .data = AG7XXX_MODEL_AG934X }, + { } +}; + +U_BOOT_DRIVER(eth_ag7xxx) = { + .name = "eth_ag7xxx", + .id = UCLASS_ETH, + .of_match = ag7xxx_eth_ids, + .ofdata_to_platdata = ag7xxx_eth_ofdata_to_platdata, + .probe = ag7xxx_eth_probe, + .remove = ag7xxx_eth_remove, + .ops = &ag7xxx_eth_ops, + .priv_auto_alloc_size = sizeof(struct ar7xxx_eth_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; -- 2.7.0

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[U-Boot] [PATCH] cmd/fdt: support single value replacement within an array
by Hannes Schmelzer 09 Jun '17

09 Jun '17

With this commit we can modify single values within an array of a dts property. This is useful if we have for example a pwm-backlight where we want to modifiy the pwm frequency per u-boot script. The pwm is described in dts like this: backlight { pwms = <0x0000002b 0x00000000 0x004c4b40>; }; For changing the frequency, here the 3rd parameter, we simply type: fdt set /backlight pwms <? ? 0x1E8480>; For doing all this we: - backup the property content into our 'SCRATCHPAD' - only modify the array-cell if the new content doesn't start with '?' Signed-off-by: Hannes Schmelzer <hannes.schmelzer(a)br-automation.com> --- cmd/fdt.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/cmd/fdt.c b/cmd/fdt.c index a21415d..e55102a 100644 --- a/cmd/fdt.c +++ b/cmd/fdt.c @@ -257,6 +257,7 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) char *prop; /* property */ int nodeoffset; /* node offset from libfdt */ static char data[SCRATCHPAD]; /* storage for the property */ + const void *ptmp; int len; /* new length of the property */ int ret; /* return value */ @@ -268,13 +269,6 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) pathp = argv[2]; prop = argv[3]; - if (argc == 4) { - len = 0; - } else { - ret = fdt_parse_prop(&argv[4], argc - 4, data, &len); - if (ret != 0) - return ret; - } nodeoffset = fdt_path_offset (working_fdt, pathp); if (nodeoffset < 0) { @@ -286,6 +280,21 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; } + if (argc == 4) { + len = 0; + } else { + ptmp = fdt_getprop(working_fdt, nodeoffset, prop, &len); + if (len > SCRATCHPAD) { + printf("prop (%d) doesn't fit in scratchpad!\n", + len); + return 1; + } + memcpy(data, ptmp, len); + ret = fdt_parse_prop(&argv[4], argc - 4, data, &len); + if (ret != 0) + return ret; + } + ret = fdt_setprop(working_fdt, nodeoffset, prop, data, len); if (ret < 0) { printf ("libfdt fdt_setprop(): %s\n", fdt_strerror(ret)); @@ -766,7 +775,11 @@ static int fdt_parse_prop(char * const *newval, int count, char *data, int *len) cp = newp; tmp = simple_strtoul(cp, &newp, 0); - *(fdt32_t *)data = cpu_to_fdt32(tmp); + if (*cp != '?') + *(fdt32_t *)data = cpu_to_fdt32(tmp); + else + newp++; + data += 4; *len += 4; -- 1.9.1

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[U-Boot] [PATCH v2 00/28] tegra: nyan-big: Support chainloading and add documentation
by Simon Glass 09 Jun '17

09 Jun '17

Every now and then someone wants to chain-load U-Boot on a Chromebook. The procedure is not very complicated but there are some oddities. This series updates a few things with allow U-Boot to start on nyan-big in this way and adds documentation on how to do it. This provides a central place where the procedure on different devices can be documented. Changes in v2: - Add new patch containing a .its file for chromium - Explain how to create dummy.txt - Add a comment about how to create a protective MBR - Add new patch containing a .its file for chromium - Add instructions and patches for chain-loading into U-Boot on jerry Simon Glass (28): display_options: Refactor to allow obtaining the banner Allow displaying the U-Boot banner on a video display arm: arm720t: Support CONFIG_SKIP_LOWLEVEL_INIT_ONLY arm: Rename HCTR to HTCR arm: Don't try to support CONFIG_ARMV7_LPAE on ARMv4T arm: Disable LPAE if not enabled power: regulator: Add more debugging and fix a missing newline tegra: Init clocks even when SPL did not run tegra: dts: Add cros-ec SPI settings tegra: spi: Wait a little after setting the clocks tegra: nyan-big: Enable the dhrystone benchmark tegra: video: Don't power up the SOR twice tegra: Enable CP15 init tegra: clock: Avoid a divide-by-zero error tegra: nyan-big: Add a .its file for chromium README: Add instructions for chain-loading U-Boot rockchip: Setup default PWM flags rockchip: Fix regualtor typo in veyron rockchip: rk3288: Add error debugging to veyron_init() rockchip: video: Add remove() methods rockchip: video: Take the vop device out of standby rockchip: jerry: Add a .its file for chromium rockchip: rk3288: Convert clock driver to use shifted masks rockchip: Init clocks again when chain-loading rockchip: rk3288: Allow setting up clocks in U-Boot proper rockchip: Enable the video display banner rockchip: jerry: Disable CONFIG_CONSOLE_SCROLL_LINES README: Add instructions for chain-loading U-Boot on jerry arch/arm/cpu/arm720t/start.S | 6 +- arch/arm/dts/rk3288-veyron-jerry.dts | 2 +- arch/arm/dts/tegra124-nyan-big-u-boot.dtsi | 9 + arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 74 +++---- arch/arm/include/asm/arch-tegra/clock.h | 3 + arch/arm/lib/cache-cp15.c | 13 +- arch/arm/mach-rockchip/rk3288-board.c | 39 +++- arch/arm/mach-tegra/board2.c | 3 + arch/arm/mach-tegra/clock.c | 10 +- arch/arm/mach-tegra/tegra124/clock.c | 18 ++ cmd/version.c | 4 +- common/board_r.c | 1 + common/console.c | 15 +- configs/chromebook_jerry_defconfig | 2 +- configs/nyan-big_defconfig | 2 + doc/README.chromium | 252 ++++++++++++++++++++++++ doc/chromium/chromebook_jerry.its | 42 ++++ doc/chromium/devkeys/kernel.keyblock | Bin 0 -> 1208 bytes doc/chromium/devkeys/kernel_data_key.vbprivk | Bin 0 -> 1199 bytes doc/chromium/nyan-big.its | 42 ++++ drivers/clk/rockchip/clk_rk3288.c | 146 +++++++------- drivers/power/regulator/regulator-uclass.c | 8 +- drivers/pwm/rk_pwm.c | 1 + drivers/spi/tegra114_spi.c | 1 + drivers/video/rockchip/rk_edp.c | 16 +- drivers/video/rockchip/rk_vop.c | 21 +- drivers/video/tegra124/sor.c | 9 + include/configs/rockchip-common.h | 2 + include/configs/tegra-common-post.h | 2 +- include/console.h | 12 ++ include/display_options.h | 15 ++ lib/display_options.c | 21 +- 32 files changed, 656 insertions(+), 135 deletions(-) create mode 100644 doc/README.chromium create mode 100644 doc/chromium/chromebook_jerry.its create mode 100644 doc/chromium/devkeys/kernel.keyblock create mode 100644 doc/chromium/devkeys/kernel_data_key.vbprivk create mode 100644 doc/chromium/nyan-big.its -- 2.13.0.219.gdb65acc882-goog

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[U-Boot] [PATCH 1/2] sun8i: h3: Add initial NanoPi M1 Plus support
by Jagan Teki 08 Jun '17

08 Jun '17

From: Jagan Teki <jagan(a)amarulasolutions.com> NanoPi M1 Plus is designed and developed by FriendlyElec for professionals, enterprise users, makers and hobbyists using the Allwinner H3 SOC. NanoPi M1 Plus key features - Allwinner H3, Quad-core Cortex-A7(a)1.2GHz - 1GB DDR3 RAM - 8GB eMMC - microSD slot - 10/100/1000M Ethernet - Serial Debug Port - 5V 2A DC power-supply Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- Note: Need to add mmc node for eMMC, will add it on next version once tested arch/arm/dts/Makefile | 1 + arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts | 64 ++++++++++++++++++++++++++++++++ board/sunxi/MAINTAINERS | 5 +++ configs/nanopi_m1_plus_defconfig | 18 +++++++++ 4 files changed, 88 insertions(+) create mode 100644 arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts create mode 100644 configs/nanopi_m1_plus_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index eaf9ada..bf16563 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -309,6 +309,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ sun8i-h3-orangepi-plus.dtb \ sun8i-h3-orangepi-plus2e.dtb \ sun8i-h3-nanopi-m1.dtb \ + sun8i-h3-nanopi-m1-plus.dtb \ sun8i-h3-nanopi-neo.dtb \ sun8i-h3-nanopi-neo-air.dtb dtb-$(CONFIG_MACH_SUN8I_R40) += \ diff --git a/arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts new file mode 100644 index 0000000..8ddd1b2 --- /dev/null +++ b/arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2017 Jagan Teki <jteki(a)openedev.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-h3-nanopi.dtsi" + +/ { + model = "FriendlyArm NanoPi M1 Plus"; + compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 010e87c..531e6e0 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -252,6 +252,11 @@ M: Mylène Josserand <mylene.josserand(a)free-electrons.com> S: Maintained F: configs/nanopi_m1_defconfig +NANOPI-M1 PLUS BOARD +M: Jagan Teki <jagan(a)amarulasolutions.com> +S: Maintained +F: configs/nanopi_m1_plus_defconfig + NANOPI-NEO BOARD M: Jelle van der Waa <jelle(a)vdwaa.nl> S: Maintained diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig new file mode 100644 index 0000000..d7a908d --- /dev/null +++ b/configs/nanopi_m1_plus_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN8I_H3=y +CONFIG_DRAM_CLK=408 +CONFIG_DRAM_ZQ=3881979 +CONFIG_DRAM_ODT_EN=y +CONFIG_MMC0_CD_PIN="PH13" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-m1-plus" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_USB_EHCI_HCD=y -- 1.9.1

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[U-Boot] [PATCH v4 0/9] rockchip: video: rk3399: enable HDMI output
by Philipp Tomsich 08 Jun '17

08 Jun '17

This series provides HDMI enablement for the RK3399 and will support video console on the RK3399 either with VOP-lit or VOP-big: - pinctrl and clk support for the hdmi node - a refactoring of rk_vop.c and rk_hdmi.c to allow for the minor differences between the RK3288 and RK3399 VOP and HDMI blocks This has been tested (on top of sjg/master) using 'bmp display' and 'setenv stdout vidconsole' on the RK3399-Q7 with various HDMI monitors, both for VOP-lit and VOP-big (setting the other one to 'disabled'). v4 splits the changes to the rk_vop and rk_hdmi components into more manageable series of changes. Changes in v4: - added patch to break down into smaller changes - added patch to break down into smaller changes - added patch to break down into smaller changes - split the massive "refactor, split and add RK3399 support"-change into smaller chunks that are more easily digestible - new patch (split off from the earlier RK3399 HDMI encoder change) - splits the large change into smaller changes Changes in v3: - splits the VOP driver into SOC-specific and common portions - moves the "maximum x" and "maximum y" resolution config into Kconfig (instead of having hard-coded values that may need to be revised each time someone adds a new device or new features) - split into separate drivers for the SOC-specific portion of the driver - rebase to sjg/next Changes in v2: - removed DEBUG from the patch (as was done in our production branches, but missing from the patch-prep branch) - updated SJG's comment (with a TODO for the RK3288) to reflect the new code structure Philipp Tomsich (9): rockchip: video: Kconfig: reformat help for VIDEO_ROCKCHIP rockchip: video: Kconfig: set MAX_XRES and MAX_YRES via Kconfig rockchip: video: refactor rk_vop and split RK3328-specific code off rockchip: video: rk3399: enable HDMI output (from the rk_vop) for the RK3399 rockchip: video: add mpixelclock settings from Linux driver rockchip: video: split RK3228-specific part off from rk_hdmi rockchip: video: rk3399: add HDMI TX support on the RK3399 rockchip: dts: rk3399: enable HDMI output in the DTS rockchip: board: puma_rk3399: enable BMP_16BPP, BMP_24BPP and BMP_32BPP arch/arm/dts/rk3399.dtsi | 39 +++++ arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 3 + arch/arm/include/asm/arch-rockchip/vop_rk3288.h | 11 ++ drivers/video/rockchip/Kconfig | 29 +++- drivers/video/rockchip/Makefile | 6 +- drivers/video/rockchip/rk3288_hdmi.c | 116 +++++++++++++++ drivers/video/rockchip/rk3288_vop.c | 95 ++++++++++++ drivers/video/rockchip/rk3399_hdmi.c | 81 +++++++++++ drivers/video/rockchip/rk3399_vop.c | 105 ++++++++++++++ drivers/video/rockchip/rk_hdmi.c | 114 ++++----------- drivers/video/rockchip/rk_hdmi.h | 32 ++++ drivers/video/rockchip/rk_vop.c | 185 ++++++++++++------------ drivers/video/rockchip/rk_vop.h | 32 ++++ include/configs/puma_rk3399.h | 4 + 14 files changed, 662 insertions(+), 190 deletions(-) create mode 100644 drivers/video/rockchip/rk3288_hdmi.c create mode 100644 drivers/video/rockchip/rk3288_vop.c create mode 100644 drivers/video/rockchip/rk3399_hdmi.c create mode 100644 drivers/video/rockchip/rk3399_vop.c create mode 100644 drivers/video/rockchip/rk_hdmi.h create mode 100644 drivers/video/rockchip/rk_vop.h -- 1.9.1

5 34

[U-Boot] [PATCH v2 0/8] drivers: i2c: davinci_i2c: Convert driver to DM
by Franklin S Cooper Jr 08 Jun '17

08 Jun '17

This patch series converts the davinci i2c driver to use device model. This updated driver has been verified on both Keystone K2G and Keystone K2L evms by performing several i2c operations in U-boot prompt. Some additional work was required to get things working on K2G due to the code that reads the on board EEPROM. DM I2C sets the default address length to a default value of 1 when the on EEPROM requires an address length of 2. Therefore, an additional function and minor changes were required to get things working properly. Franklin S Cooper Jr (8): i2c: davinci: Split functions into two parts for future DM support drivers: i2c: davinci_i2c: Update davinci i2c driver to driver model ti: common: board_detect: Introduce function to set the address length. ti: common: board_detect: Set alen to expected value before i2c read ARM: dts: k2g: Add I2C nodes to 66AK2Gx ARM: dts: keystone2: add I2C aliases for davinci I2C nodes ARM: dts: keystone-k2g-evm: Enable I2C0 and I2C1 ARM: keystone: Enable DM_I2C by default arch/arm/dts/keystone-k2g-evm.dts | 8 ++ arch/arm/dts/keystone-k2g.dtsi | 32 +++++ arch/arm/dts/keystone.dtsi | 3 + arch/arm/mach-keystone/Kconfig | 4 + board/ti/common/board_detect.c | 61 ++++++++- drivers/i2c/davinci_i2c.c | 277 +++++++++++++++++++++++++++----------- 6 files changed, 306 insertions(+), 79 deletions(-) -- 2.10.0

5 25

[U-Boot] [PATCH 1/5] mmc: sh_sdhi: Fix Kconfig entry
by Marek Vasut 07 Jun '17

07 Jun '17

The Kconfig entry depends on RMOBILE, but this was renamed to ARCH_RMOBILE in commit 1cc95f6e1b38 (ARM: Rmobile: Rename CONFIG_RMOBILE to CONFIG_ARCH_RMOBILE) . Fix this omission. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx(a)renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> --- drivers/mmc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 6ac26dd137..b2d70a37bd 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -159,7 +159,7 @@ config MMC_OMAP36XX_PINS config SH_SDHI bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support" - depends on RMOBILE + depends on ARCH_RMOBILE help Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform -- 2.11.0

4 23

[U-Boot] [PATCH] ARM: zynq: Add support for the topic-miamilite system-on-module
by Mike Looijmans 07 Jun '17

07 Jun '17

The topic-miamilite SoM contains a Zynq xc7z010 SoC, 1GB DDR3L RAM, 64MB dual-parallel QSPI NOR flash and clock sources. Signed-off-by: Mike Looijmans <mike.looijmans(a)topic.nl> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/zynq-topic-miamilite.dts | 17 ++ .../topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c | 227 +++++++++++++++++++++ board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt | 61 ++++++ configs/topic_miamilite_defconfig | 52 +++++ include/configs/topic_miamilite.h | 2 + 6 files changed, 360 insertions(+) create mode 100644 arch/arm/dts/zynq-topic-miamilite.dts create mode 100644 board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c create mode 100644 board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt create mode 100644 configs/topic_miamilite_defconfig create mode 100644 include/configs/topic_miamilite.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2b1a4e9..8745f04 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -122,6 +122,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-microzed.dtb \ zynq-picozed.dtb \ zynq-topic-miami.dtb \ + zynq-topic-miamilite.dtb \ zynq-topic-miamiplus.dtb \ zynq-zc770-xm010.dtb \ zynq-zc770-xm011.dtb \ diff --git a/arch/arm/dts/zynq-topic-miamilite.dts b/arch/arm/dts/zynq-topic-miamilite.dts new file mode 100644 index 0000000..f88cb4b --- /dev/null +++ b/arch/arm/dts/zynq-topic-miamilite.dts @@ -0,0 +1,17 @@ +/* + * Topic Miami Lite board DTS + * + * Copyright (C) 2017 Topic Embedded Products + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include "zynq-topic-miami.dts" + +/ { + model = "Topic Miami Lite Zynq Board"; + compatible = "topic,miamilite", "xlnx,zynq-7000"; +}; + +&qspi { + is-dual = <1>; +}; diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c new file mode 100644 index 0000000..ec0cc7d --- /dev/null +++ b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c @@ -0,0 +1,227 @@ +/* + * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. + * (c) Copyright 2016 Topic Embedded Products. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "../ps7_init_gpl.h" + +static unsigned long ps7_pll_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U), + EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U), + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000001U), + EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U), + EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U), + EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U), + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000002U), + EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U), + EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x00113220U), + EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x00024000U), + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U), + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U), + EMIT_MASKPOLL(0xF800010C, 0x00000004U), + EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_clock_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00302301U), + EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0xF800013C, 0x00000011U, 0x00000011U), + EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100141U), + EMIT_MASKWRITE(0xF8000144, 0x03F03F71U, 0x00100141U), + EMIT_MASKWRITE(0xF8000148, 0x00003F31U, 0x00000C01U), + EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000601U), + EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001803U), + EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000C03U), + EMIT_MASKWRITE(0xF8000158, 0x00003F33U, 0x00000601U), + EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000601U), + EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00100C00U), + EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00100C00U), + EMIT_MASKWRITE(0xF8000190, 0x03F03F30U, 0x00100600U), + EMIT_MASKWRITE(0xF80001A0, 0x03F03F30U, 0x00101800U), + EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01FC4C4DU), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_ddr_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U), + EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001081U), + EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU), + EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U), + EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U), + EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004281AU), + EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D2U), + EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x720238E5U), + EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U), + EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U), + EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U), + EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U), + EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040930U), + EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U), + EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U), + EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U), + EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U), + EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U), + EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U), + EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U), + EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U), + EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU), + EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U), + EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U), + EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U), + EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U), + EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U), + EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U), + EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U), + EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU), + EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU), + EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U), + EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U), + EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000003U), + EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U), + EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U), + EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U), + EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U), + EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U), + EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0003482CU), + EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00033032U), + EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x0002E81FU), + EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x0002F81AU), + EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U), + EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x000000ACU), + EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000B2U), + EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x0000009FU), + EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x0000009AU), + EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x00000127U), + EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x00000121U), + EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x0000010FU), + EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x00000113U), + EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000ECU), + EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000F2U), + EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000DFU), + EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000DAU), + EMIT_MASKWRITE(0xF8006190, 0xFFFFFFFFU, 0x1002E080U), + EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U), + EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU), + EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U), + EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U), + EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U), + EMIT_MASKPOLL(0xF8000B74, 0x00002000U), + EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U), + EMIT_MASKPOLL(0xF8006054, 0x00000007U), + EMIT_EXIT(), +}; + +static unsigned long ps7_mio_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U), + EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U), + EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U), + EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU), + EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU), + EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000E60U), + EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U), + EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U), + EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +static unsigned long ps7_peripherals_init_data_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U), + EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU), + EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U), + EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U), + EMIT_MASKWRITE(0xE000D000, 0x000800FFU, 0x000800C1U), + EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_MASKDELAY(0xF8F00200, 1), + EMIT_EXIT(), +}; + +static unsigned long ps7_post_config_3_0[] = { + EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), + EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU), + EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U), + EMIT_MASKWRITE(0xF8000004, 0x0000FFFFU, 0x0000767BU), + EMIT_EXIT(), +}; + +int ps7_init(void) +{ + int ret; + + ret = ps7_config(ps7_mio_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_pll_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_clock_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_ddr_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + ret = ps7_config(ps7_peripherals_init_data_3_0); + if (ret != PS7_INIT_SUCCESS) + return ret; + + return PS7_INIT_SUCCESS; +} + +int ps7_post_config(void) +{ + return ps7_config(ps7_post_config_3_0); +} diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt b/board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt new file mode 100644 index 0000000..db6e642 --- /dev/null +++ b/board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt @@ -0,0 +1,61 @@ +0xF8000120 0x1F000200 // ARM_CLK_CTRL - divisor = 2 433 MHz (?) +0xf8000700 0x202 +0xf8000704 0x202 +0xf8000708 0x202 +0xf800070c 0x202 +0xf8000710 0x202 +0xf8000714 0x202 +0xf8000718 0x202 +0xf800071c 0x200 +0xf8000720 0x202 +0xf8000724 0x202 +0xf8000728 0x202 +0xf800072c 0x202 +0xf8000730 0x202 +0xf8000734 0x202 +0xf8000738 0x12e1 +0xf800073c 0x12e0 +0xf8000740 0x1200 +0xf8000744 0x1200 +0xf8000748 0x1200 +0xf800074c 0x1200 +0xf8000750 0x1200 +0xf8000754 0x1200 +0xf8000758 0x1200 +0xf800075c 0x1200 +0xf8000760 0x1200 +0xf8000764 0x200 +0xf8000768 0x1200 +0xf800076c 0x200 +0xf8000770 0x304 +0xf8000774 0x305 +0xf8000778 0x304 +0xf800077c 0x305 +0xf8000780 0x304 +0xf8000784 0x304 +0xf8000788 0x304 +0xf800078c 0x304 +0xf8000790 0x305 +0xf8000794 0x304 +0xf8000798 0x304 +0xf800079c 0x304 +0xf80007a0 0x380 +0xf80007a4 0x380 +0xf80007a8 0x380 +0xf80007ac 0x380 +0xf80007b0 0x380 +0xf80007b4 0x380 +0xf80007b8 0x1200 +0xf80007bc 0x1200 +0xf80007c0 0x1240 +0xf80007c4 0x1240 +0xf80007c8 0x1240 +0xf80007cc 0x1240 +0xf80007d0 0x1200 +0xf80007d4 0x1200 +0xf8000830 0x380037 +0xf8000834 0x3a0039 +0xF800014C 0x00000621 // LQSPI_CLK_CTRL - ARMPLL/6 (200 MHz) +0xE000D000 0x800238C1 // QSPI config - divide-by-2 +0xE000D038 0x00000020 // QSPI loopback - internal, 0 delay +0xE000D0A0 0xE2FF06EB // LQSPI_CFG - Quad read, dual flash diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig new file mode 100644 index 0000000..8959fa6 --- /dev/null +++ b/configs/topic_miamilite_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="topic" +CONFIG_SYS_CONFIG_NAME="topic_miamilite" +CONFIG_ARCH_ZYNQ=y +CONFIG_SYS_TEXT_BASE=0x4000000 +CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt" +CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamilite" +CONFIG_BOOTDELAY=0 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="zynq-uboot> " +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DFU_RAM=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xe0000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Xilinx" +CONFIG_G_DNL_VENDOR_NUM=0x03fd +CONFIG_G_DNL_PRODUCT_NUM=0x0300 diff --git a/include/configs/topic_miamilite.h b/include/configs/topic_miamilite.h new file mode 100644 index 0000000..46ca6bd --- /dev/null +++ b/include/configs/topic_miamilite.h @@ -0,0 +1,2 @@ +#include "topic_miami.h" +#define CONFIG_SF_DUAL_FLASH -- 1.9.1

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[U-Boot] [PATCH] sandbox: Fix comparison of unsigned enum expression warning
by Tom Rini 07 Jun '17

07 Jun '17

In os_dirent_get_typename() we are checking that type falls within the known values of the enum os_dirent_t. With clang-3.8 testing this value as being >= 0 results in a warning as it will always be true. This assumes of course that we are only given valid data. Given that we want to sanity check the input, we change this to check that it falls within the range of the first to the last entry in the given enum. Cc: Simon Glass <sjg(a)chromium.org> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- arch/sandbox/cpu/os.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 35ea00ce3ca0..7243bfc1b1fd 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -395,7 +395,7 @@ const char *os_dirent_typename[OS_FILET_COUNT] = { const char *os_dirent_get_typename(enum os_dirent_t type) { - if (type >= 0 && type < OS_FILET_COUNT) + if (type >= OS_FILET_REG && type < OS_FILET_COUNT) return os_dirent_typename[type]; return os_dirent_typename[OS_FILET_UNKNOWN]; -- 1.9.1

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[U-Boot] [PATCH] buildman: Fix bloat option when 'new' only drops functions
by Tom Rini 07 Jun '17

07 Jun '17

In the case where a new build only decreases sizes and does not increase any size we still want to report what functions have been dropped when doing a bloat comparison. Cc: Simon Glass <sjg(a)chromium.org> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- This is important when doing Kconfig migrations and a given target has only decreased in size, we want to know what was dropped so we can see what needs to be re-enabled. --- tools/buildman/builder.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py index b0ea57ebb4a9..acb0810457e4 100644 --- a/tools/buildman/builder.py +++ b/tools/buildman/builder.py @@ -847,7 +847,7 @@ class Builder: delta.reverse() args = [add, -remove, grow, -shrink, up, -down, up - down] - if max(args) == 0: + if max(args) == 0 and min(args) == 0: return args = [self.ColourNum(x) for x in args] indent = ' ' * 15 -- 1.9.1

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