April 2017 - U-Boot

[U-Boot] [PATCH 3/7] omap3630: Copy Device tree from Linux 4.9.y stable
by Adam Ford 12 Apr '17

12 Apr '17

Add device tree support to allow for CONFIG_OF_CONTROL in OMAP3630 boards. DM3730 can use this same device tree. Signed-off-by: Adam Ford <aford173(a)gmail.com> Reviewed-by: Lokesh Vutla <lokeshvutla(a)ti.com> diff --git a/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi new file mode 100644 index 0000000..db47f12 --- /dev/null +++ b/arch/arm/dts/omap34xx-omap36xx-clocks.dtsi @@ -0,0 +1,268 @@ +/* + * Device Tree Source for OMAP34XX/OMAP36XX clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&cm_clocks { + security_l4_ick2: security_l4_ick2 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + aes1_ick: aes1_ick@a14 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&security_l4_ick2>; + ti,bit-shift = <3>; + reg = <0x0a14>; + }; + + rng_ick: rng_ick@a14 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&security_l4_ick2>; + reg = <0x0a14>; + ti,bit-shift = <2>; + }; + + sha11_ick: sha11_ick@a14 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&security_l4_ick2>; + reg = <0x0a14>; + ti,bit-shift = <1>; + }; + + des1_ick: des1_ick@a14 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&security_l4_ick2>; + reg = <0x0a14>; + ti,bit-shift = <0>; + }; + + cam_mclk: cam_mclk@f00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll4_m5x2_ck>; + ti,bit-shift = <0>; + reg = <0x0f00>; + ti,set-rate-parent; + }; + + cam_ick: cam_ick@f10 { + #clock-cells = <0>; + compatible = "ti,omap3-no-wait-interface-clock"; + clocks = <&l4_ick>; + reg = <0x0f10>; + ti,bit-shift = <0>; + }; + + csi2_96m_fck: csi2_96m_fck@f00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&core_96m_fck>; + reg = <0x0f00>; + ti,bit-shift = <1>; + }; + + security_l3_ick: security_l3_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l3_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + pka_ick: pka_ick@a14 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&security_l3_ick>; + reg = <0x0a14>; + ti,bit-shift = <4>; + }; + + icr_ick: icr_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <29>; + }; + + des2_ick: des2_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <26>; + }; + + mspro_ick: mspro_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <23>; + }; + + mailboxes_ick: mailboxes_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <7>; + }; + + ssi_l4_ick: ssi_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + sr1_fck: sr1_fck@c00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&sys_ck>; + reg = <0x0c00>; + ti,bit-shift = <6>; + }; + + sr2_fck: sr2_fck@c00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&sys_ck>; + reg = <0x0c00>; + ti,bit-shift = <7>; + }; + + sr_l4_ick: sr_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll2_fck: dpll2_fck@40 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&core_ck>; + ti,bit-shift = <19>; + ti,max-div = <7>; + reg = <0x0040>; + ti,index-starts-at-one; + }; + + dpll2_ck: dpll2_ck@4 { + #clock-cells = <0>; + compatible = "ti,omap3-dpll-clock"; + clocks = <&sys_ck>, <&dpll2_fck>; + reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>; + ti,low-power-stop; + ti,lock; + ti,low-power-bypass; + }; + + dpll2_m2_ck: dpll2_m2_ck@44 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll2_ck>; + ti,max-div = <31>; + reg = <0x0044>; + ti,index-starts-at-one; + }; + + iva2_ck: iva2_ck@0 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&dpll2_m2_ck>; + reg = <0x0000>; + ti,bit-shift = <0>; + }; + + modem_fck: modem_fck@a00 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&sys_ck>; + reg = <0x0a00>; + ti,bit-shift = <31>; + }; + + sad2d_ick: sad2d_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l3_ick>; + reg = <0x0a10>; + ti,bit-shift = <3>; + }; + + mad2d_ick: mad2d_ick@a18 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&l3_ick>; + reg = <0x0a18>; + ti,bit-shift = <3>; + }; + + mspro_fck: mspro_fck@a00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_96m_fck>; + reg = <0x0a00>; + ti,bit-shift = <23>; + }; +}; + +&cm_clockdomains { + cam_clkdm: cam_clkdm { + compatible = "ti,clockdomain"; + clocks = <&cam_ick>, <&csi2_96m_fck>; + }; + + iva2_clkdm: iva2_clkdm { + compatible = "ti,clockdomain"; + clocks = <&iva2_ck>; + }; + + dpll2_clkdm: dpll2_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll2_ck>; + }; + + wkup_clkdm: wkup_clkdm { + compatible = "ti,clockdomain"; + clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, + <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, + <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>; + }; + + d2d_clkdm: d2d_clkdm { + compatible = "ti,clockdomain"; + clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, + <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, + <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, + <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, + <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, + <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, + <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, + <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, + <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>, + <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>, + <&mspro_fck>; + }; +}; diff --git a/arch/arm/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi new file mode 100644 index 0000000..572cb53 --- /dev/null +++ b/arch/arm/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi @@ -0,0 +1,242 @@ +/* + * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&prm_clocks { + corex2_d3_fck: corex2_d3_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&corex2_fck>; + clock-mult = <1>; + clock-div = <3>; + }; + + corex2_d5_fck: corex2_d5_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&corex2_fck>; + clock-mult = <1>; + clock-div = <5>; + }; +}; +&cm_clocks { + dpll5_ck: dpll5_ck@d04 { + #clock-cells = <0>; + compatible = "ti,omap3-dpll-clock"; + clocks = <&sys_ck>, <&sys_ck>; + reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>; + ti,low-power-stop; + ti,lock; + }; + + dpll5_m2_ck: dpll5_m2_ck@d50 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll5_ck>; + ti,max-div = <31>; + reg = <0x0d50>; + ti,index-starts-at-one; + }; + + sgx_gate_fck: sgx_gate_fck@b00 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <1>; + reg = <0x0b00>; + }; + + core_d3_ck: core_d3_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <3>; + }; + + core_d4_ck: core_d4_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + core_d6_ck: core_d6_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <6>; + }; + + omap_192m_alwon_fck: omap_192m_alwon_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m2x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + core_d2_ck: core_d2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + sgx_mux_fck: sgx_mux_fck@b40 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>; + reg = <0x0b40>; + }; + + sgx_fck: sgx_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&sgx_gate_fck>, <&sgx_mux_fck>; + }; + + sgx_ick: sgx_ick@b10 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&l3_ick>; + reg = <0x0b10>; + ti,bit-shift = <0>; + }; + + cpefuse_fck: cpefuse_fck@a08 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_ck>; + reg = <0x0a08>; + ti,bit-shift = <0>; + }; + + ts_fck: ts_fck@a08 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&omap_32k_fck>; + reg = <0x0a08>; + ti,bit-shift = <1>; + }; + + usbtll_fck: usbtll_fck@a08 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&dpll5_m2_ck>; + reg = <0x0a08>; + ti,bit-shift = <2>; + }; + + usbtll_ick: usbtll_ick@a18 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a18>; + ti,bit-shift = <2>; + }; + + mmchs3_ick: mmchs3_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <30>; + }; + + mmchs3_fck: mmchs3_fck@a00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_96m_fck>; + reg = <0x0a00>; + ti,bit-shift = <30>; + }; + + dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 { + #clock-cells = <0>; + compatible = "ti,dss-gate-clock"; + clocks = <&dpll4_m4x2_ck>; + ti,bit-shift = <0>; + reg = <0x0e00>; + ti,set-rate-parent; + }; + + dss_ick: dss_ick_3430es2@e10 { + #clock-cells = <0>; + compatible = "ti,omap3-dss-interface-clock"; + clocks = <&l4_ick>; + reg = <0x0e10>; + ti,bit-shift = <0>; + }; + + usbhost_120m_fck: usbhost_120m_fck@1400 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll5_m2_ck>; + reg = <0x1400>; + ti,bit-shift = <1>; + }; + + usbhost_48m_fck: usbhost_48m_fck@1400 { + #clock-cells = <0>; + compatible = "ti,dss-gate-clock"; + clocks = <&omap_48m_fck>; + reg = <0x1400>; + ti,bit-shift = <0>; + }; + + usbhost_ick: usbhost_ick@1410 { + #clock-cells = <0>; + compatible = "ti,omap3-dss-interface-clock"; + clocks = <&l4_ick>; + reg = <0x1410>; + ti,bit-shift = <0>; + }; +}; + +&cm_clockdomains { + dpll5_clkdm: dpll5_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll5_ck>; + }; + + sgx_clkdm: sgx_clkdm { + compatible = "ti,clockdomain"; + clocks = <&sgx_ick>; + }; + + dss_clkdm: dss_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, + <&dss1_alwon_fck>, <&dss_ick>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, + <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, + <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, + <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, + <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, + <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, + <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, + <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, + <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, + <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, + <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>; + }; + + usbhost_clkdm: usbhost_clkdm { + compatible = "ti,clockdomain"; + clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>, + <&usbhost_ick>; + }; +}; diff --git a/arch/arm/dts/omap36xx-clocks.dtsi b/arch/arm/dts/omap36xx-clocks.dtsi new file mode 100644 index 0000000..9c7ed03 --- /dev/null +++ b/arch/arm/dts/omap36xx-clocks.dtsi @@ -0,0 +1,110 @@ +/* + * Device Tree Source for OMAP36xx clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&cm_clocks { + dpll4_ck: dpll4_ck@d00 { + #clock-cells = <0>; + compatible = "ti,omap3-dpll-per-j-type-clock"; + clocks = <&sys_ck>, <&sys_ck>; + reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; + }; + + dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,hsdiv-gate-clock"; + clocks = <&dpll4_m5x2_mul_ck>; + ti,bit-shift = <0x1e>; + reg = <0x0d00>; + ti,set-rate-parent; + ti,set-bit-to-disable; + }; + + dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,hsdiv-gate-clock"; + clocks = <&dpll4_m2x2_mul_ck>; + ti,bit-shift = <0x1b>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,hsdiv-gate-clock"; + clocks = <&dpll3_m3x2_mul_ck>; + ti,bit-shift = <0xc>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,hsdiv-gate-clock"; + clocks = <&dpll4_m3x2_mul_ck>; + ti,bit-shift = <0x1c>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,hsdiv-gate-clock"; + clocks = <&dpll4_m6x2_mul_ck>; + ti,bit-shift = <0x1f>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + uart4_fck: uart4_fck@1000 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&per_48m_fck>; + reg = <0x1000>; + ti,bit-shift = <18>; + }; +}; + +&dpll4_m2x2_mul_ck { + clock-mult = <1>; +}; + +&dpll4_m3x2_mul_ck { + clock-mult = <1>; +}; + +&dpll4_m4x2_mul_ck { + ti,clock-mult = <1>; +}; + +&dpll4_m5x2_mul_ck { + ti,clock-mult = <1>; +}; + +&dpll4_m6x2_mul_ck { + clock-mult = <1>; +}; + +&cm_clockdomains { + dpll4_clkdm: dpll4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll4_ck>; + }; + + per_clkdm: per_clkdm { + compatible = "ti,clockdomain"; + clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, + <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, + <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, + <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, + <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, + <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, + <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, + <&mcbsp4_ick>, <&uart4_fck>; + }; +}; diff --git a/arch/arm/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/dts/omap36xx-omap3430es2plus-clocks.dtsi new file mode 100644 index 0000000..a9eec1b --- /dev/null +++ b/arch/arm/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -0,0 +1,198 @@ +/* + * Device Tree Source for OMAP34xx/OMAP36xx clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&cm_clocks { + ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&corex2_fck>; + ti,bit-shift = <0>; + reg = <0x0a00>; + }; + + ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 { + #clock-cells = <0>; + compatible = "ti,composite-divider-clock"; + clocks = <&corex2_fck>; + ti,bit-shift = <8>; + reg = <0x0a40>; + ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; + }; + + ssi_ssr_fck: ssi_ssr_fck_3430es2 { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>; + }; + + ssi_sst_fck: ssi_sst_fck_3430es2 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&ssi_ssr_fck>; + clock-mult = <1>; + clock-div = <2>; + }; + + hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-hsotgusb-interface-clock"; + clocks = <&core_l3_ick>; + reg = <0x0a10>; + ti,bit-shift = <4>; + }; + + ssi_l4_ick: ssi_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + ssi_ick: ssi_ick_3430es2@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-ssi-interface-clock"; + clocks = <&ssi_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <0>; + }; + + usim_gate_fck: usim_gate_fck@c00 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&omap_96m_fck>; + ti,bit-shift = <9>; + reg = <0x0c00>; + }; + + sys_d2_ck: sys_d2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_ck>; + clock-mult = <1>; + clock-div = <2>; + }; + + omap_96m_d2_fck: omap_96m_d2_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_fck>; + clock-mult = <1>; + clock-div = <2>; + }; + + omap_96m_d4_fck: omap_96m_d4_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_fck>; + clock-mult = <1>; + clock-div = <4>; + }; + + omap_96m_d8_fck: omap_96m_d8_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_fck>; + clock-mult = <1>; + clock-div = <8>; + }; + + omap_96m_d10_fck: omap_96m_d10_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_fck>; + clock-mult = <1>; + clock-div = <10>; + }; + + dpll5_m2_d4_ck: dpll5_m2_d4_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll5_m2_ck>; + clock-mult = <1>; + clock-div = <4>; + }; + + dpll5_m2_d8_ck: dpll5_m2_d8_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll5_m2_ck>; + clock-mult = <1>; + clock-div = <8>; + }; + + dpll5_m2_d16_ck: dpll5_m2_d16_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll5_m2_ck>; + clock-mult = <1>; + clock-div = <16>; + }; + + dpll5_m2_d20_ck: dpll5_m2_d20_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll5_m2_ck>; + clock-mult = <1>; + clock-div = <20>; + }; + + usim_mux_fck: usim_mux_fck@c40 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; + ti,bit-shift = <3>; + reg = <0x0c40>; + ti,index-starts-at-one; + }; + + usim_fck: usim_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&usim_gate_fck>, <&usim_mux_fck>; + }; + + usim_ick: usim_ick@c10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&wkup_l4_ick>; + reg = <0x0c10>; + ti,bit-shift = <9>; + }; +}; + +&cm_clockdomains { + core_l3_clkdm: core_l3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>; + }; + + wkup_clkdm: wkup_clkdm { + compatible = "ti,clockdomain"; + clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, + <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, + <&gpt1_ick>, <&usim_ick>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, + <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>, + <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, + <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, + <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, + <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, + <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, + <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, + <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, + <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, + <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, + <&ssi_ick>; + }; +}; diff --git a/arch/arm/dts/omap36xx.dtsi b/arch/arm/dts/omap36xx.dtsi new file mode 100644 index 0000000..fc22f0d --- /dev/null +++ b/arch/arm/dts/omap36xx.dtsi @@ -0,0 +1,118 @@ +/* + * Device Tree Source for OMAP3 SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/media/omap3-isp.h> + +#include "omap3.dtsi" + +/ { + aliases { + serial3 = &uart4; + }; + + cpus { + /* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */ + cpu@0 { + operating-points = < + /* kHz uV */ + 300000 1012500 + 600000 1200000 + 800000 1325000 + >; + clock-latency = <300000>; /* From legacy driver */ + }; + }; + + ocp@68000000 { + uart4: serial@49042000 { + compatible = "ti,omap3-uart"; + reg = <0x49042000 0x400>; + interrupts = <80>; + dmas = <&sdma 81 &sdma 82>; + dma-names = "tx", "rx"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; + + abb_mpu_iva: regulator-abb-mpu { + compatible = "ti,abb-v1"; + regulator-name = "abb_mpu_iva"; + #address-cells = <0>; + #size-cells = <0>; + reg = <0x483072f0 0x8>, <0x48306818 0x4>; + reg-names = "base-address", "int-address"; + ti,tranxdone-status-mask = <0x4000000>; + clocks = <&sys_ck>; + ti,settling-time = <30>; + ti,clock-cycles = <8>; + ti,abb_info = < + /*uV ABB efuse rbb_m fbb_m vset_m*/ + 1012500 0 0 0 0 0 + 1200000 0 0 0 0 0 + 1325000 0 0 0 0 0 + 1375000 1 0 0 0 0 + >; + }; + + omap3_pmx_core2: pinmux@480025a0 { + compatible = "ti,omap3-padconf", "pinctrl-single"; + reg = <0x480025a0 0x5c>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + + isp: isp@480bc000 { + compatible = "ti,omap3-isp"; + reg = <0x480bc000 0x12fc + 0x480bd800 0x0600>; + interrupts = <24>; + iommus = <&mmu_isp>; + syscon = <&scm_conf 0x2f0>; + ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>; + #clock-cells = <1>; + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + bandgap@48002524 { + reg = <0x48002524 0x4>; + compatible = "ti,omap36xx-bandgap"; + #thermal-sensor-cells = <0>; + }; + }; +}; + +/* OMAP3630 needs dss_96m_fck for VENC */ +&venc { + clocks = <&dss_tv_fck>, <&dss_96m_fck>; + clock-names = "fck", "tv_dac_clk"; +}; + +&ssi { + status = "ok"; + + clocks = <&ssi_ssr_fck>, + <&ssi_sst_fck>, + <&ssi_ick>; + clock-names = "ssi_ssr_fck", + "ssi_sst_fck", + "ssi_ick"; +}; + +/include/ "omap34xx-omap36xx-clocks.dtsi" +/include/ "omap36xx-omap3430es2plus-clocks.dtsi" +/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" +/include/ "omap36xx-clocks.dtsi" diff --git a/include/dt-bindings/media/omap3-isp.h b/include/dt-bindings/media/omap3-isp.h new file mode 100644 index 0000000..4e42084 --- /dev/null +++ b/include/dt-bindings/media/omap3-isp.h @@ -0,0 +1,22 @@ +/* + * include/dt-bindings/media/omap3-isp.h + * + * Copyright (C) 2015 Sakari Ailus + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#ifndef __DT_BINDINGS_OMAP3_ISP_H__ +#define __DT_BINDINGS_OMAP3_ISP_H__ + +#define OMAP3ISP_PHY_TYPE_COMPLEX_IO 0 +#define OMAP3ISP_PHY_TYPE_CSIPHY 1 + +#endif /* __DT_BINDINGS_OMAP3_ISP_H__ */ -- 2.7.4

2 1

[U-Boot] [PATCH 2/7] omap3: Copy Device tree from Linux 4.9.y stable
by Adam Ford 12 Apr '17

12 Apr '17

Add device tree support to allow for CONFIG_OF_CONTROL in OMAP3 boards. Signed-off-by: Adam Ford <aford173(a)gmail.com> Reviewed-by: Lokesh Vutla <lokeshvutla(a)ti.com> diff --git a/arch/arm/dts/omap3.dtsi b/arch/arm/dts/omap3.dtsi new file mode 100644 index 0000000..a0f2412 --- /dev/null +++ b/arch/arm/dts/omap3.dtsi @@ -0,0 +1,854 @@ +/* + * Device Tree Source for OMAP3 SoC + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/omap.h> + +/ { + compatible = "ti,omap3430", "ti,omap3"; + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a8"; + device_type = "cpu"; + reg = <0x0>; + + clocks = <&dpll1_ck>; + clock-names = "cpu"; + + clock-latency = <300000>; /* From omap-cpufreq driver */ + }; + }; + + pmu@54000000 { + compatible = "arm,cortex-a8-pmu"; + reg = <0x54000000 0x800000>; + interrupts = <3>; + ti,hwmods = "debugss"; + }; + + /* + * The soc node represents the soc top level view. It is used for IPs + * that are not memory mapped in the MPU view or for the MPU itself. + */ + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap3-mpu"; + ti,hwmods = "mpu"; + }; + + iva: iva { + compatible = "ti,iva2.2"; + ti,hwmods = "iva"; + + dsp { + compatible = "ti,omap3-c64"; + }; + }; + }; + + /* + * XXX: Use a flat representation of the OMAP3 interconnect. + * The real OMAP interconnect network is quite complex. + * Since it will not bring real advantage to represent that in DT for + * the moment, just use a fake OCP bus entry to represent the whole bus + * hierarchy. + */ + ocp@68000000 { + compatible = "ti,omap3-l3-smx", "simple-bus"; + reg = <0x68000000 0x10000>; + interrupts = <9 10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main"; + + l4_core: l4@48000000 { + compatible = "ti,omap3-l4-core", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48000000 0x1000000>; + + scm: scm@2000 { + compatible = "ti,omap3-scm", "simple-bus"; + reg = <0x2000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2000 0x2000>; + + omap3_pmx_core: pinmux@30 { + compatible = "ti,omap3-padconf", + "pinctrl-single"; + reg = <0x30 0x238>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + + scm_conf: scm_conf@270 { + compatible = "syscon", "simple-bus"; + reg = <0x270 0x330>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x270 0x330>; + + pbias_regulator: pbias_regulator@2b0 { + compatible = "ti,pbias-omap3", "ti,pbias-omap"; + reg = <0x2b0 0x4>; + syscon = <&scm_conf>; + pbias_mmc_reg: pbias_mmc_omap2430 { + regulator-name = "pbias_mmc_omap2430"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + scm_clockdomains: clockdomains { + }; + + omap3_pmx_wkup: pinmux@a00 { + compatible = "ti,omap3-padconf", + "pinctrl-single"; + reg = <0xa00 0x5c>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + }; + }; + + aes: aes@480c5000 { + compatible = "ti,omap3-aes"; + ti,hwmods = "aes"; + reg = <0x480c5000 0x50>; + interrupts = <0>; + dmas = <&sdma 65 &sdma 66>; + dma-names = "tx", "rx"; + }; + + prm: prm@48306000 { + compatible = "ti,omap3-prm"; + reg = <0x48306000 0x4000>; + interrupts = <11>; + + prm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + prm_clockdomains: clockdomains { + }; + }; + + cm: cm@48004000 { + compatible = "ti,omap3-cm"; + reg = <0x48004000 0x4000>; + + cm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + cm_clockdomains: clockdomains { + }; + }; + + counter32k: counter@48320000 { + compatible = "ti,omap-counter32k"; + reg = <0x48320000 0x20>; + ti,hwmods = "counter_32k"; + }; + + intc: interrupt-controller@48200000 { + compatible = "ti,omap3-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x48200000 0x1000>; + }; + + sdma: dma-controller@48056000 { + compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; + reg = <0x48056000 0x1000>; + interrupts = <12>, + <13>, + <14>, + <15>; + #dma-cells = <1>; + dma-channels = <32>; + dma-requests = <96>; + }; + + gpio1: gpio@48310000 { + compatible = "ti,omap3-gpio"; + reg = <0x48310000 0x200>; + interrupts = <29>; + ti,hwmods = "gpio1"; + ti,gpio-always-on; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@49050000 { + compatible = "ti,omap3-gpio"; + reg = <0x49050000 0x200>; + interrupts = <30>; + ti,hwmods = "gpio2"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@49052000 { + compatible = "ti,omap3-gpio"; + reg = <0x49052000 0x200>; + interrupts = <31>; + ti,hwmods = "gpio3"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@49054000 { + compatible = "ti,omap3-gpio"; + reg = <0x49054000 0x200>; + interrupts = <32>; + ti,hwmods = "gpio4"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@49056000 { + compatible = "ti,omap3-gpio"; + reg = <0x49056000 0x200>; + interrupts = <33>; + ti,hwmods = "gpio5"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@49058000 { + compatible = "ti,omap3-gpio"; + reg = <0x49058000 0x200>; + interrupts = <34>; + ti,hwmods = "gpio6"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart1: serial@4806a000 { + compatible = "ti,omap3-uart"; + reg = <0x4806a000 0x2000>; + reg-shift = <2>; + interrupts-extended = <&intc 72>; + dmas = <&sdma 49 &sdma 50>; + dma-names = "tx", "rx"; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + }; + + uart2: serial@4806c000 { + compatible = "ti,omap3-uart"; + reg = <0x4806c000 0x400>; + interrupts-extended = <&intc 73>; + dmas = <&sdma 51 &sdma 52>; + dma-names = "tx", "rx"; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + }; + + uart3: serial@49020000 { + compatible = "ti,omap3-uart"; + reg = <0x49020000 0x400>; + interrupts-extended = <&intc 74>; + dmas = <&sdma 53 &sdma 54>; + dma-names = "tx", "rx"; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + }; + + i2c1: i2c@48070000 { + compatible = "ti,omap3-i2c"; + reg = <0x48070000 0x80>; + interrupts = <56>; + dmas = <&sdma 27 &sdma 28>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c1"; + }; + + i2c2: i2c@48072000 { + compatible = "ti,omap3-i2c"; + reg = <0x48072000 0x80>; + interrupts = <57>; + dmas = <&sdma 29 &sdma 30>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c2"; + }; + + i2c3: i2c@48060000 { + compatible = "ti,omap3-i2c"; + reg = <0x48060000 0x80>; + interrupts = <61>; + dmas = <&sdma 25 &sdma 26>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c3"; + }; + + mailbox: mailbox@48094000 { + compatible = "ti,omap3-mailbox"; + ti,hwmods = "mailbox"; + reg = <0x48094000 0x200>; + interrupts = <26>; + #mbox-cells = <1>; + ti,mbox-num-users = <2>; + ti,mbox-num-fifos = <2>; + mbox_dsp: dsp { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; + }; + + mcspi1: spi@48098000 { + compatible = "ti,omap2-mcspi"; + reg = <0x48098000 0x100>; + interrupts = <65>; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "mcspi1"; + ti,spi-num-cs = <4>; + dmas = <&sdma 35>, + <&sdma 36>, + <&sdma 37>, + <&sdma 38>, + <&sdma 39>, + <&sdma 40>, + <&sdma 41>, + <&sdma 42>; + dma-names = "tx0", "rx0", "tx1", "rx1", + "tx2", "rx2", "tx3", "rx3"; + }; + + mcspi2: spi@4809a000 { + compatible = "ti,omap2-mcspi"; + reg = <0x4809a000 0x100>; + interrupts = <66>; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "mcspi2"; + ti,spi-num-cs = <2>; + dmas = <&sdma 43>, + <&sdma 44>, + <&sdma 45>, + <&sdma 46>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + }; + + mcspi3: spi@480b8000 { + compatible = "ti,omap2-mcspi"; + reg = <0x480b8000 0x100>; + interrupts = <91>; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "mcspi3"; + ti,spi-num-cs = <2>; + dmas = <&sdma 15>, + <&sdma 16>, + <&sdma 23>, + <&sdma 24>; + dma-names = "tx0", "rx0", "tx1", "rx1"; + }; + + mcspi4: spi@480ba000 { + compatible = "ti,omap2-mcspi"; + reg = <0x480ba000 0x100>; + interrupts = <48>; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "mcspi4"; + ti,spi-num-cs = <1>; + dmas = <&sdma 70>, <&sdma 71>; + dma-names = "tx0", "rx0"; + }; + + hdqw1w: 1w@480b2000 { + compatible = "ti,omap3-1w"; + reg = <0x480b2000 0x1000>; + interrupts = <58>; + ti,hwmods = "hdq1w"; + }; + + mmc1: mmc@4809c000 { + compatible = "ti,omap3-hsmmc"; + reg = <0x4809c000 0x200>; + interrupts = <83>; + ti,hwmods = "mmc1"; + ti,dual-volt; + dmas = <&sdma 61>, <&sdma 62>; + dma-names = "tx", "rx"; + pbias-supply = <&pbias_mmc_reg>; + }; + + mmc2: mmc@480b4000 { + compatible = "ti,omap3-hsmmc"; + reg = <0x480b4000 0x200>; + interrupts = <86>; + ti,hwmods = "mmc2"; + dmas = <&sdma 47>, <&sdma 48>; + dma-names = "tx", "rx"; + }; + + mmc3: mmc@480ad000 { + compatible = "ti,omap3-hsmmc"; + reg = <0x480ad000 0x200>; + interrupts = <94>; + ti,hwmods = "mmc3"; + dmas = <&sdma 77>, <&sdma 78>; + dma-names = "tx", "rx"; + }; + + mmu_isp: mmu@480bd400 { + #iommu-cells = <0>; + compatible = "ti,omap2-iommu"; + reg = <0x480bd400 0x80>; + interrupts = <24>; + ti,hwmods = "mmu_isp"; + ti,#tlb-entries = <8>; + }; + + mmu_iva: mmu@5d000000 { + #iommu-cells = <0>; + compatible = "ti,omap2-iommu"; + reg = <0x5d000000 0x80>; + interrupts = <28>; + ti,hwmods = "mmu_iva"; + status = "disabled"; + }; + + wdt2: wdt@48314000 { + compatible = "ti,omap3-wdt"; + reg = <0x48314000 0x80>; + ti,hwmods = "wd_timer2"; + }; + + mcbsp1: mcbsp@48074000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x48074000 0xff>; + reg-names = "mpu"; + interrupts = <16>, /* OCP compliant interrupt */ + <59>, /* TX interrupt */ + <60>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp1"; + dmas = <&sdma 31>, + <&sdma 32>; + dma-names = "tx", "rx"; + clocks = <&mcbsp1_fck>; + clock-names = "fck"; + status = "disabled"; + }; + + mcbsp2: mcbsp@49022000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x49022000 0xff>, + <0x49028000 0xff>; + reg-names = "mpu", "sidetone"; + interrupts = <17>, /* OCP compliant interrupt */ + <62>, /* TX interrupt */ + <63>, /* RX interrupt */ + <4>; /* Sidetone */ + interrupt-names = "common", "tx", "rx", "sidetone"; + ti,buffer-size = <1280>; + ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; + dmas = <&sdma 33>, + <&sdma 34>; + dma-names = "tx", "rx"; + clocks = <&mcbsp2_fck>, <&mcbsp2_ick>; + clock-names = "fck", "ick"; + status = "disabled"; + }; + + mcbsp3: mcbsp@49024000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x49024000 0xff>, + <0x4902a000 0xff>; + reg-names = "mpu", "sidetone"; + interrupts = <22>, /* OCP compliant interrupt */ + <89>, /* TX interrupt */ + <90>, /* RX interrupt */ + <5>; /* Sidetone */ + interrupt-names = "common", "tx", "rx", "sidetone"; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; + dmas = <&sdma 17>, + <&sdma 18>; + dma-names = "tx", "rx"; + clocks = <&mcbsp3_fck>, <&mcbsp3_ick>; + clock-names = "fck", "ick"; + status = "disabled"; + }; + + mcbsp4: mcbsp@49026000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x49026000 0xff>; + reg-names = "mpu"; + interrupts = <23>, /* OCP compliant interrupt */ + <54>, /* TX interrupt */ + <55>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp4"; + dmas = <&sdma 19>, + <&sdma 20>; + dma-names = "tx", "rx"; + clocks = <&mcbsp4_fck>; + clock-names = "fck"; + status = "disabled"; + }; + + mcbsp5: mcbsp@48096000 { + compatible = "ti,omap3-mcbsp"; + reg = <0x48096000 0xff>; + reg-names = "mpu"; + interrupts = <27>, /* OCP compliant interrupt */ + <81>, /* TX interrupt */ + <82>; /* RX interrupt */ + interrupt-names = "common", "tx", "rx"; + ti,buffer-size = <128>; + ti,hwmods = "mcbsp5"; + dmas = <&sdma 21>, + <&sdma 22>; + dma-names = "tx", "rx"; + clocks = <&mcbsp5_fck>; + clock-names = "fck"; + status = "disabled"; + }; + + sham: sham@480c3000 { + compatible = "ti,omap3-sham"; + ti,hwmods = "sham"; + reg = <0x480c3000 0x64>; + interrupts = <49>; + dmas = <&sdma 69>; + dma-names = "rx"; + }; + + smartreflex_core: smartreflex@480cb000 { + compatible = "ti,omap3-smartreflex-core"; + ti,hwmods = "smartreflex_core"; + reg = <0x480cb000 0x400>; + interrupts = <19>; + }; + + smartreflex_mpu_iva: smartreflex@480c9000 { + compatible = "ti,omap3-smartreflex-iva"; + ti,hwmods = "smartreflex_mpu_iva"; + reg = <0x480c9000 0x400>; + interrupts = <18>; + }; + + timer1: timer@48318000 { + compatible = "ti,omap3430-timer"; + reg = <0x48318000 0x400>; + interrupts = <37>; + ti,hwmods = "timer1"; + ti,timer-alwon; + }; + + timer2: timer@49032000 { + compatible = "ti,omap3430-timer"; + reg = <0x49032000 0x400>; + interrupts = <38>; + ti,hwmods = "timer2"; + }; + + timer3: timer@49034000 { + compatible = "ti,omap3430-timer"; + reg = <0x49034000 0x400>; + interrupts = <39>; + ti,hwmods = "timer3"; + }; + + timer4: timer@49036000 { + compatible = "ti,omap3430-timer"; + reg = <0x49036000 0x400>; + interrupts = <40>; + ti,hwmods = "timer4"; + }; + + timer5: timer@49038000 { + compatible = "ti,omap3430-timer"; + reg = <0x49038000 0x400>; + interrupts = <41>; + ti,hwmods = "timer5"; + ti,timer-dsp; + }; + + timer6: timer@4903a000 { + compatible = "ti,omap3430-timer"; + reg = <0x4903a000 0x400>; + interrupts = <42>; + ti,hwmods = "timer6"; + ti,timer-dsp; + }; + + timer7: timer@4903c000 { + compatible = "ti,omap3430-timer"; + reg = <0x4903c000 0x400>; + interrupts = <43>; + ti,hwmods = "timer7"; + ti,timer-dsp; + }; + + timer8: timer@4903e000 { + compatible = "ti,omap3430-timer"; + reg = <0x4903e000 0x400>; + interrupts = <44>; + ti,hwmods = "timer8"; + ti,timer-pwm; + ti,timer-dsp; + }; + + timer9: timer@49040000 { + compatible = "ti,omap3430-timer"; + reg = <0x49040000 0x400>; + interrupts = <45>; + ti,hwmods = "timer9"; + ti,timer-pwm; + }; + + timer10: timer@48086000 { + compatible = "ti,omap3430-timer"; + reg = <0x48086000 0x400>; + interrupts = <46>; + ti,hwmods = "timer10"; + ti,timer-pwm; + }; + + timer11: timer@48088000 { + compatible = "ti,omap3430-timer"; + reg = <0x48088000 0x400>; + interrupts = <47>; + ti,hwmods = "timer11"; + ti,timer-pwm; + }; + + timer12: timer@48304000 { + compatible = "ti,omap3430-timer"; + reg = <0x48304000 0x400>; + interrupts = <95>; + ti,hwmods = "timer12"; + ti,timer-alwon; + ti,timer-secure; + }; + + usbhstll: usbhstll@48062000 { + compatible = "ti,usbhs-tll"; + reg = <0x48062000 0x1000>; + interrupts = <78>; + ti,hwmods = "usb_tll_hs"; + }; + + usbhshost: usbhshost@48064000 { + compatible = "ti,usbhs-host"; + reg = <0x48064000 0x400>; + ti,hwmods = "usb_host_hs"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usbhsohci: ohci@48064400 { + compatible = "ti,ohci-omap3"; + reg = <0x48064400 0x400>; + interrupt-parent = <&intc>; + interrupts = <76>; + }; + + usbhsehci: ehci@48064800 { + compatible = "ti,ehci-omap"; + reg = <0x48064800 0x400>; + interrupt-parent = <&intc>; + interrupts = <77>; + }; + }; + + gpmc: gpmc@6e000000 { + compatible = "ti,omap3430-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x6e000000 0x02d0>; + interrupts = <20>; + dmas = <&sdma 4>; + dma-names = "rxtx"; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <4>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + usb_otg_hs: usb_otg_hs@480ab000 { + compatible = "ti,omap3-musb"; + reg = <0x480ab000 0x1000>; + interrupts = <92>, <93>; + interrupt-names = "mc", "dma"; + ti,hwmods = "usb_otg_hs"; + multipoint = <1>; + num-eps = <16>; + ram-bits = <12>; + }; + + dss: dss@48050000 { + compatible = "ti,omap3-dss"; + reg = <0x48050000 0x200>; + status = "disabled"; + ti,hwmods = "dss_core"; + clocks = <&dss1_alwon_fck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dispc@48050400 { + compatible = "ti,omap3-dispc"; + reg = <0x48050400 0x400>; + interrupts = <25>; + ti,hwmods = "dss_dispc"; + clocks = <&dss1_alwon_fck>; + clock-names = "fck"; + }; + + dsi: encoder@4804fc00 { + compatible = "ti,omap3-dsi"; + reg = <0x4804fc00 0x200>, + <0x4804fe00 0x40>, + <0x4804ff00 0x20>; + reg-names = "proto", "phy", "pll"; + interrupts = <25>; + status = "disabled"; + ti,hwmods = "dss_dsi1"; + clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; + clock-names = "fck", "sys_clk"; + }; + + rfbi: encoder@48050800 { + compatible = "ti,omap3-rfbi"; + reg = <0x48050800 0x100>; + status = "disabled"; + ti,hwmods = "dss_rfbi"; + clocks = <&dss1_alwon_fck>, <&dss_ick>; + clock-names = "fck", "ick"; + }; + + venc: encoder@48050c00 { + compatible = "ti,omap3-venc"; + reg = <0x48050c00 0x100>; + status = "disabled"; + ti,hwmods = "dss_venc"; + clocks = <&dss_tv_fck>; + clock-names = "fck"; + }; + }; + + ssi: ssi-controller@48058000 { + compatible = "ti,omap3-ssi"; + ti,hwmods = "ssi"; + + status = "disabled"; + + reg = <0x48058000 0x1000>, + <0x48059000 0x1000>; + reg-names = "sys", + "gdd"; + + interrupts = <71>; + interrupt-names = "gdd_mpu"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ssi_port1: ssi-port@4805a000 { + compatible = "ti,omap3-ssi-port"; + + reg = <0x4805a000 0x800>, + <0x4805a800 0x800>; + reg-names = "tx", + "rx"; + + interrupt-parent = <&intc>; + interrupts = <67>, + <68>; + }; + + ssi_port2: ssi-port@4805b000 { + compatible = "ti,omap3-ssi-port"; + + reg = <0x4805b000 0x800>, + <0x4805b800 0x800>; + reg-names = "tx", + "rx"; + + interrupt-parent = <&intc>; + interrupts = <69>, + <70>; + }; + }; + }; +}; + +/include/ "omap3xxx-clocks.dtsi" diff --git a/arch/arm/dts/omap3xxx-clocks.dtsi b/arch/arm/dts/omap3xxx-clocks.dtsi new file mode 100644 index 0000000..7455ab5 --- /dev/null +++ b/arch/arm/dts/omap3xxx-clocks.dtsi @@ -0,0 +1,1665 @@ +/* + * Device Tree Source for OMAP3 clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&prm_clocks { + virt_16_8m_ck: virt_16_8m_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16800000>; + }; + + osc_sys_ck: osc_sys_ck@d40 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>; + reg = <0x0d40>; + }; + + sys_ck: sys_ck@1270 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&osc_sys_ck>; + ti,bit-shift = <6>; + ti,max-div = <3>; + reg = <0x1270>; + ti,index-starts-at-one; + }; + + sys_clkout1: sys_clkout1@d70 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&osc_sys_ck>; + reg = <0x0d70>; + ti,bit-shift = <7>; + }; + + dpll3_x2_ck: dpll3_x2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll3_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll3_m2x2_ck: dpll3_m2x2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll3_m2_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll4_x2_ck: dpll4_x2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + corex2_fck: corex2_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll3_m2x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + wkup_l4_ick: wkup_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sys_ck>; + clock-mult = <1>; + clock-div = <1>; + }; +}; + +&scm_clocks { + mcbsp5_mux_fck: mcbsp5_mux_fck@68 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <4>; + reg = <0x68>; + }; + + mcbsp5_fck: mcbsp5_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; + }; + + mcbsp1_mux_fck: mcbsp1_mux_fck@4 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&core_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <2>; + reg = <0x04>; + }; + + mcbsp1_fck: mcbsp1_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; + }; + + mcbsp2_mux_fck: mcbsp2_mux_fck@4 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <6>; + reg = <0x04>; + }; + + mcbsp2_fck: mcbsp2_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; + }; + + mcbsp3_mux_fck: mcbsp3_mux_fck@68 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + reg = <0x68>; + }; + + mcbsp3_fck: mcbsp3_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; + }; + + mcbsp4_mux_fck: mcbsp4_mux_fck@68 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&per_96m_fck>, <&mcbsp_clks>; + ti,bit-shift = <2>; + reg = <0x68>; + }; + + mcbsp4_fck: mcbsp4_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; + }; +}; +&cm_clocks { + dummy_apb_pclk: dummy_apb_pclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0x0>; + }; + + omap_32k_fck: omap_32k_fck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + virt_12m_ck: virt_12m_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + + virt_13m_ck: virt_13m_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + + virt_19200000_ck: virt_19200000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <19200000>; + }; + + virt_26000000_ck: virt_26000000_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <26000000>; + }; + + virt_38_4m_ck: virt_38_4m_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <38400000>; + }; + + dpll4_ck: dpll4_ck@d00 { + #clock-cells = <0>; + compatible = "ti,omap3-dpll-per-clock"; + clocks = <&sys_ck>, <&sys_ck>; + reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; + }; + + dpll4_m2_ck: dpll4_m2_ck@d48 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll4_ck>; + ti,max-div = <63>; + reg = <0x0d48>; + ti,index-starts-at-one; + }; + + dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m2_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll4_m2x2_mul_ck>; + ti,bit-shift = <0x1b>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + omap_96m_alwon_fck: omap_96m_alwon_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m2x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll3_ck: dpll3_ck@d00 { + #clock-cells = <0>; + compatible = "ti,omap3-dpll-core-clock"; + clocks = <&sys_ck>, <&sys_ck>; + reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>; + }; + + dpll3_m3_ck: dpll3_m3_ck@1140 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll3_ck>; + ti,bit-shift = <16>; + ti,max-div = <31>; + reg = <0x1140>; + ti,index-starts-at-one; + }; + + dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll3_m3_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll3_m3x2_mul_ck>; + ti,bit-shift = <0xc>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + emu_core_alwon_ck: emu_core_alwon_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll3_m3x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + sys_altclk: sys_altclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0x0>; + }; + + mcbsp_clks: mcbsp_clks { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0x0>; + }; + + dpll3_m2_ck: dpll3_m2_ck@d40 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll3_ck>; + ti,bit-shift = <27>; + ti,max-div = <31>; + reg = <0x0d40>; + ti,index-starts-at-one; + }; + + core_ck: core_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll3_m2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + dpll1_fck: dpll1_fck@940 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&core_ck>; + ti,bit-shift = <19>; + ti,max-div = <7>; + reg = <0x0940>; + ti,index-starts-at-one; + }; + + dpll1_ck: dpll1_ck@904 { + #clock-cells = <0>; + compatible = "ti,omap3-dpll-clock"; + clocks = <&sys_ck>, <&dpll1_fck>; + reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>; + }; + + dpll1_x2_ck: dpll1_x2_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll1_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll1_x2m2_ck: dpll1_x2m2_ck@944 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll1_x2_ck>; + ti,max-div = <31>; + reg = <0x0944>; + ti,index-starts-at-one; + }; + + cm_96m_fck: cm_96m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_alwon_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + omap_96m_fck: omap_96m_fck@d40 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&cm_96m_fck>, <&sys_ck>; + ti,bit-shift = <6>; + reg = <0x0d40>; + }; + + dpll4_m3_ck: dpll4_m3_ck@e40 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll4_ck>; + ti,bit-shift = <8>; + ti,max-div = <32>; + reg = <0x0e40>; + ti,index-starts-at-one; + }; + + dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m3_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll4_m3x2_mul_ck>; + ti,bit-shift = <0x1c>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + omap_54m_fck: omap_54m_fck@d40 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; + ti,bit-shift = <5>; + reg = <0x0d40>; + }; + + cm_96m_d2_fck: cm_96m_d2_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&cm_96m_fck>; + clock-mult = <1>; + clock-div = <2>; + }; + + omap_48m_fck: omap_48m_fck@d40 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&cm_96m_d2_fck>, <&sys_altclk>; + ti,bit-shift = <3>; + reg = <0x0d40>; + }; + + omap_12m_fck: omap_12m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_48m_fck>; + clock-mult = <1>; + clock-div = <4>; + }; + + dpll4_m4_ck: dpll4_m4_ck@e40 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll4_ck>; + ti,max-div = <32>; + reg = <0x0e40>; + ti,index-starts-at-one; + }; + + dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clocks = <&dpll4_m4_ck>; + ti,clock-mult = <2>; + ti,clock-div = <1>; + ti,set-rate-parent; + }; + + dpll4_m4x2_ck: dpll4_m4x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll4_m4x2_mul_ck>; + ti,bit-shift = <0x1d>; + reg = <0x0d00>; + ti,set-bit-to-disable; + ti,set-rate-parent; + }; + + dpll4_m5_ck: dpll4_m5_ck@f40 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll4_ck>; + ti,max-div = <63>; + reg = <0x0f40>; + ti,index-starts-at-one; + }; + + dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck { + #clock-cells = <0>; + compatible = "ti,fixed-factor-clock"; + clocks = <&dpll4_m5_ck>; + ti,clock-mult = <2>; + ti,clock-div = <1>; + ti,set-rate-parent; + }; + + dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll4_m5x2_mul_ck>; + ti,bit-shift = <0x1e>; + reg = <0x0d00>; + ti,set-bit-to-disable; + ti,set-rate-parent; + }; + + dpll4_m6_ck: dpll4_m6_ck@1140 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&dpll4_ck>; + ti,bit-shift = <24>; + ti,max-div = <63>; + reg = <0x1140>; + ti,index-starts-at-one; + }; + + dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m6_ck>; + clock-mult = <2>; + clock-div = <1>; + }; + + dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll4_m6x2_mul_ck>; + ti,bit-shift = <0x1f>; + reg = <0x0d00>; + ti,set-bit-to-disable; + }; + + emu_per_alwon_ck: emu_per_alwon_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll4_m6x2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + clkout2_src_gate_ck: clkout2_src_gate_ck@d70 { + #clock-cells = <0>; + compatible = "ti,composite-no-wait-gate-clock"; + clocks = <&core_ck>; + ti,bit-shift = <7>; + reg = <0x0d70>; + }; + + clkout2_src_mux_ck: clkout2_src_mux_ck@d70 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; + reg = <0x0d70>; + }; + + clkout2_src_ck: clkout2_src_ck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>; + }; + + sys_clkout2: sys_clkout2@d70 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&clkout2_src_ck>; + ti,bit-shift = <3>; + ti,max-div = <64>; + reg = <0x0d70>; + ti,index-power-of-two; + }; + + mpu_ck: mpu_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll1_x2m2_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + arm_fck: arm_fck@924 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&mpu_ck>; + reg = <0x0924>; + ti,max-div = <2>; + }; + + emu_mpu_alwon_ck: emu_mpu_alwon_ck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&mpu_ck>; + clock-mult = <1>; + clock-div = <1>; + }; + + l3_ick: l3_ick@a40 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&core_ck>; + ti,max-div = <3>; + reg = <0x0a40>; + ti,index-starts-at-one; + }; + + l4_ick: l4_ick@a40 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&l3_ick>; + ti,bit-shift = <2>; + ti,max-div = <3>; + reg = <0x0a40>; + ti,index-starts-at-one; + }; + + rm_ick: rm_ick@c40 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&l4_ick>; + ti,bit-shift = <1>; + ti,max-div = <3>; + reg = <0x0c40>; + ti,index-starts-at-one; + }; + + gpt10_gate_fck: gpt10_gate_fck@a00 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <11>; + reg = <0x0a00>; + }; + + gpt10_mux_fck: gpt10_mux_fck@a40 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <6>; + reg = <0x0a40>; + }; + + gpt10_fck: gpt10_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; + }; + + gpt11_gate_fck: gpt11_gate_fck@a00 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <12>; + reg = <0x0a00>; + }; + + gpt11_mux_fck: gpt11_mux_fck@a40 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <7>; + reg = <0x0a40>; + }; + + gpt11_fck: gpt11_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>; + }; + + core_96m_fck: core_96m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + mmchs2_fck: mmchs2_fck@a00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_96m_fck>; + reg = <0x0a00>; + ti,bit-shift = <25>; + }; + + mmchs1_fck: mmchs1_fck@a00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_96m_fck>; + reg = <0x0a00>; + ti,bit-shift = <24>; + }; + + i2c3_fck: i2c3_fck@a00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_96m_fck>; + reg = <0x0a00>; + ti,bit-shift = <17>; + }; + + i2c2_fck: i2c2_fck@a00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_96m_fck>; + reg = <0x0a00>; + ti,bit-shift = <16>; + }; + + i2c1_fck: i2c1_fck@a00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_96m_fck>; + reg = <0x0a00>; + ti,bit-shift = <15>; + }; + + mcbsp5_gate_fck: mcbsp5_gate_fck@a00 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <10>; + reg = <0x0a00>; + }; + + mcbsp1_gate_fck: mcbsp1_gate_fck@a00 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <9>; + reg = <0x0a00>; + }; + + core_48m_fck: core_48m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_48m_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + mcspi4_fck: mcspi4_fck@a00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_48m_fck>; + reg = <0x0a00>; + ti,bit-shift = <21>; + }; + + mcspi3_fck: mcspi3_fck@a00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_48m_fck>; + reg = <0x0a00>; + ti,bit-shift = <20>; + }; + + mcspi2_fck: mcspi2_fck@a00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_48m_fck>; + reg = <0x0a00>; + ti,bit-shift = <19>; + }; + + mcspi1_fck: mcspi1_fck@a00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_48m_fck>; + reg = <0x0a00>; + ti,bit-shift = <18>; + }; + + uart2_fck: uart2_fck@a00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_48m_fck>; + reg = <0x0a00>; + ti,bit-shift = <14>; + }; + + uart1_fck: uart1_fck@a00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_48m_fck>; + reg = <0x0a00>; + ti,bit-shift = <13>; + }; + + core_12m_fck: core_12m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_12m_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + hdq_fck: hdq_fck@a00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_12m_fck>; + reg = <0x0a00>; + ti,bit-shift = <22>; + }; + + core_l3_ick: core_l3_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l3_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + sdrc_ick: sdrc_ick@a10 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_l3_ick>; + reg = <0x0a10>; + ti,bit-shift = <1>; + }; + + gpmc_fck: gpmc_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&core_l3_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + core_l4_ick: core_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + mmchs2_ick: mmchs2_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <25>; + }; + + mmchs1_ick: mmchs1_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <24>; + }; + + hdq_ick: hdq_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <22>; + }; + + mcspi4_ick: mcspi4_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <21>; + }; + + mcspi3_ick: mcspi3_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <20>; + }; + + mcspi2_ick: mcspi2_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <19>; + }; + + mcspi1_ick: mcspi1_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <18>; + }; + + i2c3_ick: i2c3_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <17>; + }; + + i2c2_ick: i2c2_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <16>; + }; + + i2c1_ick: i2c1_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <15>; + }; + + uart2_ick: uart2_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <14>; + }; + + uart1_ick: uart1_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <13>; + }; + + gpt11_ick: gpt11_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <12>; + }; + + gpt10_ick: gpt10_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <11>; + }; + + mcbsp5_ick: mcbsp5_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <10>; + }; + + mcbsp1_ick: mcbsp1_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <9>; + }; + + omapctrl_ick: omapctrl_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <6>; + }; + + dss_tv_fck: dss_tv_fck@e00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&omap_54m_fck>; + reg = <0x0e00>; + ti,bit-shift = <2>; + }; + + dss_96m_fck: dss_96m_fck@e00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&omap_96m_fck>; + reg = <0x0e00>; + ti,bit-shift = <2>; + }; + + dss2_alwon_fck: dss2_alwon_fck@e00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_ck>; + reg = <0x0e00>; + ti,bit-shift = <1>; + }; + + dummy_ck: dummy_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + gpt1_gate_fck: gpt1_gate_fck@c00 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <0>; + reg = <0x0c00>; + }; + + gpt1_mux_fck: gpt1_mux_fck@c40 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + reg = <0x0c40>; + }; + + gpt1_fck: gpt1_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; + }; + + aes2_ick: aes2_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + ti,bit-shift = <28>; + reg = <0x0a10>; + }; + + wkup_32k_fck: wkup_32k_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_32k_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + gpio1_dbck: gpio1_dbck@c00 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&wkup_32k_fck>; + reg = <0x0c00>; + ti,bit-shift = <3>; + }; + + sha12_ick: sha12_ick@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <27>; + }; + + wdt2_fck: wdt2_fck@c00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&wkup_32k_fck>; + reg = <0x0c00>; + ti,bit-shift = <5>; + }; + + wdt2_ick: wdt2_ick@c10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&wkup_l4_ick>; + reg = <0x0c10>; + ti,bit-shift = <5>; + }; + + wdt1_ick: wdt1_ick@c10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&wkup_l4_ick>; + reg = <0x0c10>; + ti,bit-shift = <4>; + }; + + gpio1_ick: gpio1_ick@c10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&wkup_l4_ick>; + reg = <0x0c10>; + ti,bit-shift = <3>; + }; + + omap_32ksync_ick: omap_32ksync_ick@c10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&wkup_l4_ick>; + reg = <0x0c10>; + ti,bit-shift = <2>; + }; + + gpt12_ick: gpt12_ick@c10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&wkup_l4_ick>; + reg = <0x0c10>; + ti,bit-shift = <1>; + }; + + gpt1_ick: gpt1_ick@c10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&wkup_l4_ick>; + reg = <0x0c10>; + ti,bit-shift = <0>; + }; + + per_96m_fck: per_96m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_96m_alwon_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + per_48m_fck: per_48m_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_48m_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + uart3_fck: uart3_fck@1000 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&per_48m_fck>; + reg = <0x1000>; + ti,bit-shift = <11>; + }; + + gpt2_gate_fck: gpt2_gate_fck@1000 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <3>; + reg = <0x1000>; + }; + + gpt2_mux_fck: gpt2_mux_fck@1040 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + reg = <0x1040>; + }; + + gpt2_fck: gpt2_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; + }; + + gpt3_gate_fck: gpt3_gate_fck@1000 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <4>; + reg = <0x1000>; + }; + + gpt3_mux_fck: gpt3_mux_fck@1040 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <1>; + reg = <0x1040>; + }; + + gpt3_fck: gpt3_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; + }; + + gpt4_gate_fck: gpt4_gate_fck@1000 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <5>; + reg = <0x1000>; + }; + + gpt4_mux_fck: gpt4_mux_fck@1040 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <2>; + reg = <0x1040>; + }; + + gpt4_fck: gpt4_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; + }; + + gpt5_gate_fck: gpt5_gate_fck@1000 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <6>; + reg = <0x1000>; + }; + + gpt5_mux_fck: gpt5_mux_fck@1040 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <3>; + reg = <0x1040>; + }; + + gpt5_fck: gpt5_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; + }; + + gpt6_gate_fck: gpt6_gate_fck@1000 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <7>; + reg = <0x1000>; + }; + + gpt6_mux_fck: gpt6_mux_fck@1040 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <4>; + reg = <0x1040>; + }; + + gpt6_fck: gpt6_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; + }; + + gpt7_gate_fck: gpt7_gate_fck@1000 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <8>; + reg = <0x1000>; + }; + + gpt7_mux_fck: gpt7_mux_fck@1040 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <5>; + reg = <0x1040>; + }; + + gpt7_fck: gpt7_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; + }; + + gpt8_gate_fck: gpt8_gate_fck@1000 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <9>; + reg = <0x1000>; + }; + + gpt8_mux_fck: gpt8_mux_fck@1040 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <6>; + reg = <0x1040>; + }; + + gpt8_fck: gpt8_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; + }; + + gpt9_gate_fck: gpt9_gate_fck@1000 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <10>; + reg = <0x1000>; + }; + + gpt9_mux_fck: gpt9_mux_fck@1040 { + #clock-cells = <0>; + compatible = "ti,composite-mux-clock"; + clocks = <&omap_32k_fck>, <&sys_ck>; + ti,bit-shift = <7>; + reg = <0x1040>; + }; + + gpt9_fck: gpt9_fck { + #clock-cells = <0>; + compatible = "ti,composite-clock"; + clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>; + }; + + per_32k_alwon_fck: per_32k_alwon_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&omap_32k_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + gpio6_dbck: gpio6_dbck@1000 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&per_32k_alwon_fck>; + reg = <0x1000>; + ti,bit-shift = <17>; + }; + + gpio5_dbck: gpio5_dbck@1000 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&per_32k_alwon_fck>; + reg = <0x1000>; + ti,bit-shift = <16>; + }; + + gpio4_dbck: gpio4_dbck@1000 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&per_32k_alwon_fck>; + reg = <0x1000>; + ti,bit-shift = <15>; + }; + + gpio3_dbck: gpio3_dbck@1000 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&per_32k_alwon_fck>; + reg = <0x1000>; + ti,bit-shift = <14>; + }; + + gpio2_dbck: gpio2_dbck@1000 { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&per_32k_alwon_fck>; + reg = <0x1000>; + ti,bit-shift = <13>; + }; + + wdt3_fck: wdt3_fck@1000 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&per_32k_alwon_fck>; + reg = <0x1000>; + ti,bit-shift = <12>; + }; + + per_l4_ick: per_l4_ick { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&l4_ick>; + clock-mult = <1>; + clock-div = <1>; + }; + + gpio6_ick: gpio6_ick@1010 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <17>; + }; + + gpio5_ick: gpio5_ick@1010 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <16>; + }; + + gpio4_ick: gpio4_ick@1010 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <15>; + }; + + gpio3_ick: gpio3_ick@1010 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <14>; + }; + + gpio2_ick: gpio2_ick@1010 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <13>; + }; + + wdt3_ick: wdt3_ick@1010 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <12>; + }; + + uart3_ick: uart3_ick@1010 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <11>; + }; + + uart4_ick: uart4_ick@1010 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <18>; + }; + + gpt9_ick: gpt9_ick@1010 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <10>; + }; + + gpt8_ick: gpt8_ick@1010 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <9>; + }; + + gpt7_ick: gpt7_ick@1010 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <8>; + }; + + gpt6_ick: gpt6_ick@1010 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <7>; + }; + + gpt5_ick: gpt5_ick@1010 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <6>; + }; + + gpt4_ick: gpt4_ick@1010 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <5>; + }; + + gpt3_ick: gpt3_ick@1010 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <4>; + }; + + gpt2_ick: gpt2_ick@1010 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <3>; + }; + + mcbsp2_ick: mcbsp2_ick@1010 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <0>; + }; + + mcbsp3_ick: mcbsp3_ick@1010 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <1>; + }; + + mcbsp4_ick: mcbsp4_ick@1010 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&per_l4_ick>; + reg = <0x1010>; + ti,bit-shift = <2>; + }; + + mcbsp2_gate_fck: mcbsp2_gate_fck@1000 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <0>; + reg = <0x1000>; + }; + + mcbsp3_gate_fck: mcbsp3_gate_fck@1000 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <1>; + reg = <0x1000>; + }; + + mcbsp4_gate_fck: mcbsp4_gate_fck@1000 { + #clock-cells = <0>; + compatible = "ti,composite-gate-clock"; + clocks = <&mcbsp_clks>; + ti,bit-shift = <2>; + reg = <0x1000>; + }; + + emu_src_mux_ck: emu_src_mux_ck@1140 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; + reg = <0x1140>; + }; + + emu_src_ck: emu_src_ck { + #clock-cells = <0>; + compatible = "ti,clkdm-gate-clock"; + clocks = <&emu_src_mux_ck>; + }; + + pclk_fck: pclk_fck@1140 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&emu_src_ck>; + ti,bit-shift = <8>; + ti,max-div = <7>; + reg = <0x1140>; + ti,index-starts-at-one; + }; + + pclkx2_fck: pclkx2_fck@1140 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&emu_src_ck>; + ti,bit-shift = <6>; + ti,max-div = <3>; + reg = <0x1140>; + ti,index-starts-at-one; + }; + + atclk_fck: atclk_fck@1140 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&emu_src_ck>; + ti,bit-shift = <4>; + ti,max-div = <3>; + reg = <0x1140>; + ti,index-starts-at-one; + }; + + traceclk_src_fck: traceclk_src_fck@1140 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; + ti,bit-shift = <2>; + reg = <0x1140>; + }; + + traceclk_fck: traceclk_fck@1140 { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&traceclk_src_fck>; + ti,bit-shift = <11>; + ti,max-div = <7>; + reg = <0x1140>; + ti,index-starts-at-one; + }; + + secure_32k_fck: secure_32k_fck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + gpt12_fck: gpt12_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&secure_32k_fck>; + clock-mult = <1>; + clock-div = <1>; + }; + + wdt1_fck: wdt1_fck { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&secure_32k_fck>; + clock-mult = <1>; + clock-div = <1>; + }; +}; + +&cm_clockdomains { + core_l3_clkdm: core_l3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&sdrc_ick>; + }; + + dpll3_clkdm: dpll3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll3_ck>; + }; + + dpll1_clkdm: dpll1_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll1_ck>; + }; + + per_clkdm: per_clkdm { + compatible = "ti,clockdomain"; + clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, + <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, + <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, + <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, + <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, + <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, + <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, + <&mcbsp4_ick>; + }; + + emu_clkdm: emu_clkdm { + compatible = "ti,clockdomain"; + clocks = <&emu_src_ck>; + }; + + dpll4_clkdm: dpll4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dpll4_ck>; + }; + + wkup_clkdm: wkup_clkdm { + compatible = "ti,clockdomain"; + clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, + <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, + <&gpt1_ick>; + }; + + dss_clkdm: dss_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, + <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, + <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, + <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, + <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, + <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, + <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, + <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, + <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>; + }; +}; -- 2.7.4

2 1

[U-Boot] [PATCH v4] imx: i.mx6q: add the initial support for LogicPD i.MX6Q SOM
by Adam Ford 12 Apr '17

12 Apr '17

Logic PD has an i.MX6Q system on module (SOM) with a development kit. The SOM has a built-in microSD socket, DDR and NAND flash. The development kit has an SMSC Ethernet PHY, serial debug port and a variety of peripherals. This have been verified to boot the i.MX6Q version over either SD on the development kit or NAND built into the SOM. Items in the dtsi file are specific to the SOM itself. Items in the dts file are in the baseboard. Future versions of the SOM will come out supporting the same basebord and potentially future base boards will come out supporting the same SOM. Signed-off-by: Adam Ford <aford173(a)gmail.com> --- Changes in V4: - Eliminate DM_THERMAL - Fix typo README - Elminate more dead/unnecessary code - Re-order device tree file contents - Add I2C_EEPROM - Remove device tree items U-Boot cannot support - Fix 80 character warning Changes in V3: - Add OF_CONTROL and device tree - Switch to DM_I2C - Switch to DM_ETH - Switch to DM_MMC - Switch to DM_PMIC - Switch to DM_REGULATOR - Switch to DM_GPIO - Fix Ethernet reset to play nicely with DM_GPIO and DM_ETH - Remove more unnecessary code with DM enabled. Changes in V2: - Alphabetize the modified Kconfig file - Clean up README file. - Elminate fdt_high and initrd_high and add bootm_size - Changed MTDPARTS_DEFAULT to increase the kernel size to 16MB - Cleaned up the mx6q_2x_MT41K512M16HA.cfg to include headers, replace hard-coded addresses with human-readable ones, and remove dead code - Updated mx6q_2x_MT41K512M16HA.cfg to use BOOT_OFFSET since SD and NAND have the same offset - Removed 'ifdef' references that were always true. - Removed CPU references that didn't exist. - And made local variables static - Add reference to worked used to derrive this code diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 190e5c6..b9f325f 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -155,6 +155,19 @@ config TARGET_MX6CUBOXI select BOARD_LATE_INIT select SUPPORT_SPL +config TARGET_MX6LOGICPD + bool "Logic PD i.MX6 SOM" + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select DM + select DM_ETH + select DM_GPIO + select DM_I2C + select DM_MMC + select DM_PMIC + select DM_REGULATOR + select OF_CONTROL + config TARGET_MX6QARM2 bool "mx6qarm2" @@ -404,6 +417,7 @@ source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" source "board/samtec/vining_2000/Kconfig" source "board/liebherr/mccmon6/Kconfig" +source "board/logicpd/imx6/Kconfig" source "board/seco/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig" source "board/technexion/pico-imx6ul/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0fbbb9b..a95f2db 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -319,6 +319,7 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ imx6dl-icore-rqs.dtb \ imx6q-icore.dtb \ imx6q-icore-rqs.dtb \ + imx6q-logicpd.dtb \ imx6sx-sabreauto.dtb \ imx6ul-geam-kit.dtb \ imx6ul-isiot-emmc.dtb \ diff --git a/arch/arm/dts/imx6q-logicpd.dts b/arch/arm/dts/imx6q-logicpd.dts new file mode 100644 index 0000000..d1e7a38 --- /dev/null +++ b/arch/arm/dts/imx6q-logicpd.dts @@ -0,0 +1,190 @@ +/* + * Copyright 2017 Logic PD, Inc. + * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6qdl-logicpd.dtsi" + +/ { + model = "Logic PD i.MX6QDL SOM"; + compatible = "fsl,imx6q"; + + reg_usb_otg_vbus: regulator-otg-vbus@0 { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_h1_vbus: regulator-usbh1vbus@1 { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + }; + + reg_3v3: regulator-3v3@2 { + compatible = "regulator-fixed"; + regulator-name = "reg_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + vbus-supply = <&reg_usb_h1_vbus>; + status = "okay"; +}; + +&usbh2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh2>; + phy_type = "hsic"; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <&reg_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-speed = <10>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* nINT */ + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 /* Ethernet Reset */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x130b0 + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x130b0 + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x130b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 + >; + }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* USB_H1_PWR_EN */ + >; + }; + + pinctrl_usbh2: usbh2grp { + fsl,pins = < + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x17030 + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x13030 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 /* USB_OTG_PWR_EN */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; +}; diff --git a/arch/arm/dts/imx6qdl-logicpd.dtsi b/arch/arm/dts/imx6qdl-logicpd.dtsi new file mode 100644 index 0000000..db1a63d --- /dev/null +++ b/arch/arm/dts/imx6qdl-logicpd.dtsi @@ -0,0 +1,361 @@ +/* + * Copyright 2016 Logic PD + * This file is adapted from imx6qdl-sabresd.dtsi. + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "imx6q.dtsi" + +/ { + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x10000000 0x80000000>; + }; +}; + +/* Reroute power feeding the CPU to come from the external PMIC */ +&reg_arm +{ + vin-supply = <&sw1a_reg>; +}; + +&reg_soc +{ + vin-supply = <&sw1c_reg>; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pmic: pfuze100@08 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vddcore"; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vddsoc"; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "gen_3v3"; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-name = "sw3a_vddr"; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-name = "sw3b_vddr"; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "gen_rgmii"; + }; + + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-name = "gen_5v0"; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "gen_vsns"; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "gen_1v5"; + }; + + vgen2_reg: vgen2 { + regulator-name = "vgen2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-name = "gen_vadj_0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + vgen4_reg: vgen4 { + regulator-name = "gen_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-name = "gen_adj_1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-name = "gen_2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + }; + }; + + mfg_eeprom: at24@51 { + compatible = "atmel,24c64"; + pagesize = <32>; + read-only; + reg = <0x51>; + }; + + user_eeprom: at24@52 { + compatible = "atmel,24c64"; + pagesize = <32>; + reg = <0x52>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x1b0b0 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x80000000 + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x80000000 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x80000000 + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x80000000 + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000 + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000 + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000 + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x80000000 + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x80000000 + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x80000000 + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x80000000 + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x80000000 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x80000000 + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x80000000 + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x80000000 + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x80000000 + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x80000000 + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x80000000 + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x80000000 + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x80000000 + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x80000000 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x80000000 + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x80000000 + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x80000000 + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000 + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x80000000 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x80000000 + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x80000000 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000 + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x80000000 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x80000000 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x80000000 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 + MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x80000000 + MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x80000000 + MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x80000000 + MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x80000000 + MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x80000000 + MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x80000000 + MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x80000000 + MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x80000000 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x80000000 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WL_IRQ */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1f0b0 /* WLAN_EN */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1f0b0 /* BT_EN */ + >; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <&sw2_reg>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@0 { + compatible = "ti,wl1837"; + reg = <2>; + interrupt-parent = <&gpio7>; + interrupts = <1 GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/board/logicpd/imx6/Kconfig b/board/logicpd/imx6/Kconfig new file mode 100644 index 0000000..f5e2f58 --- /dev/null +++ b/board/logicpd/imx6/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX6LOGICPD + +config SYS_BOARD + default "imx6" + +config SYS_VENDOR + default "logicpd" + +config SYS_CONFIG_NAME + default "imx6_logic" + +endif diff --git a/board/logicpd/imx6/MAINTAINERS b/board/logicpd/imx6/MAINTAINERS new file mode 100644 index 0000000..5db7d2c --- /dev/null +++ b/board/logicpd/imx6/MAINTAINERS @@ -0,0 +1,6 @@ +MX6LOGICPD BOARD +M: Adam Ford <aford173(a)gmail.com> +S: Maintained +F: board/logicpd/imx6/ +F: include/configs/imx6_logic.h +F: configs/imx6q_logic_defconfig diff --git a/board/logicpd/imx6/Makefile b/board/logicpd/imx6/Makefile new file mode 100644 index 0000000..337df92 --- /dev/null +++ b/board/logicpd/imx6/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg(a)denx.de> +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := imx6logic.o + diff --git a/board/logicpd/imx6/README b/board/logicpd/imx6/README new file mode 100644 index 0000000..df43b55 --- /dev/null +++ b/board/logicpd/imx6/README @@ -0,0 +1,37 @@ +U-Boot for LogicPD i.MX6 Development Kit +---------------------------------------- + +This file contains information for the port of U-Boot to the Logic PD Development kit. + +Logic PD has an i.MX6 System On Module (SOM) and a correspondong development +board. SOM has a built-in microSD socket, DDR and NAND flash. The development kit has +an SMSC Ethernet PHY, serial debug port and a variety of peripherals. + +On the intial release, the SOM came with either an i.MX6D or i.MX6Q. + +For more details about Logic PD i.MX6 Development kit, visit: +https://www.logicpd.com/ + +Building U-Boot for Logic PD Development Kit +-------------------------------------------- +To build U-Boot for the Dual and Quad variants: + + make imx6q_logic_defconfig + make u-boot.imx ARCH=arm CROSS_COMPILE=arm-linux- + + +Flashing U-Boot into the SD card +-------------------------------- + +See README.imximage for details on booting from SD + +Flashing U-Boot into NAND +------------------------- +Once in Linux with MTD support for the NAND on /dev/mtd0, program U-Boot with the following: +with: + + kobs-ng init -v -x u-boot-dtb.imx + +Additional Support Documentation can be found at: +https://support.logicpd.com/ + diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c new file mode 100644 index 0000000..5576799 --- /dev/null +++ b/board/logicpd/imx6/imx6logic.c @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2017 Logic PD, Inc. + * + * Author: Adam Ford <aford173(a)gmail.com> + * + * Based on SabreSD by Fabio Estevam <fabio.estevam(a)nxp.com> + * and updates by Jagan Teki <jagan(a)amarulasolutions.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <miiphy.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <linux/sizes.h> +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/iomux-v3.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart3_pads[] = { + MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void fixup_enet_clock(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct gpio_desc nint; + struct gpio_desc reset; + int ret; + + /* Set Ref Clock to 50 MHz */ + enable_fec_anatop_clock(0, ENET_50MHZ); + + /* Set GPIO_16 as ENET_REF_CLK_OUT */ + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); + + /* Request GPIO Pins to reset Ethernet with new clock */ + ret = dm_gpio_lookup_name("GPIO4_7", &nint); + if (ret) { + printf("Unable to lookup GPIO4_7\n"); + return; + } + + ret = dm_gpio_request(&nint, "eth0_nInt"); + if (ret) { + printf("Unable to request eth0_nInt\n"); + return; + } + + /* Ensure nINT is input or PHY won't startup */ + dm_gpio_set_dir_flags(&nint, GPIOD_IS_IN); + + ret = dm_gpio_lookup_name("GPIO4_9", &reset); + if (ret) { + printf("Unable to lookup GPIO4_9\n"); + return; + } + + ret = dm_gpio_request(&reset, "eth0_reset"); + if (ret) { + printf("Unable to request eth0_reset\n"); + return; + } + + /* Reset LAN8710A PHY */ + dm_gpio_set_dir_flags(&reset, GPIOD_IS_OUT); + dm_gpio_set_value(&reset, 0); + udelay(150); + dm_gpio_set_value(&reset, 1); + mdelay(50); +} + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); +} + +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), +}; + +static void setup_nand_pins(void) +{ + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_early_init_f(void) +{ + fixup_enet_clock(); + setup_iomux_uart(); + setup_nand_pins(); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + return 0; +} + +int board_late_init(void) +{ + setenv("board_name", "imx6logic"); + + if (is_mx6dq()) { + setenv("board_rev", "MX6DQ"); + setenv("fdt_file", "imx6q-logicpd.dtb"); + } + + return 0; +} diff --git a/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg b/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg new file mode 100644 index 0000000..b206548 --- /dev/null +++ b/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2017 Logic PD, Inc. + * Adam Ford <aford173(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#include <asm/imx-common/imximage.cfg> + +/* image version */ +IMAGE_VERSION 2 + +BOOT_OFFSET FLASH_OFFSET_STANDARD + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +#define __ASSEMBLY__ +#include <config.h> +#include "asm/arch-mx6/mx6-ddr.h" +#include "asm/arch-mx6/iomux.h" +#include "asm/arch-mx6/crm_regs.h" + +DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 +DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 +DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 +DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 +DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 +DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030 +DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 +DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 +DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 +DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 +DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 +DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 +DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 +DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 +DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A +DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B +DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03340338 +DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0334032C +DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4036383C +DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x2E384038 +DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 +DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 +DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 +DATA 4, MX6_MMDC_P0_MDCFG0, 0xB8BE7955 +DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 +DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB +DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 +DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 +DATA 4, MX6_MMDC_P0_MDOR, 0x00BE1023 +DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 +DATA 4, MX6_MMDC_P0_MDCTL, 0x85190000 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00888032 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031 +DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030 +DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 +DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 +DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007 +DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 +DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 +DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, CCM_CCGR0, 0x00C03F3F +DATA 4, CCM_CCGR1, 0x0030FC03 +DATA 4, CCM_CCGR2, 0x0FFFC000 +DATA 4, CCM_CCGR3, 0x3FF00000 +DATA 4, CCM_CCGR4, 0xFFFFF300 +DATA 4, CCM_CCGR5, 0x0F0000F3 +DATA 4, CCM_CCGR6, 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 MX6_IOMUXC_GPR4 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 MX6_IOMUXC_GPR6 0x007F007F +DATA 4 MX6_IOMUXC_GPR7 0x007F007F diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig new file mode 100644 index 0000000..503b14c --- /dev/null +++ b/configs/imx6q_logic_defconfig @@ -0,0 +1,38 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6LOGICPD=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg,MX6Q" +CONFIG_BOOTDELAY=3 +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="i.MX6 Logic # " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_BLK is not set +CONFIG_SYS_I2C_MXC=y +# CONFIG_DM_MMC_OPS is not set +CONFIG_NAND_MXS=y +CONFIG_FEC_MXC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR_PFUZE100=y diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h new file mode 100644 index 0000000..bb95dd8 --- /dev/null +++ b/include/configs/imx6_logic.h @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2017 Logic PD, Inc. + * + * Configuration settings for the LogicPD i.MX6 SOM. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX6LOGIC_CONFIG_H +#define __IMX6LOGIC_CONFIG_H + +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONSOLE_DEV "ttymxc0" + +#include <config_distro_defaults.h> +#include "mx6_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) + +#define CONFIG_MXC_UART + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* Dev kit SD card */ + +/* Ethernet Configs */ +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_PHY_SMSC + +/* Command definition */ +#define CONFIG_CMD_BMODE + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "bootm_size=0x10000000\0" \ + "fdt_addr_r=0x18000000\0" \ + "fdt_addr=0x18000000\0" \ + "ramdisk_addr_r=0x13000000\0" \ + "ramdiskaddr=0x13000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_file=rootfs.cpio.uboot\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "console=" CONSOLE_DEV "\0" \ + "mmcdev=1\0" \ + "mmcpart=1\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "nandroot=ubi0:rootfs rootfstype=ubifs\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate}" \ + " root=${mmcroot} ${mtdparts}\0" \ + "nandargs=setenv bootargs console=${console},${baudrate}" \ + " ubi.mtd=fs root=${nandroot} ${mtdparts}\0" \ + "ramargs=setenv bootargs console=${console},${baudrate}" \ + " root=/dev/ram rw ${mtdparts}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...;" \ + " source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};" \ + " setenv kernelsize ${filesize}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdiskaddr}" \ + " ${ramdisk_file}; setenv ramdisksize ${filesize}\0" \ + "mmcboot=echo Booting from mmc...; run mmcargs; run loadimage;" \ + " run loadfdt; bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcramboot=run ramargs; run loadimage;" \ + " run loadfdt; run loadramdisk;" \ + " bootz ${loadaddr} ${ramdiskaddr} ${fdt_addr}\0" \ + "nandboot=echo Booting from nand ...; " \ + " run nandargs;" \ + " nand read ${loadaddr} kernel ${kernelsize};" \ + " nand read ${fdt_addr} dtb;" \ + " bootz ${loadaddr} - ${fdt_addr}\0" \ + "nandramboot=echo Booting RAMdisk from nand ...; " \ + " nand read ${ramdiskaddr} fs ${ramdisksize};" \ + " nand read ${loadaddr} kernel ${kernelsize};" \ + " nand read ${fdt_addr} dtb;" \ + " run ramargs;" \ + " bootz ${loadaddr} ${ramdiskaddr} ${fdt_addr}\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs" \ + " ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "autoboot=mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#define CONFIG_BOOTCOMMAND \ + "run autoboot" + +#define CONFIG_ARP_TIMEOUT 200UL + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x10010000 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 + +#define CONFIG_STACKSIZE (128 * 1024) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x400000 +#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE + +/* NAND stuff */ +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 + +/* MTD device */ +# define CONFIG_MTD_DEVICE +# define CONFIG_CMD_MTDPARTS +# define CONFIG_MTD_PARTITIONS +# define MTDIDS_DEFAULT "nand0=gpmi-nand" +# define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:4m(uboot)," \ + "1m(env),16m(kernel),1m(dtb),-(fs)" + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#define CONFIG_APBH_DMA +#define CONFIG_APBH_DMA_BURST +#define CONFIG_APBH_DMA_BURST8 + +/* EEPROM contains serial no, MAC addr and other Logic PD info */ +#define CONFIG_I2C_EEPROM + +#endif /* __IMX6LOGIC_CONFIG_H */ -- 2.7.4

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[U-Boot] [PATCH] cmd_mmc: fix arg parsing for setdsr subcmd
by Markus Niebel 12 Apr '17

12 Apr '17

From: Markus Niebel <Markus.Niebel(a)tq-group.com> The handler do_setdsr receives only the dsr parameter, the action is parsed before. Error was introduced when restructuring the mmc command implementation in commit 1fd93c6e7d8a1e4d6261058cefab11b875ded252. Reported-by: Michael Krummsdorf <Michael.Krummsdorf(a)tq-group.com> Signed-off-by: Markus Niebel <Markus.Niebel(a)tq-group.com> --- cmd/mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/mmc.c b/cmd/mmc.c index b8dcc26..f83032e 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -710,7 +710,7 @@ static int do_mmc_setdsr(cmd_tbl_t *cmdtp, int flag, if (argc != 2) return CMD_RET_USAGE; - val = simple_strtoul(argv[2], NULL, 16); + val = simple_strtoul(argv[1], NULL, 16); mmc = find_mmc_device(curr_device); if (!mmc) { -- 1.9.1

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[U-Boot] [PATCH] imx: ventana: config: set MMC env Partition to 1
by Tim Harvey 12 Apr '17

12 Apr '17

Partition 1 equates to EMMC boot0 Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- include/configs/gw_ventana.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index c3908de..8191d43 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -232,6 +232,7 @@ #endif #if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_SYS_MMC_ENV_PART 1 #define CONFIG_ENV_OFFSET (709 * SZ_1K) #define CONFIG_ENV_SIZE (128 * SZ_1K) #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (128 * SZ_1K)) -- 2.7.4

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[U-Boot] [PATCH v3] mx6sabresd: README: Add eMMC boot configuration
by Breno Lima 12 Apr '17

12 Apr '17

Explain how to flash the eMMC and how to boot from it. Signed-off-by: Breno Lima <breno.lima(a)nxp.com> --- Changes since v2: -Fix number of methods for booting mx6sabresd boards. board/freescale/mx6sabresd/README | 55 +++++++++++++++++++++++++++++++++------ 1 file changed, 47 insertions(+), 8 deletions(-) diff --git a/board/freescale/mx6sabresd/README b/board/freescale/mx6sabresd/README index 5814b9d..bc0c0d0 100644 --- a/board/freescale/mx6sabresd/README +++ b/board/freescale/mx6sabresd/README @@ -1,17 +1,19 @@ How to use and build U-Boot on mx6sabresd: ---------------------------------- -Currently there are three methods for booting mx6sabresd boards: +Currently there are four methods for booting mx6sabresd boards: -1. Booting via Normal U-Boot (u-boot.imx) +1. Booting from SD card via normal U-Boot (u-boot.imx) -2. Booting via SPL (SPL and u-boot.img) +2. Booting from eMMC via normal U-Boot -3. Booting via Falcon mode (SPL launches the kernel directly) +3. Booting via SPL (SPL and u-boot.img) +4. Booting via Falcon mode (SPL launches the kernel directly) -1. Booting via Normal U-Boot ----------------------------- + +1. Booting from SD card via normal U-Boot +----------------------------------------- $ make mx6qsabresd_defconfig (If you want to build for mx6qsabresd) @@ -28,7 +30,44 @@ This will generate the image called u-boot.imx. $ sudo dd if=u-boot.imx of=/dev/sdb bs=1K seek=1 && sync -2. Booting via SPL +2. Booting from eMMC via normal U-Boot +-------------------------------------- + +$ make mx6qsabresd_defconfig (If you want to build for mx6qsabresd) + +or + +$ make mx6dlsabresd_defconfig (If you want to build for mx6dlsabresd) + +$ make + +This will generate the image called u-boot.imx. + +- Flash the u-boot.imx binary into the eMMC: + +Set SW6 to download mode: 00001100 + +Plug a usb cable to USB-OTG and load the u-boot image using the imx_usb_loader +tool (https://github.com/boundarydevices/imx_usb_loader): + +$ sudo ./imx_usb u-boot.imx + +In U-boot change the eMMC partition config: + +=> mmc partconf 2 1 0 0 + +Mount the eMMC in the host PC: + +=> ums 0 mmc 2 + +Flash the u-boot.imx binary + +$ sudo dd if=u-boot.imx of=/dev/sdX bs=1K seek=1 && sync + +Set SW6 to eMMC 8-bit boot: 11010110 + + +3. Booting via SPL ------------------ Other method for building U-Boot on mx6qsabresd and mx6qpsabresd is @@ -48,7 +87,7 @@ $ sudo dd if=SPL of=/dev/sdb bs=1K seek=1 && sync $ sudo dd if=u-boot.img of=/dev/sdbbs=1K seek=69 && sync -3. Booting via Falcon mode +4. Booting via Falcon mode -------------------------- $ make mx6sabresd_spl_defconfig -- 2.7.4

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[U-Boot] [PATCH] Set console speed to 115200 on mx6cuboxi.
by Vagrant Cascadian 12 Apr '17

12 Apr '17

By default, u-boot itself outputs on the serial console at 115200, so it may as well pass the same value to the booted operating system as well. Signed-off-by: Vagrant Cascadian <vagrant(a)debian.org> --- include/configs/mx6cuboxi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 2782911da3..84fdf656cd 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -84,7 +84,7 @@ "initrd_high=0xffffffff\0" \ "fdt_high=0xffffffff\0" \ "ip_dyn=yes\0" \ - "console=" CONSOLE_DEV "\0" \ + "console=" CONSOLE_DEV ",115200\0" \ "bootm_size=0x10000000\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "update_sd_firmware=" \ -- 2.11.0

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[U-Boot] [PATCH 1/4] board: advantech: dms-ba16: Add the configuration options for display initialization
by Ken Lin 12 Apr '17

12 Apr '17

Add the configuration options for display initialization in case we need to do the display initialization in kernel to support different timing settings Signed-off-by: Ken Lin <yungching0725(a)gmail.com> --- board/advantech/dms-ba16/dms-ba16.c | 3 +++ include/configs/advantech_dms-ba16.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/board/advantech/dms-ba16/dms-ba16.c b/board/advantech/dms-ba16/dms-ba16.c index 20750fb0ce..a67752f1ca 100644 --- a/board/advantech/dms-ba16/dms-ba16.c +++ b/board/advantech/dms-ba16/dms-ba16.c @@ -539,6 +539,8 @@ int board_late_init(void) #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif + +#if defined(CONFIG_VIDEO_IPUV3) /* * We need at least 200ms between power on and backlight on * as per specifications from CHI MEI @@ -555,6 +557,7 @@ int board_late_init(void) gpio_direction_output(LVDS_BACKLIGHT_GP, 1); pwm_enable(0); +#endif #ifdef CONFIG_CMD_SATA setup_ba16_sata(); diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h index 14e9c06fac..53a45b21a4 100644 --- a/include/configs/advantech_dms-ba16.h +++ b/include/configs/advantech_dms-ba16.h @@ -262,6 +262,7 @@ #define CONFIG_SYS_FSL_USDHC_NUM 3 /* Framebuffer */ +#ifdef CONFIG_VIDEO #define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN @@ -272,6 +273,7 @@ #define CONFIG_IPUV3_CLK 260000000 #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP +#endif #define CONFIG_PWM_IMX #define CONFIG_IMX6_PWM_PER_CLK 66000000 -- 2.11.0

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[U-Boot] [PATCH] wandboard: Enable SATA for quad
by Nicolas Chauvet 12 Apr '17

12 Apr '17

Having sata first will makes preference to sata boot if both sata0 and mmc0 have a boot partition This change was not tested against wanboard solo/dual, but it does operate correctly when there is no sata disk connected on quad. (it falls back to mmc0 boot) Tested with current u-boot 2017.03-rc2 with Fedora 25 workstation armhfp Signed-off-by: Nicolas Chauvet <kwizart(a)gmail.com> --- include/configs/wandboard.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 7e9757a..3101d1b 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -128,6 +128,7 @@ BOOTENV #define BOOT_TARGET_DEVICES(func) \ + func(SATA, sata, 0) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ func(USB, usb, 0) \ -- 2.7.4

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[U-Boot] [PATCH 1/5] i.MX6Q: icorem6: Add modeboot env via board_late_init
by Jagan Teki 12 Apr '17

12 Apr '17

From: Jagan Teki <jagan(a)amarulasolutions.com> Add runtime, modeboot env which is setting mmcboot, or nandboot based on the bootdevice so-that conditional macros b/w MMC and NAND for CONFIG_BOOTCOMMAND should be avoided in config files. Cc: Matteo Lisi <matteo.lisi(a)engicam.com> Cc: Michael Trimarchi <michael(a)amarulasolutions.com> Cc: Stefano Babic <sbabic(a)denx.de> Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- arch/arm/cpu/armv7/mx6/Kconfig | 1 + board/engicam/icorem6/icorem6.c | 19 +++++++++++++++++++ include/configs/imx6qdl_icore.h | 36 ++++++++++++++++-------------------- 3 files changed, 36 insertions(+), 20 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 9174136..37f271b 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -160,6 +160,7 @@ config TARGET_MX6QARM2 config TARGET_MX6Q_ICORE bool "Support Engicam i.Core" + select BOARD_LATE_INIT select MX6QDL select OF_CONTROL select DM diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c index 171ec45..f78f8c9 100644 --- a/board/engicam/icorem6/icorem6.c +++ b/board/engicam/icorem6/icorem6.c @@ -205,6 +205,25 @@ int board_early_init_f(void) return 0; } +int board_late_init(void) +{ + switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> + IMX6_BMODE_SHIFT) { + case IMX6_BMODE_SD: + case IMX6_BMODE_ESD: + setenv("modeboot", "mmcboot"); + break; + case IMX6_BMODE_NAND: + setenv("modeboot", "nandboot"); + break; + default: + setenv("modeboot", ""); + break; + } + + return 0; +} + int board_init(void) { /* Address of boot parameters */ diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h index 5a28b15..b517e87 100644 --- a/include/configs/imx6qdl_icore.h +++ b/include/configs/imx6qdl_icore.h @@ -64,7 +64,7 @@ "fitboot=echo Booting FIT image from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ - "mmcboot=echo Booting from mmc ...; " \ + "_mmcboot=run mmcargs; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ @@ -79,6 +79,20 @@ "else " \ "bootm; " \ "fi\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadfit; then " \ + "run fitboot; " \ + "else " \ + "if run loadimage; then " \ + "run _mmcboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "fi\0" \ "nandboot=echo Booting from nand ...; " \ "if mtdparts; then " \ "echo Starting nand boot ...; " \ @@ -90,25 +104,7 @@ "nand read ${fdt_addr} dtb 0x100000; " \ "bootm ${loadaddr} - ${fdt_addr}\0" -#ifdef CONFIG_NAND_MXS -# define CONFIG_BOOTCOMMAND "run nandboot" -#else -# define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadfit; then " \ - "run fitboot; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "fi; " \ - "fi; " \ - "fi; " \ - "fi" -#endif +#define CONFIG_BOOTCOMMAND "run $modeboot" /* Miscellaneous configurable options */ #define CONFIG_SYS_MEMTEST_START 0x80000000 -- 1.9.1

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