April 2017 - U-Boot

[U-Boot] [PATCH v2] arm: psci: make psci usable on single core socs
by Yuantian Tang 18 Apr '17

18 Apr '17

PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao(a)nxp.com> Signed-off-by: Tang Yuantian <andy.tang(a)nxp.com> --- v2: - refine the title and commit message arch/arm/cpu/armv8/cpu-dt.c | 13 +++------- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 35 ++++++++++++--------------- arch/arm/cpu/armv8/sec_firmware.c | 2 +- arch/arm/include/asm/arch-fsl-layerscape/mp.h | 4 +++ arch/arm/include/asm/armv8/sec_firmware.h | 7 ++++++ 5 files changed, 31 insertions(+), 30 deletions(-) diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c index 5156a15..e3c8aa2 100644 --- a/arch/arm/cpu/armv8/cpu-dt.c +++ b/arch/arm/cpu/armv8/cpu-dt.c @@ -7,25 +7,19 @@ #include <common.h> #include <asm/psci.h> #include <asm/system.h> -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT #include <asm/armv8/sec_firmware.h> -#endif +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT int psci_update_dt(void *fdt) { -#ifdef CONFIG_MP -#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI) - -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT /* * If the PSCI in SEC Firmware didn't work, avoid to update the * device node of PSCI. But still return 0 instead of an error * number to support detecting PSCI dynamically and then switching * the SMP boot method between PSCI and spin-table. */ - if (sec_firmware_support_psci_version() == 0xffffffff) + if (sec_firmware_support_psci_version() == PSCI_INVALID_VER) return 0; -#endif fdt_psci(fdt); #if defined(CONFIG_ARMV8_PSCI) && !defined(CONFIG_ARMV8_SECURE_BASE) @@ -34,7 +28,6 @@ int psci_update_dt(void *fdt) __secure_end - __secure_start); #endif -#endif -#endif return 0; } +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index ea6c090..ccddd49 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -14,18 +14,14 @@ #include <asm/arch/soc.h> #include <asm/arch/cpu.h> #include <asm/arch/speed.h> -#ifdef CONFIG_MP #include <asm/arch/mp.h> -#endif #include <efi_loader.h> #include <fm_eth.h> #include <fsl-mc/fsl_mc.h> #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> #endif -#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT #include <asm/armv8/sec_firmware.h> -#endif #ifdef CONFIG_SYS_FSL_DDR #include <fsl_ddr.h> #endif @@ -474,13 +470,19 @@ int cpu_eth_init(bd_t *bis) return error; } -int arch_early_init_r(void) +static inline int check_psci(void) { -#ifdef CONFIG_MP - int rv = 1; - u32 psci_ver = 0xffffffff; -#endif + unsigned int psci_ver; + psci_ver = sec_firmware_support_psci_version(); + if (psci_ver == PSCI_INVALID_VER) + return 1; + + return 0; +} + +int arch_early_init_r(void) +{ #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 u32 svr_dev_id; /* @@ -494,18 +496,13 @@ int arch_early_init_r(void) #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR) erratum_a009942_check_cpo(); #endif -#ifdef CONFIG_MP -#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \ - defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI) - /* Check the psci version to determine if the psci is supported */ - psci_ver = sec_firmware_support_psci_version(); -#endif - if (psci_ver == 0xffffffff) { - rv = fsl_layerscape_wake_seconday_cores(); - if (rv) + if (check_psci()) { + printf("PSCI: PSCI does not exist.\n"); + + /* if PSCI does not exist, boot secondary cores here */ + if (fsl_layerscape_wake_seconday_cores()) printf("Did not wake secondary cores\n"); } -#endif #ifdef CONFIG_SYS_HAS_SERDES fsl_serdes_init(); diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index ec9cf40..4afa3ad 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -227,7 +227,7 @@ unsigned int sec_firmware_support_psci_version(void) if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) return _sec_firmware_support_psci_version(); - return 0xffffffff; + return PSCI_INVALID_VER; } #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h index d0832b5..fd3f851 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -31,7 +31,11 @@ extern u64 __spin_table[]; extern u64 __real_cntfrq; extern u64 *secondary_boot_code; extern size_t __secondary_boot_code_size; +#ifdef CONFIG_MP int fsl_layerscape_wake_seconday_cores(void); +#else +static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; } +#endif void *get_spin_tbl_addr(void); phys_addr_t determine_mp_bootpg(void); void secondary_boot_func(void); diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h index bcdb1b0..bc1d97d 100644 --- a/arch/arm/include/asm/armv8/sec_firmware.h +++ b/arch/arm/include/asm/armv8/sec_firmware.h @@ -7,12 +7,19 @@ #ifndef __SEC_FIRMWARE_H_ #define __SEC_FIRMWARE_H_ +#define PSCI_INVALID_VER 0xffffffff + int sec_firmware_init(const void *, u32 *, u32 *); int _sec_firmware_entry(const void *, u32 *, u32 *); bool sec_firmware_is_valid(const void *); #ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI unsigned int sec_firmware_support_psci_version(void); unsigned int _sec_firmware_support_psci_version(void); +#else +static inline unsigned int sec_firmware_support_psci_version(void) +{ + return PSCI_INVALID_VER; +} #endif #endif /* __SEC_FIRMWARE_H_ */ -- 2.1.0.27.g96db324

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Re: [U-Boot] [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
by york sun 18 Apr '17

18 Apr '17

On 02/16/2017 01:12 PM, york.sun(a)nxp.com wrote: > On 02/03/2017 06:08 AM, Suresh Gupta wrote: <snip> >> +static void erratum_a009007(void) >> +{ >> +/* TODO:implement the out_be16 instead of writew which is taking >> +little endian style */ > > Did you mean to remind yourself to finish this before sending this > patch? You know we already have out_be16(), don't you? > Suresh, Are you going to send an update? York

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[U-Boot] [PATCH] board/t1024rdb: enable board-level reset when issuing reset command
by Shengzhou Liu 18 Apr '17

18 Apr '17

As board-specific reset logic, it needs to issue reset signal via CPLD when issuing 'reset' command in u-boot, this patch solves the issue of reset command not working on T1024RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)nxp.com> --- board/freescale/t102xrdb/t102xrdb.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index 56f7c1a..f370f72 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -167,6 +167,13 @@ unsigned long get_board_ddr_clk(void) return CONFIG_DDR_CLK_FREQ; } +#ifdef CONFIG_TARGET_T1024RDB +void board_reset(void) +{ + CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); +} +#endif + int misc_init_r(void) { return 0; -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram
by Ruchika Gupta 18 Apr '17

18 Apr '17

Fir E6500 cores, L2 cache has been used as init_ram. L1 cache is a write through cache on E6500.If lines are not locked in both L1 and L2 caches, crashes are observed during secure boot. This patch locks/unlocks both L1 as well as L2 cache to prevent the crash. Signed-off-by: Ruchika Gupta <ruchika.gupta(a)nxp.com> --- arch/powerpc/cpu/mpc85xx/start.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index c3e1234..b9a4cb5 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1145,8 +1145,9 @@ switch_as: li r0,0 1: dcbz r0,r3 -#ifdef CONFIG_E6500 /* Lock/unlock L2 cache instead of L1 */ +#ifdef CONFIG_E6500 /* Lock/unlock L2 cache long with L1 */ dcbtls 2, r0, r3 + dcbtls 0, r0, r3 #else dcbtls 0, r0, r3 #endif @@ -1790,8 +1791,9 @@ unlock_ram_in_cache: slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) mtctr r4 1: dcbi r0,r3 -#ifdef CONFIG_E6500 /* lock/unlock L2 cache instead of L1 */ +#ifdef CONFIG_E6500 /* lock/unlock L2 cache long with L1 */ dcblc 2, r0, r3 + dcblc 0, r0, r3 #else dcblc r0,r3 #endif -- 1.9.1

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[U-Boot] [v2] armv8/fsl-layerscape: fdt: avoid incorrect fixing with CONFIG_SYS_CLK_FREQ
by Yangbo Lu 18 Apr '17

18 Apr '17

Current sysclk fixing would fix all clocks with 'fixed-clock' compatible. This patch is to fix sysclk by path to avoid any incorrect fixing. Signed-off-by: Yangbo Lu <yangbo.lu(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 762a95b..05c4577 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -373,8 +373,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif - do_fixup_by_compat_u32(blob, "fixed-clock", - "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); + do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency", + CONFIG_SYS_CLK_FREQ, 1); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v3] armv8: fsl-lsch3: Instantiate TZASC configuration in 2 groups
by Ashish Kumar 18 Apr '17

18 Apr '17

Number of TZASC instances may vary across NXP SoCs. So put TZASC configuration under instance specific defines. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> --- v3: Fix indentation in commit message arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8 ++++++++ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 24 +++++++++++++----------- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index e3fe15d..fbb95cd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -66,6 +66,8 @@ config ARCH_LS2080A select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_LE select SYS_FSL_SRDS_2 + select FSL_TZASC_1 + select FSL_TZASC_2 select SYS_FSL_ERRATUM_A008336 select SYS_FSL_ERRATUM_A008511 select SYS_FSL_ERRATUM_A008514 @@ -213,6 +215,12 @@ config SYS_FSL_SRDS_2 config SYS_HAS_SERDES bool +config FSL_TZASC_1 + bool + +config FSL_TZASC_2 + bool + endmenu menu "Layerscape clock tree configuration" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index a2185f2..79d1637 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -229,38 +229,40 @@ ENTRY(lowlevel_init) * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just * placeholders. */ +#ifdef CONFIG_FSL_TZASC_1 ldr x1, =TZASC_GATE_KEEPER(0) ldr w0, [x1] /* Filter 0 Gate Keeper Register */ orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */ str w0, [x1] - ldr x1, =TZASC_GATE_KEEPER(1) - ldr w0, [x1] /* Filter 0 Gate Keeper Register */ - orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */ - str w0, [x1] - ldr x1, =TZASC_REGION_ATTRIBUTES_0(0) ldr w0, [x1] /* Region-0 Attributes Register */ orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */ orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */ str w0, [x1] + ldr x1, =TZASC_REGION_ID_ACCESS_0(0) + ldr w0, [x1] /* Region-0 Access Register */ + mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ + str w0, [x1] +#endif +#ifdef CONFIG_FSL_TZASC_2 + ldr x1, =TZASC_GATE_KEEPER(1) + ldr w0, [x1] /* Filter 0 Gate Keeper Register */ + orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */ + str w0, [x1] + ldr x1, =TZASC_REGION_ATTRIBUTES_0(1) ldr w0, [x1] /* Region-1 Attributes Register */ orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */ orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */ str w0, [x1] - ldr x1, =TZASC_REGION_ID_ACCESS_0(0) - ldr w0, [x1] /* Region-0 Access Register */ - mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ - str w0, [x1] - ldr x1, =TZASC_REGION_ID_ACCESS_0(1) ldr w0, [x1] /* Region-1 Attributes Register */ mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ str w0, [x1] - +#endif isb dsb sy #endif -- 2.7.4

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[U-Boot] [PATCH] armv8: ls2080a: Add serdes2 protocol 0x51 support
by Santan Kumar 18 Apr '17

18 Apr '17

Signed-off-by: Santan Kumar <santan.kumar(a)nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c index ab83e85..4db3c76 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c @@ -70,6 +70,7 @@ static struct serdes_config serdes2_cfg_tbl[] = { SATA2 } }, {0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, SATA2 } }, + {0x51, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, {0x57, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII15, SGMII16 } }, {} }; -- 1.9.1

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[U-Boot] [PATCH] arm64/ls1046a: Enable ERRATUM_A008850 for ls1046a SoC
by Shengzhou Liu 18 Apr '17

18 Apr '17

Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index a99b1c6..25588c8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -36,6 +36,7 @@ config ARCH_LS1046A select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008336 select SYS_FSL_ERRATUM_A008511 + select SYS_FSL_ERRATUM_A008850 select SYS_FSL_ERRATUM_A009801 select SYS_FSL_ERRATUM_A009803 select SYS_FSL_ERRATUM_A009942 -- 2.1.0.27.g96db324

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[U-Boot] [Patch 3/3,v2] armv7: ls1021a: Drop macro CONFIG_LS102XA
by York Sun 18 Apr '17

18 Apr '17

Use CONFIG_ARCH_LS1021A instead. Signed-off-by: York Sun <york.sun(a)nxp.com> Reviewed-by: Alison Wang <Alison.wang(a)nxp.com> --- Change log v2: Fix a typo in Makefile arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/dts/Makefile | 2 +- arch/arm/include/asm/arch-ls102xa/config.h | 2 +- arch/arm/include/asm/config.h | 2 +- board/freescale/common/arm_sleep.c | 6 +++--- board/freescale/common/fsl_chain_of_trust.c | 2 +- board/freescale/common/fsl_validate.c | 2 +- drivers/i2c/mxc_i2c.c | 2 +- drivers/qe/qe.c | 6 +++--- drivers/usb/common/fsl-errata.c | 2 +- include/configs/ls1021aiot.h | 2 -- include/configs/ls1021aqds.h | 2 -- include/configs/ls1021atwr.h | 2 -- include/fsl_errata.h | 4 ++-- include/linux/immap_qe.h | 2 +- include/linux/usb/xhci-fsl.h | 2 +- include/tsec.h | 2 +- include/usb/ehci-ci.h | 2 +- scripts/config_whitelist.txt | 1 - 19 files changed, 20 insertions(+), 27 deletions(-) diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 02e8778..999ab47 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,7 +12,7 @@ obj-y += cache_v7.o cache_v7_asm.o obj-y += cpu.o cp15.o obj-y += syslib.o -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_ARCH_MX7ULP)$(CONFIG_LS102XA),) +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_ARCH_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_ARCH_MX7ULP)$(CONFIG_ARCH_LS1021A),) ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a2c0717..1ecbb32 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -166,7 +166,7 @@ dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ am571x-idk.dtb dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb -dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \ +dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ ls1021a-qds-lpuart.dtb \ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ ls1021a-iot-duart.dtb diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 2f7233f..5c4da0f 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -108,7 +108,7 @@ #define DCU_LAYER_MAX_NUM 16 -#ifdef CONFIG_LS102XA +#ifdef CONFIG_ARCH_LS1021A #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #else diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index 1ad221a..5674d37 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -14,7 +14,7 @@ #define CONFIG_STATIC_RELA #endif -#if defined(CONFIG_LS102XA) || \ +#if defined(CONFIG_ARCH_LS1021A) || \ defined(CONFIG_CPU_PXA27X) || \ defined(CONFIG_CPU_MONAHANS) || \ defined(CONFIG_CPU_PXA25X) || \ diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c index 16fd445..6ed5d9e 100644 --- a/board/freescale/common/arm_sleep.c +++ b/board/freescale/common/arm_sleep.c @@ -13,7 +13,7 @@ #endif #include <asm/armv7.h> -#if defined(CONFIG_LS102XA) +#if defined(CONFIG_ARCH_LS1021A) #include <asm/arch/immap_ls102xa.h> #endif @@ -66,7 +66,7 @@ static void dp_ddr_restore(void) *dst++ = *src++; } -#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_LS102XA) +#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A) void ls1_psci_resume_fixup(void) { u32 tmp; @@ -104,7 +104,7 @@ static void dp_resume_prepare(void) #ifdef CONFIG_U_QE u_qe_resume(); #endif -#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_LS102XA) +#if defined(CONFIG_ARMV7_PSCI) && defined(CONFIG_ARCH_LS1021A) ls1_psci_resume_fixup(); #endif } diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 438e781..aad1b93 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -22,7 +22,7 @@ #include <asm/fsl_pamu.h> #endif -#ifdef CONFIG_LS102XA +#ifdef CONFIG_ARCH_LS1021A #include <asm/arch/immap_ls102xa.h> #endif diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 125655a..ed48c5c 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -15,7 +15,7 @@ #include <u-boot/rsa-mod-exp.h> #include <hash.h> #include <fsl_secboot_err.h> -#ifdef CONFIG_LS102XA +#ifdef CONFIG_ARCH_LS1021A #include <asm/arch/immap_ls102xa.h> #endif diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index eb789f5..13ec0e6 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -589,7 +589,7 @@ static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr, #endif static struct mxc_i2c_bus mxc_i2c_buses[] = { -#if defined(CONFIG_LS102XA) || defined(CONFIG_VF610) || \ +#if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \ defined(CONFIG_FSL_LAYERSCAPE) { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG }, { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG }, diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 4231594..4f0a278 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -13,7 +13,7 @@ #include <asm/io.h> #include <linux/immap_qe.h> #include <fsl_qe.h> -#ifdef CONFIG_LS102XA +#ifdef CONFIG_ARCH_LS1021A #include <asm/arch/immap_ls102xa.h> #endif @@ -355,7 +355,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware) size_t length; const struct qe_header *hdr; #ifdef CONFIG_DEEP_SLEEP -#ifdef CONFIG_LS102XA +#ifdef CONFIG_ARCH_LS1021A struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; #else ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -494,7 +494,7 @@ int u_qe_upload_firmware(const struct qe_firmware *firmware) size_t length; const struct qe_header *hdr; #ifdef CONFIG_DEEP_SLEEP -#ifdef CONFIG_LS102XA +#ifdef CONFIG_ARCH_LS1021A struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; #else ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c index 6069c93..338ac08 100644 --- a/drivers/usb/common/fsl-errata.c +++ b/drivers/usb/common/fsl-errata.c @@ -204,7 +204,7 @@ bool has_erratum_a010151(void) case SVR_LS1043A: return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); #endif -#ifdef CONFIG_LS102XA +#ifdef CONFIG_ARCH_LS1021A case SOC_VER_LS1020: case SOC_VER_LS1021: case SOC_VER_LS1022: diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index d8bbc80..35d17b9 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -7,8 +7,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_LS102XA - #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR #define CONFIG_SYS_FSL_CLK diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index b349b36..62d9af4 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -7,8 +7,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_LS102XA - #define CONFIG_ARMV7_PSCI_1_0 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index fcf035b..8bd419e 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -7,8 +7,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_LS102XA - #define CONFIG_ARMV7_PSCI_1_0 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR diff --git a/include/fsl_errata.h b/include/fsl_errata.h index 8441f91..89051aa 100644 --- a/include/fsl_errata.h +++ b/include/fsl_errata.h @@ -10,7 +10,7 @@ #include <common.h> #if defined(CONFIG_PPC) #include <asm/processor.h> -#elif defined(CONFIG_LS102XA) +#elif defined(CONFIG_ARCH_LS1021A) #include <asm/arch-ls102xa/immap_ls102xa.h> #elif defined(CONFIG_FSL_LAYERSCAPE) #include <asm/arch/soc.h> @@ -66,7 +66,7 @@ static inline bool has_erratum_a008378(void) switch (soc) { -#ifdef CONFIG_LS102XA +#ifdef CONFIG_ARCH_LS1021A case SOC_VER_LS1020: case SOC_VER_LS1021: case SOC_VER_LS1022: diff --git a/include/linux/immap_qe.h b/include/linux/immap_qe.h index 6d1f88e..d952efa 100644 --- a/include/linux/immap_qe.h +++ b/include/linux/immap_qe.h @@ -24,7 +24,7 @@ #endif #endif -#ifdef CONFIG_LS102XA +#ifdef CONFIG_ARCH_LS1021A #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index e0dff30..bd54089 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -54,7 +54,7 @@ struct fsl_xhci { struct dwc3 *dwc3_reg; }; -#if defined(CONFIG_LS102XA) || defined(CONFIG_ARCH_LS1012A) +#if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_ARCH_LS1012A) #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 diff --git a/include/tsec.h b/include/tsec.h index fb27edf..e99a7fa 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -20,7 +20,7 @@ #ifndef CONFIG_DM_ETH -#ifdef CONFIG_LS102XA +#ifdef CONFIG_ARCH_LS1021A #define TSEC_SIZE 0x40000 #define TSEC_MDIO_OFFSET 0x40000 #else diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index 882aed4..8f3437a 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -159,7 +159,7 @@ #elif defined(CONFIG_MPC512X) #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR 0 -#elif defined(CONFIG_LS102XA) +#elif defined(CONFIG_ARCH_LS1021A) #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR 0 #endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 8a2bc6b..e35b819 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1698,7 +1698,6 @@ CONFIG_LPC_IO_BASE CONFIG_LPUART CONFIG_LPUART_32B_REG CONFIG_LQ038J7DH53 -CONFIG_LS102XA CONFIG_LS102XA_STREAM_ID CONFIG_LSCHLV2 CONFIG_LSXHL -- 2.7.4

1 1

[U-Boot] [PATCH 1/3] armv8: ls2080a: Drop macro CONFIG_LS2080A
by York Sun 18 Apr '17

18 Apr '17

Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 2 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 6 +++--- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 +- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 2 +- arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 +- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 +- arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +- arch/arm/include/asm/fsl_secure_boot.h | 4 ++-- configs/ls2080a_emu_defconfig | 2 +- configs/ls2080a_simu_defconfig | 2 +- configs/ls2080aqds_SECURE_BOOT_defconfig | 1 - configs/ls2080aqds_defconfig | 1 - configs/ls2080aqds_nand_defconfig | 2 +- configs/ls2080aqds_qspi_defconfig | 2 +- configs/ls2080ardb_SECURE_BOOT_defconfig | 1 - configs/ls2080ardb_defconfig | 1 - configs/ls2080ardb_nand_defconfig | 2 +- drivers/crypto/fsl/jr.c | 2 +- drivers/net/ldpaa_eth/Makefile | 2 +- include/linux/usb/xhci-fsl.h | 2 +- scripts/config_whitelist.txt | 1 - 21 files changed, 19 insertions(+), 24 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index c9ab93e..04354d7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -22,7 +22,7 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o endif endif -ifneq ($(CONFIG_LS2080A),) +ifneq ($(CONFIG_ARCH_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index cebbb0f..606403a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -91,7 +91,7 @@ static inline void early_mmu_setup(void) static void fix_pcie_mmu_map(void) { -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A unsigned int i; u32 svr, ver; struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -522,7 +522,7 @@ int timer_init(void) #ifdef CONFIG_FSL_LSCH3 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; #endif -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET; u32 svr_dev_id; #endif @@ -540,7 +540,7 @@ int timer_init(void) out_le32(cltbenr, 0xf); #endif -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A /* * In certain Layerscape SoCs, the clock for each core's * has an enable bit in the PMU Physical Core Time Base Enable diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index a2185f2..fa6b6e6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -76,7 +76,7 @@ ENTRY(lowlevel_init) #ifdef CONFIG_FSL_LSCH3 /* Set Wuo bit for RN-I 20 */ -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A ldr x0, =CCI_AUX_CONTROL_BASE(20) ldr x1, =0x00000010 bl ccn504_set_aux diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 73a8680..2434860 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -47,7 +47,7 @@ void board_init_f(ulong dummy) memset((void *)gd, 0, sizeof(gd_t)); board_early_init_f(); timer_init(); -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A env_init(); #endif get_clocks(); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index b5b08aa..898bd84 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -18,7 +18,7 @@ */ #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 #define CONFIG_SYS_PAGE_SIZE 0x10000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index bcf3e38..95c3e2f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -249,7 +249,7 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 70181c5..a8f9a50 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -9,7 +9,7 @@ #include <config.h> -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A enum srds_prtcl { /* * Nobody will check whether the device 'NONE' has been configured, diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index d98a1e8..6a21396 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -46,14 +46,14 @@ #endif -#if defined(CONFIG_LS1043A) || defined(CONFIG_LS2080A) +#if defined(CONFIG_LS1043A) || defined(CONFIG_ARCH_LS2080A) /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit * Similiarly for LS2080 */ #define CONFIG_ESBC_ADDR_64BIT #endif -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A #define CONFIG_EXTRA_ENV \ "setenv fdt_high 0xa0000000;" \ "setenv initrd_high 0xcfffffff;" \ diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig index edf7685..6211b6b 100644 --- a/configs/ls2080a_emu_defconfig +++ b/configs/ls2080a_emu_defconfig @@ -5,7 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="EMU,LS2080A" +CONFIG_SYS_EXTRA_OPTIONS="EMU" CONFIG_BOOTDELAY=10 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_CONSOLE is not set diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig index 5cc9316..b6f7709 100644 --- a/configs/ls2080a_simu_defconfig +++ b/configs/ls2080a_simu_defconfig @@ -5,7 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2080A" +CONFIG_SYS_EXTRA_OPTIONS="SIMU" CONFIG_BOOTDELAY=10 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_CONSOLE is not set diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index 6ab9703..45e5d87 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -7,7 +7,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="LS2080A" CONFIG_BOOTDELAY=10 CONFIG_CMD_GREPENV=y CONFIG_CMD_GPT=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index fb9a3e4..770dea0 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -7,7 +7,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="LS2080A" CONFIG_BOOTDELAY=10 CONFIG_CMD_GREPENV=y CONFIG_CMD_GPT=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 2a649c5..aa4f134 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -10,7 +10,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="NAND, LS2080A" +CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_ENV_SUPPORT=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index a81e7c6..6deb0ac 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -5,7 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT,LS2080A" +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 CONFIG_CMD_GREPENV=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 70baf0e..19c9db5 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -7,7 +7,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="LS2080A" CONFIG_BOOTDELAY=10 CONFIG_CMD_GREPENV=y CONFIG_CMD_GPT=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index a1e552d..e0cb7f8 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -7,7 +7,6 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="LS2080A" CONFIG_BOOTDELAY=10 CONFIG_CMD_GREPENV=y CONFIG_CMD_GPT=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 81987fe..cd57374 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -10,7 +10,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="NAND, LS2080A" +CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_BOOTDELAY=10 CONFIG_SPL=y CONFIG_SPL_ENV_SUPPORT=y diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 1b88229..2c1753d 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -586,7 +586,7 @@ int sec_init_idx(uint8_t sec_idx) * For AXI Read - Cacheable, Read allocate * Only For LS2080a, to solve CAAM coherency issues */ -#ifdef CONFIG_LS2080A +#ifdef CONFIG_ARCH_LS2080A mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT); mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT); #else diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile index 5587aa6..08675ec 100644 --- a/drivers/net/ldpaa_eth/Makefile +++ b/drivers/net/ldpaa_eth/Makefile @@ -6,4 +6,4 @@ obj-y += ldpaa_wriop.o obj-y += ldpaa_eth.o -obj-$(CONFIG_LS2080A) += ls2080a.o +obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index 1fa3161..23e5939 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -58,7 +58,7 @@ struct fsl_xhci { #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 -#elif defined(CONFIG_LS2080A) +#elif defined(CONFIG_ARCH_LS2080A) #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 668f238..0f39c65 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1809,7 +1809,6 @@ CONFIG_LQ038J7DH53 CONFIG_LS102XA CONFIG_LS102XA_STREAM_ID CONFIG_LS1043A -CONFIG_LS2080A CONFIG_LSCHLV2 CONFIG_LSXHL CONFIG_LUAN -- 2.7.4

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