March 2017 - U-Boot

[U-Boot] [PATCH 0/3] board: at91sam9g20ek/at91sam9260ek: convert to support DM and DT
by Wenyou Yang 03 Mar '17

03 Mar '17

The purpose of the patch set is to convert the board to support the Driver Model and the Device Tree. Wenyou Yang (3): ARM: dts: at91: add dts file for at91sam9g20/at91sam9260 board: at91sam9g20ek/at91sam9260ek: move config options to defconfig board: at91sam9260ek: clean up code arch/arm/dts/Makefile | 5 + arch/arm/dts/at91sam9260.dtsi | 136 +++++++-------- arch/arm/dts/at91sam9260ek.dts | 211 +++++++++++++++++++++++ arch/arm/dts/at91sam9g20.dtsi | 4 +- arch/arm/dts/at91sam9g20ek.dts | 29 ++++ arch/arm/dts/at91sam9g20ek_2mmc.dts | 56 +++++++ arch/arm/dts/at91sam9g20ek_common.dtsi | 223 +++++++++++++++++++++++++ board/atmel/at91sam9260ek/at91sam9260ek.c | 73 -------- configs/at91sam9260ek_dataflash_cs0_defconfig | 15 +- configs/at91sam9260ek_dataflash_cs1_defconfig | 15 +- configs/at91sam9260ek_nandflash_defconfig | 15 +- configs/at91sam9g20ek_2mmc_defconfig | 16 +- configs/at91sam9g20ek_2mmc_nandflash_defconfig | 16 +- configs/at91sam9g20ek_dataflash_cs0_defconfig | 15 +- configs/at91sam9g20ek_dataflash_cs1_defconfig | 15 +- configs/at91sam9g20ek_nandflash_defconfig | 16 +- include/configs/at91sam9260ek.h | 9 - 17 files changed, 705 insertions(+), 164 deletions(-) create mode 100644 arch/arm/dts/at91sam9260ek.dts create mode 100644 arch/arm/dts/at91sam9g20ek.dts create mode 100644 arch/arm/dts/at91sam9g20ek_2mmc.dts create mode 100644 arch/arm/dts/at91sam9g20ek_common.dtsi -- 2.11.0

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[U-Boot] [PATCH 0/2] clk: at91: enhance the peripheral clock
by Wenyou Yang 03 Mar '17

03 Mar '17

The purpose of the patch set is to enhance the peripheral clock to support both at9sam9x5's and at91rm9200's peripheral clock, and align the clk-master's compatibles with kernel's. Wenyou Yang (2): clk: at91: enhance the peripheral clock clk: at91: align clk-master's compatibles with kernel's drivers/clk/at91/clk-master.c | 1 + drivers/clk/at91/clk-peripheral.c | 19 ++++++++++++++++--- 2 files changed, 17 insertions(+), 3 deletions(-) -- 2.11.0

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[U-Boot] x86: SecureBoot: Bay Trail
by Markus Valentin 03 Mar '17

03 Mar '17

Hi, i'm implementing Secure Boot with U-Boot on a Intel Atom E3800 Series (Bay Trail) based Plattform. I did manage to get the first boot stage (Initial Boot Block) verified by the Trusted Execution Engine, next i need to verify the "ramstage" as they call it. Intel provides a manual on how to enable Secure Boot with coreboot in this manual they extract the "ramstage" from the coreboot.rom file via cbfs. How can i get the equivalent for the coreboot-ramstage from U-Boot? Best regards Markus

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Re: [U-Boot] [PATCH] drivers: net: phy: atheros: apply the previous register setting for AR8031 to fix the voltage peak issue
by Ken.Lin 03 Mar '17

03 Mar '17

> -----Original Message----- > From: Sekhar Nori [mailto:nsekhar@ti.com] > Sent: Monday, February 6, 2017 12:53 AM > To: Ken.Lin; ken <Ken Lin>; sbabic(a)denx.de > Cc: u-boot(a)lists.denx.de; martin.donnelly(a)ge.com; Peter.Chiang; Peter.Stretz; > akshay.bhat(a)timesys.com; joe.hershberger(a)ni.com; > albert.u.uboot(a)aribaud.net > Subject: Re: [PATCH] drivers: net: phy: atheros: apply the previous register > setting for AR8031 to fix the voltage peak issue > > On Saturday 04 February 2017 12:26 AM, Ken.Lin wrote: > > > > > >> -----Original Message----- > >> From: Sekhar Nori [mailto:nsekhar@ti.com] > >> Sent: Thursday, February 2, 2017 9:44 PM > >> To: ken <Ken Lin>; sbabic(a)denx.de > >> Cc: u-boot(a)lists.denx.de; martin.donnelly(a)ge.com; Ken.Lin; > >> Peter.Chiang; Peter.Stretz; akshay.bhat(a)timesys.com; > >> joe.hershberger(a)ni.com; albert.u.uboot(a)aribaud.net > >> Subject: Re: [PATCH] drivers: net: phy: atheros: apply the previous > >> register setting for AR8031 to fix the voltage peak issue > >> > >> On Friday 03 February 2017 02:53 AM, ken <Ken Lin> wrote: > >>> Apply the previous setting for the reserved bits in SetDes Test and > >>> System Mode Control register to avoid the voltage peak issue while > >>> we do the IEEE PHY comformance test > >>> > >>> Signed-off-by: ken Lin <ken.lin(a)advantech.com> Tested on Advantech > >>> DMS-BA16 board > >>> Tested-by: Ken Lin <ken.lin(a)advantech.com> > >>> --- > >>> drivers/net/phy/atheros.c | 6 ++++++ > >>> 1 file changed, 6 insertions(+) > >>> > >>> diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c > >>> index b34cdd3d87..82fe228604 100644 > >>> --- a/drivers/net/phy/atheros.c > >>> +++ b/drivers/net/phy/atheros.c > >>> @@ -28,6 +28,8 @@ static int ar8021_config(struct phy_device > >>> *phydev) > >>> > >>> static int ar8031_config(struct phy_device *phydev) { > >>> + int regval; > >>> + > >>> if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || > >>> phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { > >>> phy_write(phydev, MDIO_DEVAD_NONE, > >> AR803x_PHY_DEBUG_ADDR_REG, @@ > >>> -44,6 +46,10 @@ static int ar8031_config(struct phy_device *phydev) > >>> AR803x_RGMII_RX_CLK_DLY); > >>> } > >>> > >>> + phy_write(phydev, MDIO_DEVAD_NONE, > >> AR803x_PHY_DEBUG_ADDR_REG, AR803x_DEBUG_REG_5); > >>> + regval = phy_read(phydev, MDIO_DEVAD_NONE, > >> AR803x_PHY_DEBUG_DATA_REG); > >>> + phy_write(phydev, MDIO_DEVAD_NONE, > >> AR803x_PHY_DEBUG_DATA_REG, > >>> + regval | 0x3C47); > >> > >> I thought I had responded to this, but probably the mail did not go through. > >> > >> What you have defeats the purpose of reading back the register. The > >> idea of reading back was to avoid using any hardcoded reset state of the > register. > >> > >> Also, your patch does nothing to the existing code writing to > >> AR803x_DEBUG_REG_5. > >> So you have two unneeded writes now. Does the following work for you > >> (not compiled or tested). > >> > > > > The register setting would turn out to be 0x3D47 on our project boards and > our signal measurement results show the patch (v2 version, > https://patchwork.ozlabs.org/patch/723461/)) could fix the voltage peak issue. > > The proposed solution is to follow the implementation in previous commits, > which include the reserved bits settings in SerDes Test and System Mode Control > register. > > So what does the register setting turn out to be with my patch below ? > > What are the "previous commits" you refer to ? > When I dig around the commit history, I could find the related config change info for AR8031. The original setting for the reserved bits in SerDes Test and System Mode Control register are not 0 (0x3C47). commit d584c68ce0f5bf2f430ccfb2ba00bd506206fb91 Author: Fabio Estevam <fabio.estevam(a)nxp.com> Date: Tue Jan 5 17:02:52 2016 -0200 phy: atheros: Use ar8035_config for AR8031 Commit 08ad9b068afb88 (" ar8031: modify the config func of ar8031 to ar8021_config") selected 'ar8021_config' as the configuration function for AR8031. The correct would be to use 'ar8035_config' instead as AR8031/AR8035 have the same programming model and even share the same phy driver in the linux kernel: drivers/net/phy/at803x.c. Tested on a mx6qsabresd and wandboard, which now can work without any PHY setup code in the board files. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> Acked-by: Joe Hershberger <joe.hershberger(a)ni.com> diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index d509e30..ba57b1a 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -51,7 +51,7 @@ static struct phy_driver AR8031_driver = { .uid = 0x4dd074, .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, - .config = ar8021_config, + .config = ar8035_config, .startup = genphy_startup, .shutdown = genphy_shutdown, }; commit ce412b79e72557702185443501478646a938b5fe Author: Mugunthan V N <mugunthanvnm(a)ti.com> Date: Thu Oct 13 19:33:36 2016 +0530 drivers: net: phy: atheros: add separate config for AR8031 In the current driver implementation, config() callback is common for AR8035 and AR8031 phy. In config() callback, driver tries to configure MMD Access Control Register and MMD Access Address Data Register unconditionally for both phy versions which leads to auto negotiation failure in AM335x EVMsk second port which uses AR8031 Giga bit RGMII phy. Fixing this by adding separate config for AR8031 phy. Reviewed-by: Sekhar Nori <nsekhar(a)ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm(a)ti.com> Acked-by: Joe Hershberger <joe.hershberger(a)ni.com> diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 694a338..b34cdd3 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -8,6 +8,15 @@ */ #include <phy.h> +#define AR803x_PHY_DEBUG_ADDR_REG 0x1d +#define AR803x_PHY_DEBUG_DATA_REG 0x1e + +#define AR803x_DEBUG_REG_5 0x5 +#define AR803x_RGMII_TX_CLK_DLY 0x100 + +#define AR803x_DEBUG_REG_0 0x0 +#define AR803x_RGMII_RX_CLK_DLY 0x8000 + static int ar8021_config(struct phy_device *phydev) { phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); @@ -17,6 +26,32 @@ static int ar8021_config(struct phy_device *phydev) return 0; } +static int ar8031_config(struct phy_device *phydev) +{ + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, + AR803x_DEBUG_REG_5); + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, + AR803x_RGMII_TX_CLK_DLY); + } + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, + AR803x_DEBUG_REG_0); + phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, + AR803x_RGMII_RX_CLK_DLY); + } + + phydev->supported = phydev->drv->features; + + genphy_config_aneg(phydev); + genphy_restart_aneg(phydev); + + return 0; +} + When I checked the NXP u-boot codebase (git://git.freescale.com/imx/uboot-imx.git, branch l5.1.1_2.1.0-ga), It seems NXP worked with the PHY vendors and set the reserved bits to 0x3D47. commit 9082eeac5de1335d663016668c9b89c290f5c79b Author: Andy Fleming <afleming(a)freescale.com> Date: Thu Apr 7 21:56:05 2011 -0500 phylib: Add a bunch of PHY drivers from tsec The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> Acked-by: Detlev Zundel <dzu(a)denx.de> +/* + * Atheros PHY drivers + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Copyright 2011 Freescale Semiconductor, Inc. + * author Andy Fleming + * + */ +#include <phy.h> + +static int ar8021_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); + + return 0; +} + +struct phy_driver AR8021_driver = { + .name = "AR8021", + .uid = 0x4dd040, + .mask = 0xfffff0, + .features = PHY_GBIT_FEATURES, + .config = ar8021_config, + .startup = genphy_startup, + .shutdown = genphy_shutdown, +}; + +int phy_atheros_init(void) +{ + phy_register(&AR8021_driver); + + return 0; +} commit 626ee1e32eeb4fc89e0f406d6067ed6e71d8302f Author: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> Date: Thu Aug 8 16:33:35 2013 +0800 phylib: update atheros ar803x phy As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the common driver. Currently AR8031_driver didn't work for AR8033, hence updated it to have it work on AR8031/AR8033. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 0f2dfd6..7a1453f 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -48,11 +48,11 @@ static struct phy_driver AR8021_driver = { }; static struct phy_driver AR8031_driver = { - .name = "AR8031", + .name = "AR8031/AR8033", .uid = 0x4dd074, .mask = 0xfffff0, .features = PHY_GBIT_FEATURES, - .config = genphy_config, + .config = ar8021_config, .startup = genphy_startup, .shutdown = genphy_shutdown, }; > >> Thanks, > >> Sekhar > >> > >> ---8<--- > >> diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c > >> index > >> b34cdd3d87dc..aff9eb3d18c6 100644 > >> --- a/drivers/net/phy/atheros.c > >> +++ b/drivers/net/phy/atheros.c > >> @@ -28,12 +28,16 @@ static int ar8021_config(struct phy_device > >> *phydev) > >> > >> static int ar8031_config(struct phy_device *phydev) { > >> + int regval; > >> + > >> if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || > >> phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { > >> phy_write(phydev, MDIO_DEVAD_NONE, > AR803x_PHY_DEBUG_ADDR_REG, > >> AR803x_DEBUG_REG_5); > >> + regval = phy_read(phydev, MDIO_DEVAD_NONE, > >> + AR803x_PHY_DEBUG_DATA_REG); > >> phy_write(phydev, MDIO_DEVAD_NONE, > AR803x_PHY_DEBUG_DATA_REG, > >> - AR803x_RGMII_TX_CLK_DLY); > >> + regval | AR803x_RGMII_TX_CLK_DLY); > >> } > >> > >> if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || > > Thanks, > Sekhar > > > -- > This message has been scanned for viruses and dangerous content by > MailScanner, and is believed to be clean. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.

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[U-Boot] TODO list for u-boot
by Sebastian Panceac 02 Mar '17

02 Mar '17

Hi everyone, I was looking through the TO DO list of u-boot, because I want to contribute to the project. This list here seems to be outdated http://www.denx.de/wiki/U-Boot/Tasks. For example I checked the "Set Environment to Default Values" task from the list, and it's seems to be implemented now. The "Group Environment Variables" TODO doesn't seem to be implemented. Is this feature still wanted? Is there any updated list of TODOs? Thank you!

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[U-Boot] [PATCH][v2] armv8:ls2080a: Reorganise NAND_BOOT code in config flag
by Santan Kumar 02 Mar '17

02 Mar '17

Add CONFIG_NAND_BOOT config flag to organise NAND_BOOT specific code in config flag like -nand-boot specfic errata errata_rcw_src() -CONFIG_SYS_NAND_U_BOOT_DST,etc Signed-off-by: Santan Kumar <santan.kumar(a)nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini(a)nxp.com> --- Changes for v2: Rebased to latest codebase Incorporated York's comments to defined CONFIG_NAND_BOOT in new line arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +- configs/ls2080aqds_nand_defconfig | 1 + configs/ls2080ardb_nand_defconfig | 1 + include/configs/ls2080a_common.h | 5 +++++ include/configs/ls2080aqds.h | 4 +++- 5 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 9489f85..fa68baf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -134,7 +134,7 @@ void erratum_a009635(void) static void erratum_rcw_src(void) { -#if defined(CONFIG_SPL) +#if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT) u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE; u32 val; diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 8910938..bc0b9b1 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -12,6 +12,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_NAND_BOOT=y CONFIG_SYS_EXTRA_OPTIONS="NAND, LS2080A" CONFIG_BOOTDELAY=10 CONFIG_SPL=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 8223111..d449190 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -12,6 +12,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_NAND_BOOT=y CONFIG_SYS_EXTRA_OPTIONS="NAND, LS2080A" CONFIG_BOOTDELAY=10 CONFIG_SPL=y diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 4173d9a..ae72939 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -216,6 +216,7 @@ unsigned long long get_qixis_addr(void); #define CONFIG_PANIC_HANG /* do not reset board on panic */ +#ifdef CONFIG_SPL #define CONFIG_SPL_BSS_START_ADDR 0x80100000 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 #define CONFIG_SPL_FRAMEWORK @@ -225,11 +226,15 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_TEXT_BASE 0x1800a000 +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST +#endif #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 #define CONFIG_SYS_MONITOR_LEN (640 * 1024) +#endif #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 08d1586..93f6b51 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -197,7 +197,8 @@ unsigned long get_board_ddr_clk(void); FTIM2_GPCM_TWP(0x3E)) #define CONFIG_SYS_CS3_FTIM3 0x0 -#if defined(CONFIG_SPL) && defined(CONFIG_NAND) +#if defined(CONFIG_SPL) +#if defined(CONFIG_NAND_BOOT) #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR @@ -233,6 +234,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SPL_PAD_TO 0x20000 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) +#endif #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -- 1.9.1

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[U-Boot] Someone expert in lvds timings ?
by far5893 02 Mar '17

02 Mar '17

I'm trying to generate u-boot timings for http://www.notebook-lcd.ru/pdf/QD17EL07_REV_11.pdf page 11. i try (x:640,y:1024,depth:24,pclk_khz:54000,le:45,ri:200,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0) LCD panel timing details does someone have experience in writing such timings ? The panel is dual channel but i create an Y cable to feed two channels from only one supported by u-boot(but i try one channel only cable). My scope is to validate my setup for try to add dual lvds channel support on u-boot on A10(cubieboard1). Thanks

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[U-Boot] [PATCH] powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram
by Ruchika Gupta 02 Mar '17

02 Mar '17

Fir E6500 cores, L2 cache has been used as init_ram. L1 cache is a write through cache on E6500.If lines are not locked in both L1 and L2 caches, crashes are observed during secure boot. This patch locks/unlocks both L1 as well as L2 cache to prevent the crash. Signed-off-by: Ruchika Gupta <ruchika.gupta(a)nxp.com> --- arch/powerpc/cpu/mpc85xx/start.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index c3e1234..b9a4cb5 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1145,8 +1145,9 @@ switch_as: li r0,0 1: dcbz r0,r3 -#ifdef CONFIG_E6500 /* Lock/unlock L2 cache instead of L1 */ +#ifdef CONFIG_E6500 /* Lock/unlock L2 cache long with L1 */ dcbtls 2, r0, r3 + dcbtls 0, r0, r3 #else dcbtls 0, r0, r3 #endif @@ -1790,8 +1791,9 @@ unlock_ram_in_cache: slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) mtctr r4 1: dcbi r0,r3 -#ifdef CONFIG_E6500 /* lock/unlock L2 cache instead of L1 */ +#ifdef CONFIG_E6500 /* lock/unlock L2 cache long with L1 */ dcblc 2, r0, r3 + dcblc 0, r0, r3 #else dcblc r0,r3 #endif -- 1.9.1

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[U-Boot] [PATCH v2 6/8] dts: socfpga: Add trigger-address property to QSPI device
by Rush, Jason A. 02 Mar '17

02 Mar '17

Add the 'cdns,trigger-address' property to the cadence QSPI device node for Altera SoC devices. Signed-off-by: Jason A. Rush <jason.rush(a)gd-ms.com> --- Changed in v2: - renamed trigger-base to trigger-address arch/arm/dts/socfpga.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 8588221e57..ac26d05722 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -646,6 +646,7 @@ num-cs = <4>; fifo-depth = <128>; sram-size = <128>; + trigger-address = <0x00000000>; bus-num = <2>; status = "disabled"; }; -- 2.11.0

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[U-Boot] [PATCH v4 08/11] armv8: layerscape: Fix the sequence of changing MMU table
by York Sun 01 Mar '17

01 Mar '17

This patch follows the break-before-make process when making changes to MMU table. MMU is disabled before changing TTBR to avoid any potential race condition. Signed-off-by: York Sun <york.sun(a)nxp.com> --- Changes in v4: Revert the change of C bit in v3 patch. Changes in v3: Instead of flushing d-cache, following the break-before-make process to change MMU table. Changes in v2: None arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 800ad62..afb6cd1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -181,21 +181,14 @@ static inline void final_mmu_setup(void) setup_pgtables(); gd->arch.tlb_addr = tlb_addr_save; - /* flush new MMU table */ - flush_dcache_range(gd->arch.tlb_addr, - gd->arch.tlb_addr + gd->arch.tlb_size); + /* Disable cache and MMU */ + dcache_disable(); /* TLBs are invalidated */ + invalidate_icache_all(); /* point TTBR to the new table */ set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), MEMORY_ATTRIBUTES); - /* - * EL3 MMU is already enabled, just need to invalidate TLB to load the - * new table. The new table is compatible with the current table, if - * MMU somehow walks through the new table before invalidation TLB, - * it still works. So we don't need to turn off MMU here. - * When EL2 MMU table is created by calling this function, MMU needs - * to be enabled. - */ + set_sctlr(get_sctlr() | CR_M); } -- 2.7.4

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