January 2017 - U-Boot

[U-Boot] [PATCH] arm: dts: imx53-cx9020: fix packetloss on fec_mxc
by linux-kernel-dev＠beckhoff.com 30 Jan '17

30 Jan '17

From: Patrick Bruenn <p.bruenn(a)beckhoff.com> The pinmuxing for i.MX53 FEC ethernet copied from <kernel>/arch/arm/boot/dts/imx53-qsb-common.dtsi (at least until v4.9) was bad. It is different from the manual pinmuxing in <u-boot>/board/freescale/mx53loco/mx53loco.c which was used in cx9020 implementation previously before mainlining into u-boot. It seems the bug in imx53-qsb kernel device tree is hidden for so long, because it was never used, by the kernel driver. Signed-off-by: Patrick Bruenn <p.bruenn(a)beckhoff.com> --- arch/arm/dts/imx53-cx9020.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/dts/imx53-cx9020.dts b/arch/arm/dts/imx53-cx9020.dts index 9610301..c928e72 100644 --- a/arch/arm/dts/imx53-cx9020.dts +++ b/arch/arm/dts/imx53-cx9020.dts @@ -114,16 +114,16 @@ MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 - MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 + MX53_PAD_FEC_MDC__FEC_MDC 0x4 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec -- 2.7.4

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[U-Boot] [PATCH v8 0/7] arm: socfpga: update default u-boot environment
by Dalon Westergreen 30 Jan '17

30 Jan '17

From: Dalon Westergreen <dalon.westergreen(a)intel.com> These patches update the boot and os partition numbers in the default uboot environment for a number of socfpga boards. Per request, common environment configurations have been moved to a shared header. Changed in v8: Revert CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION to be 1 per request Changed in v7: Changed the bootloader partition to 3 to match the default layout for socfpga. commit 61520ac4d5545cc8d2e1792092e46ab8043d5f36 changed this to 1 which broke a number of socfpga kits. The default sdcard layour places partition 3 at the start of the fpga at +1MB. The partition is of type 0xA2. This is followed by partition 1 (FAT), and partition 2 (RootFS). Partition 1 should be the FAT partition or windows appears not to recognize the sdcard. Changed in v6: Changed CONFIG_SYS_MMCSD_FS_BOOT_PARTITION to be 1 for SPL_FAT and 2 for SPL_EXT support. I believe this is the original intent for whomever changed CONFIG_SYS_MMCSD_FS_BOOT_PARTITION to be 2. This allows us to keep the original sdcard layout and support FAT and EXT loading of the u-boot image Changes in v5: - Fixed sockit linux devicetree name - Changed default socfpga.dtb to match board name - sr1500 -> socfpga_cyclone5_sr1500.dtb - de1 -> socfpga_cyclone5_de1_soc.dtb Changes in v4: - Removed extraneous define in socfpga_common.h and only use CONFIG_EXTRA_ENV_SETTINGS for common uboot environment Changes in v3: - Corrected error in common default environment Dalon Westergreen (7): arm: socfpga: add env settings to common header arm: socfpga: update de0 nano default environment arm: socfpga: update cyclone5 socdk default environment arm: socfpga: update arria5 socdk default environment arm: socfpga: Update DE1 environment arm: socfpga: Update SoCKit environment arm: socfpga: Update sr1500 environment configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 3 +-- configs/socfpga_de1_soc_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + include/configs/socfpga_arria5_socdk.h | 25 ------------------------ include/configs/socfpga_common.h | 33 +++++++++++++++++++++++++++++++- include/configs/socfpga_cyclone5_socdk.h | 25 ------------------------ include/configs/socfpga_de0_nano_soc.h | 19 +----------------- include/configs/socfpga_de1_soc.h | 19 +----------------- include/configs/socfpga_sockit.h | 27 +------------------------- include/configs/socfpga_sr1500.h | 25 ------------------------ 13 files changed, 41 insertions(+), 140 deletions(-) -- 2.7.4

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[U-Boot] [PATCH v2] SPL: add support to boot from a partition type
by Dalon Westergreen 30 Jan '17

30 Jan '17

From: Dalon Westergreen <dalon.westergreen(a)intel.com> the socfpga bootrom supports mmc booting from either a raw image starting at 0x0, or from a partition of type 0xa2. This patch adds support for locating the boot image in the first type 0xa2 partition found. Signed-off-by: Dalon Westergreen <dalon.westergreen(a)intel.com> --- common/spl/Kconfig | 17 +++++++++++++++++ common/spl/spl_mmc.c | 13 +++++++++++++ disk/part_dos.c | 1 + include/part.h | 1 + 4 files changed, 32 insertions(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index b1aa148..a0430ec 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -97,6 +97,23 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR Address on the MMC to load U-Boot from, when the MMC is being used in raw mode. Units: MMC sectors (1 sector = 512 bytes). +config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE + bool "MMC raw mode: by partition type" + depends on SPL + default y if ARCH_SOCFPGA + help + Use partition type for specifying U-Boot partition on MMC/SD in + raw mode. U-Boot will be loaded from the first partition of this + type to be found. + +config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE + hex "Partition Type on the MMC to load U-Boot from" + depends on SPL && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE + default 0xa2 if ARCH_SOCFPGA + help + Partition Type on the MMC to load U-Boot from, when the MMC is being + used in raw mode. + config TPL bool depends on SPL && SUPPORT_TPL diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 0cd355c..cce9584 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -157,6 +157,19 @@ static int mmc_load_image_raw_partition(struct spl_image_info *spl_image, disk_partition_t info; int err; +#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE + if ( partition == -1 ) { + /* Only support MBR so DOS_ENTRY_NUMBERS */ + for (partition = 1; partition <= DOS_ENTRY_NUMBERS; partition++) { + err = part_get_info(mmc_get_blk_desc(mmc), partition, &info); + if(err) + continue; + if(info.sys_ind == CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE) + break; + } + } +#endif + err = part_get_info(mmc_get_blk_desc(mmc), partition, &info); if (err) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT diff --git a/disk/part_dos.c b/disk/part_dos.c index ed78334..f485f11 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -217,6 +217,7 @@ static int part_get_info_extended(struct blk_desc *dev_desc, #ifdef CONFIG_PARTITION_UUIDS sprintf(info->uuid, "%08x-%02x", disksig, part_num); #endif + info->sys_ind = pt->sys_ind; return 0; } diff --git a/include/part.h b/include/part.h index 0979005..a58b687 100644 --- a/include/part.h +++ b/include/part.h @@ -59,6 +59,7 @@ typedef struct disk_partition { #ifdef CONFIG_PARTITION_TYPE_GUID char type_guid[37]; /* type GUID as string, if exists */ #endif + uchar sys_ind; /* partition type */ } disk_partition_t; /* Misc _get_dev functions */ -- 2.7.4

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[U-Boot] [PATCH v2 0/8] Add workaround for USB PHY errata
by Suresh Gupta 30 Jan '17

30 Jan '17

The patch set implement USB PHY errata workaround which are required for LS series of freescale platforms which have Synopsis UTMI PHY Suresh Gupta (8): armv8: Add workaround for USB erratum A-009008 armv8: Add workaround for USB erratum A-009798 armv8: Add workaround for USB erratum A-008997 armv8: Add workaround for USB erratum A-009007 armv7: Add workaround for USB erratum A-009008 armv7: Add workaround for USB erratum A-009798 armv7: Add workaround for USB erratum A-008997 armv7: Add workaround for USB erratum A-009007 arch/arm/cpu/armv7/ls102xa/Kconfig | 16 +++ arch/arm/cpu/armv7/ls102xa/soc.c | 51 +++++++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 24 +++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 117 +++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 20 ++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 13 +++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 19 ++++ 7 files changed, 260 insertions(+) -- 1.9.3

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[U-Boot] [PATCH v2 8/8] armv7: Add workaround for USB erratum A-009007
by Suresh Gupta 30 Jan '17

30 Jan '17

From: Suresh Gupta <suresh.gupta(a)freescale.com> Rx Compliance tests may fail intermittently at high jitter frequencies using default register values Changes identified in test setup makes the Rx compliance test pass Signed-off-by: Sriram Dash <sriram.dash(a)nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat(a)nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta(a)nxp.com> --- Changes in v2: Clean up the code after Scott comments, Previously in v1, we was defining the pointer as u32, then casting it to u8, and then passing it to a 16-bit accessor. arch/arm/cpu/armv7/ls102xa/Kconfig | 4 ++++ arch/arm/cpu/armv7/ls102xa/soc.c | 12 ++++++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 5 +++++ 3 files changed, 21 insertions(+) diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index a68674f..b7d785e 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -8,6 +8,7 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997 + select SYS_FSL_ERRATUM_A009007 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE if SYS_FSL_DDR @@ -54,6 +55,9 @@ config SYS_FSL_ERRATUM_A009798 config SYS_FSL_ERRATUM_A008997 bool "Workaround for USB PHY erratum A008997" +config SYS_FSL_ERRATUM_A009007 + bool "Workaround for USB PHY erratum A009007" + config SYS_FSL_SRDS_1 bool diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 3d6cc5f..edb64d5 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -94,6 +94,17 @@ static void erratum_a008997(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ } +static void erratum_a009007(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009007 + void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE; + writew(USB_PHY_RX_EQ_VAL_1, usb_phy + USB_PHY_RX_OVRD_IN_HI); + writew(USB_PHY_RX_EQ_VAL_2, usb_phy + USB_PHY_RX_OVRD_IN_HI); + writew(USB_PHY_RX_EQ_VAL_3, usb_phy + USB_PHY_RX_OVRD_IN_HI); + writew(USB_PHY_RX_EQ_VAL_4, usb_phy + USB_PHY_RX_OVRD_IN_HI); +#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */ +} + void s_init(void) { } @@ -184,6 +195,7 @@ int arch_soc_init(void) erratum_a009008(); erratum_a009798(); erratum_a008997(); + erratum_a009007(); return 0; } diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index c0e4372..9c4c926 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -182,10 +182,15 @@ struct ccsr_gur { #define USB_PHY_MPLL_OVRD_IN_HI 0x0024 #define USB_PHY_LEVEL_OVRD_IN 0x002a #define USB_PHY_TX_OVRD_IN_HI 0x2002 +#define USB_PHY_RX_OVRD_IN_HI 0x200c #define USB_PHY_TX_OVRD_DRV_LO_VAL 0x784C #define USB_PHY_MPLL_OVRD_IN_HI_VAL 0x0080 #define USB_PHY_LEVEL_OVRD_IN_VAL 0xA9A5 #define USB_PHY_TX_OVRD_IN_HI_VAL 0x0003 +#define USB_PHY_RX_EQ_VAL_1 0x0000 +#define USB_PHY_RX_EQ_VAL_2 0x8000 +#define USB_PHY_RX_EQ_VAL_3 0x8004 +#define USB_PHY_RX_EQ_VAL_4 0x800C /* Supplemental Configuration Unit */ struct ccsr_scfg { -- 1.9.3

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[U-Boot] [PATCH v2 2/8] armv8: Add workaround for USB erratum A-009798
by Suresh Gupta 30 Jan '17

30 Jan '17

From: Suresh Gupta <suresh.gupta(a)freescale.com> The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receiver Compliance test failure for a 100mV threshold. The changes shift the threshold from ~100mV towards ~130mV resulting in passing of USB High Speed Receiver Sensitivity Compliance test Signed-off-by: Sriram Dash <sriram.dash(a)nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat(a)nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta(a)nxp.com> --- Changes in v2: None arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 ++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 21 +++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 + .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + 4 files changed, 29 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 666a3d1..10daaa2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -19,6 +19,7 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A009798 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 @@ -35,6 +36,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A010539 select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A009798 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 @@ -61,6 +63,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A009008 + select SYS_FSL_ERRATUM_A009798 config FSL_LSCH2 bool @@ -108,6 +111,9 @@ config SYS_FSL_ERRATUM_A010539 config SYS_FSL_ERRATUM_A009008 bool "Workaround for USB PHY erratum A009008" +config SYS_FSL_ERRATUM_A009798 + bool "Workaround for USB PHY erratum A009798" + config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape" default 4 if ARCH_LS1043A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 951ccba..910f345 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -75,6 +75,25 @@ static void erratum_a009008(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ } +static void erratum_a009798(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009798 +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A) + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4); + scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE); + val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4); + scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE); + val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4); + scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE); +#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4); + scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE); +#endif +#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ +} + #if defined(CONFIG_FSL_LSCH3) /* * This erratum requires setting a value to eddrtqcr1 to @@ -218,6 +237,7 @@ void fsl_lsch3_early_init_f(void) erratum_a008514(); erratum_a008336(); erratum_a009008(); + erratum_a009798(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. @@ -395,6 +415,7 @@ void fsl_lsch2_early_init_f(void) erratum_a009660(); erratum_a010539(); erratum_a009008(); + erratum_a009798(); } #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index fe37bc1..ca4a31fe 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -341,6 +341,7 @@ struct ccsr_gur { #define SCFG_USB3PRM1CR_USB2 0x07C #define SCFG_USB3PRM1CR_USB3 0x088 #define USB_TXVREFTUNE 0x9 +#define USB_SQRXTUNE 0xFC7FFFFF #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 9aad471..d726256 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -138,6 +138,7 @@ #define SCFG_USB3PRM1CR 0x000 #define SCFG_USB3PRM1CR_INIT 0x27672b2a #define USB_TXVREFTUNE 0x9 +#define USB_SQRXTUNE 0xFC7FFFFF #define SCFG_QSPICLKCTLR 0x10 #define TP_ITYP_AV 0x00000001 /* Initiator available */ -- 1.9.3

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[U-Boot] HAB and fuse reading
by Vincent 30 Jan '17

30 Jan '17

Hi ! I'm wondering why the is_hab_enabled function (see arch/arm/imx-common/hab.c) is reading the fuses rather than the OCOTP shadow registers ? During my attempts at secure boot I realized two things: - by default, if secure boot is not enabled, the HAB rom will block any authenticate code - if the secure boot fuse is not burnt, but the shadow register is written by software before calling the HAB entry point, authenticate works fine. Since the ROM seems to read the shadow register rather than the fuse, why is u-boot doing differently ? Best regards, Vincent

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[U-Boot] [PATCH 2/2][v4] armv8: ls1012a: Add support of PPA
by Prabhakar Kushwaha 30 Jan '17

30 Jan '17

The PPA implements PSCI which requires for power managment. Added support of PPA for LS1012AQDS, LS1012ARDB and LS1012AFRDM. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini(a)nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- Changes for v2: Enabled FSL_LS_PPA Changes for v3: Rebased and updated as per latest PPA code Changes for v4: Sending as it is board/freescale/ls1012afrdm/ls1012afrdm.c | 6 ++++++ board/freescale/ls1012aqds/ls1012aqds.c | 7 +++++++ board/freescale/ls1012ardb/ls1012ardb.c | 6 ++++++ configs/ls1012afrdm_qspi_defconfig | 1 + configs/ls1012aqds_qspi_defconfig | 1 + configs/ls1012ardb_qspi_defconfig | 1 + 6 files changed, 22 insertions(+) diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index c2432c3..789cae2 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -9,6 +9,9 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> +#ifdef CONFIG_FSL_LS_PPA +#include <asm/arch/ppa.h> +#endif #include <asm/arch/soc.h> #include <hwconfig.h> #include <environment.h> @@ -74,6 +77,9 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif return 0; } diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index bdd9529..4281790 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -10,6 +10,9 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> +#ifdef CONFIG_FSL_LS_PPA +#include <asm/arch/ppa.h> +#endif #include <asm/arch/fdt.h> #include <asm/arch/soc.h> #include <ahci.h> @@ -113,6 +116,10 @@ int board_init(void) #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif + +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif return 0; } diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 2dece02..e3a8a76 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -9,6 +9,9 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> +#ifdef CONFIG_FSL_LS_PPA +#include <asm/arch/ppa.h> +#endif #include <asm/arch/soc.h> #include <hwconfig.h> #include <ahci.h> @@ -110,6 +113,9 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif return 0; } diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index 8932650..8b42962 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm" # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_FSL_LS_PPA=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 0bb40d0..d400276 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_FSL_LS_PPA=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index 6fed6c7..06c4243 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_FSL_LS_PPA=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" -- 2.7.4

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[U-Boot] [PATCH 2/2][v3] armv8: ls1012a: Add support of PPA
by Prabhakar Kushwaha 30 Jan '17

30 Jan '17

The PPA implements PSCI which requires for power managment. Added support of PPA for LS1012AQDS, LS1012ARDB and LS1012AFRDM. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini(a)nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- Changes for v2: Enabled FSL_LS_PPA Changes for v3: Rebased and updated as per latest PPA code board/freescale/ls1012afrdm/ls1012afrdm.c | 6 ++++++ board/freescale/ls1012aqds/ls1012aqds.c | 7 +++++++ board/freescale/ls1012ardb/ls1012ardb.c | 6 ++++++ configs/ls1012afrdm_qspi_defconfig | 1 + configs/ls1012aqds_qspi_defconfig | 1 + configs/ls1012ardb_qspi_defconfig | 1 + 6 files changed, 22 insertions(+) diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index c2432c3..789cae2 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -9,6 +9,9 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> +#ifdef CONFIG_FSL_LS_PPA +#include <asm/arch/ppa.h> +#endif #include <asm/arch/soc.h> #include <hwconfig.h> #include <environment.h> @@ -74,6 +77,9 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif return 0; } diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 704019e..507bdaf 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -10,6 +10,9 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> +#ifdef CONFIG_FSL_LS_PPA +#include <asm/arch/ppa.h> +#endif #include <asm/arch/fdt.h> #include <asm/arch/soc.h> #include <ahci.h> @@ -114,6 +117,10 @@ int board_init(void) #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif + +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif return 0; } diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 2dece02..e3a8a76 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -9,6 +9,9 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> +#ifdef CONFIG_FSL_LS_PPA +#include <asm/arch/ppa.h> +#endif #include <asm/arch/soc.h> #include <hwconfig.h> #include <ahci.h> @@ -110,6 +113,9 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif return 0; } diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index 8932650..8b42962 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm" # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_FSL_LS_PPA=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 0bb40d0..d400276 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_FSL_LS_PPA=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index 6fed6c7..06c4243 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_FSL_LS_PPA=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" -- 2.7.4

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[U-Boot] [PATCH 5/5][v6] arch: powerpc: update the eLBC IP input clock
by Prabhakar Kushwaha 30 Jan '17

30 Jan '17

eLBC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock ratio register (LCRR) used in current implementation governs eLBC IP output cloc. Update sys_info->freq_localbus to represent eLBC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- Changes for v5: Added first time in patch Changes for v6: Updated subject description README | 3 +++ arch/powerpc/cpu/mpc85xx/Kconfig | 14 ++++++++++++++ arch/powerpc/cpu/mpc85xx/speed.c | 28 ++-------------------------- arch/powerpc/cpu/mpc86xx/speed.c | 14 +------------- 4 files changed, 20 insertions(+), 39 deletions(-) diff --git a/README b/README index 9fda381..b27e757 100644 --- a/README +++ b/README @@ -507,6 +507,9 @@ The following options need to be configured: CONFIG_SYS_FSL_IFC_CLK_DIV Defines divider of platform clock(clock input to IFC controller). + CONFIG_SYS_FSL_LBC_CLK_DIV + Defines divider of platform clock(clock input to eLBC controller). + CONFIG_SYS_FSL_PBL_PBI It enables addition of RCW (Power on reset configuration) in built image. Please refer doc/README.pblimage for more details diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 765d328..7442495 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1307,6 +1307,20 @@ config SYS_FSL_IFC_CLK_DIV Defines divider of platform clock(clock input to IFC controller). +config SYS_FSL_LBC_CLK_DIV + int "Divider of platform clock" + depends on FSL_ELBC + default 2 if ARCH_P2041 || \ + ARCH_P3041 || \ + ARCH_P4080 || \ + ARCH_P5020 || \ + ARCH_P5040 + default 1 + + help + Defines divider of platform clock(clock input to + eLBC controller). + source "board/freescale/b4860qds/Kconfig" source "board/freescale/bsc9131rdb/Kconfig" source "board/freescale/bsc9132qds/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index adba092..cb8281e 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -607,32 +607,8 @@ void get_sys_info(sys_info_t *sys_info) #endif /* CONFIG_FSL_CORENET */ #if defined(CONFIG_FSL_LBC) - uint lcrr_div; -#if defined(CONFIG_SYS_LBC_LCRR) - /* We will program LCRR to this value later */ - lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; -#else - lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; -#endif - if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { -#if defined(CONFIG_FSL_CORENET) - /* If this is corenet based SoC, bit-representation - * for four times the clock divider values. - */ - lcrr_div *= 4; -#elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \ - !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_ARCH_MPC8560) - /* - * Yes, the entire PQ38 family use the same - * bit-representation for twice the clock divider values. - */ - lcrr_div *= 2; -#endif - sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div; - } else { - /* In case anyone cares what the unknown value is */ - sys_info->freq_localbus = lcrr_div; - } + sys_info->freq_localbus = sys_info->freq_systembus / + CONFIG_SYS_FSL_LBC_CLK_DIV; #endif #if defined(CONFIG_FSL_IFC) diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c index 05f23db..b9e2100 100644 --- a/arch/powerpc/cpu/mpc86xx/speed.c +++ b/arch/powerpc/cpu/mpc86xx/speed.c @@ -78,19 +78,7 @@ void get_sys_info(sys_info_t *sys_info) break; } -#if defined(CONFIG_SYS_LBC_LCRR) - /* We will program LCRR to this value later */ - lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; -#else - lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV; -#endif - if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { - sys_info->freq_localbus = sys_info->freq_systembus - / (lcrr_div * 2); - } else { - /* In case anyone cares what the unknown value is */ - sys_info->freq_localbus = lcrr_div; - } + sys_info->freq_localbus = sys_info->freq_systembus; } -- 2.7.4

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