September 2016 - U-Boot

[U-Boot] [PATCH v1] ARM: at91/dt: sama5d2: Fix the warning from dtc
by Wenyou Yang 28 Oct '16

28 Oct '16

Fix the warning from dtc like, ---8<---- Warning (unit_address_vs_reg): Node /ahb/apb/pmc@f0014000/periph64ck/sdmmc0_hclk has a reg or ranges property, but no unit name --->8---- Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> --- arch/arm/dts/sama5d2.dtsi | 140 +++++++++++++++++++++++----------------------- 1 file changed, 70 insertions(+), 70 deletions(-) diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index 19feb66..a881d9e 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -79,7 +79,7 @@ #clock-cells = <0>; }; - plla: pllack { + plla: pllack@0 { compatible = "atmel,sama5d3-clk-pll"; #clock-cells = <0>; clocks = <&main>; @@ -146,17 +146,17 @@ interrupt-parent = <&pmc>; clocks = <&main>, <&plladiv>, <&utmi>, <&mck>; - prog0: prog0 { + prog0: prog@0 { #clock-cells = <0>; reg = <0>; }; - prog1: prog1 { + prog1: prog@1 { #clock-cells = <0>; reg = <1>; }; - prog2: prog2 { + prog2: prog@2 { #clock-cells = <0>; reg = <2>; }; @@ -167,49 +167,49 @@ #address-cells = <1>; #size-cells = <0>; - ddrck: ddrck { + ddrck: ddrck@2 { #clock-cells = <0>; reg = <2>; clocks = <&mck>; }; - lcdck: lcdck { + lcdck: lcdck@3 { #clock-cells = <0>; reg = <3>; clocks = <&mck>; }; - uhpck: uhpck { + uhpck: uhpck@6 { #clock-cells = <0>; reg = <6>; clocks = <&usb>; }; - udpck: udpck { + udpck: udpck@7 { #clock-cells = <0>; reg = <7>; clocks = <&usb>; }; - pck0: pck0 { + pck0: pck0@8 { #clock-cells = <0>; reg = <8>; clocks = <&prog0>; }; - pck1: pck1 { + pck1: pck1@9 { #clock-cells = <0>; reg = <9>; clocks = <&prog1>; }; - pck2: pck2 { + pck2: pck2@10 { #clock-cells = <0>; reg = <10>; clocks = <&prog2>; }; - iscck: iscck { + iscck: iscck@18 { #clock-cells = <0>; reg = <18>; clocks = <&mck>; @@ -222,203 +222,203 @@ #size-cells = <0>; clocks = <&h32ck>; - macb0_clk: macb0_clk { + macb0_clk: macb0_clk@5 { #clock-cells = <0>; reg = <5>; atmel,clk-output-range = <0 83000000>; }; - tdes_clk: tdes_clk { + tdes_clk: tdes_clk@11 { #clock-cells = <0>; reg = <11>; atmel,clk-output-range = <0 83000000>; }; - matrix1_clk: matrix1_clk { + matrix1_clk: matrix1_clk@14 { #clock-cells = <0>; reg = <14>; }; - hsmc_clk: hsmc_clk { + hsmc_clk: hsmc_clk@17 { #clock-cells = <0>; reg = <17>; }; - pioA_clk: pioA_clk { + pioA_clk: pioA_clk@18 { #clock-cells = <0>; reg = <18>; atmel,clk-output-range = <0 83000000>; }; - flx0_clk: flx0_clk { + flx0_clk: flx0_clk@19 { #clock-cells = <0>; reg = <19>; atmel,clk-output-range = <0 83000000>; }; - flx1_clk: flx1_clk { + flx1_clk: flx1_clk@20 { #clock-cells = <0>; reg = <20>; atmel,clk-output-range = <0 83000000>; }; - flx2_clk: flx2_clk { + flx2_clk: flx2_clk@21 { #clock-cells = <0>; reg = <21>; atmel,clk-output-range = <0 83000000>; }; - flx3_clk: flx3_clk { + flx3_clk: flx3_clk@22 { #clock-cells = <0>; reg = <22>; atmel,clk-output-range = <0 83000000>; }; - flx4_clk: flx4_clk { + flx4_clk: flx4_clk@23 { #clock-cells = <0>; reg = <23>; atmel,clk-output-range = <0 83000000>; }; - uart0_clk: uart0_clk { + uart0_clk: uart0_clk@24 { #clock-cells = <0>; reg = <24>; atmel,clk-output-range = <0 83000000>; }; - uart1_clk: uart1_clk { + uart1_clk: uart1_clk@25 { #clock-cells = <0>; reg = <25>; atmel,clk-output-range = <0 83000000>; }; - uart2_clk: uart2_clk { + uart2_clk: uart2_clk@26 { #clock-cells = <0>; reg = <26>; atmel,clk-output-range = <0 83000000>; }; - uart3_clk: uart3_clk { + uart3_clk: uart3_clk@27 { #clock-cells = <0>; reg = <27>; atmel,clk-output-range = <0 83000000>; }; - uart4_clk: uart4_clk { + uart4_clk: uart4_clk@28 { #clock-cells = <0>; reg = <28>; atmel,clk-output-range = <0 83000000>; }; - twi0_clk: twi0_clk { + twi0_clk: twi0_clk@29 { reg = <29>; #clock-cells = <0>; atmel,clk-output-range = <0 83000000>; }; - twi1_clk: twi1_clk { + twi1_clk: twi1_clk@30 { #clock-cells = <0>; reg = <30>; atmel,clk-output-range = <0 83000000>; }; - spi0_clk: spi0_clk { + spi0_clk: spi0_clk@33 { #clock-cells = <0>; reg = <33>; atmel,clk-output-range = <0 83000000>; }; - spi1_clk: spi1_clk { + spi1_clk: spi1_clk@34 { #clock-cells = <0>; reg = <34>; atmel,clk-output-range = <0 83000000>; }; - tcb0_clk: tcb0_clk { + tcb0_clk: tcb0_clk@35 { #clock-cells = <0>; reg = <35>; atmel,clk-output-range = <0 83000000>; }; - tcb1_clk: tcb1_clk { + tcb1_clk: tcb1_clk@36 { #clock-cells = <0>; reg = <36>; atmel,clk-output-range = <0 83000000>; }; - pwm_clk: pwm_clk { + pwm_clk: pwm_clk@38 { #clock-cells = <0>; reg = <38>; atmel,clk-output-range = <0 83000000>; }; - adc_clk: adc_clk { + adc_clk: adc_clk@40 { #clock-cells = <0>; reg = <40>; atmel,clk-output-range = <0 83000000>; }; - uhphs_clk: uhphs_clk { + uhphs_clk: uhphs_clk@41 { #clock-cells = <0>; reg = <41>; atmel,clk-output-range = <0 83000000>; }; - udphs_clk: udphs_clk { + udphs_clk: udphs_clk@42 { #clock-cells = <0>; reg = <42>; atmel,clk-output-range = <0 83000000>; }; - ssc0_clk: ssc0_clk { + ssc0_clk: ssc0_clk@43 { #clock-cells = <0>; reg = <43>; atmel,clk-output-range = <0 83000000>; }; - ssc1_clk: ssc1_clk { + ssc1_clk: ssc1_clk@44 { #clock-cells = <0>; reg = <44>; atmel,clk-output-range = <0 83000000>; }; - trng_clk: trng_clk { + trng_clk: trng_clk@47 { #clock-cells = <0>; reg = <47>; atmel,clk-output-range = <0 83000000>; }; - pdmic_clk: pdmic_clk { + pdmic_clk: pdmic_clk@48 { #clock-cells = <0>; reg = <48>; atmel,clk-output-range = <0 83000000>; }; - i2s0_clk: i2s0_clk { + i2s0_clk: i2s0_clk@54 { #clock-cells = <0>; reg = <54>; atmel,clk-output-range = <0 83000000>; }; - i2s1_clk: i2s1_clk { + i2s1_clk: i2s1_clk@55 { #clock-cells = <0>; reg = <55>; atmel,clk-output-range = <0 83000000>; }; - can0_clk: can0_clk { + can0_clk: can0_clk@56 { #clock-cells = <0>; reg = <56>; atmel,clk-output-range = <0 83000000>; }; - can1_clk: can1_clk { + can1_clk: can1_clk@57 { #clock-cells = <0>; reg = <57>; atmel,clk-output-range = <0 83000000>; }; - classd_clk: classd_clk { + classd_clk: classd_clk@59 { #clock-cells = <0>; reg = <59>; atmel,clk-output-range = <0 83000000>; @@ -431,67 +431,67 @@ #size-cells = <0>; clocks = <&mck>; - dma0_clk: dma0_clk { + dma0_clk: dma0_clk@6 { #clock-cells = <0>; reg = <6>; }; - dma1_clk: dma1_clk { + dma1_clk: dma1_clk@7 { #clock-cells = <0>; reg = <7>; }; - aes_clk: aes_clk { + aes_clk: aes_clk@9 { #clock-cells = <0>; reg = <9>; }; - aesb_clk: aesb_clk { + aesb_clk: aesb_clk@10 { #clock-cells = <0>; reg = <10>; }; - sha_clk: sha_clk { + sha_clk: sha_clk@12 { #clock-cells = <0>; reg = <12>; }; - mpddr_clk: mpddr_clk { + mpddr_clk: mpddr_clk@13 { #clock-cells = <0>; reg = <13>; }; - matrix0_clk: matrix0_clk { + matrix0_clk: matrix0_clk@15 { #clock-cells = <0>; reg = <15>; }; - sdmmc0_hclk: sdmmc0_hclk { + sdmmc0_hclk: sdmmc0_hclk@31 { #clock-cells = <0>; reg = <31>; }; - sdmmc1_hclk: sdmmc1_hclk { + sdmmc1_hclk: sdmmc1_hclk@32 { #clock-cells = <0>; reg = <32>; }; - lcdc_clk: lcdc_clk { + lcdc_clk: lcdc_clk@45 { #clock-cells = <0>; reg = <45>; }; - isc_clk: isc_clk { + isc_clk: isc_clk@46 { #clock-cells = <0>; reg = <46>; }; - qspi0_clk: qspi0_clk { + qspi0_clk: qspi0_clk@52 { #clock-cells = <0>; reg = <52>; }; - qspi1_clk: qspi1_clk { + qspi1_clk: qspi1_clk@53 { #clock-cells = <0>; reg = <53>; }; @@ -504,62 +504,62 @@ interrupt-parent = <&pmc>; clocks = <&main>, <&plla>, <&utmi>, <&mck>; - sdmmc0_gclk: sdmmc0_gclk { + sdmmc0_gclk: sdmmc0_gclk@31 { #clock-cells = <0>; reg = <31>; }; - sdmmc1_gclk: sdmmc1_gclk { + sdmmc1_gclk: sdmmc1_gclk@32 { #clock-cells = <0>; reg = <32>; }; - tcb0_gclk: tcb0_gclk { + tcb0_gclk: tcb0_gclk@35 { #clock-cells = <0>; reg = <35>; atmel,clk-output-range = <0 83000000>; }; - tcb1_gclk: tcb1_gclk { + tcb1_gclk: tcb1_gclk@36 { #clock-cells = <0>; reg = <36>; atmel,clk-output-range = <0 83000000>; }; - pwm_gclk: pwm_gclk { + pwm_gclk: pwm_gclk@38 { #clock-cells = <0>; reg = <38>; atmel,clk-output-range = <0 83000000>; }; - pdmic_gclk: pdmic_gclk { + pdmic_gclk: pdmic_gclk@48 { #clock-cells = <0>; reg = <48>; }; - i2s0_gclk: i2s0_gclk { + i2s0_gclk: i2s0_gclk@54 { #clock-cells = <0>; reg = <54>; }; - i2s1_gclk: i2s1_gclk { + i2s1_gclk: i2s1_gclk@55 { #clock-cells = <0>; reg = <55>; }; - can0_gclk: can0_gclk { + can0_gclk: can0_gclk@56 { #clock-cells = <0>; reg = <56>; atmel,clk-output-range = <0 80000000>; }; - can1_gclk: can1_gclk { + can1_gclk: can1_gclk@57 { #clock-cells = <0>; reg = <57>; atmel,clk-output-range = <0 80000000>; }; - classd_gclk: classd_gclk { + classd_gclk: classd_gclk@59 { #clock-cells = <0>; reg = <59>; atmel,clk-output-range = <0 100000000>; -- 2.7.4

3 2

[U-Boot] [PATCH v2] clk: at91: Fix at91-pmc and at91-sckc's class ID
by Wenyou Yang 28 Oct '16

28 Oct '16

The at91-pmc and at91-sckc aren't the clock providers, change their class ID from UCLASS_CLK to UCLASS_SIMPLE_BUS, they also don't need to bind the child nodes explicitly, the .post_bind callback of simple_bus uclass will do it for them. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> Acked-by: Stephen Warren <swarren(a)nvidia.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: - Collect the tags. drivers/clk/at91/pmc.c | 10 ++-------- drivers/clk/at91/sckc.c | 17 +++++------------ 2 files changed, 7 insertions(+), 20 deletions(-) diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c index a08d7e8..76ff387 100644 --- a/drivers/clk/at91/pmc.c +++ b/drivers/clk/at91/pmc.c @@ -14,21 +14,15 @@ DECLARE_GLOBAL_DATA_PTR; -static int at91_pmc_bind(struct udevice *dev) -{ - return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); -} - static const struct udevice_id at91_pmc_match[] = { { .compatible = "atmel,sama5d2-pmc" }, {} }; U_BOOT_DRIVER(at91_pmc) = { - .name = "at91-pmc-core", - .id = UCLASS_CLK, + .name = "at91-pmc", + .id = UCLASS_SIMPLE_BUS, .of_match = at91_pmc_match, - .bind = at91_pmc_bind, }; int at91_pmc_core_probe(struct udevice *dev) diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c index b207611..6035e20 100644 --- a/drivers/clk/at91/sckc.c +++ b/drivers/clk/at91/sckc.c @@ -6,25 +6,18 @@ */ #include <common.h> -#include <clk-uclass.h> #include <dm/device.h> #include <dm/root.h> DECLARE_GLOBAL_DATA_PTR; -static int at91_sckc_clk_bind(struct udevice *dev) -{ - return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); -} - -static const struct udevice_id at91_sckc_clk_match[] = { +static const struct udevice_id at91_sckc_match[] = { { .compatible = "atmel,at91sam9x5-sckc" }, {} }; -U_BOOT_DRIVER(at91_sckc_clk) = { - .name = "at91_sckc_clk", - .id = UCLASS_CLK, - .of_match = at91_sckc_clk_match, - .bind = at91_sckc_clk_bind, +U_BOOT_DRIVER(at91_sckc) = { + .name = "at91-sckc", + .id = UCLASS_SIMPLE_BUS, + .of_match = at91_sckc_match, }; -- 2.7.4

2 1

[U-Boot] [PATCH] AT91: Correct misspelling of "redundent" in partition names
by Robert P. J. Day 28 Oct '16

28 Oct '16

Signed-off-by: Robert P. J. Day <rpjday(a)crashcourse.ca> --- given that this misspelling is being used for partition names, i won't treat it as a normal typo, so sending a separate patch just for this. diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 051186d..3e55d13 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -75,7 +75,7 @@ #define CONFIG_BOOTARGS \ "console=ttyS0,115200 earlyprintk " \ "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ - "256K(env),256k(env_redundent),256k(spare)," \ + "256K(env),256k(env_redundant),256k(spare)," \ "512k(dtb),6M(kernel)ro,-(rootfs) " \ "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index a383de6..0d24814 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -152,7 +152,7 @@ #define CONFIG_BOOTARGS \ "console=ttyS0,115200 earlyprintk " \ "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ - "256K(env),256k(env_redundent),256k(spare)," \ + "256K(env),256k(env_redundant),256k(spare)," \ "512k(dtb),6M(kernel)ro,-(rootfs) " \ "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

3 2

[U-Boot] [PATCH 0/6] at91: at91sam9g15 improvements
by Heiko Schocher 28 Oct '16

28 Oct '16

This series add some missing things for an at91sam9g15 board, which gets not mainlined, but there are common fixes, which are posted with this patchserie. 2 important things: - enable icache for AT91 based boards speeds up them a lot, for example reading 8MiB from an SPI NOR flash into RAM takes with icache off ~15 seconds with icache enabled only ~5 seconds. gurnard board defines a board specific enable_caches() function which enables dcache .. with acomment that this breaks Ethernet MAC ... I removed this board specific function, and dcache enable functions should be added in arch/arm/mach-at91/arm926ejs/cache.c - SPL clock fix, posted as RFC, as it may breaks other boards. If so, we may make clock settings in SPL board configurable through a weak function? buildman finds no new errors/warnings with the patches from this patchseries applied. Heiko Schocher (6): arm: at91: mpddrc: add missing MPDDRC_MD defines ARM: at91: clock: correct PRES offset for at91sam9x5 arm, at91: add icache support arm, at91: add some missing fields in PIO struct at91: add function to set IO drive [RFC] at91: SPL clock fix for AT91SAM9G15 based boards. arch/arm/mach-at91/arm926ejs/Makefile | 1 + arch/arm/mach-at91/arm926ejs/cache.c | 29 ++++++++++++++++++++++++++ arch/arm/mach-at91/arm926ejs/clock.c | 6 ++++++ arch/arm/mach-at91/include/mach/at91_pio.h | 11 +++++++++- arch/arm/mach-at91/include/mach/atmel_mpddrc.h | 3 +++ arch/arm/mach-at91/include/mach/gpio.h | 2 ++ arch/arm/mach-at91/spl_at91.c | 13 +++++++++--- board/bluewater/gurnard/gurnard.c | 6 ------ drivers/gpio/at91_gpio.c | 29 ++++++++++++++++++++++++++ 9 files changed, 90 insertions(+), 10 deletions(-) create mode 100644 arch/arm/mach-at91/arm926ejs/cache.c -- 2.5.5

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[U-Boot] [PATCH] mmc: Tinification of the mmc code
by Marek Vasut 28 Oct '16

28 Oct '16

Add new configuration option CONFIG_MMC_TINY which strips away all memory allocation within the MMC code and code for handling multiple cards. This allows extremely space-constrained SPL code use the MMC framework. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> Cc: Simon Glass <sjg(a)chromium.org> --- common/spl/spl_mmc.c | 4 ++++ drivers/mmc/Makefile | 2 ++ drivers/mmc/mmc.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++- include/mmc.h | 1 + 4 files changed, 65 insertions(+), 1 deletion(-) diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index ae42221..51f0f24 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -300,7 +300,11 @@ int spl_mmc_load_image(u32 boot_device) if (part == 7) part = 0; +#ifdef CONFIG_MMC_TINY + err = mmc_switch_part(mmc, part); +#else err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part); +#endif if (err) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT puts("spl: mmc partition switch failed\n"); diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 3da4817..4d986cb 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -10,8 +10,10 @@ obj-$(CONFIG_GENERIC_MMC) += mmc-uclass.o endif ifndef CONFIG_BLK +ifndef CONFIG_MMC_TINY obj-$(CONFIG_GENERIC_MMC) += mmc_legacy.o endif +endif obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o obj-$(CONFIG_ATMEL_SDHCI) += atmel_sdhci.o diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index d687345..1f240ed 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -21,6 +21,29 @@ #include <div64.h> #include "mmc_private.h" +#if defined(CONFIG_MMC_TINY) +static struct mmc mmc_static; +struct mmc *find_mmc_device(int dev_num) +{ + return &mmc_static; +} + +void mmc_do_preinit(void) +{ + struct mmc *m = &mmc_static; +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT + mmc_set_preinit(m, 1); +#endif + if (m->preinit) + mmc_start_init(m); +} + +struct blk_desc *mmc_get_blk_desc(struct mmc *mmc) +{ + return &mmc->block_dev; +} +#endif + __weak int board_mmc_getwp(struct mmc *mmc) { return -1; @@ -238,7 +261,11 @@ static ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, if (!mmc) return 0; +#ifdef CONFIG_MMC_TINY + err = mmc_switch_part(mmc, block_dev->hwpart); +#else err = blk_dselect_hwpart(block_dev, block_dev->hwpart); +#endif if (err < 0) return 0; @@ -568,7 +595,7 @@ static int mmc_set_capacity(struct mmc *mmc, int part_num) return 0; } -static int mmc_switch_part(struct mmc *mmc, unsigned int part_num) +int mmc_switch_part(struct mmc *mmc, unsigned int part_num) { int ret; @@ -1585,6 +1612,34 @@ int mmc_unbind(struct udevice *dev) return 0; } +#elif defined(CONFIG_MMC_TINY) +static struct mmc mmc_static = { + .dsr_imp = 0, + .dsr = 0xffffffff, + .block_dev = { + .if_type = IF_TYPE_MMC, + .removable = 1, + .devnum = 0, + .block_read = mmc_bread, + .block_write = mmc_bwrite, + .block_erase = mmc_berase, + .part_type = 0, + }, +}; + +struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) +{ + struct mmc *mmc = &mmc_static; + + mmc->cfg = cfg; + mmc->priv = priv; + + return mmc; +} + +void mmc_destroy(struct mmc *mmc) +{ +} #else struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) { @@ -1834,8 +1889,10 @@ int mmc_initialize(bd_t *bis) initialized = 1; #ifndef CONFIG_BLK +#ifndef CONFIG_MMC_TINY mmc_list_init(); #endif +#endif ret = mmc_probe(bis); if (ret) return ret; diff --git a/include/mmc.h b/include/mmc.h index a5c6573..08a59c2 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -444,6 +444,7 @@ struct mmc *find_mmc_device(int dev_num); int mmc_set_dev(int dev_num); void print_mmc_devices(char separator); int get_mmc_num(void); +int mmc_switch_part(struct mmc *mmc, unsigned int part_num); int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf, enum mmc_hwpart_conf_mode mode); int mmc_getcd(struct mmc *mmc); -- 2.7.0

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[U-Boot] [PATCH 2/2] armv8: ls1046aqds: add lpuart support
by shh.xie＠gmail.com 27 Oct '16

27 Oct '16

From: Shaohui Xie <Shaohui.Xie(a)nxp.com> LPUART0 is used by default, and it's using platform clock, if a different clock is preferred, user can define CONFIG_LPUART_CLK. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)nxp.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-ls1046a-qds-lpuart.dts | 16 ++++++++++ arch/arm/dts/fsl-ls1046a-qds.dtsi | 4 +++ arch/arm/dts/fsl-ls1046a.dtsi | 54 +++++++++++++++++++++++++++++++++ board/freescale/ls1046aqds/ls1046aqds.c | 21 +++++++++++++ configs/ls1046aqds_lpuart_defconfig | 29 ++++++++++++++++++ include/configs/ls1046aqds.h | 8 +++++ 7 files changed, 133 insertions(+) create mode 100644 arch/arm/dts/fsl-ls1046a-qds-lpuart.dts create mode 100644 configs/ls1046aqds_lpuart_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 715e9bd..4a7d53b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -144,6 +144,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ fsl-ls1046a-qds-duart.dtb \ + fsl-ls1046a-qds-lpuart.dtb \ fsl-ls1046a-rdb.dtb \ fsl-ls1012a-qds.dtb \ fsl-ls1012a-rdb.dtb \ diff --git a/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts new file mode 100644 index 0000000..21243d0 --- /dev/null +++ b/arch/arm/dts/fsl-ls1046a-qds-lpuart.dts @@ -0,0 +1,16 @@ +/* + * Device Tree file for Freescale Layerscape-1046A family SoC. + * + * Copyright (C) 2016, Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "fsl-ls1046a-qds.dtsi" + +/ { + chosen { + stdout-path = &lpuart0; + }; +}; diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi index c512293..a49ca08 100644 --- a/arch/arm/dts/fsl-ls1046a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi @@ -75,3 +75,7 @@ &duart1 { status = "okay"; }; + +&lpuart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 87dd997..359a9d1 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -151,6 +151,60 @@ clocks = <&clockgen 4 0>; }; + lpuart0: serial@2950000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2950000 0x0 0x1000>; + interrupts = <0 48 0x4>; + clocks = <&clockgen 4 0>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart1: serial@2960000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2960000 0x0 0x1000>; + interrupts = <0 49 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@2970000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2970000 0x0 0x1000>; + interrupts = <0 50 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart3: serial@2980000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2980000 0x0 0x1000>; + interrupts = <0 51 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial@2990000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2990000 0x0 0x1000>; + interrupts = <0 52 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@29a0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x29a0000 0x0 0x1000>; + interrupts = <0 53 0x4>; + clocks = <&clockgen 4 1>; + clock-names = "ipg"; + status = "disabled"; + }; + qspi: quadspi@1550000 { compatible = "fsl,vf610-qspi"; #address-cells = <1>; diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 8c18538..96d929d 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -120,6 +120,16 @@ unsigned long get_board_ddr_clk(void) return 66666666; } +#ifdef CONFIG_LPUART +u32 get_lpuart_clk(void) +{ +#ifdef CONFIG_LPUART_CLK + return CONFIG_LPUART_CLK; +#endif + return gd->bus_clk; +} +#endif + int select_i2c_ch_pca9547(u8 ch) { int ret; @@ -157,6 +167,9 @@ int board_early_init_f(void) struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; u32 usb_pwrfault; #endif +#ifdef CONFIG_LPUART + u8 uart; +#endif #ifdef CONFIG_SYS_I2C_EARLY_INIT i2c_early_init_f(); @@ -175,6 +188,14 @@ int board_early_init_f(void) out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); #endif +#ifdef CONFIG_LPUART + /* We use lpuart0 as system console */ + uart = QIXIS_READ(brdcfg[14]); + uart &= ~CFG_UART_MUX_MASK; + uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; + QIXIS_WRITE(brdcfg[14], uart); +#endif + return 0; } diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig new file mode 100644 index 0000000..8e5b45d --- /dev/null +++ b/configs/ls1046aqds_lpuart_defconfig @@ -0,0 +1,29 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1046AQDS=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-lpuart" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART" +CONFIG_BOOTDELAY=10 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_FSL_DSPI=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 2e5c2f1..bc71770 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -132,6 +132,14 @@ unsigned long get_board_ddr_clk(void); #endif #endif +/* LPUART */ +#ifdef CONFIG_LPUART +#define CONFIG_LPUART_32B_REG +#define CFG_UART_MUX_MASK 0x6 +#define CFG_UART_MUX_SHIFT 1 +#define CFG_LPUART_EN 0x2 +#endif + /* SATA */ #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v3 0/4] armv8/fsl-layerscape: add dwc3 gadget driver support
by Rajat Srivastava 26 Oct '16

26 Oct '16

From: Rajesh Bhagat <rajesh.bhagat(a)nxp.com> Adds support for dwc3 gadget driver for ARM v8 platform of layerscape series. Currently this patch has been tested for LS1043A Rajat Srivastava (3): usb: dwc3: Add helper functions to enable snooping and burst settings armv8/fsl-layerscape: add dwc3 gadget driver support armv8/fsl-layerscape: enable dwc3 gadget driver support Rajesh Bhagat (1): usb: ums: support multiple controllers using controller_index arch/arm/cpu/armv8/fsl-layerscape/soc.c | 93 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++ cmd/usb_mass_storage.c | 2 +- drivers/usb/dwc3/core.c | 45 +++++++++++ drivers/usb/dwc3/core.h | 7 ++ drivers/usb/gadget/f_mass_storage.c | 11 ++- include/configs/ls1043aqds.h | 15 ++++ include/usb_mass_storage.h | 2 +- 8 files changed, 177 insertions(+), 4 deletions(-) -- 2.6.2.198.g614a2ac

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[U-Boot] [PATCH] power: regulator: Add limits checking while setting voltage and current
by Keerthy 26 Oct '16

26 Oct '16

Currently the specific set ops functions are directly called without any check for voltage/current limits for a regulator. Check for them and proceed. Signed-off-by: Keerthy <j-keerthy(a)ti.com> --- drivers/power/regulator/regulator-uclass.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 4434e36..089455e 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -41,6 +41,11 @@ int regulator_get_value(struct udevice *dev) int regulator_set_value(struct udevice *dev, int uV) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + if (uV < uc_pdata->min_uV || uV > uc_pdata->max_uV) + return -EINVAL; if (!ops || !ops->set_value) return -ENOSYS; @@ -61,6 +66,11 @@ int regulator_get_current(struct udevice *dev) int regulator_set_current(struct udevice *dev, int uA) { const struct dm_regulator_ops *ops = dev_get_driver_ops(dev); + struct dm_regulator_uclass_platdata *uc_pdata; + + uc_pdata = dev_get_uclass_platdata(dev); + if (uA < uc_pdata->min_uA || uA > uc_pdata->max_uA) + return -EINVAL; if (!ops || !ops->set_current) return -ENOSYS; -- 1.9.1

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[U-Boot] [PATCH v3 0/3]spi: Add ZynqMP QSPI driver support
by Siva Durga Prasad Paladugu 26 Oct '16

26 Oct '16

This series adds the qspi driver support for zynqmp Also sent a patch for not setting quad enable bit in the series as zynqmp qspi series wont work for micron devices with out that patch. Siva Durga Prasad Paladugu (3): spi: spi_flash: Dont set quad enable for micron in all cases spi: zynqmp_qspi: Add QSPI driver support for ZynqMP spi: zynqmp_qspi: Add qspi driver support for ZynqMP boards configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 4 + configs/xilinx_zynqmp_zcu102_defconfig | 4 + configs/xilinx_zynqmp_zcu102_revB_defconfig | 4 + drivers/mtd/spi/spi_flash.c | 13 +- drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/zynqmp_qspi.c | 705 +++++++++++++++++++++++ include/spi.h | 2 +- 8 files changed, 740 insertions(+), 2 deletions(-) create mode 100644 drivers/spi/zynqmp_qspi.c -- 2.7.4

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[U-Boot] [PATCH 1/2] dt: net: add DWC EQoS binding
by Stephen Warren 21 Oct '16

21 Oct '16

From: Stephen Warren <swarren(a)nvidia.com> The Synopsys DWC EQoS is a configurable Ethernet MAC/DMA IP block which supports multiple options for bus type, clocking and reset structure, and feature list. This patch imports the binding from the Linux kernel, including my V3 patch to extend the binding to cover the Tegra186, which is applied for next-20160912. So far, my changes have been acked by Lars Persson, the original author of the binding. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- .../net/snps,dwc-qos-ethernet.txt | 166 +++++++++++++++++++++ 1 file changed, 166 insertions(+) create mode 100644 doc/device-tree-bindings/net/snps,dwc-qos-ethernet.txt diff --git a/doc/device-tree-bindings/net/snps,dwc-qos-ethernet.txt b/doc/device-tree-bindings/net/snps,dwc-qos-ethernet.txt new file mode 100644 index 000000000000..d93f71ce8346 --- /dev/null +++ b/doc/device-tree-bindings/net/snps,dwc-qos-ethernet.txt @@ -0,0 +1,166 @@ +* Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC) + +This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service) +IP block. The IP supports multiple options for bus type, clocking and reset +structure, and feature list. Consequently, a number of properties and list +entries in properties are marked as optional, or only required in specific HW +configurations. + +Required properties: +- compatible: One of: + - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10" + Represents the IP core when integrated into the Axis ARTPEC-6 SoC. + - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10" + Represents the IP core when integrated into the NVIDIA Tegra186 SoC. + - "snps,dwc-qos-ethernet-4.10" + This combination is deprecated. It should be treated as equivalent to + "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be + compatible with earlier revisions of this binding. +- reg: Address and length of the register set for the device +- clocks: Phandle and clock specifiers for each entry in clock-names, in the + same order. See ../clock/clock-bindings.txt. +- clock-names: May contain any/all of the following depending on the IP + configuration, in any order: + - "tx" + The EQOS transmit path clock. The HW signal name is clk_tx_i. + In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX + path. In other configurations, other clocks (such as tx_125, rmii) may + drive the PHY TX path. + - "rx" + The EQOS receive path clock. The HW signal name is clk_rx_i. + In some configurations (e.g. GMII/RGMII), this clock is derived from the + PHY's RX clock output. In other configurations, other clocks (such as + rx_125, rmii) may drive the EQOS RX path. + In cases where the PHY clock is directly fed into the EQOS receive path + without intervening logic, the DT need not represent this clock, since it + is assumed to be fully under the control of the PHY device/driver. In + cases where SoC integration adds additional logic to this path, such as a + SW-controlled clock gate, this clock should be represented in DT. + - "slave_bus" + The CPU/slave-bus (CSR) interface clock. This applies to any bus type; + APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other + buses). + - "master_bus" + The master bus interface clock. Only required in configurations that use a + separate clock for the master and slave bus interfaces. The HW signal name + is hclk_i (AHB) or aclk_i (AXI). + - "ptp_ref" + The PTP reference clock. The HW signal name is clk_ptp_ref_i. + - "phy_ref_clk" + This clock is deprecated and should not be used by new compatible values. + It is equivalent to "tx". + - "apb_pclk" + This clock is deprecated and should not be used by new compatible values. + It is equivalent to "slave_bus". + + Note: Support for additional IP configurations may require adding the + following clocks to this list in the future: clk_rx_125_i, clk_tx_125_i, + clk_pmarx_0_i, clk_pmarx1_i, clk_rmii_i, clk_revmii_rx_i, clk_revmii_tx_i. + Configurations exist where multiple similar clocks are used at once, e.g. all + of clk_rx_125_i, clk_pmarx_0_i, clk_pmarx1_i. For this reason it is best to + extend the binding with a separate clock-names entry for each of those RX + clocks, rather than repurposing the existing "rx" clock-names entry as a + generic/logical clock in a similar fashion to "master_bus" and "slave_bus". + This will allow easy support for configurations that support multiple PHY + interfaces using a mux, and hence need to have explicit control over + specific RX clocks. + + The following compatible values require the following set of clocks: + - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10": + - "slave_bus" + - "master_bus" + - "rx" + - "tx" + - "ptp_ref" + - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10": + - "slave_bus" + - "master_bus" + - "tx" + - "ptp_ref" + - "snps,dwc-qos-ethernet-4.10" (deprecated): + - "phy_ref_clk" + - "apb_clk" +- interrupt-parent: Should be the phandle for the interrupt controller + that services interrupts for this device +- interrupts: Should contain the core's combined interrupt signal +- phy-mode: See ethernet.txt file in the same directory +- resets: Phandle and reset specifiers for each entry in reset-names, in the + same order. See ../reset/reset.txt. +- reset-names: May contain any/all of the following depending on the IP + configuration, in any order: + - "eqos". The reset to the entire module. The HW signal name is hreset_n + (AHB) or aresetn_i (AXI). + + The following compatible values require the following set of resets: + (the reset properties may be omitted if empty) + - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10": + - "eqos". + - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10": + - None. + - "snps,dwc-qos-ethernet-4.10" (deprecated): + - None. + +Optional properties: +- dma-coherent: Present if dma operations are coherent +- mac-address: See ethernet.txt in the same directory +- local-mac-address: See ethernet.txt in the same directory +- phy-reset-gpios: Phandle and specifier for any GPIO used to reset the PHY. + See ../gpio/gpio.txt. +- snps,en-lpi: If present it enables use of the AXI low-power interface +- snps,write-requests: Number of write requests that the AXI port can issue. + It depends on the SoC configuration. +- snps,read-requests: Number of read requests that the AXI port can issue. + It depends on the SoC configuration. +- snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB + representing 4, then 8 etc. +- snps,txpbl: DMA Programmable burst length for the TX DMA +- snps,rxpbl: DMA Programmable burst length for the RX DMA +- snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during + TX low-power mode. +- phy-handle: See ethernet.txt file in the same directory +- mdio device tree subnode: When the GMAC has a phy connected to its local + mdio, there must be device tree subnode with the following + required properties: + - compatible: Must be "snps,dwc-qos-ethernet-mdio". + - #address-cells: Must be <1>. + - #size-cells: Must be <0>. + + For each phy on the mdio bus, there must be a node with the following + fields: + + - reg: phy id used to communicate to phy. + - device_type: Must be "ethernet-phy". + - fixed-mode device tree subnode: see fixed-link.txt in the same directory + +Examples: +ethernet2@40010000 { + clock-names = "phy_ref_clk", "apb_pclk"; + clocks = <&clkc 17>, <&clkc 15>; + compatible = "snps,dwc-qos-ethernet-4.10"; + interrupt-parent = <&intc>; + interrupts = <0x0 0x1e 0x4>; + reg = <0x40010000 0x4000>; + phy-handle = <&phy2>; + phy-mode = "gmii"; + phy-reset-gpios = <&gpioctlr 43 GPIO_ACTIVE_LOW>; + + snps,en-tx-lpi-clockgating; + snps,en-lpi; + snps,write-requests = <2>; + snps,read-requests = <16>; + snps,burst-map = <0x7>; + snps,txpbl = <8>; + snps,rxpbl = <2>; + + dma-coherent; + + mdio { + #address-cells = <0x1>; + #size-cells = <0x0>; + phy2: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + device_type = "ethernet-phy"; + reg = <0x1>; + }; + }; +}; -- 2.9.3

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