September 2016 - U-Boot

[U-Boot] ZynqMP breakage
by Alexander Graf 08 Sep '16

08 Sep '16

Hi Michal, I just tried to run the latest u-boot master + a few patches to implement generic PSCI RTS support on zynqmp and got this: e U-Boot 2016.09-rc1-00453-ga0592f1 (Aug 16 2016 - 20:27:40 +0200) Xilinx ZynqMP ZCU102 I2C: ready DRAM: 4 GiB EL Level: EL2 MMC: sdhci@ff170000: 0 Using default environment In: serial@ff000000 Out: serial@ff000000 Err: serial@ff000000 Bootmode: SD_MODE1 SCSI: SATA link 0 timeout. Target spinup took 0 ms. AHCI 0001.0301 32 slots 2 ports 6 Gbps 0x3 impl SATA mode flags: 64bit ncq pm clo only pmp fbss pio slum part ccc apst scanning bus for devices... "Synchronous Abort" handler, esr 0x96000004 ELR: 7ff42d20 LR: 7ff3ff10 x0 : 0000000000000000 x1 : 0000000000000000 x2 : 0000000000000001 x3 : 000000007df1aa80 x4 : aaaaaaaaaaaaaaaa x5 : 0000000000000001 x6 : 0000000000000200 x7 : 0000000000000004 x8 : 000000007ff9f800 x9 : 0000000000000008 x10: 000000007ff9f8f0 x11: 0000000000000000 x12: 00000000ffffffff x13: 00000000ffffffff x14: 000000007ff8242f x15: 000000007ff82435 x16: 000000007ff84388 x17: 000000007ff84388 x18: 000000007df1ade8 x19: 000000007df1aa80 x20: 000000007ff92cb8 x21: 000000007ff9f800 x22: 000000007ff9f000 x23: 0000000000000078 x24: 000000007ff9f8f0 x25: 0000000000000000 x26: 000000007ff9f800 x27: 000000007ff9f000 x28: 000000007ff9fb00 x29: 000000007df1aca0 Resetting CPU ... resetting … Is this a known problem? Alex

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[U-Boot] [PATCH V4 1/2] mmc: sd: extracting erase related information from sd status
by Peng Fan 08 Sep '16

08 Sep '16

Add function to read SD_STATUS information. According to the information, get erase_timeout/erase_size/erase_offset. Add a structure sd_ssr to include the erase related information. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Stefan Wahren <stefan.wahren(a)i2se.com> Cc: Clemens Gruber <clemens.gruber(a)pqgruber.com> Cc: Kever Yang <kever.yang(a)rock-chips.com> Cc: Eric Nelson <eric(a)nelint.com> Cc: Stephen Warren <swarren(a)nvidia.com> --- V4: include linux/sizes.h in mmc.h to avoid build break. I dropped patch [2,3,4]/5 in V2, which is not a must in this optimization case. V3: No change. V2: Address Jaehoon's comments for V1 drivers/mmc/mmc.c | 68 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/mmc.h | 9 ++++++++ 2 files changed, 77 insertions(+) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 43ea0bb..0312da9 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -21,6 +21,14 @@ #include <div64.h> #include "mmc_private.h" +static const unsigned int sd_au_size[] = { + 0, SZ_16K / 512, SZ_32K / 512, + SZ_64K / 512, SZ_128K / 512, SZ_256K / 512, + SZ_512K / 512, SZ_1M / 512, SZ_2M / 512, + SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512, + SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512, +}; + #ifndef CONFIG_DM_MMC_OPS __weak int board_mmc_getwp(struct mmc *mmc) { @@ -945,6 +953,62 @@ retry_scr: return 0; } +static int sd_read_ssr(struct mmc *mmc) +{ + int err, i; + struct mmc_cmd cmd; + ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16); + struct mmc_data data; + int timeout = 3; + unsigned int au, eo, et, es; + + cmd.cmdidx = MMC_CMD_APP_CMD; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = mmc->rca << 16; + + err = mmc_send_cmd(mmc, &cmd, NULL); + if (err) + return err; + + cmd.cmdidx = SD_CMD_APP_SD_STATUS; + cmd.resp_type = MMC_RSP_R1; + cmd.cmdarg = 0; + +retry_ssr: + data.dest = (char *)ssr; + data.blocksize = 64; + data.blocks = 1; + data.flags = MMC_DATA_READ; + + err = mmc_send_cmd(mmc, &cmd, &data); + if (err) { + if (timeout--) + goto retry_ssr; + + return err; + } + + for (i = 0; i < 16; i++) + ssr[i] = be32_to_cpu(ssr[i]); + + au = (ssr[2] >> 12) & 0xF; + if ((au <= 9) || (mmc->version == SD_VERSION_3)) { + mmc->ssr.au = sd_au_size[au]; + es = (ssr[3] >> 24) & 0xFF; + es |= (ssr[2] & 0xFF) << 8; + et = (ssr[3] >> 18) & 0x3F; + if (es && et) { + eo = (ssr[3] >> 16) & 0x3; + mmc->ssr.erase_timeout = (et * 1000) / es; + mmc->ssr.erase_offset = eo * 1000; + } + } else { + debug("Invalid Allocation Unit Size.\n"); + } + + return 0; +} + /* frequency bases */ /* divided by 10 to be nice to platforms without floating point */ static const int fbase[] = { @@ -1350,6 +1414,10 @@ static int mmc_startup(struct mmc *mmc) mmc_set_bus_width(mmc, 4); } + err = sd_read_ssr(mmc); + if (err) + return err; + if (mmc->card_caps & MMC_MODE_HS) mmc->tran_speed = 50000000; else diff --git a/include/mmc.h b/include/mmc.h index aa6d5d1..e815eb3 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -11,6 +11,7 @@ #define _MMC_H_ #include <linux/list.h> +#include <linux/sizes.h> #include <linux/compiler.h> #include <part.h> @@ -102,6 +103,7 @@ #define SD_CMD_SWITCH_UHS18V 11 #define SD_CMD_APP_SET_BUS_WIDTH 6 +#define SD_CMD_APP_SD_STATUS 13 #define SD_CMD_ERASE_WR_BLK_START 32 #define SD_CMD_ERASE_WR_BLK_END 33 #define SD_CMD_APP_SEND_OP_COND 41 @@ -392,6 +394,12 @@ struct mmc_config { unsigned char part_type; }; +struct sd_ssr { + unsigned int au; /* In sectors */ + unsigned int erase_timeout; /* In milliseconds */ + unsigned int erase_offset; /* In milliseconds */ +}; + /* * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device * with mmc_get_mmc_dev(). @@ -426,6 +434,7 @@ struct mmc { uint write_bl_len; uint erase_grp_size; /* in 512-byte sectors */ uint hc_wp_grp_size; /* in 512-byte sectors */ + struct sd_ssr ssr; /* SD status register */ u64 capacity; u64 capacity_user; u64 capacity_boot; -- 2.6.2

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[U-Boot] [PATCH 0/4] sunxi: Pine64 fixes
by Andre Przywara 08 Sep '16

08 Sep '16

Some patches to fix the Pine64 support: The first two patches revert two patches that actually broke booting Pine64 via the boot0 blob, already in 2016.07. This has been discussed on IRC before, the commit messages contain some details on the reasons for the revert. As the intent of those original fixes was to help the (not yet upstream) SPL support, we don't loose anything as the Pine64 uses the U-Boot proper only at the moment. Patch 3/4 removes the usage of a non-existing config symbol. Patch 4/4 fixes a compiler warning when compiling sunxi's board.c with a 64-bit compiler. Please apply for the 2016.09 release to allow booting Pine64s with a recent U-Boot. Thanks, Andre. Andre Przywara (4): Revert "sunxi: Move the SPL stack top to 0x1A000 on Allwinner A64/A80" Revert "sunxi: Downclock AHB1 to 100MHz on Allwinner A64" sunxi: Kconfig: rename non-existent SUN50I_A64 config symbol sunxi: fix 64-bit compiler warning for SPL header parsing arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 ----- board/sunxi/Kconfig | 2 +- board/sunxi/board.c | 2 +- include/configs/sunxi-common.h | 5 +++-- 4 files changed, 5 insertions(+), 9 deletions(-) -- 2.8.2

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[U-Boot] [PATCH] armv8: ls1043a: Extend the size for SPL
by Gong Qianyu 08 Sep '16

08 Sep '16

The SPL images are growing much bigger especially when DEBUG is ON. So need to fix the values for them. Signed-off-by: Gong Qianyu <Qianyu.Gong(a)nxp.com> --- include/configs/ls1043a_common.h | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index e55fcb2..fa20e6d 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -69,16 +69,22 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_DRIVERS_MISC_SUPPORT #define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xf0 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x110 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500 #define CONFIG_SPL_TEXT_BASE 0x10000000 -#define CONFIG_SPL_MAX_SIZE 0x1d000 -#define CONFIG_SPL_STACK 0x1001e000 -#define CONFIG_SPL_PAD_TO 0x1d000 +/* + * CONFIG_SPL_MAX_SIZE is limited by OCRAM memory size(128 KiB) and + * a reserved stack size(4 KiB). + * So notice that even if DEBUG is ON, the SPL image(spl/u-boot-spl.bin) + * should not be > 124 KiB. + */ +#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */ +#define CONFIG_SPL_STACK 0x10020000 +#define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */ -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ - CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 @@ -101,11 +107,12 @@ #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_DRIVERS_MISC_SUPPORT #define CONFIG_SPL_TEXT_BASE 0x10000000 -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_MAX_SIZE 0x1d000 /* 116 KiB */ +#define CONFIG_SPL_STACK 0x1001f000 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) #define CONFIG_SPL_BSS_START_ADDR 0x80100000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -- 2.1.0.27.g96db324

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[U-Boot] ddr: Invalid SPD module type definitions for SO-DIMM with ECC
by Ralf Göbel 08 Sep '16

08 Sep '16

Hi, it think the SPD module type definitions for DDR4 SO-DIMM with ECC in the file include/ddr_spd.h are swapped: #define DDR4_SPD_MODULETYPE_72B_SO_UDIMM (0x08) #define DDR4_SPD_MODULETYPE_72B_SO_RDIMM (0x09) According to JEDEC document SPD4.1.2.L-4, UDIMM is 0x9 and RDIMM is 0x8. Can someone verify this? Regards, Ralf

1 0

[U-Boot] [PATCH v2] sunxi: display: Use PWM to drive backlight where applicable
by Hans de Goede 08 Sep '16

08 Sep '16

When the backlight's pwm input is connected to a pwm output of the SoC, actually use pwm to drive the backlight. The mean reason for doing this is to fix the backlight turning off for aprox. 1 second while the kernel is booting. This is caused by the kernel actually using pwm to drive the backlight, so that it can dim the backlight. First the pwm driver loads and switches the pinmux for the pin driving the backlight's pwm input to the pwm controller. Then about 1s later the actual backlight driver loads and tells the pwm driver to actually update the pwm settings, which have a power-on-reset value of "off". An additional advantage is that this allows us to initatiate the backlight at 80%, which is the kernel default, avoiding a brightness change while the kernel loads. Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- Changes in v2: -Fix pwm mmio base-address being wrong for sun6i / sun8i -Add support for pwm on sun6i --- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 7 ++++++ arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++ arch/arm/include/asm/arch-sunxi/pwm.h | 34 +++++++++++++++++++++++++++++ drivers/video/sunxi_display.c | 12 +++++++++- 4 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-sunxi/pwm.h diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index cd009d7..5f93830 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -76,8 +76,15 @@ #define SUNXI_INTC_BASE 0x01c20400 #define SUNXI_PIO_BASE 0x01c20800 #define SUNXI_TIMER_BASE 0x01c20c00 +#ifndef CONFIG_SUNXI_GEN_SUN6I +#define SUNXI_PWM_BASE 0x01c20e00 +#endif #define SUNXI_SPDIF_BASE 0x01c21000 +#ifdef CONFIG_SUNXI_GEN_SUN6I +#define SUNXI_PWM_BASE 0x01c21400 +#else #define SUNXI_AC97_BASE 0x01c21400 +#endif #define SUNXI_IR0_BASE 0x01c21800 #define SUNXI_IR1_BASE 0x01c21c00 diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index bff7d14..85a4ec3 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -150,6 +150,7 @@ enum sunxi_gpio_number { #define SUN6I_GPA_SDC3 4 #define SUN8I_H3_GPA_UART0 2 +#define SUN4I_GPB_PWM 2 #define SUN4I_GPB_TWI0 2 #define SUN4I_GPB_TWI1 2 #define SUN5I_GPB_TWI1 2 @@ -186,6 +187,8 @@ enum sunxi_gpio_number { #define SUN6I_GPG_TWI3 2 #define SUN5I_GPG_UART1 4 +#define SUN6I_GPH_PWM 2 +#define SUN8I_GPH_PWM 2 #define SUN4I_GPH_SDC1 5 #define SUN6I_GPH_TWI0 2 #define SUN8I_GPH_TWI0 2 diff --git a/arch/arm/include/asm/arch-sunxi/pwm.h b/arch/arm/include/asm/arch-sunxi/pwm.h new file mode 100644 index 0000000..5884b5d --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/pwm.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2016 Hans de Goede <hdegoede(a)redhat.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_PWM_H +#define _SUNXI_PWM_H + +#define SUNXI_PWM_CTRL_REG (SUNXI_PWM_BASE + 0) +#define SUNXI_PWM_CH0_PERIOD (SUNXI_PWM_BASE + 4) + +#define SUNXI_PWM_CTRL_PRESCALE0(x) ((x) & 0xf) +#define SUNXI_PWM_CTRL_ENABLE0 (0x5 << 4) +#define SUNXI_PWM_CTRL_POLARITY0(x) ((x) << 5) + +#define SUNXI_PWM_PERIOD_80PCT 0x04af03c0 + +#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN5I +#define SUNXI_PWM_PIN0 SUNXI_GPB(2) +#define SUNXI_PWM_MUX SUN4I_GPB_PWM +#endif + +#if defined CONFIG_MACH_SUN6I +#define SUNXI_PWM_PIN0 SUNXI_GPH(13) +#define SUNXI_PWM_MUX SUN6I_GPH_PWM +#endif + +#if defined CONFIG_MACH_SUN8I_A23 || defined CONFIG_MACH_SUN8I_A33 +#define SUNXI_PWM_PIN0 SUNXI_GPH(0) +#define SUNXI_PWM_MUX SUN8I_GPH_PWM +#endif + +#endif diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index 56f6c8e..00a38f9 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -12,6 +12,7 @@ #include <asm/arch/clock.h> #include <asm/arch/display.h> #include <asm/arch/gpio.h> +#include <asm/arch/pwm.h> #include <asm/global_data.h> #include <asm/gpio.h> #include <asm/io.h> @@ -34,7 +35,6 @@ #define PWM_ON 1 #define PWM_OFF 0 #endif - DECLARE_GLOBAL_DATA_PTR; enum sunxi_monitor { @@ -743,6 +743,16 @@ static void sunxi_lcdc_backlight_enable(void) gpio_direction_output(pin, 1); pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM); +#ifdef SUNXI_PWM_PIN0 + if (pin == SUNXI_PWM_PIN0) { + writel(SUNXI_PWM_CTRL_POLARITY0(PWM_ON) | + SUNXI_PWM_CTRL_ENABLE0 | + SUNXI_PWM_CTRL_PRESCALE0(0xf), SUNXI_PWM_CTRL_REG); + writel(SUNXI_PWM_PERIOD_80PCT, SUNXI_PWM_CH0_PERIOD); + sunxi_gpio_set_cfgpin(pin, SUNXI_PWM_MUX); + return; + } +#endif if (pin >= 0) gpio_direction_output(pin, PWM_ON); } -- 2.9.3

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[U-Boot] [PATCH] sun5i: Add defconfig and dts file for the Empire Electronix M712 tablet
by Hans de Goede 08 Sep '16

08 Sep '16

Add a defconfig and dts file for the Empire Electronix M712 tablet, this is a 7" A13 tablet, with micro-usb (otg), headphone and micro-sd slots on the outside. It uses a Goodix gt811 touchscreen controller, a RTL8188CTV wifi chip and a DMART06 (1238a4) accelerometer. The dts file is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/sun5i-a13-empire-electronix-m712.dts | 51 +++++++++++++++++++++++ board/sunxi/MAINTAINERS | 1 + configs/Empire_electronix_m712_defconfig | 22 ++++++++++ 4 files changed, 75 insertions(+) create mode 100644 arch/arm/dts/sun5i-a13-empire-electronix-m712.dts create mode 100644 configs/Empire_electronix_m712_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6d1b94c..7d1944f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -182,6 +182,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \ sun5i-a13-ampe-a76.dtb \ sun5i-a13-difrnce-dit4350.dtb \ sun5i-a13-empire-electronix-d709.dtb \ + sun5i-a13-empire-electronix-m712.dtb \ sun5i-a13-hsg-h702.dtb \ sun5i-a13-inet-86vs.dtb \ sun5i-a13-inet-98v-rev2.dtb \ diff --git a/arch/arm/dts/sun5i-a13-empire-electronix-m712.dts b/arch/arm/dts/sun5i-a13-empire-electronix-m712.dts new file mode 100644 index 0000000..b1e2afd --- /dev/null +++ b/arch/arm/dts/sun5i-a13-empire-electronix-m712.dts @@ -0,0 +1,51 @@ +/* + * Copyright 2016 Hans de Goede <hdegoede(a)redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sun5i-reference-design-tablet.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "Empire Electronix M712 tablet"; + compatible = "empire-electronix,m712", "allwinner,sun5i-a13"; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index c1d0f55..7072bd8 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -28,6 +28,7 @@ F: configs/Auxtek-T004_defconfig F: configs/CHIP_defconfig F: configs/difrnce_dit4350_defconfig F: configs/Empire_electronix_d709_defconfig +F: configs/Empire_electronix_m712_defconfig F: configs/inet98v_rev2_defconfig F: configs/mk802_a10s_defconfig F: configs/q8_a13_tablet_defconfig diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig new file mode 100644 index 0000000..224098f --- /dev/null +++ b/configs/Empire_electronix_m712_defconfig @@ -0,0 +1,22 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN5I=y +CONFIG_DRAM_CLK=408 +CONFIG_MMC0_CD_PIN="PG0" +CONFIG_USB0_VBUS_PIN="PG12" +CONFIG_USB0_VBUS_DET="PG1" +CONFIG_USB0_ID_DET="PG2" +CONFIG_AXP_GPIO=y +# CONFIG_VIDEO_HDMI is not set +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_POWER="AXP0-0" +CONFIG_VIDEO_LCD_BL_EN="AXP0-1" +CONFIG_VIDEO_LCD_BL_PWM="PB2" +CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-m712" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_USB_MUSB_HOST=y -- 2.9.3

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[U-Boot] [PATCH 0/9] MIPS L2 cache support
by Paul Burton 08 Sep '16

08 Sep '16

This series introduces support for initialising & maintaining L2 caches on MIPS systems. This allows U-Boot to function correctly on systems where such caches are present, whereas without performing L2 maintenance it is likely to fail with cache coherence issues when writing code or performing DMA transfers. Paul Burton (9): MIPS: Add arch-wide arch_cpu_init MIPS: Probe cache line sizes once during boot MIPS: Enable use of the instruction cache earlier MIPS: Preserve Config implementation-defined bits MIPS: If we don't need DDR for cache init, init cache first MIPS: Define register names for cache init MIPS: Map CM Global Control Registers MIPS: L2 cache support MIPS: Malta: Enable CM & L2 support arch/mips/Kconfig | 28 +++++ arch/mips/cpu/Makefile | 2 + arch/mips/cpu/cm_init.S | 45 +++++++ arch/mips/cpu/cpu.c | 8 ++ arch/mips/cpu/start.S | 26 +++-- arch/mips/include/asm/cache.h | 9 ++ arch/mips/include/asm/cm.h | 57 +++++++++ arch/mips/include/asm/global_data.h | 7 ++ arch/mips/include/asm/mipsregs.h | 6 + arch/mips/include/asm/u-boot-mips.h | 12 ++ arch/mips/lib/cache.c | 101 +++++++++++++--- arch/mips/lib/cache_init.S | 226 ++++++++++++++++++++++++++++++++---- arch/mips/mach-ath79/cpu.c | 3 +- board/imgtec/malta/lowlevel_init.S | 6 - 14 files changed, 482 insertions(+), 54 deletions(-) create mode 100644 arch/mips/cpu/cm_init.S create mode 100644 arch/mips/include/asm/cm.h -- 2.9.3

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[U-Boot] [PATCH v2] fsl-ifc-nand : Corrected the programming of chip select
by Matt Weber 08 Sep '16

08 Sep '16

Corrected the chip selection in IFC_NAND_CSEL register. Due to this issue in multi-chip nand use-case, IFC was always pointing to the last probed chip even though the user select another device through "nand device <dev>" command. Also, remove the usage of ifc_ctrl->cs_nand from driver as chipselect is a property of the chip not the controller. Signed-off-by: Matthew Weber <matthew.weber(a)rockwellcollins.com> Signed-off-by: Ronak Desai <ronak.desai(a)rockwellcollins.com> --- v1 -> v2 [ Scott W - Update fsl_ifc_sram_init() with correct csel and cs_nand removed. --- drivers/mtd/nand/fsl_ifc_nand.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 7001cbd..1912fc1 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -48,7 +48,6 @@ struct fsl_ifc_ctrl { /* device info */ struct fsl_ifc regs; void __iomem *addr; /* Address of assigned IFC buffer */ - unsigned int cs_nand; /* On which chipsel NAND is connected */ unsigned int page; /* Last page written to / read from */ unsigned int read_bytes; /* Number of bytes read during command */ unsigned int column; /* Saved column from SEQIN */ @@ -296,7 +295,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) int i; /* set the chip select for NAND Transaction */ - ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); + ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT); /* start read/write seq */ ifc_out32(&ifc->ifc_nand.nandseq_strt, @@ -798,7 +797,7 @@ static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip) { } -static int fsl_ifc_sram_init(uint32_t ver) +static int fsl_ifc_sram_init(uint32_t ver, struct fsl_ifc_mtd *priv) { struct fsl_ifc_runtime *ifc = ifc_ctrl->regs.rregs; uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0; @@ -823,7 +822,7 @@ static int fsl_ifc_sram_init(uint32_t ver) return 1; } - cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT; + cs = priv->bank; /* Save CSOR and CSOR_ext */ csor = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor); @@ -850,7 +849,7 @@ static int fsl_ifc_sram_init(uint32_t ver) ifc_out32(&ifc->ifc_nand.col0, 0x0); /* set the chip select for NAND Transaction */ - ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); + ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT); /* start read seq */ ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT); @@ -912,7 +911,6 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND && (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) { - ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT; break; } } @@ -1029,7 +1027,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) ver = ifc_in32(&gregs->ifc_rev); if (ver >= FSL_IFC_V1_1_0) - ret = fsl_ifc_sram_init(ver); + ret = fsl_ifc_sram_init(ver, priv); if (ret) return ret; -- 1.9.1

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[U-Boot] [PATCH] board: ks2: README: Update to add K2G support
by Lokesh Vutla 07 Sep '16

07 Sep '16

Update the README to add support for K2G EVM. Also - Add steps on how to use MMC boot - Fix load address when using CCS - Update build target to u-boot.bin from u-boot-dtb.bin as all ks2 platforms uses DT. Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- board/ti/ks2_evm/README | 40 ++++++++++++++++++++++++++++++---------- 1 file changed, 30 insertions(+), 10 deletions(-) diff --git a/board/ti/ks2_evm/README b/board/ti/ks2_evm/README index 05baff6..5430c7d 100644 --- a/board/ti/ks2_evm/README +++ b/board/ti/ks2_evm/README @@ -20,6 +20,9 @@ The K2E SoC details are available at The K2L SoC details are available at http://www.ti.com/lit/ds/symlink/tci6630k2l.pdf +The K2G SoC details are available at + http://www.ti.com/lit/ds/symlink/66ak2g02.pdf + Board configuration: ==================== @@ -30,6 +33,7 @@ Some of the peripherals that are configured by U-Boot |K2HK |2 |512MB |6MB |4(2) |2 |3 |3 | |K2E |4 |512MB |2MB |8(2) |2 |3 |3 | |K2L |2 |512MB |2MB |4(2) |4 |3 |3 | +|K2G |2 |256MB |1MB |1 |1 |1 |1 | +------+-------+-------+-----------+-----------+-------+-------+----+ There are only 2 eth port installed on the boards. @@ -47,44 +51,48 @@ Board configuration files: include/configs/k2hk_evm.h include/configs/k2e_evm.h include/configs/k2l_evm.h +include/configs/k2g_evm.h As U-Boot is migrating to Kconfig there is also board defconfig files configs/k2e_evm_defconfig configs/k2hk_evm_defconfig configs/k2l_evm_defconfig +configs/k2g_evm_defconfig Supported boot modes: - SPI NOR boot - AEMIF NAND boot - UART boot + - MMC boot (Only on K2G) Supported image formats: - - u-boot-dtb.bin: for loading and running u-boot-dtb.bin through + - u-boot.bin: for loading and running u-boot.bin through Texas Instruments code composure studio (CCS) and for UART boot. - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot - - MLO: gpimage for programming AEMIF NAND flash for NAND boot + - MLO: gpimage for programming AEMIF NAND flash for NAND boot, MMC boot. Build instructions: =================== -Examples for k2hk, for k2e and k2l just replace k2hk prefix accordingly. +Examples for k2hk, for k2e, k2l and k2g just replace k2hk prefix accordingly. Don't forget to add ARCH=arm and CROSS_COMPILE. -To build u-boot-dtb.bin, u-boot-spi.gph, MLO: +To build u-boot.bin, u-boot-spi.gph, MLO: >make k2hk_evm_defconfig >make Load and Run U-Boot on keystone EVMs using CCS ========================================= -Need Code Composer Studio (CCS) installed on a PC to load and run u-boot-dtb.bin +Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin on EVM. See instructions at below link for installing CCS on a Windows PC. http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started# Installing_Code_Composer_Studio -Use u-boot-dtb.bin from the build folder for loading and running U-Boot binary +Use u-boot.bin from the build folder for loading and running U-Boot binary on EVM. Follow instructions at K2HK http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup K2E http://processors.wiki.ti.com/index.php/EVMK2E_Hardware_Setup K2L http://processors.wiki.ti.com/index.php/TCIEVMK2L_Hardware_Setup +K2G http://processors.wiki.ti.com/index.php/66AK2G02_GP_EVM_Hardware_Setup to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode" and Power ON the EVM. Follow instructions to connect serial port of EVM to @@ -100,13 +108,13 @@ loading the U-Boot binary on the target EVM. Instead do the following:- is connected: Unknown)" at the debug window (This is created once Target configuration is launched) and select "Connect Target". 2. Once target connect is successful, choose Tools->Load Memory option from the - top level menu. At the Load Memory window, choose the file u-boot-dtb.bin + top level menu. At the Load Memory window, choose the file u-boot.bin through "Browse" button and click "next >" button. In the next window, enter - Start address as 0xc001000, choose Type-size "32 bits" and click "Finish" + Start address as 0xc000000, choose Type-size "32 bits" and click "Finish" button. 3. Click View -> Registers from the top level menu to view registers window. 4. From Registers, window expand "Core Registers" to view PC. Edit PC value - to be 0xc001000. From the "Run" top level menu, select "Free Run" + to be 0xc000000. From the "Run" top level menu, select "Free Run" 5. The U-Boot prompt is shown at the Tera Term/ Hyper terminal console as below and type any key to stop autoboot as instructed := @@ -167,8 +175,20 @@ Load and Run U-Boot on keystone EVMs using UART download Open BMC and regular UART terminals. -1. On the regular UART port start xmodem transfer of the u-boot-dtb.bin +1. On the regular UART port start xmodem transfer of the u-boot.bin 2. Using BMC terminal set the ARM-UART bootmode and reboot the EVM BMC> bootmode #4 MBC> reboot 3. When xmodem is complete you should see the U-Boot starts on the UART port + +Load and Run U-Boot on K2G EVMs using MMC +======================================================== + +Open BMC and regular UART terminals. + +1. Set the SW3 dip switch to "ARM MMC Boot mode" as per instruction at + http://processors.wiki.ti.com/index.php/66AK2G02_GP_EVM_Hardware_Setup +2. Create SD card partitions as per steps given in Hardware Setup Guide. +3. Copy MLO to Boot Partition. +4. Insert SD card and Power on the EVM. + The EVM now boots with U-Boot image from SD card. -- 2.9.3

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