September 2016 - U-Boot

[U-Boot] [arm] Where to put files for armv8 ThunderX
by Aaron Williams 14 Sep '16

14 Sep '16

I have just been handed the task of cleaning up our U-Boot port to our ThunderX armv8 chip and am wondering where I should put the files specific to our chip. The people who previously worked on the chip created a subdirectory under u-boot and have things scattered about. Should I create a subdirectory under arch/arm/cpu/armv8 like arch/arm/cpu/armv8/mach-thunderx or should I create a mach-thunderx directory directly under the cpu directory? I'm assuming include files should go under arch/arm/include/asm/arch-thunderx. I very much want to get this stuff pushed upstream so I don't run into the situation we've been stuck with our Octeon MIPS processors. My biggest problem is that a lot of code doesn't work. I'm still trying to get up to speed with the armv8 U-Boot. -Aaron -- Aaron Williams Software Engineer Cavium, Inc. (408) 943-7198 (510) 789-8988 (cell)

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[U-Boot] [PATCH] colibri_t30: fix usb ethernet functionality
by Marcel Ziswiler 14 Sep '16

14 Sep '16

Since commit aa7a648747d8c704a9a81c9e493d386930724e9d ("net: Stop including NFS overhead in defragment max") the following has been reproducibly observed while trying to transfer data over TFTP: Load address: 0x80408000 Loading: EHCI timed out on TD - token=0x8008d80 T EHCI timed out on TD - token=0x88008d80 Rx: failed to receive: -5 This patch fixes this by upping our maximal de-fragmentation aka IP packet size again. Signed-off-by: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> --- include/configs/colibri_t30.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index fbb235d..3431cde 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -48,6 +48,7 @@ /* General networking support */ #define CONFIG_IP_DEFRAG +#define CONFIG_NET_MAXDEFRAG (16384 + 4096 + 24) #define CONFIG_TFTP_BLOCKSIZE 16384 #define CONFIG_TFTP_TSIZE -- 2.5.5

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[U-Boot] recommended place to add some custom settings to u-boot environment?
by Robert P. J. Day 14 Sep '16

14 Sep '16

on my target board, there is some non-linux environment info in "var=val" form that i want to drag into the current environment whenever u-boot starts up. my plan is just to import that content into a (new) hash table, then tweak it a bit before further adding it to "env_htab". the logistics seem pretty straightforward, i'm just curious as to where the *right*(?) place is to do this. currently, we're not taking advantage of CONFIG_MISC_INIT_R, so it seems that would be a reasonable place to do that, in the board source file. does that make sense? at that point, all of the normal environment will have been initialized, and i'll have access to "env_htab". thoughts? is there a better place to "adjust" the u-boot environment once u-boot has done its normal work? thanks. rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

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[U-Boot] [PATCH v2 0/5] Enhance fs tests
by Stefan Brüns 14 Sep '16

14 Sep '16

The first 3 patches do some cleanups for the current test, especially TC11 had some issues (strange match for expected output, use of unitialized variable). The last two patches add test cases for handling ".". Ext4 used to crash, as a match on the first entry of a directory block was not handled correctly. v2: Updated: test/fs: Restructure file path specification to allow some flexibility * avoid creation of paths with double slashes test/fs: Check writes using "." (same dir) relative path * fix issues copied from TC11 * delete written file in cleanup Added: test/fs: remove use of undefined WRITE_FILE variable test/fs: strip noise from filesystem code prior to checking results Stefan Brüns (5): test/fs: Restructure file path specification to allow some flexibility test/fs: remove use of undefined WRITE_FILE variable test/fs: strip noise from filesystem code prior to checking results test/fs: Check ext4 behaviour if dirent is first entry in directory block test/fs: Check writes using "." (same dir) relative path test/fs/fs-test.sh | 131 +++++++++++++++++++++++++++++++---------------------- 1 file changed, 78 insertions(+), 53 deletions(-) -- 2.10.0

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[U-Boot] [PATCH 00/12] ARM: uniphier: UniPhier SoC updates for v2016.11-rc1
by Masahiro Yamada 14 Sep '16

14 Sep '16

I want to get this series in during this merge window. - DM migration * remove legacy xHCI driver * convert MMC driver to CONFIG_BLOCK - Pinctrl driver improvements * New pin-group * Macro cleanup - Misc fixes, cleanups * Fix DRAM size of LD21 SoC * Consolidate board init functions Masahiro Yamada (12): ARM: uniphier: sort select:s alphabetically usb: uniphier: remove UniPhier xHCI driver and select DM_USB ARM: uniphier: delete unnecessary xHCI pin-mux settings ARM: uniphier: enable Generic EHCI driver for Pro4 SoC mmc: uniphier-sd: migrate to CONFIG_BLK pinctrl: uniphier: add System Bus pin-mux settings pinctrl: uniphier: move register base macros from header to .c file ARM: uniphier: remove IECTRL setup code of LD4 SoC ARM: uniphier: use checkboard() instead of misc_init_f() ARM: uniphier: merge board init functions into board_init() ARM: uniphier: fix DRAM size of LD21 SoC package ARM: uniphier: introduce flags to adjust DRAM timing for LD20/LD21 arch/arm/Kconfig | 16 ++-- arch/arm/mach-uniphier/Makefile | 5 +- arch/arm/mach-uniphier/board_common.c | 20 ----- arch/arm/mach-uniphier/board_early_init_r.c | 15 ---- .../{board_early_init_f.c => board_init.c} | 12 ++- arch/arm/mach-uniphier/boards.c | 29 +++++++- arch/arm/mach-uniphier/init.h | 12 ++- arch/arm/mach-uniphier/micro-support-card.c | 2 +- arch/arm/mach-uniphier/micro-support-card.h | 12 +-- arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c | 12 --- arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c | 6 -- arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c | 11 --- arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c | 7 -- arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c | 7 -- arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c | 11 --- arch/arm/mach-uniphier/print_misc_info.c | 12 --- configs/uniphier_ld4_sld8_defconfig | 1 - configs/uniphier_pro4_defconfig | 2 + configs/uniphier_sld3_defconfig | 1 - drivers/mmc/Kconfig | 1 + drivers/mmc/uniphier-sd.c | 50 ++++++------- drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 4 + drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c | 9 +++ drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 9 +++ drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c | 18 +++++ drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c | 21 ++++++ drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c | 30 ++++++++ drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c | 30 ++++++++ drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c | 9 +++ drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c | 21 ++++++ drivers/pinctrl/uniphier/pinctrl-uniphier.h | 4 - drivers/usb/host/Kconfig | 7 -- drivers/usb/host/Makefile | 1 - drivers/usb/host/xhci-uniphier.c | 85 ---------------------- include/configs/uniphier.h | 3 - include/fdtdec.h | 1 - lib/fdtdec.c | 1 - 37 files changed, 238 insertions(+), 259 deletions(-) delete mode 100644 arch/arm/mach-uniphier/board_common.c delete mode 100644 arch/arm/mach-uniphier/board_early_init_r.c rename arch/arm/mach-uniphier/{board_early_init_f.c => board_init.c} (94%) delete mode 100644 arch/arm/mach-uniphier/print_misc_info.c delete mode 100644 drivers/usb/host/xhci-uniphier.c -- 1.9.1

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[U-Boot] [RFC] board/liteboard: Add support for liteSOM and liteBoard
by Marcin Niestroj 14 Sep '16

14 Sep '16

liteSOM is a System On Module (http://grinn-global.com/litesom/). It can't exists on its own, but will be used as part of other boards. Hardware specification: * NXP i.MX6UL processor * 256M or 512M DDR3 memory * optional eMMC (uSDHC2) liteBoard is a development board which uses liteSOM as its base. Hardware specification: * liteSOM (i.MX6UL, DRAM, eMMC) * Ethernet PHY (id 0) * USB host (usb_otg1) * MicroSD slot (uSDHC1) The main question is: how should liteSOM sources be integrated? I didn't find similar modules, which are part of different boards in u-boot tree. For now, I've put source into arch/arm/mach-litesom, but I guess it is not the best place for them. The patch below compiles and runs successfully on liteBoard. It is based on 2016-09-rc2. Signed-off-by: Marcin Niestroj <m.niestroj(a)grinn-global.com> --- arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + arch/arm/cpu/armv7/mx6/Kconfig | 5 + arch/arm/mach-litesom/Kconfig | 6 + arch/arm/mach-litesom/Makefile | 6 + arch/arm/mach-litesom/include/litesom.h | 16 ++ arch/arm/mach-litesom/litesom.c | 207 ++++++++++++++++++++++++ board/grinn/liteboard/Kconfig | 12 ++ board/grinn/liteboard/MAINTAINERS | 6 + board/grinn/liteboard/Makefile | 6 + board/grinn/liteboard/README | 31 ++++ board/grinn/liteboard/board.c | 271 ++++++++++++++++++++++++++++++++ configs/liteboard_defconfig | 22 +++ include/configs/liteboard.h | 175 +++++++++++++++++++++ 14 files changed, 766 insertions(+) create mode 100644 arch/arm/mach-litesom/Kconfig create mode 100644 arch/arm/mach-litesom/Makefile create mode 100644 arch/arm/mach-litesom/include/litesom.h create mode 100644 arch/arm/mach-litesom/litesom.c create mode 100644 board/grinn/liteboard/Kconfig create mode 100644 board/grinn/liteboard/MAINTAINERS create mode 100644 board/grinn/liteboard/Makefile create mode 100644 board/grinn/liteboard/README create mode 100644 board/grinn/liteboard/board.c create mode 100644 configs/liteboard_defconfig create mode 100644 include/configs/liteboard.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c871eaf..4216a15 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -913,6 +913,8 @@ source "arch/arm/mach-keystone/Kconfig" source "arch/arm/mach-kirkwood/Kconfig" +source "arch/arm/mach-litesom/Kconfig" + source "arch/arm/mach-mvebu/Kconfig" source "arch/arm/cpu/armv7/mx7/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 42093c2..3e804d7 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -58,6 +58,7 @@ machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_KEYSTONE) += keystone # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD machine-$(CONFIG_KIRKWOOD) += kirkwood +machine-$(CONFIG_LITESOM) += litesom machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MVEBU) += mvebu # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 78383f0..1f72413 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -140,6 +140,10 @@ config TARGET_PICO_IMX6UL bool "PICO-IMX6UL-EMMC" select MX6UL +config TARGET_LITEBOARD + bool "Grinn liteBoard (i.MX6UL)" + select LITESOM + config TARGET_PLATINUM_PICON bool "platinum-picon" select SUPPORT_SPL @@ -217,6 +221,7 @@ source "board/freescale/mx6slevk/Kconfig" source "board/freescale/mx6sxsabresd/Kconfig" source "board/freescale/mx6sxsabreauto/Kconfig" source "board/freescale/mx6ul_14x14_evk/Kconfig" +source "board/grinn/liteboard/Kconfig" source "board/phytec/pcm058/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" diff --git a/arch/arm/mach-litesom/Kconfig b/arch/arm/mach-litesom/Kconfig new file mode 100644 index 0000000..9b7f36d --- /dev/null +++ b/arch/arm/mach-litesom/Kconfig @@ -0,0 +1,6 @@ +config LITESOM + bool + select MX6UL + select DM + select DM_THERMAL + select SUPPORT_SPL diff --git a/arch/arm/mach-litesom/Makefile b/arch/arm/mach-litesom/Makefile new file mode 100644 index 0000000..b15eb64 --- /dev/null +++ b/arch/arm/mach-litesom/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2016 Grinn +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := litesom.o diff --git a/arch/arm/mach-litesom/include/litesom.h b/arch/arm/mach-litesom/include/litesom.h new file mode 100644 index 0000000..6833949 --- /dev/null +++ b/arch/arm/mach-litesom/include/litesom.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2016 Grinn + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_ARM_MACH_LITESOM_SOM_H__ +#define __ARCH_ARM_MACH_LITESOM_SOM_H__ + +int litesom_mmc_init(bd_t *bis); + +#ifdef CONFIG_SPL_BUILD +void litesom_init_f(void); +#endif + +#endif diff --git a/arch/arm/mach-litesom/litesom.c b/arch/arm/mach-litesom/litesom.c new file mode 100644 index 0000000..edb6039 --- /dev/null +++ b/arch/arm/mach-litesom/litesom.c @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright (C) 2016 Grinn + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx6ul_pins.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/io.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <linux/sizes.h> +#include <mmc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_v3_cfg_t const emmc_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* RST_B */ + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg emmc_cfg = {USDHC2_BASE_ADDR, 0, 8}; + +#define EMMC_PWR_GPIO IMX_GPIO_NR(4, 10) + +int litesom_mmc_init(bd_t *bis) +{ + int ret; + + /* eMMC */ + imx_iomux_v3_setup_multiple_pads(emmc_pads, ARRAY_SIZE(emmc_pads)); + gpio_direction_output(EMMC_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(EMMC_PWR_GPIO, 1); + emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + + ret = fsl_esdhc_initialize(bis, &emmc_cfg); + if (ret) { + printf("Warning: failed to initialize mmc dev 1 (eMMC)\n"); + return ret; + } + + return 0; +} +#endif + +#ifdef CONFIG_SPL_BUILD +#include <libfdt.h> +#include <spl.h> +#include <asm/arch/mx6-ddr.h> + + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000008, + .dram_sdqs0 = 0x00000038, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00070007, + .p0_mpdgctrl0 = 0x41490145, + .p0_mprddlctl = 0x40404546, + .p0_mpwrdlctl = 0x4040524D, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, + .cs_density = 20, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 800, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + writel(0xFFFFFFFF, &ccm->CCGR7); +} + +static void spl_dram_init(void) +{ + unsigned long ram_size; + + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); + + /* + * Get actual RAM size, so we can adjust DDR row size for <512M + * memories + */ + ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, SZ_512M); + if (ram_size < SZ_512M) { + mem_ddr.rowaddr = 14; + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); + } +} + +void litesom_init_f(void) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + +#ifdef CONFIG_BOARD_EARLY_INIT_F + board_early_init_f(); +#endif + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* + * TODO: Based on README we should return here, as bss clear and board_init_r calls are not needed + */ + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif diff --git a/board/grinn/liteboard/Kconfig b/board/grinn/liteboard/Kconfig new file mode 100644 index 0000000..e035872 --- /dev/null +++ b/board/grinn/liteboard/Kconfig @@ -0,0 +1,12 @@ +if TARGET_LITEBOARD + +config SYS_BOARD + default "liteboard" + +config SYS_VENDOR + default "grinn" + +config SYS_CONFIG_NAME + default "liteboard" + +endif diff --git a/board/grinn/liteboard/MAINTAINERS b/board/grinn/liteboard/MAINTAINERS new file mode 100644 index 0000000..b4474f1 --- /dev/null +++ b/board/grinn/liteboard/MAINTAINERS @@ -0,0 +1,6 @@ +LITEBOARD +M: Marcin Niestroj <m.niestroj(a)grinn-global.com> +S: Maintained +F: board/grinn/liteboard/ +F: include/configs/liteboard.h +F: configs/liteboard_defconfig diff --git a/board/grinn/liteboard/Makefile b/board/grinn/liteboard/Makefile new file mode 100644 index 0000000..e2492d6 --- /dev/null +++ b/board/grinn/liteboard/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2016 Grinn +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o diff --git a/board/grinn/liteboard/README b/board/grinn/liteboard/README new file mode 100644 index 0000000..bee0394 --- /dev/null +++ b/board/grinn/liteboard/README @@ -0,0 +1,31 @@ +How to use U-Boot on Grinn's liteBoard +-------------------------------------- + +- Build U-Boot for liteBoard: + +$ make mrproper +$ make liteboard_defconfig +$ make + +This will generate the SPL image called SPL and the u-boot.img. + +- Flash the SPL image into the micro SD card: + +sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + +- Flash the u-boot.img image into the micro SD card: + +sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Jumper settings: + +S1: 0 1 0 1 1 1 + +where 0 means bottom position and 1 means top position (from the +switch label numbers reference). + +- Insert the micro SD card in the board. + +- Connect USB cable between liteBoard and the PC for the power and console. + +- U-Boot messages should come up. diff --git a/board/grinn/liteboard/board.c b/board/grinn/liteboard/board.c new file mode 100644 index 0000000..e375998 --- /dev/null +++ b/board/grinn/liteboard/board.c @@ -0,0 +1,271 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright (C) 2016 Grinn + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx6ul_pins.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/io.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <linux/sizes.h> +#include <linux/fb.h> +#include <litesom.h> +#include <miiphy.h> +#include <mmc.h> +#include <netdev.h> +#include <usb.h> +#include <usb/ehci-ci.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_ESDHC +static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4}; + +#define SD_CD_GPIO IMX_GPIO_NR(1, 19) + +static int mmc_get_env_devno(void) +{ + u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + int dev_no; + u32 bootsel; + + bootsel = (soc_sbmr & 0x000000FF) >> 6 ; + + /* If not boot from sd/mmc, use default value */ + if (bootsel != 1) + return CONFIG_SYS_MMC_ENV_DEV; + + /* BOOT_CFG2[3] and BOOT_CFG2[4] */ + dev_no = (soc_sbmr & 0x00001800) >> 11; + + return dev_no; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(SD_CD_GPIO); + break; + case USDHC2_BASE_ADDR: + ret = 1; + break; + } + + return ret; + +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + + /* SD */ + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_direction_input(SD_CD_GPIO); + sd_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + ret = fsl_esdhc_initialize(bis, &sd_cfg); + if (ret) { + printf("Warning: failed to initialize mmc dev 0 (SD)\n"); + return ret; + } + + return litesom_mmc_init(bis); +} + +static int check_mmc_autodetect(void) +{ + char *autodetect_str = getenv("mmcautodetect"); + + if ((autodetect_str != NULL) && + (strcmp(autodetect_str, "yes") == 0)) { + return 1; + } + + return 0; +} + +void board_late_mmc_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_devno(); + + if (!check_mmc_autodetect()) + return; + + setenv_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + dev_no); + setenv("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + setup_iomux_fec(); + + return fecmxc_initialize(bis); +} + +static int setup_fec(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], + set gpr1[17]*/ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(0, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +int board_usb_phy_mode(int port) +{ + return USB_INIT_HOST; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_init(); +#endif + + return 0; +} + +int checkboard(void) +{ + puts("Board: Grinn liteBoard\n"); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + litesom_init_f(); +} +#endif diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig new file mode 100644 index 0000000..f853461 --- /dev/null +++ b/configs/liteboard_defconfig @@ -0,0 +1,22 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_LITEBOARD=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg" +CONFIG_BOOTDELAY=1 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h new file mode 100644 index 0000000..67e159c --- /dev/null +++ b/include/configs/liteboard.h @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright (C) 2016 Grinn + * + * Configuration settings for the Grinn liteBoard (i.MX6UL). + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __LITEBOARD_CONFIG_H +#define __LITEBOARD_CONFIG_H + +#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> +#include "mx6_common.h" + +/* SPL options */ +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#include "imx6_spl.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#ifdef CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +#define CONFIG_DEFAULT_FDT_FILE "imx6ul-liteboard.dtb" + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_128M) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (8 * SZ_64K) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 0 +#define CONFIG_MMCROOT "/dev/mmcblk0p2" + +#define CONFIG_CMD_BMODE + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define CONFIG_FEC_ENET_DEV 0 + +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_PHYLIB +#define CONFIG_PHY_SMSC +#endif + +#define CONFIG_IMX_THERMAL + +#endif -- 2.9.3

2 2

[U-Boot] really weird return codes in mcf5373l.c, misc_init_r()
by Robert P. J. Day 14 Sep '16

14 Sep '16

ok, now i'm just being entertained by the truly strange code i'm running across. here's a snippet from board/astro/mcf5373l/mcf5373l.c; what strikes you as odd about it? int misc_init_r(void) { int retval = 0; puts("Configure Xilinx FPGA..."); retval = astro5373l_xilinx_load(); if (!retval) { puts("failed!\n"); return retval; } puts("done\n"); puts("Configure Altera FPGA..."); retval = astro5373l_altera_load(); if (!retval) { puts("failed!\n"); return retval; } puts("done\n"); return retval; } yes, if astro5373l_xilinx_load() returns zero, then "!retval" is true, at which point that call will have failed, and this routine will return ... zero. same with the code below that. so under what circumstances can that routine return zero? oh ... it can't: /* Initialize the fpga. Return 1 on success, 0 on failure. */ int astro5373l_xilinx_load(void) { int i; fpga_init(); for (i = 0; i < CONFIG_FPGA_COUNT; i++) { /* * I did not yet manage to get relocation work properly, * so set stuff here instead of static initialisation: */ xilinx_fns.pre = xilinx_pre_config_fn; xilinx_fns.pgm = xilinx_pgm_config_fn; xilinx_fns.clk = xilinx_clk_config_fn; xilinx_fns.init = xilinx_init_config_fn; xilinx_fns.done = xilinx_done_config_fn; xilinx_fns.wr = xilinx_wr_config_fn; xilinx_fns.bwr = xilinx_fastwr_config_fn; xilinx_fpga[i].iface_fns = (void *)&xilinx_fns; fpga_add(fpga_xilinx, &xilinx_fpga[i]); } return 1; i've seen other strange examples like this. rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

1 0

[U-Boot] eb_cpu5282.c board returns failure(?) from misc_init_r()
by Robert P. J. Day 14 Sep '16

14 Sep '16

i was just perusing the underlying code for invoking initcalls (mostly because i forgot to return the correct value, and bricked my target board), and i see this in lib/initcall.c: ret = (*init_fnc_ptr)(); if (ret) { printf("initcall sequence %p failed at call %p (err=%d)\n", init_sequence, (char *)*init_fnc_ptr - reloc_ofs, ret); return -1; } so, perfectly reasonably, if an initcall returns a non-zero value, that's failure, which is why misc_init_r() should, as long as everything succeeds, return zero, correct? but there's this in board/BuS/eb_cpu5282/eb_cpu5282.c: int misc_init_r(void) { #ifdef CONFIG_HW_WATCHDOG hw_watchdog_init(); #endif return 1; } i haven't dug into this any further to see if that's a special case, but isn't that going to return failure every time it's invoked? it may be that that board doesn't define the watchdog or the use of misc_init_r(), but that just seems ... wrong? thoughts? rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

1 0

[U-Boot] [PATCH 1/2] armv8/fsl-lsch2: refactor the clock system initialization
by Zhiqiang Hou 14 Sep '16

14 Sep '16

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Up to now, there are 3 kinds of SoC under Layerscape Chassis 2, such as LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of difference, for instance the IP modules have different divisors to get clock from Platform PLL. And the core cluster and platform PLL maybe have different reference clock, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Chissis 2. This patch is to map the sys_info->freq_systembus to the Platform PLL, and handle the different divisor of IP modules separately between different SoCs. And separate cluster and platform PLL reference clock. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> --- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 96 ++++++++++++++++++---- .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 + include/configs/ls1012a_common.h | 6 +- include/configs/ls1043a_common.h | 2 +- 4 files changed, 86 insertions(+), 19 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 8922197..4fb736d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -52,22 +52,28 @@ void get_sys_info(struct sys_info *sys_info) uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; + unsigned long cluster_clk; sys_info->freq_systembus = sysclk; +#ifdef CONFIG_CLUSTER_CLK_FREQ + cluster_clk = CONFIG_CLUSTER_CLK_FREQ; +#else + cluster_clk = sysclk; +#endif #ifdef CONFIG_DDR_CLK_FREQ sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; #else sys_info->freq_ddrbus = sysclk; #endif -#ifdef CONFIG_LS1012A - sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> - FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & - FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; -#else + /* The freq_systembus is used to record frequency of platform PLL */ sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; + +#ifdef CONFIG_LS1012A + sys_info->freq_ddrbus = 2 * sys_info->freq_systembus; +#else sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK; @@ -76,7 +82,7 @@ void get_sys_info(struct sys_info *sys_info) for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff; if (ratio[i] > 4) - freq_c_pll[i] = sysclk * ratio[i]; + freq_c_pll[i] = cluster_clk * ratio[i]; else freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; } @@ -91,11 +97,6 @@ void get_sys_info(struct sys_info *sys_info) freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } -#ifdef CONFIG_LS1012A - sys_info->freq_systembus = sys_info->freq_ddrbus / 2; - sys_info->freq_ddrbus *= 2; -#endif - #define HWA_CGA_M1_CLK_SEL 0xe0000000 #define HWA_CGA_M1_CLK_SHIFT 29 #ifdef CONFIG_SYS_DPAA_FMAN @@ -148,7 +149,11 @@ void get_sys_info(struct sys_info *sys_info) break; } #else +#ifdef CONFIG_LS1043A sys_info->freq_sdhc = sys_info->freq_systembus; +#elif defined(CONFIG_LS1046A) || defined(CONFIG_LS1012A) + sys_info->freq_sdhc = sys_info->freq_systembus / 2; +#endif #endif #endif @@ -156,7 +161,11 @@ void get_sys_info(struct sys_info *sys_info) ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; +#ifdef CONFIG_LS1043A sys_info->freq_localbus = sys_info->freq_systembus / ccr; +#elif defined(CONFIG_LS1046A) + sys_info->freq_localbus = sys_info->freq_systembus / 2 / ccr; +#endif #endif } @@ -179,41 +188,98 @@ int get_clocks(void) return 1; } +/******************************************** + * get_bus_freq + * return platform PLL freq in Hz + *********************************************/ ulong get_bus_freq(ulong dummy) { + if (!gd->bus_clk) + get_clocks(); + return gd->bus_clk; } ulong get_ddr_freq(ulong dummy) { + if (!gd->mem_clk) + get_clocks(); + return gd->mem_clk; } #ifdef CONFIG_FSL_ESDHC int get_sdhc_freq(ulong dummy) { + if (!gd->arch.sdhc_clk) + get_clocks(); + return gd->arch.sdhc_clk; } #endif int get_serial_clock(void) { - return gd->bus_clk; +#ifdef CONFIG_LS1043A + return get_bus_freq(0); +#elif defined(CONFIG_LS1046A) + return get_bus_freq(0) / 2; +#elif defined(CONFIG_LS1012A) + return get_bus_freq(0) / 4; +#else + return 0; +#endif +} + +int get_i2c_freq(ulong dummy) +{ +#ifdef CONFIG_LS1043A + return get_bus_freq(0); +#elif defined(CONFIG_LS1046A) + return get_bus_freq(0) / 2; +#elif defined(CONFIG_LS1012A) + return get_bus_freq(0) / 4; +#else + return 0; +#endif } +int get_dspi_freq(ulong dummy) +{ +#ifdef CONFIG_LS1043A + return get_bus_freq(0); +#elif defined(CONFIG_LS1046A) + return get_bus_freq(0) / 2; +#elif defined(CONFIG_LS1012A) + return get_bus_freq(0) / 4; +#else + return 0; +#endif +} + +int get_uart_freq(ulong dummy) +{ +#ifdef CONFIG_LS1043A + return get_bus_freq(0); +#elif defined(CONFIG_LS1046A) + return get_bus_freq(0) / 2; +#else + return 0; +#endif +} unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { case MXC_I2C_CLK: - return get_bus_freq(0); + return get_i2c_freq(0); #if defined(CONFIG_FSL_ESDHC) case MXC_ESDHC_CLK: return get_sdhc_freq(0); #endif case MXC_DSPI_CLK: - return get_bus_freq(0); + return get_dspi_freq(0); case MXC_UART_CLK: - return get_bus_freq(0); + return get_uart_freq(0); default: printf("Unsupported clock\n"); } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 95a4293..ee10765 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -136,6 +136,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; + /* frequency of platform PLL */ unsigned long freq_systembus; unsigned long freq_ddrbus; unsigned long freq_localbus; diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index fba2fac..928fd76 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -24,8 +24,8 @@ #define CONFIG_SYS_TEXT_BASE 0x40100000 #define CONFIG_SYS_FSL_CLK -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 125000000 +#define CONFIG_SYS_CLK_FREQ 125000000 +#define CONFIG_CLUSTER_CLK_FREQ 100000000 #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F 1 @@ -86,7 +86,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index e55fcb2..3b55699 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -50,7 +50,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -- 2.1.0.27.g96db324

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[U-Boot] tftp using ENC424J600
by Edward Wingate 14 Sep '16

14 Sep '16

Can u-boot currently do tftp using a Microchip ENC424J600? This is an ethernet over SPI module. Thanks for any information.

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