September 2016 - U-Boot

[U-Boot] [PATCH 1/5] arm: mvebu: add support for Synology DS109 board
by Walter Schweizer 20 Sep '16

20 Sep '16

Synology DS109 is based on MV88F6281. The code is based on Dreamplug code with modificatons from Synologys open source repository. Signed-off-by: Walter Schweizer <swwa(a)users.sourceforge.net> --- arch/arm/mach-kirkwood/Kconfig | 4 + board/Synology/ds109/Kconfig | 12 +++ board/Synology/ds109/Makefile | 9 ++ board/Synology/ds109/ds109.c | 169 ++++++++++++++++++++++++++++++++++++++ board/Synology/ds109/ds109.h | 44 ++++++++++ board/Synology/ds109/kwbimage.cfg | 147 +++++++++++++++++++++++++++++++++ board/Synology/ds109/openocd.cfg | 115 ++++++++++++++++++++++++++ configs/ds109_defconfig | 16 ++++ include/configs/ds109.h | 118 ++++++++++++++++++++++++++ 9 files changed, 634 insertions(+) create mode 100644 board/Synology/ds109/Kconfig create mode 100644 board/Synology/ds109/Makefile create mode 100644 board/Synology/ds109/ds109.c create mode 100644 board/Synology/ds109/ds109.h create mode 100644 board/Synology/ds109/kwbimage.cfg create mode 100644 board/Synology/ds109/openocd.cfg create mode 100644 configs/ds109_defconfig create mode 100644 include/configs/ds109.h diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 9205b1e..9c24921 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -10,6 +10,9 @@ config TARGET_OPENRD config TARGET_DREAMPLUG bool "DreamPlug Board" +config TARGET_DS109 + bool "Synology DS109" + config TARGET_GURUPLUG bool "GuruPlug Board" @@ -59,6 +62,7 @@ config SYS_SOC source "board/Marvell/openrd/Kconfig" source "board/Marvell/dreamplug/Kconfig" +source "board/Synology/ds109/Kconfig" source "board/Marvell/guruplug/Kconfig" source "board/Marvell/sheevaplug/Kconfig" source "board/buffalo/lsxl/Kconfig" diff --git a/board/Synology/ds109/Kconfig b/board/Synology/ds109/Kconfig new file mode 100644 index 0000000..a7c75ae --- /dev/null +++ b/board/Synology/ds109/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DS109 + +config SYS_BOARD + default "ds109" + +config SYS_VENDOR + default "Synology" + +config SYS_CONFIG_NAME + default "ds109" + +endif diff --git a/board/Synology/ds109/Makefile b/board/Synology/ds109/Makefile new file mode 100644 index 0000000..eeeb64d --- /dev/null +++ b/board/Synology/ds109/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := ds109.o diff --git a/board/Synology/ds109/ds109.c b/board/Synology/ds109/ds109.c new file mode 100644 index 0000000..8ab1387 --- /dev/null +++ b/board/Synology/ds109/ds109.c @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2009-2012 + * Wojciech Dubowik <wojciech.dubowik(a)neratec.com> + * Luka Perkov <luka(a)openwrt.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <asm/arch/mpp.h> +#include "ds109.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + mvebu_config_gpio(DS109_OE_VAL_LOW, + DS109_OE_VAL_HIGH, + DS109_OE_LOW, DS109_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + static const u32 kwmpp_config[] = { + MPP0_SPI_SCn, /* SPI Flash */ + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, + MPP4_GPIO, + MPP5_GPO, + MPP6_SYSRST_OUTn, /* Reset signal */ + MPP7_GPO, + MPP8_TW_SDA, /* I2C */ + MPP9_TW_SCK, /* I2C */ + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, + MPP13_UART1_TXD, + MPP14_UART1_RXD, + MPP15_GPIO, + MPP16_GPIO, + MPP17_GPIO, + MPP18_GPO, + MPP19_GPO, + MPP20_SATA1_ACTn, + MPP21_SATA0_ACTn, + MPP22_GPIO, /* HDD2 FAIL LED */ + MPP23_GPIO, /* HDD1 FAIL LED */ + MPP24_GPIO, + MPP25_GPIO, + MPP26_GPIO, + MPP27_GPIO, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GPIO, + MPP31_GPIO, /* HDD2 */ + MPP32_GPIO, /* FAN A */ + MPP33_GPIO, /* FAN B */ + MPP34_GPIO, /* FAN C */ + MPP35_GPIO, /* FAN SENSE */ + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_GPIO, + MPP41_GPIO, + MPP42_GPIO, + MPP43_GPIO, + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, + MPP48_GPIO, + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +/* Synology reset uses UART */ +#include <ns16550.h> +#define SOFTWARE_SHUTDOWN 0x31 +#define SOFTWARE_REBOOT 0x43 +#define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE +void reset_misc(void) +{ + int b_d; + printf("Synology reset..."); + udelay(50000); + + b_d = ns16550_calc_divisor((NS16550_t)CONFIG_SYS_NS16550_COM2, + CONFIG_SYS_NS16550_CLK, 9600); + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM2, b_d); + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM2, SOFTWARE_REBOOT); +} + +/* Support old kernels */ +void setup_board_tags(struct tag **in_params) +{ + unsigned int boardId; + struct tag *params; + struct tag_mv_uboot *t; + + printf("Synology board tags..."); + params = *in_params; + t = (struct tag_mv_uboot *)&params->u; + + t->uboot_version = VER_NUM; + + boardId = SYNO_DS109_ID; + t->uboot_version |= boardId; + + t->tclk = CONFIG_SYS_TCLK; + t->sysclk = CONFIG_SYS_TCLK*2; + + params->hdr.tag = ATAG_MV_UBOOT; + params->hdr.size = tag_size(tag_mv_uboot); + params = tag_next(params); + *in_params = params; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and enable MV88E1116 PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { + printf("Error: 88E1116 could not read PHY dev address\n"); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Synology/ds109/ds109.h b/board/Synology/ds109/ds109.h new file mode 100644 index 0000000..95d924c --- /dev/null +++ b/board/Synology/ds109/ds109.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2009-2012 + * Wojciech Dubowik <wojciech.dubowik(a)neratec.com> + * Luka Perkov <luka(a)openwrt.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DS109_H +#define __DS109_H + +#define DS109_OE_LOW (~(0)) +#define DS109_OE_HIGH (~(0)) +#define DS109_OE_VAL_LOW ((1 << 22)|(1 << 23)) +#define DS109_OE_VAL_HIGH ((1 << 1)|1) + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_MAC_CTRL2_REG 21 + +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +/* Marvell uboot parameters */ +#define ATAG_MV_UBOOT 0x41000403 +#define VER_NUM 0x03040400 /* 3.4.4 */ +#define BOARD_ID_BASE 0x0 +#define SYNO_DS109_ID (BOARD_ID_BASE+0x15) + +struct tag_mv_uboot { + u32 uboot_version; + u32 tclk; + u32 sysclk; + u32 isusbhost; + char macaddr[4][6]; + u16 mtu[4]; + u32 fw_image_base; + u32 fw_image_size; +}; + +#endif /* __DS109_H */ diff --git a/board/Synology/ds109/kwbimage.cfg b/board/Synology/ds109/kwbimage.cfg new file mode 100644 index 0000000..19d77e3 --- /dev/null +++ b/board/Synology/ds109/kwbimage.cfg @@ -0,0 +1,147 @@ +# +# (C) Copyright 2011 +# Jason Cooper <u-boot(a)lakedaemon.net> +# +# Based on work by: +# Marvell Semiconductor <www.marvell.com> +# Written-by: Siddarth Gore <gores(a)marvell.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.kwbimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0/1 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b9b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x000000cc # DDR Address Control +# bit1-0: 01, Cs0width=x8 +# bit3-2: 10, Cs0size=1Gb +# bit5-4: 01, Cs1width=x8 +# bit7-6: 10, Cs1size=1Gb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000C52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low) +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E803 # CPU ODT Control +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/Synology/ds109/openocd.cfg b/board/Synology/ds109/openocd.cfg new file mode 100644 index 0000000..baa512a --- /dev/null +++ b/board/Synology/ds109/openocd.cfg @@ -0,0 +1,115 @@ +# Synology DS109 + +interface ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x000b +ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010 +ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040 + +adapter_khz 2000 + +# length of reset signal: [ms] +adapter_nsrst_assert_width 1000 + +# don't talk to JTAG after reset for: [ms] +adapter_nsrst_delay 200 + +source [find target/feroceon.cfg] + +reset_config trst_and_srst srst_nogate + +proc ds109_init { } { + + # We need to assert DBGRQ while holding nSRST down. + # However DBGACK will be set only when nSRST is released. + # Furthermore, the JTAG interface doesn't respond at all when + # the CPU is in the WFI (wait for interrupts) state, so it is + # possible that initial tap examination failed. So let's + # re-examine the target again here when nSRST is asserted which + # should then succeed. + jtag_reset 0 1 + feroceon.cpu arp_examine + halt 0 + jtag_reset 0 0 + wait_halt + #reset run + #soft_reset_halt + + arm mcr 15 0 0 1 0 0x00052078 + + mww 0xD00100e0 0x1b1b1b9b ;# + mww 0xD0020134 0xbbbbbbbb ;# + mww 0xD0020138 0x00bbbbbb ;# + mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register + mww 0xD0001404 0x39743000 ;# Dunit Control Low Register + mww 0xD0001408 0x22125551 ;# DDR SDRAM Timing (Low) Register + mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register + mww 0xD0001410 0x0000000d ;# DDR SDRAM Address Control Register + mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register + mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register + mww 0xD000141C 0x00000C62 ;# DDR SDRAM Mode Register + mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register + mww 0xD0001424 0x0000F1FF ;# Dunit Control High Register + mww 0xD0001428 0x00085520 ;# Dunit Control High Register + mww 0xD000147c 0x00008552 ;# Dunit Control High Register + mww 0xD0001500 0x00000000 ;# + mww 0xD0001504 0x07FFFFF1 ;# CS0n Size Register + mww 0xD0001508 0x10000000 ;# CS1n Base Register + mww 0xD000150C 0x00000000 ;# CS1n Size Register + mww 0xD0001510 0x20000000 ;# + mww 0xD0001514 0x00000000 ;# CS2n Size Register + mww 0xD000151C 0x00000000 ;# CS3n Size Register + mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register + mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister + mww 0xD000149C 0x0000F80F ;# DDR2 Dunit ODT Control Register + mww 0xD0001480 0x00000001 ;# DDR SDRAM Initialization Control Register + mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + mww 0xD0020204 0x00000000 ;# " + + mww 0xD0010000 0x01111111 ;# MPP 0 to 7 + mww 0xD0010004 0x11113322 ;# MPP 8 to 15 + mww 0xD0010008 0x00001111 ;# MPP 16 to 23 +} + +proc ds109_load { } { + # load u-Boot into RAM and execute it + ds109_init + load_image u-boot.bin 0x00600000 bin + resume 0x00600000 +} diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig new file mode 100644 index 0000000..34a4673 --- /dev/null +++ b/configs/ds109_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_DS109=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SYS_NS16550=y diff --git a/include/configs/ds109.h b/include/configs/ds109.h new file mode 100644 index 0000000..987038f --- /dev/null +++ b/include/configs/ds109.h @@ -0,0 +1,118 @@ +/* + * (C) Copyright 2011 + * Jason Cooper <u-boot(a)lakedaemon.net> + * + * Based on work by: + * Marvell Semiconductor <www.marvell.com> + * Written-by: Siddarth Gore <gores(a)marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_DS109_H +#define _CONFIG_DS109_H + +/* + * FIXME: This belongs in mach-types.h. However, we only pull mach-types + * from Linus' kernel.org tree. This hasn't been updated primarily due to + * the recent arch/arm reshuffling. So, in the meantime, we'll place it + * here. + */ +#include <asm/mach-types.h> +#ifdef MACH_TYPE_SYNOLOGY +#error "MACH_TYPE_SYNOLOGY has been defined properly, please remove this." +#else +#define MACH_TYPE_SYNOLOGY 527 +#endif + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nDS109" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ +#define CONFIG_MACH_TYPE MACH_TYPE_SYNOLOGY + +/* + * Commands configuration + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +/* + * mv-plug-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-plug-common.h" + +/* + * Environment variables configurations + */ +#ifdef CONFIG_SPI_FLASH +#define CONFIG_ENV_IS_IN_SPI_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64k */ +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ +#endif + +#ifdef CONFIG_CMD_SF +#define CONFIG_HARD_SPI 1 +#define CONFIG_KIRKWOOD_SPI 1 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */ +#endif + +/* + * max 4k env size is enough, but in case of nand + * it has to be rounded to sector size + */ +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_ADDR 0x3d0000 +#define CONFIG_ENV_OFFSET 0x3d0000 /* env starts here */ + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \ + "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\ + "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ + "bootm 0x6400000;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "x_bootcmd_ethernet=ping 192.168.1.2\0" \ + "x_bootcmd_usb=usb start\0" \ + "x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \ + "x_bootargs=console=ttyS0,115200\0" \ + "x_bootargs_root=root=/dev/sda2 rootdelay=10\0" \ + "ipaddr=192.168.1.5\0" + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} /* enable one port */ +#define CONFIG_PHY_BASE_ADR 8 +#endif /* CONFIG_CMD_NET */ + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#endif /*CONFIG_MVSATA_IDE*/ + +#endif /* _CONFIG_DS109_H */ + +/* + * * RTC driver configuration + * */ +#ifdef CONFIG_CMD_DATE +#undef CONFIG_RTC_MV +#define CONFIG_RTC_RS5C372A +#endif /* CONFIG_CMD_DATE */ + + -- 2.1.4

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[U-Boot] [PATCH 1/3] ARM: tegra: fix USB ULPI PHY reset signal inversion confusion
by Stephen Warren 20 Sep '16

20 Sep '16

From: Stephen Warren <swarren(a)nvidia.com> USB ULPI PHY reset signals are typically active low. Consequently, they should be marked as GPIO_ACTIVE_LOW in device tree, and indeed they are in the Linux kernel DTs, and in DT properties that U-Boot doesn't yet use. However, in DT properties that U-Boot does use, the value has been set to 0 (== GPIO_ACTIVE_HIGH) to work around a bug in U-Boot. This change fixes the DT to correctly represent the HW, and fixes the Tegra USB driver to cope with the fact that dm_gpio_set_value() internally handles any inversions implied by the DT value GPIO_ACTIVE_LOW. Cc: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- arch/arm/dts/tegra20-colibri.dts | 3 ++- arch/arm/dts/tegra20-harmony.dts | 3 ++- drivers/usb/host/ehci-tegra.c | 13 +++++++++++-- 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/tegra20-colibri.dts b/arch/arm/dts/tegra20-colibri.dts index a291d93c7d01..777f63e5bdb6 100644 --- a/arch/arm/dts/tegra20-colibri.dts +++ b/arch/arm/dts/tegra20-colibri.dts @@ -39,7 +39,8 @@ usb@c5004000 { statuc = "okay"; /* VBUS_LAN */ - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts index cace74339483..5aec150b5e61 100644 --- a/arch/arm/dts/tegra20-harmony.dts +++ b/arch/arm/dts/tegra20-harmony.dts @@ -626,7 +626,8 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>; + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) + GPIO_ACTIVE_LOW>; }; usb-phy@c5004000 { diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 31d54ab285bf..c10597861873 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -600,9 +600,18 @@ static int init_ulpi_usb_controller(struct fdt_usb *config, /* reset ULPI phy */ if (dm_gpio_is_valid(&config->phy_reset_gpio)) { - dm_gpio_set_value(&config->phy_reset_gpio, 0); - mdelay(5); + /* + * This GPIO is typically active-low, and marked as such in + * device tree. dm_gpio_set_value() takes this into account + * and inverts the value we pass here if required. In other + * words, this first call logically asserts the reset signal, + * which typically results in driving the physical GPIO low, + * and the second call logically de-asserts the reset signal, + * which typically results in driver the GPIO high. + */ dm_gpio_set_value(&config->phy_reset_gpio, 1); + mdelay(5); + dm_gpio_set_value(&config->phy_reset_gpio, 0); } /* Reset the usb controller */ -- 2.9.3

3 6

[U-Boot] [PATCH 0/2] Add sdram capacity auto detect for rk3288
by Kever Yang 20 Sep '16

20 Sep '16

The rk3288 spl size is very close to 32KB while the rk3288 bootrom has the limitation of maximum size of SPL is 32KB. After apply this patch, the SPL size will exceed 32KB if we do not enable macro CONFIG_ROCKCHIP_SPL_BACK_TO_BROM. I think this patch is usful and should be go upstream other than the size issue. This patch has test with 2GB DDR3 and 2GB/4GB LPDDR3. Kever Yang (2): rk3288: sdram: auto-detect the capacity dts: rk3288: remove node in dmc which not need anymore arch/arm/dts/rk3288-evb.dts | 3 - arch/arm/dts/rk3288-fennec.dts | 3 - arch/arm/dts/rk3288-firefly.dts | 2 - arch/arm/dts/rk3288-miniarm.dts | 3 - arch/arm/dts/rk3288-popmetal.dts | 3 - arch/arm/dts/rk3288-rock2-square.dts | 2 - arch/arm/dts/rk3288-veyron.dtsi | 2 - arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 237 ++++++++++++++++++++++----- 8 files changed, 198 insertions(+), 57 deletions(-) -- 1.9.1

4 12

[U-Boot] [PATCH v2 00/17] imx6: Add Engicam i.CoreM6 QDL modules support
by Jagan Teki 20 Sep '16

20 Sep '16

This series supports Engicam i.CoreM6 QDL modules on top of u-boot-imx.git/next and test on the respective starter kits as well. Changes for v2: - Make static to local iomux structure in board file - Corrected rowaddr in mx6_ddr3_cfg - Used imx_ddr_size - Add FEC support and tested the same - Add DM_GPIO, DM_MMC support - Add pinctrl support - Add devicetree support Jagan Teki (17): imx: iomux-v3: Fix build error with snvs base serial: Kconfig: Add MXC_UART entry thermal: Kconfig: Add IMX_THERMAL entry Kconfig: Add DEFAULT_FDT_FILE entry arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial support imx6: icorem6: Add ENET support imx: s/docs\/README.imximage/doc\/README.imximage/g arm: dts: Add devicetree for i.MX6DL arm: dts: Add devicetree for i.MX6DQL arm: dts: imx6dl: Add pinctrl defines dt-bindings: clock: imx6qdl: Add clock defines arm: imx6q: Add devicetree support for Engicam i.CoreM6 DualLite/Solo imx6q: icorem6: Enable pinctrl driver engicam: icorem6: Add DM_GPIO, DM_MMC support arm: dts: Add devicetree for i.MX6Q arm: dts: imx6q: Add pinctrl defines arm: imx6q: Add devicetree support for Engicam i.CoreM6 Quad/Dual arch/arm/cpu/armv7/mx6/Kconfig | 11 + arch/arm/dts/Makefile | 4 +- arch/arm/dts/imx6dl-icore.dts | 59 ++ arch/arm/dts/imx6dl-pinfunc.h | 1091 +++++++++++++++++++++++ arch/arm/dts/imx6dl.dtsi | 133 +++ arch/arm/dts/imx6q-icore.dts | 59 ++ arch/arm/dts/imx6q-pinfunc.h | 1047 ++++++++++++++++++++++ arch/arm/dts/imx6q.dtsi | 300 +++++++ arch/arm/dts/imx6qdl-icore.dtsi | 234 +++++ arch/arm/dts/imx6qdl.dtsi | 1281 +++++++++++++++++++++++++++ arch/arm/imx-common/iomux-v3.c | 2 +- board/barco/titanium/imximage.cfg | 2 +- board/ccv/xpress/imximage.cfg | 2 +- board/denx/m53evk/imximage.cfg | 2 +- board/engicam/icorem6/Kconfig | 12 + board/engicam/icorem6/MAINTAINERS | 6 + board/engicam/icorem6/Makefile | 6 + board/engicam/icorem6/README | 38 + board/engicam/icorem6/icorem6.c | 474 ++++++++++ board/freescale/mx6sabresd/mx6dlsabresd.cfg | 2 +- board/freescale/mx6slevk/imximage.cfg | 2 +- board/freescale/mx6ullevk/imximage.cfg | 2 +- board/freescale/mx7dsabresd/imximage.cfg | 2 +- board/freescale/s32v234evb/s32v234evb.cfg | 2 +- board/freescale/vf610twr/imximage.cfg | 2 +- board/phytec/pcm052/imximage.cfg | 2 +- board/technexion/pico-imx6ul/imximage.cfg | 2 +- board/toradex/colibri_imx7/imximage.cfg | 2 +- board/toradex/colibri_vf/imximage.cfg | 2 +- board/warp/imximage.cfg | 2 +- board/warp7/imximage.cfg | 2 +- common/Kconfig | 6 + configs/imx6qdl_icore_defconfig | 32 + drivers/serial/Kconfig | 7 + drivers/thermal/Kconfig | 13 + include/configs/imx6qdl_icore.h | 131 +++ include/dt-bindings/clock/imx6qdl-clock.h | 274 ++++++ 37 files changed, 5233 insertions(+), 17 deletions(-) create mode 100644 arch/arm/dts/imx6dl-icore.dts create mode 100644 arch/arm/dts/imx6dl-pinfunc.h create mode 100644 arch/arm/dts/imx6dl.dtsi create mode 100644 arch/arm/dts/imx6q-icore.dts create mode 100644 arch/arm/dts/imx6q-pinfunc.h create mode 100644 arch/arm/dts/imx6q.dtsi create mode 100644 arch/arm/dts/imx6qdl-icore.dtsi create mode 100644 arch/arm/dts/imx6qdl.dtsi create mode 100644 board/engicam/icorem6/Kconfig create mode 100644 board/engicam/icorem6/MAINTAINERS create mode 100644 board/engicam/icorem6/Makefile create mode 100644 board/engicam/icorem6/README create mode 100644 board/engicam/icorem6/icorem6.c create mode 100644 configs/imx6qdl_icore_defconfig create mode 100644 include/configs/imx6qdl_icore.h create mode 100644 include/dt-bindings/clock/imx6qdl-clock.h -- 2.7.4

4 31

[U-Boot] [PATCH] WIP: usb: xhci-pci: Add DM support
by Stefan Roese 20 Sep '16

20 Sep '16

This patch adds DM support to the xHCI PCI driver. Enabling its use e.g. in x86 platforms. Status: On the congatec BayTrail SoM, xHCI still does not work correctly with this patch. Some internal timeouts lead to resets (BUG). Additional work is needed here. I'm posting this version as WIP so that other developers interested in this support might use it as a start. I might get back to it in a few weeks as well. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: George McCollister <george.mccollister(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> --- drivers/usb/host/xhci-pci.c | 81 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index 361fcce..63daaa6 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -7,12 +7,15 @@ */ #include <common.h> +#include <dm.h> #include <errno.h> #include <pci.h> #include <usb.h> #include "xhci.h" +#ifndef CONFIG_DM_USB + /* * Create the appropriate control structures to manage a new XHCI host * controller. @@ -58,3 +61,81 @@ int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, void xhci_hcd_stop(int index) { } + +#else + +struct xhci_pci_priv { + struct xhci_ctrl ctrl; /* Needs to come first in this struct! */ +}; + +static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr, + struct xhci_hcor **ret_hcor) +{ + struct xhci_hccr *hccr; + struct xhci_hcor *hcor; + u32 cmd; + + hccr = (struct xhci_hccr *)dm_pci_map_bar(dev, + PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + hcor = (struct xhci_hcor *)((uintptr_t) hccr + + HC_LENGTH(xhci_readl(&hccr->cr_capbase))); + + debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n", + (u32)hccr, (u32)hcor, + (u32)HC_LENGTH(xhci_readl(&hccr->cr_capbase))); + + *ret_hccr = hccr; + *ret_hcor = hcor; + + /* enable busmaster */ + dm_pci_read_config32(dev, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER; + dm_pci_write_config32(dev, PCI_COMMAND, cmd); +} + +static int xhci_pci_probe(struct udevice *dev) +{ + struct xhci_hccr *hccr; + struct xhci_hcor *hcor; + + xhci_pci_init(dev, &hccr, &hcor); + + return xhci_register(dev, hccr, hcor); +} + +static int xhci_pci_remove(struct udevice *dev) +{ + int ret; + + ret = xhci_deregister(dev); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id xhci_pci_ids[] = { + { .compatible = "xhci-pci" }, + { } +}; + +U_BOOT_DRIVER(xhci_pci) = { + .name = "xhci_pci", + .id = UCLASS_USB, + .probe = xhci_pci_probe, + .remove = xhci_pci_remove, + .of_match = xhci_pci_ids, + .ops = &xhci_usb_ops, + .platdata_auto_alloc_size = sizeof(struct usb_platdata), + .priv_auto_alloc_size = sizeof(struct xhci_pci_priv), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; + +static struct pci_device_id xhci_pci_supported[] = { + { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0) }, + {}, +}; + +U_BOOT_PCI_DEVICE(xhci_pci, xhci_pci_supported); + +#endif /* CONFIG_DM_USB */ -- 2.9.2

3 3

[U-Boot] [PATCH] cmd/fdt: add possibilty to have 'extrasize' on fdt resize
by Hannes Schmelzer 20 Sep '16

20 Sep '16

Sometimes devicetree nodes and or properties are added out of the u-boot console, maybe through some script or manual interaction. The devicetree as loaded or embedded is quite small, so the devicetree has to be resized to take up those new nodes/properties. In original the devicetree was only extended by effective 4 * add_mem_rsv. With this commit we can add an argument to the "fdt resize" command, which takes the extrasize to be added. Signed-off-by: Hannes Schmelzer <hannes.schmelzer(a)br-automation.com> --- board/compulab/cm_fx6/cm_fx6.c | 2 +- cmd/fdt.c | 9 +++++++-- common/fdt_support.c | 3 ++- common/image-fdt.c | 2 +- include/fdt_support.h | 2 +- 5 files changed, 12 insertions(+), 6 deletions(-) diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index 566c19b..fbd6226 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -602,7 +602,7 @@ int ft_board_setup(void *blob, bd_t *bd) char baseboard_name[16]; int err; - fdt_shrink_to_minimum(blob); /* Make room for new properties */ + fdt_shrink_to_minimum(blob, 0); /* Make room for new properties */ /* MAC addr */ if (eth_getenv_enetaddr("ethaddr", enetaddr)) { diff --git a/cmd/fdt.c b/cmd/fdt.c index 58af772..b503357 100644 --- a/cmd/fdt.c +++ b/cmd/fdt.c @@ -662,7 +662,12 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif /* resize the fdt */ else if (strncmp(argv[1], "re", 2) == 0) { - fdt_shrink_to_minimum(working_fdt); + uint extrasize; + if (argc > 2) + extrasize = simple_strtoul(argv[2], NULL, 16); + else + extrasize = 0; + fdt_shrink_to_minimum(working_fdt, extrasize); } else { /* Unrecognized command */ @@ -1056,7 +1061,7 @@ static char fdt_help_text[] = "fdt systemsetup - Do system-specific set up\n" #endif "fdt move <fdt> <newaddr> <length> - Copy the fdt to <addr> and make it active\n" - "fdt resize - Resize fdt to size + padding to 4k addr\n" + "fdt resize [<extrasize>] - Resize fdt to size + padding to 4k addr + some optional <extrasize> if needed\n" "fdt print <path> [<prop>] - Recursive print starting at <path>\n" "fdt list <path> [<prop>] - Print one level starting at <path>\n" "fdt get value <var> <path> <prop> - Get <property> and store in <var>\n" diff --git a/common/fdt_support.c b/common/fdt_support.c index 2020586..0609470 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -523,7 +523,7 @@ void fdt_fixup_ethernet(void *fdt) } /* Resize the fdt to its actual size + a bit of padding */ -int fdt_shrink_to_minimum(void *blob) +int fdt_shrink_to_minimum(void *blob, uint extrasize) { int i; uint64_t addr, size; @@ -551,6 +551,7 @@ int fdt_shrink_to_minimum(void *blob) actualsize = fdt_off_dt_strings(blob) + fdt_size_dt_strings(blob) + 5 * sizeof(struct fdt_reserve_entry); + actualsize += extrasize; /* Make it so the fdt ends on a page boundary */ actualsize = ALIGN(actualsize + ((uintptr_t)blob & 0xfff), 0x1000); actualsize = actualsize - ((uintptr_t)blob & 0xfff); diff --git a/common/image-fdt.c b/common/image-fdt.c index d6ee225..2ef1253 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -503,7 +503,7 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, lmb_free(lmb, (phys_addr_t)(u32)(uintptr_t)blob, (phys_size_t)fdt_totalsize(blob)); - ret = fdt_shrink_to_minimum(blob); + ret = fdt_shrink_to_minimum(blob, 0); if (ret < 0) goto err; of_size = ret; diff --git a/include/fdt_support.h b/include/fdt_support.h index e9f3497..2957fbc 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -167,7 +167,7 @@ void ft_pci_setup(void *blob, bd_t *bd); int ft_system_setup(void *blob, bd_t *bd); void set_working_fdt_addr(ulong addr); -int fdt_shrink_to_minimum(void *blob); +int fdt_shrink_to_minimum(void *blob, uint extrasize); int fdt_increase_size(void *fdt, int add_len); int fdt_fixup_nor_flash_size(void *blob); -- 1.9.1

3 2

[U-Boot] [PATCH 0/2] Add TOPIC Miami boards
by Mike Looijmans 20 Sep '16

20 Sep '16

These patches add support for the Miami range of boards from TOPIC. The boards are based on Xilinx Zynq SoCs, these two patches are for the 7-series, the Ultrascale MPSOC boards are to be added later. Please note that the "ps7_init_gpl" files are largely generated by a tool and as a result of that, contain many style issues. Mike Looijmans (2): Add topic-miami board support Add topic_miamiplus board arch/arm/dts/Makefile | 2 + arch/arm/dts/zynq-topic-miami.dts | 98 + arch/arm/dts/zynq-topic-miamiplus.dts | 22 + board/xilinx/zynq/zynq-topic-miami/ps7_init_gpl.c | 4324 +++++++++++++++++++ board/xilinx/zynq/zynq-topic-miami/ps7_init_gpl.h | 118 + .../zynq/zynq-topic-miamiplus/ps7_init_gpl.c | 4425 ++++++++++++++++++++ .../zynq/zynq-topic-miamiplus/ps7_init_gpl.h | 150 + configs/topic_miami_defconfig | 47 + configs/topic_miamiplus_defconfig | 47 + include/configs/topic_miami.h | 147 + include/configs/topic_miamiplus.h | 2 + 11 files changed, 9382 insertions(+) create mode 100644 arch/arm/dts/zynq-topic-miami.dts create mode 100644 arch/arm/dts/zynq-topic-miamiplus.dts create mode 100644 board/xilinx/zynq/zynq-topic-miami/ps7_init_gpl.c create mode 100644 board/xilinx/zynq/zynq-topic-miami/ps7_init_gpl.h create mode 100644 board/xilinx/zynq/zynq-topic-miamiplus/ps7_init_gpl.c create mode 100644 board/xilinx/zynq/zynq-topic-miamiplus/ps7_init_gpl.h create mode 100644 configs/topic_miami_defconfig create mode 100644 configs/topic_miamiplus_defconfig create mode 100644 include/configs/topic_miami.h create mode 100644 include/configs/topic_miamiplus.h -- 1.9.1

2 8

[U-Boot] [PATCH v6] spi: pl022_spi: Add support for ARM PL022 spi controller
by Michael Brandl 20 Sep '16

20 Sep '16

Dear U-Boot (SPI) Developers, this patch seems to be my only chance to get spi working without/before Linux. I'm a student from Augsburg (Germany) experimenting with the Hikey Board from 96boards. The hi6220 processor from HiSilicon isn't fully documented, there is just one document called Function Description: http://mirror.lemaker.org/Hi6220V100_Multi-Mode_Application_Processor_Funct… U-Boot already supports the Hikey Board to be loaded from ARM Trusted Firmware (ATF) but only UART and SDMMC is supported by now. I cloned the u-boot-spi.git and tried to integrate this patch but I'm not experienced enough to adjust the specific config for the Hikey Board. Taking a look at armv7 devices with spi support I started like this: +++ b/arch/arm/include/asm/arch-hi6220/hi6220.h +/*Hi6220V100_Multi-Mode_Application_Processor_Function_Description on p.5-45*/ +#define HI6220_SPI_BASE 0xF7106000 +++ b/include/configs/hikey.h +/* Synchronous Serial Port PL022 for SPI */ +#define CONFIG_PL022_SPI +++ b/board/hisilicon/hikey/hikey.c int board_init(void) { +#ifdef CONFIG_PL022_SPI + hikey_spi0_hw_init(); +#endif return 0; } +static void hikey_spi0_hw_init(void) +{ + hi6220_pinmux_config(PERIPH_ID_SPI0) +// at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ + gpio_request(0, "PWR_HOLD_GPIO0_0"); + gpio_direction_output(0, 1); + + /* Enable clock */ +// at91_periph_clk_enable(ATMEL_ID_SPI0); +/* from Kernel { HI6220_SPI_CLK, "spi_clk", "clk_150m", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 9, 0, }, */ + hi6220_clk_enable(PERI_CLK0_SPI0, &peri_sc->clk3_en); + +} +#endif /* CONFIG_PL022_SPI */ + +++ b/arch/arm/cpu/armv8/hisilicon/pinmux.c +static void hi6220_spi_config(int peripheral) +{ + switch (peripheral) { + case PERIPH_ID_SPI0: +// at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ +// at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ +// at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ + break; + + case PERIPH_ID_SPI1: + break; + + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return; + } +} Maybe you can help me to get spi working on Hikey. My overall aim is to port the pl022 driver then to ARM TF ... maybe also that could be interessing for you. With kind Regards, Michael Brandl On Wed, Jan 8, 2014 at 2:49 PM, Armando Visconti <armando.visconti at st.com <http://lists.denx.de/mailman/listinfo/u-boot>> wrote: >/Hello Jagan, />//>/Sorry for late reply. />//>//>//>/On 12/20/2013 8:03 PM, Jagan Teki wrote: />>//>>/On Fri, Oct 4, 2013 at 12:20 PM, Jagan Teki <jagannadh.teki at gmail.com <http://lists.denx.de/mailman/listinfo/u-boot>> />>/wrote: />>>//>>>/Hi Vipin, />>>//>>>/I have few quick comments, please fix it. />>>/Please use the u-boot-spi.git with master-probe branch for testing this />>>/driver. />>>/Let me know for any issues/concerns. />>>//>>>/On Wed, Jun 12, 2013 at 7:55 PM, Jagan Teki <jagannadh.teki at gmail.com <http://lists.denx.de/mailman/listinfo/u-boot>> />>>/wrote: />>>>//>>>>/Thanks for v6 sent. />>>>//>>>>/Have you tested this? />>>>/on which board, include/configs/*.h file? />>>>//>>>>/-- />>>>/Thanks, />>>>/Jagan. />>>>//>>>>/On Wed, Jun 12, 2013 at 6:17 PM, Armando Visconti />>>>/<armando.visconti at st.com <http://lists.denx.de/mailman/listinfo/u-boot>> wrote: />>>>>//>>>>>/This patch adds the support for the ARM PL022 SPI controller for the />>>>>/standard />>>>>/variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX />>>>>/FIFO. />>>>>//>>>>>/Signed-off-by: Armando Visconti <armando.visconti at st.com <http://lists.denx.de/mailman/listinfo/u-boot>> />>>>>/Signed-off-by: Vipin Kumar <vipin.kumar at st.com <http://lists.denx.de/mailman/listinfo/u-boot>> />>>>>/Acked-by: Stefan Roese <sr at denx.de <http://lists.denx.de/mailman/listinfo/u-boot>> />>>>>/--- />>>>>/v5->v6 />>>>>//>>>>>/1. Make use of spi_alloc_slave() macro. />>>>>/2. Changed the identation on 'if statement' as requested />>>>>/by Jagan. />>>>>//>>>>>/drivers/spi/Makefile | 1 + />>>>>/drivers/spi/pl022_spi.c | 308 />>>>>/++++++++++++++++++++++++++++++++++++++++++++++++ />>>>>/2 files changed, 309 insertions(+) />>>>>/create mode 100644 drivers/spi/pl022_spi.c />>>>>//>>>>>/diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile />>>>>/index d08609e..b6443b1 100644 />>>>>/--- a/drivers/spi/Makefile />>>>>/+++ b/drivers/spi/Makefile />>>>>/@@ -47,6 +47,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o />>>>>/COBJS-$(CONFIG_MXS_SPI) += mxs_spi.o />>>>>/COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o />>>>>/COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o />>>>>/+COBJS-$(CONFIG_PL022_SPI) += pl022_spi.o />>>>>/COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o />>>>>/COBJS-$(CONFIG_SH_SPI) += sh_spi.o />>>>>/COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o />>>>>/diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c />>>>>/new file mode 100644 />>>>>/index 0000000..5b47413 />>>>>/--- /dev/null />>>>>/+++ b/drivers/spi/pl022_spi.c />>>>>/@@ -0,0 +1,308 @@ />>>>>/+/* />>>>>/+ * (C) Copyright 2012 />>>>>/+ * Armando Visconti, ST Microelectronics, armando.visconti at st.com. <http://lists.denx.de/mailman/listinfo/u-boot> />>>>>/+ * />>>>>/+ * Driver for ARM PL022 SPI Controller. Based on atmel_spi.c />>>>>/+ * by Atmel Corporation. />>>>>/+ * />>>>>/+ * This program is free software; you can redistribute it and/or />>>>>/+ * modify it under the terms of the GNU General Public License as />>>>>/+ * published by the Free Software Foundation; either version 2 of />>>>>/+ * the License, or (at your option) any later version. />>>>>/+ * />>>>>/+ * This program is distributed in the hope that it will be useful, />>>>>/+ * but WITHOUT ANY WARRANTY; without even the implied warranty of />>>>>/+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the />>>>>/+ * GNU General Public License for more details. />>>>>/+ * />>>>>/+ * You should have received a copy of the GNU General Public License />>>>>/+ * along with this program; if not, write to the Free Software />>>>>/+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, />>>>>/+ * MA 02111-1307 USA />>>>>/+ */ />>>//>>>/Use latest SPDX-License-Identifier: />>>/check for any existing one. />>>//>>>>>/+ />>>>>/+#include <common.h> />>>>>/+#include <malloc.h> />>>>>/+#include <spi.h> />>>>>/+#include <asm/io.h> />>>>>/+#include <asm/arch/hardware.h> />>>>>/+ />>>>>/+/* SSP registers mapping */ />>>>>/+struct pl022 { />>>//>>>/Something like pl022_spi_regs />>>//>>>>>/+ u32 ssp_cr0; /* 0x000 */ />>>>>/+ u32 ssp_cr1; /* 0x004 */ />>>>>/+ u32 ssp_dr; /* 0x008 */ />>>>>/+ u32 ssp_sr; /* 0x00c */ />>>>>/+ u32 ssp_cpsr; /* 0x010 */ />>>>>/+ u32 ssp_imsc; /* 0x014 */ />>>>>/+ u32 ssp_ris; /* 0x018 */ />>>>>/+ u32 ssp_mis; /* 0x01c */ />>>>>/+ u32 ssp_icr; /* 0x020 */ />>>>>/+ u32 ssp_dmacr; /* 0x024 */ />>>>>/+ u8 reserved_1[0x080 - 0x028]; />>>>>/+ u32 ssp_itcr; /* 0x080 */ />>>>>/+ u32 ssp_itip; /* 0x084 */ />>>>>/+ u32 ssp_itop; /* 0x088 */ />>>>>/+ u32 ssp_tdr; /* 0x08c */ />>>>>/+ u8 reserved_2[0xFE0 - 0x090]; />>>>>/+ u32 ssp_pid0; /* 0xfe0 */ />>>>>/+ u32 ssp_pid1; /* 0xfe4 */ />>>>>/+ u32 ssp_pid2; /* 0xfe8 */ />>>>>/+ u32 ssp_pid3; /* 0xfec */ />>>>>/+ u32 ssp_cid0; /* 0xff0 */ />>>>>/+ u32 ssp_cid1; /* 0xff4 */ />>>>>/+ u32 ssp_cid2; /* 0xff8 */ />>>>>/+ u32 ssp_cid3; /* 0xffc */ />>>>>/+}; />>>>>/+ />>>//>>>/-- TAG+ />>>>>//>>>>>/+/* SSP Control Register 0 - SSP_CR0 */ />>>>>/+#define SSP_CR0_SPO (0x1 << 6) />>>>>/+#define SSP_CR0_SPH (0x1 << 7) />>>>>/+#define SSP_CR0_8BIT_MODE (0x07) />>>>>/+#define SSP_SCR_MAX (0xFF) />>>>>/+#define SSP_SCR_SHFT 8 />>>>>/+ />>>>>/+/* SSP Control Register 0 - SSP_CR1 */ />>>>>/+#define SSP_CR1_MASK_SSE (0x1 << 1) />>>>>/+ />>>>>/+#define SSP_CPSR_MAX (0xFE) />>>>>/+ />>>>>/+/* SSP Status Register - SSP_SR */ />>>>>/+#define SSP_SR_MASK_TFE (0x1 << 0) /* Transmit FIFO />>>>>/empty */ />>>>>/+#define SSP_SR_MASK_TNF (0x1 << 1) /* Transmit FIFO not />>>>>/full */ />>>>>/+#define SSP_SR_MASK_RNE (0x1 << 2) /* Receive FIFO not />>>>>/empty */ />>>>>/+#define SSP_SR_MASK_RFF (0x1 << 3) /* Receive FIFO full />>>>>/*/ />>>>>/+#define SSP_SR_MASK_BSY (0x1 << 4) /* Busy Flag */ />>>>>/+ />>>//>>>/--- TAG - />>>//>>>/Bit mask macros - please place after headers. />>>/We follow a simple format to write spi driver - please check />>>/http://patchwork.ozlabs.org/patch/265683/ />>>//>>>/And try to verify your code w.r.t above format - let me know any />>>/comments. />>>//>>>>>/+struct pl022_spi_slave { />>>>>/+ struct spi_slave slave; />>>>>/+ void *regs; />>>//>>>/Please use the structure pointer instead of void. />>>//>>>>>/+ unsigned int freq; />>>>>/+}; />>>>>/+ />>>>>/+static inline struct pl022_spi_slave *to_pl022_spi(struct spi_slave />>>>>/*slave) />>>>>/+{ />>>>>/+ return container_of(slave, struct pl022_spi_slave, slave); />>>>>/+} />>>>>/+ />>>>>/+/* />>>>>/+ * Following three functions should be provided by the />>>>>/+ * board support package. />>>>>/+ */ />>>>>/+int __weak spi_cs_is_valid(unsigned int bus, unsigned int cs) />>>>>/+{ />>>>>/+ return 1; />>>>>/+} />>>>>/+ />>>>>/+void __weak spi_cs_activate(struct spi_slave *slave) />>>>>/+{ />>>>>/+ /* do nothing */ />>>>>/+} />>>>>/+ />>>>>/+void __weak spi_cs_deactivate(struct spi_slave *slave) />>>>>/+{ />>>>>/+ /* do nothing */ />>>>>/+} />>>>>/+ />>>>>/+void spi_init(void) />>>>>/+{ />>>>>/+ /* do nothing */ />>>>>/+} />>>>>/+ />>>>>/+/* />>>>>/+ * ARM PL022 exists in different 'flavors'. />>>>>/+ * This drivers currently support the standard variant (0x00041022), />>>>>/that has a />>>>>/+ * 16bit wide and 8 locations deep TX/RX FIFO. />>>>>/+ */ />>>>>/+static int pl022_is_supported(struct pl022_spi_slave *ps) />>>>>/+{ />>>>>/+ struct pl022 *pl022 = (struct pl022 *)ps->regs; />>>>>/+ />>>>>/+ /* PL022 version is 0x00041022 */ />>>>>/+ if ((readl(&pl022->ssp_pid0) == 0x22) && />>>>>/+ (readl(&pl022->ssp_pid1) == 0x10) && />>>>>/+ ((readl(&pl022->ssp_pid2) & 0xf) == 0x04) && />>>>>/+ (readl(&pl022->ssp_pid3) == 0x00)) />>>>>/+ return 1; />>>>>/+ />>>>>/+ return 0; />>>>>/+} />>>>>/+ />>>>>/+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, />>>>>/+ unsigned int max_hz, unsigned int mode) />>>>>/+{ />>>>>/+ struct pl022_spi_slave *ps; />>>>>/+ struct pl022 *pl022; />>>>>/+ u16 scr = 1, prescaler, cr0 = 0, cpsr = 0; />>>>>/+ />>>>>/+ if (!spi_cs_is_valid(bus, cs)) />>>>>/+ return NULL; />>>>>/+ />>>>>/+ ps = spi_alloc_slave(struct pl022_spi_slave, bus, cs); />>>>>/+ if (!ps) />>>>>/+ return NULL; />>>>>/+ />>>>>/+ ps->freq = max_hz; />>>>>/+ />>>>>/+ switch (bus) { />>>>>/+ case 0: />>>>>/+ ps->regs = (void *)CONFIG_SYS_SPI_BASE; />>>>>/+ break; />>>>>/+#ifdef CONFIG_SYS_SPI_BASE1 />>>>>/+ case 1: />>>>>/+ ps->regs = (void *)CONFIG_SYS_SPI_BASE1; />>>>>/+ break; />>>>>/+#endif />>>>>/+#ifdef CONFIG_SYS_SPI_BASE2 />>>>>/+ case 2: />>>>>/+ ps->regs = (void *)CONFIG_SYS_SPI_BASE2; />>>>>/+ break; />>>>>/+#endif />>>>>/+#ifdef CONFIG_SYS_SPI_BASE3 />>>>>/+ case 3: />>>>>/+ ps->regs = (void *)CONFIG_SYS_SPI_BASE3; />>>>>/+ break; />>>>>/+#endif />>>>>/+ default: />>>>>/+ free(ps); />>>>>/+ return NULL; />>>>>/+ } />>>>>/+ />>>>>/+ pl022 = (struct pl022 *)ps->regs; />>>>>/+ />>>>>/+ /* Check the PL022 version */ />>>>>/+ if (!pl022_is_supported(ps)) { />>>>>/+ free(ps); />>>>>/+ return NULL; />>>>>/+ } />>>>>/+ />>>>>/+ /* Set requested polarity and 8bit mode */ />>>>>/+ cr0 = SSP_CR0_8BIT_MODE; />>>>>/+ cr0 |= (mode & SPI_CPHA) ? SSP_CR0_SPH : 0; />>>>>/+ cr0 |= (mode & SPI_CPOL) ? SSP_CR0_SPO : 0; />>>>>/+ />>>>>/+ writel(cr0, &pl022->ssp_cr0); />>>>>/+ />>>>>/+ /* Program the SSPClk frequency */ />>>>>/+ prescaler = CONFIG_SYS_SPI_CLK / ps->freq; />>>>>/+ />>>>>/+ if (prescaler <= 0xFF) { />>>>>/+ cpsr = prescaler; />>>>>/+ } else { />>>>>/+ for (scr = 1; scr <= SSP_SCR_MAX; scr++) { />>>>>/+ if (!(prescaler % scr)) { />>>>>/+ cpsr = prescaler / scr; />>>>>/+ if (cpsr <= SSP_CPSR_MAX) />>>>>/+ break; />>>>>/+ } />>>>>/+ } />>>>>/+ />>>>>/+ if (scr > SSP_SCR_MAX) { />>>>>/+ scr = SSP_SCR_MAX; />>>>>/+ cpsr = prescaler / scr; />>>>>/+ cpsr &= SSP_CPSR_MAX; />>>>>/+ } />>>>>/+ } />>>>>/+ />>>>>/+ if (cpsr & 0x1) />>>>>/+ cpsr++; />>>>>/+ />>>>>/+ writel(cpsr, &pl022->ssp_cpsr); />>>>>/+ cr0 = readl(&pl022->ssp_cr0); />>>>>/+ writel(cr0 | (scr - 1) << SSP_SCR_SHFT, &pl022->ssp_cr0); />>>>>/+ />>>>>/+ return &ps->slave; />>>>>/+} />>>>>/+ />>>>>/+void spi_free_slave(struct spi_slave *slave) />>>>>/+{ />>>>>/+ struct pl022_spi_slave *ps = to_pl022_spi(slave); />>>>>/+ />>>>>/+ free(ps); />>>>>/+} />>>>>/+ />>>>>/+int spi_claim_bus(struct spi_slave *slave) />>>>>/+{ />>>>>/+ struct pl022_spi_slave *ps = to_pl022_spi(slave); />>>>>/+ struct pl022 *pl022 = (struct pl022 *)ps->regs; />>>>>/+ />>>>>/+ /* Enable the SPI hardware */ />>>>>/+ setbits_le32(&pl022->ssp_cr1, SSP_CR1_MASK_SSE); />>>>>/+ />>>>>/+ return 0; />>>>>/+} />>>>>/+ />>>>>/+void spi_release_bus(struct spi_slave *slave) />>>>>/+{ />>>>>/+ struct pl022_spi_slave *ps = to_pl022_spi(slave); />>>>>/+ struct pl022 *pl022 = (struct pl022 *)ps->regs; />>>>>/+ />>>>>/+ /* Disable the SPI hardware */ />>>>>/+ writel(0x0, &pl022->ssp_cr1); />>>>>/+} />>>>>/+ />>>>>/+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, />>>>>/+ const void *dout, void *din, unsigned long flags) />>>>>/+{ />>>>>/+ struct pl022_spi_slave *ps = to_pl022_spi(slave); />>>>>/+ struct pl022 *pl022 = (struct pl022 *)ps->regs; />>>>>/+ u32 len_tx = 0, len_rx = 0, len; />>>>>/+ u32 ret = 0; />>>>>/+ const u8 *txp = dout; />>>>>/+ u8 *rxp = din, value; />>>>>/+ />>>>>/+ if (bitlen == 0) />>>>>/+ /* Finish any previously submitted transfers */ />>>>>/+ goto out; />>>>>/+ />>>>>/+ /* />>>>>/+ * TODO: The controller can do non-multiple-of-8 bit />>>>>/+ * transfers, but this driver currently doesn't support it. />>>>>/+ * />>>>>/+ * It's also not clear how such transfers are supposed to be />>>>>/+ * represented as a stream of bytes...this is a limitation of />>>>>/+ * the current SPI interface. />>>>>/+ */ />>>>>/+ if (bitlen % 8) { />>>>>/+ ret = -1; />>>>>/+ />>>>>/+ /* Errors always terminate an ongoing transfer */ />>>>>/+ flags |= SPI_XFER_END; />>>>>/+ goto out; />>>>>/+ } />>>>>/+ />>>>>/+ len = bitlen / 8; />>>>>/+ />>>>>/+ if (flags & SPI_XFER_BEGIN) />>>>>/+ spi_cs_activate(slave); />>>>>/+ />>>>>/+ while (len_tx < len) { />>>>>/+ if (readl(&pl022->ssp_sr) & SSP_SR_MASK_TNF) { />>>>>/+ value = (txp != NULL) ? *txp++ : 0; />>>>>/+ writel(value, &pl022->ssp_dr); />>>>>/+ len_tx++; />>>>>/+ } />>>>>/+ />>>>>/+ if (readl(&pl022->ssp_sr) & SSP_SR_MASK_RNE) { />>>>>/+ value = readl(&pl022->ssp_dr); />>>>>/+ if (rxp) />>>>>/+ *rxp++ = value; />>>>>/+ len_rx++; />>>>>/+ } />>>>>/+ } />>>>>/+ />>>>>/+ while (len_rx < len_tx) { />>>>>/+ if (readl(&pl022->ssp_sr) & SSP_SR_MASK_RNE) { />>>>>/+ value = readl(&pl022->ssp_dr); />>>>>/+ if (rxp) />>>>>/+ *rxp++ = value; />>>>>/+ len_rx++; />>>>>/+ } />>>>>/+ } />>>>>/+ />>>>>/+out: />>>>>/+ if (flags & SPI_XFER_END) />>>>>/+ spi_cs_deactivate(slave); />>>>>/+ />>>>>/+ return ret; />>>>>/+} />>>>>/-- />>>>>/1.7.11.7 />>//>>/Ping />>//>//>/Unfortunately lot of changes happened to our organization />/and we (myself and Vipin) are no longer able to proceed in doing />/this job. />//>/So I think we need to drop this patch, unless someone from the />/u-boot community has the possibility to (and is willing to) proceed />/in implementing and testing the proper changes. /

4 5

[U-Boot] [PATCH] mmc: cat u8 to u64 to avoid unexpected error
by Haibo Chen 20 Sep '16

20 Sep '16

Suspicious implicit sign extension exist. ext_csd[] is defined as "u8", capacity is defined as u64, so u8 is promoted to signed int first int the "|" expersion, then the sign extended to u64. if the tmp sign value is largeer than 0x7fffffff, after the sign extension, the upper bits of the result will all be 1. Thanks to coverity <http://www.coverity.com> e.g. u8 data_8; u64 data_64; data_8 = 0x80; data_64 = data_8 << 24; //0xffffffff80000000 data_64 = ((u64)data_8) << 24; //0x80000000 Signed-off-by: Haibo Chen <haibo.chen(a)nxp.com> --- drivers/mmc/mmc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 43ea0bb..c1d1dc6 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1176,10 +1176,10 @@ static int mmc_startup(struct mmc *mmc) * ext_csd's capacity is valid if the value is more * than 2GB */ - capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 - | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 - | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 - | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; + capacity = ((u64)ext_csd[EXT_CSD_SEC_CNT]) << 0 + | ((u64)ext_csd[EXT_CSD_SEC_CNT + 1]) << 8 + | ((u64)ext_csd[EXT_CSD_SEC_CNT + 2]) << 16 + | ((u64)ext_csd[EXT_CSD_SEC_CNT + 3]) << 24; capacity *= MMC_MAX_BLOCK_LEN; if ((capacity >> 20) > 2 * 1024) mmc->capacity_user = capacity; -- 1.9.1

3 5

[U-Boot] [PATCH v1] dm/mmc: gen_atmel_mci: Add driver model support for mci
by Wenyou Yang 20 Sep '16

20 Sep '16

Add the driver model support for Atmel mci while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> --- drivers/mmc/Kconfig | 9 +++ drivers/mmc/gen_atmel_mci.c | 160 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 169 insertions(+) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index a71afa5..e56eb94 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -44,6 +44,15 @@ config ATMEL_SDHCI It is compliant with the SD Host Controller Standard V3.0 specification. +config GENERIC_ATMEL_MCI + bool "Atmel Multimedia Card Interface support" + depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91 + help + This enables support for Atmel High Speed Multimedia Card Interface + (HSMCI), which supports the MultiMedia Card (MMC) Specification V4.3, + the SD Memory Card Specification V2.0, the SDIO V2.0 specification + and CE-ATA V1.1. + config ROCKCHIP_DWMMC bool "Rockchip SD/MMC controller support" depends on DM_MMC && OF_CONTROL diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index 69770df..3ebc998 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -10,6 +10,7 @@ */ #include <common.h> +#include <clk.h> #include <mmc.h> #include <part.h> #include <malloc.h> @@ -18,8 +19,11 @@ #include <asm/byteorder.h> #include <asm/arch/clk.h> #include <asm/arch/hardware.h> +#include <dm/device.h> #include "atmel_mci.h" +DECLARE_GLOBAL_DATA_PTR; + #ifndef CONFIG_SYS_MMC_CLK_OD # define CONFIG_SYS_MMC_CLK_OD 150000 #endif @@ -37,6 +41,10 @@ struct atmel_mci_priv { struct atmel_mci *mci; unsigned int initialized:1; unsigned int curr_clk; +#ifdef CONFIG_DM_MMC + struct mmc mmc; + ulong bus_clk_rate; +#endif }; /* Read Atmel MCI IP version */ @@ -57,10 +65,18 @@ static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg) cmdr, cmdr & 0x3F, arg, status, msg); } +#ifndef CONFIG_DM_MMC /* Setup for MCI Clock and Block Size */ static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) { struct atmel_mci_priv *priv = mmc->priv; +#else +static void mci_set_mode(struct atmel_mci_priv *priv, u32 hz, u32 blklen) +{ + struct mmc *mmc = &priv->mmc; + +#endif + atmel_mci_t *mci = priv->mci; u32 bus_hz = get_mci_clk_rate(); u32 clkdiv = 255; @@ -202,10 +218,18 @@ io_fail: * Sends a command out on the bus and deals with the block data. * Takes the mmc pointer, a command pointer, and an optional data pointer. */ +#ifndef CONFIG_DM_MMC static int mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { struct atmel_mci_priv *priv = mmc->priv; +#else +static int atmel_mci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct atmel_mci_priv *priv = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); +#endif atmel_mci_t *mci = priv->mci; u32 cmdr; u32 error_flags = 0; @@ -335,17 +359,29 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) return 0; } +#ifndef CONFIG_DM_MMC /* Entered into mmc structure during driver init */ static void mci_set_ios(struct mmc *mmc) { struct atmel_mci_priv *priv = mmc->priv; +#else +static int atmel_mci_set_ios(struct udevice *dev) +{ + struct atmel_mci_priv *priv = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); +#endif + atmel_mci_t *mci = priv->mci; int bus_width = mmc->bus_width; unsigned int version = atmel_mci_get_version(mci); int busw; /* Set the clock speed */ +#ifndef CONFIG_DM_MMC mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN); +#else + mci_set_mode(priv, mmc->clock, MMC_DEFAULT_BLKLEN); +#endif /* * set the bus width and select slot for this interface @@ -370,12 +406,22 @@ static void mci_set_ios(struct mmc *mmc) writel(busw << 7 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); } + +#ifdef CONFIG_DM_MMC + return 0; +#endif } + +#ifndef CONFIG_DM_MMC /* Entered into mmc structure during driver init */ static int mci_init(struct mmc *mmc) { struct atmel_mci_priv *priv = mmc->priv; +#else +static int atmel_mci_hw_init(struct atmel_mci_priv *priv) +{ +#endif atmel_mci_t *mci = priv->mci; /* Initialize controller */ @@ -390,11 +436,16 @@ static int mci_init(struct mmc *mmc) writel(~0UL, &mci->idr); /* Set default clocks and blocklen */ +#ifndef CONFIG_DM_MMC mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); +#else + mci_set_mode(priv, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); +#endif return 0; } +#ifndef CONFIG_DM_MMC static const struct mmc_ops atmel_mci_ops = { .send_cmd = mci_send_cmd, .set_ios = mci_set_ios, @@ -454,3 +505,112 @@ int atmel_mci_init(void *regs) return 0; } +#endif + +#ifdef CONFIG_DM_MMC +static const struct dm_mmc_ops atmel_mci_mmc_ops = { + .send_cmd = atmel_mci_send_cmd, + .set_ios = atmel_mci_set_ios, +}; + +static int atmel_mci_setup_cfg(struct atmel_mci_priv *priv) +{ + struct mmc_config *cfg; + u32 version; + + cfg = &priv->cfg; + cfg->name = "Atmel mci"; + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + + version = atmel_mci_get_version(priv->mci); + if ((version & 0xf00) >= 0x300) { + cfg->host_caps = MMC_MODE_8BIT; + cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; + } + + cfg->host_caps |= MMC_MODE_4BIT; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + cfg->f_min = get_mci_clk_rate() / (2 * 256); + cfg->f_max = get_mci_clk_rate() / (2 * 1); + + return 0; +} + +static int atmel_mci_enable_clk(struct udevice *dev) +{ + struct atmel_mci_priv *priv = dev_get_priv(dev); + struct clk clk; + ulong clk_rate; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return -EINVAL; + + ret = clk_enable(&clk); + if (ret) + return ret; + + clk_rate = clk_get_rate(&clk); + if (!clk_rate) + return -EINVAL; + + priv->bus_clk_rate = clk_rate; + + clk_free(&clk); + + return 0; +} + +static int atmel_mci_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct atmel_mci_priv *priv = dev_get_priv(dev); + struct mmc *mmc; + int ret; + + ret = atmel_mci_enable_clk(dev); + if (ret) + return ret; + + priv->mci = (struct atmel_mci *)dev_get_addr_ptr(dev); + + atmel_mci_setup_cfg(priv); + + mmc = &priv->mmc; + mmc->cfg = &priv->cfg; + mmc->dev = dev; + upriv->mmc = mmc; + + atmel_mci_hw_init(priv); + + return 0; +} + +static int atmel_mci_bind(struct udevice *dev) +{ + struct atmel_mci_priv *priv = dev_get_priv(dev); + int ret; + + ret = mmc_bind(dev, &priv->mmc, &priv->cfg); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id atmel_mci_ids[] = { + { .compatible = "atmel,hsmci" }, + { } +}; + +U_BOOT_DRIVER(atmel_mci) = { + .name = "atmel-mci", + .id = UCLASS_MMC, + .of_match = atmel_mci_ids, + .bind = atmel_mci_bind, + .probe = atmel_mci_probe, + .priv_auto_alloc_size = sizeof(struct atmel_mci_priv), + .ops = &atmel_mci_mmc_ops, +}; +#endif -- 2.7.4

2 1