August 2016 - U-Boot

[U-Boot] A64 fastboot, faster way to compile/test
by jonsmirl＠gmail.com 15 Aug '16

15 Aug '16

I'm trying out various versions of the A64 u-boot -- Allwinner lichee, longsleep, apritzel, etc on the Pine64. I can get all of them up to the prompt, but fastboot doesn't work in an of them. There is code from Allwinner in there for implementing fastboot, but so far I've had no luck getting it to do anything. I added a bunch of debug and the USB controller does not appear to be generating interrupts. Has anyone worked with A64 fastboot? Any tips on what might be wrong? I want a faster was to update the SD Card without physically moving it between machines. -- Jon Smirl jonsmirl(a)gmail.com

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[U-Boot] [PATCH v2 0/5] add pinctrl driver for rk3399
by Kever Yang 15 Aug '16

15 Aug '16

This patch set add the pinctrl driver for rk3399 and enable pinctrl for pwm module. Module with pinctrl driver support and with interrupt number and default pinctrl in dts node will get pinctrl initialized when driver probe. Module like pwm which without interrupt number need to call the pinctrl API manually. Changes in v2: - move and reg value MACRO in C source, and use MASK/SHIFT Kever Yang (5): rk3399: syscon: add support for pmugrf pinctrl: add driver for rk3399 config: evb-rk3399: enable pinctrl driver rk3399: enable the pwm2/3 pinctrl in board init dts: rk3399: add pinctrl for sdmmc arch/arm/dts/rk3399.dtsi | 37 ++ arch/arm/include/asm/arch-rockchip/clock.h | 1 + arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 330 ++++++++++++++++++ arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 1 + board/rockchip/evb_rk3399/evb-rk3399.c | 31 +- configs/evb-rk3399_defconfig | 2 + drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3399.c | 441 ++++++++++++++++++++++++ 9 files changed, 852 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3399.h create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3399.c -- 1.9.1

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[U-Boot] [PATCH 1/2 v3] x86: Add DFI BT700 BayTrail board support
by Stefan Roese 15 Aug '16

15 Aug '16

This patch adds support for the DFI BayTrail BT700 QSeven SoM installed on the DFI Q7X-151 baseboard. The baseboard is equipped with the Nuvoton NCT6102D Super IO chip providing the UART as console. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> --- v3: - Change comment Winbond > Nuvoton - Remove unneeded compatible property in HS-UART DTS node v2: - Added missing text to Kconfig entry arch/x86/Kconfig | 4 + arch/x86/dts/Makefile | 1 + arch/x86/dts/dfi-bt700-q7x-151.dts | 22 +++ arch/x86/dts/dfi-bt700.dtsi | 308 ++++++++++++++++++++++++++++++ board/dfi/Kconfig | 29 +++ board/dfi/dfi-bt700/Kconfig | 28 +++ board/dfi/dfi-bt700/MAINTAINERS | 8 + board/dfi/dfi-bt700/Makefile | 8 + board/dfi/dfi-bt700/acpi/mainboard.asl | 13 ++ board/dfi/dfi-bt700/dfi-bt700.c | 30 +++ board/dfi/dfi-bt700/dsdt.asl | 14 ++ board/dfi/dfi-bt700/start.S | 9 + configs/dfi-bt700-internal-uart_defconfig | 61 ++++++ configs/dfi-bt700-q7x-151_defconfig | 63 ++++++ include/configs/dfi-bt700.h | 74 +++++++ 15 files changed, 672 insertions(+) create mode 100644 arch/x86/dts/dfi-bt700-q7x-151.dts create mode 100644 arch/x86/dts/dfi-bt700.dtsi create mode 100644 board/dfi/Kconfig create mode 100644 board/dfi/dfi-bt700/Kconfig create mode 100644 board/dfi/dfi-bt700/MAINTAINERS create mode 100644 board/dfi/dfi-bt700/Makefile create mode 100644 board/dfi/dfi-bt700/acpi/mainboard.asl create mode 100644 board/dfi/dfi-bt700/dfi-bt700.c create mode 100644 board/dfi/dfi-bt700/dsdt.asl create mode 100644 board/dfi/dfi-bt700/start.S create mode 100644 configs/dfi-bt700-internal-uart_defconfig create mode 100644 configs/dfi-bt700-q7x-151_defconfig create mode 100644 include/configs/dfi-bt700.h diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 29d1120..5193ee7 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -17,6 +17,9 @@ config VENDOR_CONGATEC config VENDOR_COREBOOT bool "coreboot" +config VENDOR_DFI + bool "dfi" + config VENDOR_EFI bool "efi" @@ -35,6 +38,7 @@ endchoice source "board/advantech/Kconfig" source "board/congatec/Kconfig" source "board/coreboot/Kconfig" +source "board/dfi/Kconfig" source "board/efi/Kconfig" source "board/emulation/Kconfig" source "board/google/Kconfig" diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 4f07f41..ca086bd 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -9,6 +9,7 @@ dtb-y += bayleybay.dtb \ conga-qeval20-qa3-e3845.dtb \ cougarcanyon2.dtb \ crownbay.dtb \ + dfi-bt700-q7x-151.dtb \ efi.dtb \ galileo.dtb \ minnowmax.dtb \ diff --git a/arch/x86/dts/dfi-bt700-q7x-151.dts b/arch/x86/dts/dfi-bt700-q7x-151.dts new file mode 100644 index 0000000..31d9679 --- /dev/null +++ b/arch/x86/dts/dfi-bt700-q7x-151.dts @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2014, Bin Meng <bmeng.cn(a)gmail.com> + * Copyright (C) 2016 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "dfi-bt700.dtsi" + +#include "serial.dtsi" + +/ { + model = "DFI-BT700"; + compatible = "dfi,bt700", "intel,baytrail"; + + aliases { + serial0 = &serial; + spi0 = &spi; + }; +}; diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi new file mode 100644 index 0000000..75ee6ad --- /dev/null +++ b/arch/x86/dts/dfi-bt700.dtsi @@ -0,0 +1,308 @@ +/* + * Copyright (C) 2014, Bin Meng <bmeng.cn(a)gmail.com> + * Copyright (C) 2016 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/gpio/x86-gpio.h> +#include <dt-bindings/interrupt-router/intel-irq.h> + +#include "skeleton.dtsi" +#include "rtc.dtsi" +#include "tsc_timer.dtsi" + +/ { + config { + silent_console = <0>; + }; + + pch_pinctrl { + compatible = "intel,x86-pinctrl"; + reg = <0 0>; + + /* Add UART1 PAD configuration (SIO HS-UART) */ + uart1_txd@0 { + pad-offset = <0x10>; + mode-func = <1>; + }; + + uart1_rxd@0 { + pad-offset = <0x20>; + mode-func = <1>; + }; + + /* + * As of today, the latest version FSP (gold4) for BayTrail + * misses the PAD configuration of the SD controller's Card + * Detect signal. The default PAD value for the CD pin sets + * the pin to work in GPIO mode, which causes card detect + * status cannot be reflected by the Present State register + * in the SD controller (bit 16 & bit 18 are always zero). + * + * Configure this pin to function 1 (SD controller). + */ + sdmmc3_cd@0 { + pad-offset = <0x3a0>; + mode-func = <1>; + }; + }; + + chosen { + stdout-path = "/serial"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <1>; + intel,apic-id = <2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <2>; + intel,apic-id = <4>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <3>; + intel,apic-id = <6>; + }; + }; + + pci { + compatible = "intel,pci-baytrail", "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + + pciuart0: uart@1e,3 { + compatible = "pci8086,0f0a.00", + "pci8086,0f0a", + "pciclass,070002", + "pciclass,0700", + "ns16550"; + u-boot,dm-pre-reloc; + reg = <0x0200f310 0x0 0x0 0x0 0x0>; + reg-shift = <2>; + clock-frequency = <58982400>; + current-speed = <115200>; + }; + + pch@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "pci8086,0f1c", "intel,pch9"; + #address-cells = <1>; + #size-cells = <1>; + + irq-router { + compatible = "intel,irq-router"; + intel,pirq-config = "ibase"; + intel,ibase-offset = <0x50>; + intel,actl-addr = <0>; + intel,pirq-link = <8 8>; + intel,pirq-mask = <0xdee0>; + intel,pirq-routing = < + /* BayTrail PCI devices */ + PCI_BDF(0, 2, 0) INTA PIRQA + PCI_BDF(0, 3, 0) INTA PIRQA + PCI_BDF(0, 16, 0) INTA PIRQA + PCI_BDF(0, 17, 0) INTA PIRQA + PCI_BDF(0, 18, 0) INTA PIRQA + PCI_BDF(0, 19, 0) INTA PIRQA + PCI_BDF(0, 20, 0) INTA PIRQA + PCI_BDF(0, 21, 0) INTA PIRQA + PCI_BDF(0, 22, 0) INTA PIRQA + PCI_BDF(0, 23, 0) INTA PIRQA + PCI_BDF(0, 24, 0) INTA PIRQA + PCI_BDF(0, 24, 1) INTC PIRQC + PCI_BDF(0, 24, 2) INTD PIRQD + PCI_BDF(0, 24, 3) INTB PIRQB + PCI_BDF(0, 24, 4) INTA PIRQA + PCI_BDF(0, 24, 5) INTC PIRQC + PCI_BDF(0, 24, 6) INTD PIRQD + PCI_BDF(0, 24, 7) INTB PIRQB + PCI_BDF(0, 26, 0) INTA PIRQA + PCI_BDF(0, 27, 0) INTA PIRQA + PCI_BDF(0, 28, 0) INTA PIRQA + PCI_BDF(0, 28, 1) INTB PIRQB + PCI_BDF(0, 28, 2) INTC PIRQC + PCI_BDF(0, 28, 3) INTD PIRQD + PCI_BDF(0, 29, 0) INTA PIRQA + PCI_BDF(0, 30, 0) INTA PIRQA + PCI_BDF(0, 30, 1) INTD PIRQD + PCI_BDF(0, 30, 2) INTB PIRQB + PCI_BDF(0, 30, 3) INTC PIRQC + PCI_BDF(0, 30, 4) INTD PIRQD + PCI_BDF(0, 30, 5) INTB PIRQB + PCI_BDF(0, 31, 3) INTB PIRQB + + /* + * PCIe root ports downstream + * interrupts + */ + PCI_BDF(1, 0, 0) INTA PIRQA + PCI_BDF(1, 0, 0) INTB PIRQB + PCI_BDF(1, 0, 0) INTC PIRQC + PCI_BDF(1, 0, 0) INTD PIRQD + PCI_BDF(2, 0, 0) INTA PIRQB + PCI_BDF(2, 0, 0) INTB PIRQC + PCI_BDF(2, 0, 0) INTC PIRQD + PCI_BDF(2, 0, 0) INTD PIRQA + PCI_BDF(3, 0, 0) INTA PIRQC + PCI_BDF(3, 0, 0) INTB PIRQD + PCI_BDF(3, 0, 0) INTC PIRQA + PCI_BDF(3, 0, 0) INTD PIRQB + PCI_BDF(4, 0, 0) INTA PIRQD + PCI_BDF(4, 0, 0) INTB PIRQA + PCI_BDF(4, 0, 0) INTC PIRQB + PCI_BDF(4, 0, 0) INTD PIRQC + >; + }; + + spi: spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich9-spi"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "stmicro,n25q064a", + "spi-flash"; + memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x006f0000 0x00010000>; + }; + }; + }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x20>; + bank-name = "C"; + }; + + gpiod { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x60 0x20>; + bank-name = "D"; + }; + + gpioe { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x80 0x20>; + bank-name = "E"; + }; + + gpiof { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0xA0 0x20>; + bank-name = "F"; + }; + }; + }; + + fsp { + compatible = "intel,baytrail-fsp"; + fsp,mrc-init-tseg-size = <0>; + fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-spd-addr1 = <0xa0>; + fsp,mrc-init-spd-addr2 = <0xa2>; + fsp,emmc-boot-mode = <1>; + fsp,enable-sdio; + fsp,enable-sdcard; + fsp,enable-hsuart0; + fsp,enable-hsuart1; + fsp,enable-spi; + fsp,enable-sata; + fsp,sata-mode = <1>; + fsp,enable-lpe; + fsp,lpss-sio-enable-pci-mode; + fsp,enable-dma0; + fsp,enable-dma1; + fsp,enable-i2c0; + fsp,enable-i2c1; + fsp,enable-i2c2; + fsp,enable-i2c3; + fsp,enable-i2c4; + fsp,enable-i2c5; + fsp,enable-i2c6; + fsp,enable-pwm0; + fsp,enable-pwm1; + fsp,igd-dvmt50-pre-alloc = <2>; + fsp,aperture-size = <2>; + fsp,gtt-size = <2>; + fsp,scc-enable-pci-mode; + fsp,os-selection = <4>; + fsp,emmc45-ddr50-enabled; + fsp,emmc45-retune-timer-value = <8>; + fsp,enable-igd; + fsp,enable-memory-down; + fsp,memory-down-params { + compatible = "intel,baytrail-fsp-mdp"; + fsp,dram-speed = <2>; /* 2=1333MHz */ + fsp,dram-type = <1>; /* 1=DDR3L */ + fsp,dimm-0-enable; + fsp,dimm-width = <1>; /* 1=x16, 2=x32 */ + fsp,dimm-density = <3>; /* 3=8Gbit */ + fsp,dimm-bus-width = <3>; /* 3=64bits */ + fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b */ + + /* These following values might need a re-visit */ + fsp,dimm-tcl = <8>; + fsp,dimm-trpt-rcd = <8>; + fsp,dimm-twr = <8>; + fsp,dimm-twtr = <4>; + fsp,dimm-trrd = <6>; + fsp,dimm-trtp = <4>; + fsp,dimm-tfaw = <22>; + }; + }; + + microcode { + update@0 { +#include "microcode/m0130673325.dtsi" + }; + update@1 { +#include "microcode/m0130679907.dtsi" + }; + }; +}; diff --git a/board/dfi/Kconfig b/board/dfi/Kconfig new file mode 100644 index 0000000..25d0a11 --- /dev/null +++ b/board/dfi/Kconfig @@ -0,0 +1,29 @@ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn(a)gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +if VENDOR_DFI + +choice + prompt "Mainboard model" + optional + +config TARGET_DFI_BT700 + bool "DFI BT700 BayTrail" + help + This is the DFI Q7X-151 baseboard equipped with the + DFI BayTrail Bt700 SoM. It contains an Atom E3845 with + Ethernet (in non-PCIe-x4 configuration), micro-SD, USB 2, + USB 3, SATA, serial console and DisplayPort video out. + It requires some binary blobs - see README.x86 for details. + + Note that PCIE_ECAM_BASE is set up by the FSP so the value used + by U-Boot matches that value. + +endchoice + +source "board/dfi/dfi-bt700/Kconfig" + +endif diff --git a/board/dfi/dfi-bt700/Kconfig b/board/dfi/dfi-bt700/Kconfig new file mode 100644 index 0000000..3f0acb3 --- /dev/null +++ b/board/dfi/dfi-bt700/Kconfig @@ -0,0 +1,28 @@ +if TARGET_DFI_BT700 + +config SYS_BOARD + default "dfi-bt700" + +config SYS_VENDOR + default "dfi" + +config SYS_SOC + default "baytrail" + +config SYS_CONFIG_NAME + default "dfi-bt700" + +config SYS_TEXT_BASE + default 0xfff00000 if !EFI_STUB + default 0x01110000 if EFI_STUB + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR if !EFI_STUB + select INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + +config PCIE_ECAM_BASE + default 0xe0000000 + +endif diff --git a/board/dfi/dfi-bt700/MAINTAINERS b/board/dfi/dfi-bt700/MAINTAINERS new file mode 100644 index 0000000..9c3d699 --- /dev/null +++ b/board/dfi/dfi-bt700/MAINTAINERS @@ -0,0 +1,8 @@ +congatec DFI-BT700 +M: Stefan Roese <sr(a)denx.de> +S: Maintained +F: board/dfi/dfi-bt700 +F: include/configs/dfi-bt700.h +F: configs/dfi-bt700-q7x-151_defconfig +F: arch/x86/dts/dfi-bt700.dtsi +F: arch/x86/dts/dfi-bt700-q7x-151.dts diff --git a/board/dfi/dfi-bt700/Makefile b/board/dfi/dfi-bt700/Makefile new file mode 100644 index 0000000..8052f5e --- /dev/null +++ b/board/dfi/dfi-bt700/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2015, Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += dfi-bt700.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/dfi/dfi-bt700/acpi/mainboard.asl b/board/dfi/dfi-bt700/acpi/mainboard.asl new file mode 100644 index 0000000..544a049 --- /dev/null +++ b/board/dfi/dfi-bt700/acpi/mainboard.asl @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} + +/* TODO: Need add Nuvoton SuperIO chipset NCT6102D ASL codes */ diff --git a/board/dfi/dfi-bt700/dfi-bt700.c b/board/dfi/dfi-bt700/dfi-bt700.c new file mode 100644 index 0000000..8645bdc --- /dev/null +++ b/board/dfi/dfi-bt700/dfi-bt700.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <nuvoton_nct6102d.h> +#include <asm/gpio.h> +#include <asm/ibmpc.h> +#include <asm/pnp_def.h> + +int board_early_init_f(void) +{ +#ifdef CONFIG_INTERNAL_UART + /* Disable the legacy UART which is enabled per default */ + nct6102d_uarta_disable(); +#else + /* + * The FSP enables the BayTrail internal legacy UART (again). + * Disable it again, so that the Nuvoton one can be used. + */ + setup_internal_uart(0); +#endif + + /* Disable the watchdog which is enabled per default */ + nct6102d_wdt_disable(); + + return 0; +} diff --git a/board/dfi/dfi-bt700/dsdt.asl b/board/dfi/dfi-bt700/dsdt.asl new file mode 100644 index 0000000..6042011 --- /dev/null +++ b/board/dfi/dfi-bt700/dsdt.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/board/dfi/dfi-bt700/start.S b/board/dfi/dfi-bt700/start.S new file mode 100644 index 0000000..2c941a4 --- /dev/null +++ b/board/dfi/dfi-bt700/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015, Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/configs/dfi-bt700-internal-uart_defconfig b/configs/dfi-bt700-internal-uart_defconfig new file mode 100644 index 0000000..1a7315d --- /dev/null +++ b/configs/dfi-bt700-internal-uart_defconfig @@ -0,0 +1,61 @@ +CONFIG_X86=y +CONFIG_DM_I2C=y +CONFIG_VENDOR_DFI=y +CONFIG_DEFAULT_DEVICE_TREE="dfi-bt700" +CONFIG_TARGET_DFI_BT700=y +CONFIG_HAVE_INTEL_ME=y +CONFIG_ENABLE_MRC_CACHE=y +CONFIG_SMP=y +CONFIG_HAVE_VGA_BIOS=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_MP_TABLE=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CPU=y +CONFIG_NUVOTON_NCT6102D=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_DM_PCI=y +CONFIG_DM_RTC=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0x3f8 +CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_SYS_NS16550=y +CONFIG_ICH_SPI=y +CONFIG_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_VIDEO_VESA=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_114=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig new file mode 100644 index 0000000..6f00004 --- /dev/null +++ b/configs/dfi-bt700-q7x-151_defconfig @@ -0,0 +1,63 @@ +CONFIG_X86=y +CONFIG_DM_I2C=y +CONFIG_VENDOR_DFI=y +CONFIG_DEFAULT_DEVICE_TREE="dfi-bt700-q7x-151" +CONFIG_TARGET_DFI_BT700=y +CONFIG_HAVE_INTEL_ME=y +CONFIG_ENABLE_MRC_CACHE=y +CONFIG_SMP=y +CONFIG_HAVE_VGA_BIOS=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_ACPI_TABLE=y +CONFIG_SEABIOS=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CPU=y +CONFIG_NUVOTON_NCT6102D=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_DM_PCI=y +CONFIG_DM_RTC=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0x3f8 +CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_SYS_NS16550=y +CONFIG_ICH_SPI=y +CONFIG_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_VIDEO_VESA=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_114=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h new file mode 100644 index 0000000..23d8a0a --- /dev/null +++ b/include/configs/dfi-bt700.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_BOARD_EARLY_INIT_F + +#ifndef CONFIG_INTERNAL_UART +/* Use BayTrail internal HS UART which is memory-mapped */ +#undef CONFIG_SYS_NS16550_PORT_MAPPED +#endif + +#define CONFIG_PCI_PNP + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT} + +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SDMA + +#undef CONFIG_USB_MAX_CONTROLLER_COUNT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_RTL8152 + +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO +#define CONFIG_CMD_BMP + +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x006ef000 + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_BOOTARGS \ + "root=/dev/sda1 ro quiet" +#define CONFIG_BOOTCOMMAND \ + "load scsi 0:1 03000000 /boot/vmlinuz-${kernel-ver}-generic;" \ + "load scsi 0:1 04000000 /boot/initrd.img-${kernel-ver}-generic;" \ + "run boot" + +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel-ver=4.4.0-24\0" \ + "boot=zboot 03000000 0 04000000 ${filesize}\0" \ + "upd_uboot=usb reset;tftp 100000 dfi/u-boot.rom;" \ + "sf probe;sf update 100000 0 800000;saveenv\0" + +#define CONFIG_PREBOOT + +#endif /* __CONFIG_H */ -- 2.9.2

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[U-Boot] [PATCH] ARM64: zynqmp: Wire up both USBs available on ZynqMP
by Michal Simek 15 Aug '16

15 Aug '16

The second USB wasn't enabled. This patch fixes it. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- board/xilinx/zynqmp/zynqmp.c | 20 ++++++++++++++++++-- include/configs/xilinx_zynqmp.h | 2 +- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 0c5d9979316f..7b4b5ffd89f4 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -283,13 +283,20 @@ int checkboard(void) } #ifdef CONFIG_USB_DWC3 -static struct dwc3_device dwc3_device_data = { +static struct dwc3_device dwc3_device_data0 = { .maximum_speed = USB_SPEED_HIGH, .base = ZYNQMP_USB0_XHCI_BASEADDR, .dr_mode = USB_DR_MODE_PERIPHERAL, .index = 0, }; +static struct dwc3_device dwc3_device_data1 = { + .maximum_speed = USB_SPEED_HIGH, + .base = ZYNQMP_USB1_XHCI_BASEADDR, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 1, +}; + int usb_gadget_handle_interrupts(void) { dwc3_uboot_handle_interrupt(0); @@ -298,7 +305,16 @@ int usb_gadget_handle_interrupts(void) int board_usb_init(int index, enum usb_init_type init) { - return dwc3_uboot_init(&dwc3_device_data); + debug("%s: index %x\n", __func__, index); + + switch (index) { + case 0: + return dwc3_uboot_init(&dwc3_device_data0); + case 1: + return dwc3_uboot_init(&dwc3_device_data1); + }; + + return -1; } int board_usb_cleanup(int index, enum usb_init_type init) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 78d8bf476872..96b6da8bed4b 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -115,7 +115,7 @@ #define CONFIG_SYS_LOAD_ADDR 0x8000000 #if defined(CONFIG_ZYNQMP_USB) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_XHCI_ZYNQMP -- 1.9.1

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[U-Boot] [PATCH v4] arm: cache: always flush cache line size for page table
by Stefan Agner 15 Aug '16

15 Aug '16

From: Stefan Agner <stefan.agner(a)toradex.com> The page table is maintained by the CPU, hence it is safe to always align cache flush to a whole cache line size. This allows to use mmu_page_table_flush for a single page table, e.g. when configure only small regions through mmu_set_region_dcache_behaviour. Signed-off-by: Stefan Agner <stefan.agner(a)toradex.com> Tested-by: Fabio Estevam <fabio.estevam(a)nxp.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v4: - Fixed spelling misstake for real Changes in v3: - Fixed spelling misstake Changes in v2: - Move cache line alignment from mmu_page_table_flush to mmu_set_region_dcache_behaviour arch/arm/lib/cache-cp15.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 1121dc3..488094e 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -62,6 +62,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option) { u32 *page_table = (u32 *)gd->arch.tlb_addr; + phys_addr_t startpt, stoppt; unsigned long upto, end; end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; @@ -70,7 +71,17 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, option); for (upto = start; upto < end; upto++) set_section_dcache(upto, option); - mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); + + /* + * Make sure range is cache line aligned + * Only CPU maintains page tables, hence it is safe to always + * flush complete cache lines... + */ + startpt = (phys_addr_t)&page_table[start]; + startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); + stoppt = (phys_addr_t)&page_table[end]; + stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE); + mmu_page_table_flush(startpt, stoppt); } __weak void dram_bank_mmu_setup(int bank) -- 2.9.0

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[U-Boot] [PATCH 0/3] Fix several possible crashes/corruptions in ext4
by Stefan Brüns 14 Aug '16

14 Aug '16

The U-Boot ext4 support has some bugs which either cause U-Boot crashes or lead to filesystem corruption. This series goes on top of the endian patch series by Michael Walle. The first patch has been sent earlier but contained a bug. Stefan Brüns (3): ext4: fix possible crash on directory traversal, ignore deleted entries ext4: propagate error if creation of directory entry fails ext4: Do not crash when trying to grow a directory using extents fs/ext4/ext4_common.c | 77 ++++++++++++++++++++++----------------------------- fs/ext4/ext4_common.h | 2 +- fs/ext4/ext4_write.c | 6 ++-- include/ext4fs.h | 2 +- 4 files changed, 39 insertions(+), 48 deletions(-) -- 2.9.2

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[U-Boot] CACHE: Misaligned operation
by Clemens Gruber 14 Aug '16

14 Aug '16

Hi, I just tested the current U-Boot master on my i.MX6Q board and the following two warnings showed up on the console: U-Boot 2016.09-rc1-00377-gb8698a2 CPU: Freescale i.MX6Q rev1.5 at 792 MHz Reset cause: POR DRAM: 1 GiB CACHE: Misaligned operation at range [4fff0000, 4fff0004] CACHE: Misaligned operation at range [4fff0024, 4fff0028] (But everything works fine, as far as I can tell for now) I did a git bisect and found out that these two warning messages are shown since commit 96e451bfa39b (arm: Show cache warnings in U-Boot proper only), where a debug statement was changed to a non-SPL warning. Was this intentional and is this warning something to be worried about? If not, we could add a new macro debug_non_spl with debug_cond !_SPL_BUILD && DEBUG and use that in check_cache_range. What do you think? Thanks, Clemens

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[U-Boot] tegra124 jetson-tk1 ethernet problems.
by Peter Chubb 13 Aug '16

13 Aug '16

Hi Folks, Since patch 96350f729c42 "dm: tegra: net: Convert tegra boards to driver model for Ethernet" booting via dhcp has been broken on the Jetson TK1. I tried applying "net: Probe PCI before looking for ethernet devices"; this `works' in that the ethernet device is detected and works, but I end up with huge numbers of CACHE: Misaligned operation at range [fffb8c00, fffb8c2e] messages on the serial console. These come from the flush_cache() calls in net/rtl8169.c. I suggest the attached patch (or something like it): diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 1cc0b40..ebbadd2 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -476,7 +476,10 @@ static void rtl_inval_rx_desc(struct RxDesc *desc) static void rtl_flush_rx_desc(struct RxDesc *desc) { #ifndef CONFIG_SYS_NONCACHED_MEMORY - flush_cache((unsigned long)desc, sizeof(*desc)); + unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); + unsigned long size = ALIGN(sizeof(*desc), ARCH_DMA_MINALIGN); + + flush_cache(start, size); #endif } @@ -493,21 +496,28 @@ static void rtl_inval_tx_desc(struct TxDesc *desc) static void rtl_flush_tx_desc(struct TxDesc *desc) { #ifndef CONFIG_SYS_NONCACHED_MEMORY - flush_cache((unsigned long)desc, sizeof(*desc)); + unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); + unsigned long sz = ALIGN(sizeof *desc, ARCH_DMA_MINALIGN); + + flush_cache(start, sz); #endif } static void rtl_inval_buffer(void *buf, size_t size) { - unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); - unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); + unsigned long end = ALIGN((unsigned long)buf + size, ARCH_DMA_MINALIGN); - invalidate_dcache_range(start, end); + /* buf is aligned to RTL8169_ALIGN, + * which is a multiple of ARCH_DMA_ALIGN + */ + invalidate_dcache_range((unsigned long)buf, end); } static void rtl_flush_buffer(void *buf, size_t size) { - flush_cache((unsigned long)buf, size); + unsigned long sz = ALIGN(size, ARCH_DMA_MINALIGN); + + flush_cache((unsigned long)buf, sz); } /************************************************************************** -- Dr Peter Chubb Tel: +61 2 9490 5852 http://www.data61.csiro.au http://www.ssrg.nicta.com.au Software Systems Research Group/NICTA/Data61

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[U-Boot] [PATCH] ARM: make ARMV7_LPAE select PHYS_64BIT
by Masahiro Yamada 13 Aug '16

13 Aug '16

As you see in arch/arm/include/asm/types.h, CONFIG_PHYS_64BIT determines the size of phys_addr_t. The ARM Large Physical Address Extension allows CPUs to access a physical address space larger than 4GB, so the physical address may not fit in 32bit long phys_addr_t. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- I did Buildman test, but not run-time test. Looks like bcm283x (RPI) is the only arch that selects ARMV7_LPAE, so I hope Stephen will check this patch. arch/arm/cpu/armv7/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index 0560178..1697e61 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig @@ -45,6 +45,7 @@ config ARMV7_PSCI_NR_CPUS config ARMV7_LPAE boolean "Use LPAE page table format" if EXPERT depends on CPU_V7 + select PHYS_64BIT default n ---help--- Say Y here to use the long descriptor page table format. This is -- 1.9.1

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[U-Boot] Please pull u-boot-dm
by Simon Glass 13 Aug '16

13 Aug '16

Hi, This include a prerequisite for a forthcoming Tegra pull request. The following changes since commit 28cd88baa3f11cdb52be3b6d0610dcf32c60871a: Merge branch 'master' of git://git.denx.de/u-boot-uniphier (2016-08-11 10:45:53 -0400) are available in the git repository at: git://git.denx.de/u-boot-dm.git for you to fetch changes up to b647f55420310beb8f576e23f3b6a69745126f71: misc: add "call" uclass op (2016-08-12 11:01:22 -0600) ---------------------------------------------------------------- John Keeping (2): power: regulator: act8846: fix reading values power: pmic: act8846: add missing newline to debug statements Stephen Warren (3): fdt_support: fdt_translate_address() blob const correctness fdt: allow fdtdec_get_addr_size_*() to translate addresses misc: add "call" uclass op common/fdt_support.c | 21 +++++++++++---------- drivers/core/device.c | 2 +- drivers/gpio/mpc85xx_gpio.c | 2 +- drivers/i2c/fsl_i2c.c | 2 +- drivers/misc/misc-uclass.c | 11 +++++++++++ drivers/mmc/msm_sdhci.c | 3 ++- drivers/net/cpsw.c | 3 ++- drivers/power/pmic/act8846.c | 4 ++-- drivers/power/regulator/act8846.c | 4 ++-- drivers/spmi/spmi-msm.c | 5 +++-- include/fdt_support.h | 5 +++-- include/fdtdec.h | 14 +++++++++++--- include/misc.h | 35 +++++++++++++++++++++++++++++++++++ lib/fdtdec.c | 22 +++++++++++++++------- 14 files changed, 100 insertions(+), 33 deletions(-) Regards, Simon

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