August 2016 - U-Boot

[U-Boot] [BUG] divide by 0 in spi flash probe
by Chris Packham 30 Aug '16

30 Aug '16

Hi, I'm updating support for a board which uses the Armada-385 from u-boot v2016.05 to use the latest master (v2016.09-rc2 plus a bit). When I run "sf probe" I get a divide by 0 in mvebu_spi_set_speed because hz has made it through as 0. When I run saveenv (env is in SPI) I don't get the divide by 0. I'll do some more digging tomorrow but just thought I'd get this email off now in case it rings any bells for anyone. Thanks, Chris

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[U-Boot] [PATCH v3 1/4] mx6: ddr: Allow changing REFSEL and REFR fields
by Fabio Estevam 30 Aug '16

30 Aug '16

From: Fabio Estevam <fabio.estevam(a)nxp.com> Currently MX6 SPL DDR initialization hardcodes the REF_SEL and REFR fields of the MDREF register as 1 and 7, respectively. Looking at the MDREF initialization done via DCD we see that boards do need to initialize these fields differently: $ git grep 0x021b0020 board/ board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */ board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800 board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800 board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800 So introduce a mechanism for users to configure REFSEL and REFR fields as needed. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- Changes since v2: - Do not make this mx6ul specific (Eric) arch/arm/cpu/armv7/mx6/ddr.c | 15 ++++++++++++--- arch/arm/include/asm/arch-mx6/mx6-ddr.h | 2 ++ 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index f151eec..ebc7903 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -1183,7 +1183,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, volatile struct mmdc_p_regs *mmdc0; volatile struct mmdc_p_regs *mmdc1; u32 val; - u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd; + u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd, refsel, refr; u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */ u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr; @@ -1472,8 +1472,17 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, MMDC1(mpzqhwctrl, val); /* Step 12: Configure and activate periodic refresh */ - mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */ - (7 << 11); /* REFR: Refresh Rate - 8 refreshes */ + if (!sysinfo->refsel) + refsel = 1; /* REF_SEL: Periodic refresh cycle: 32kHz */ + else + refsel = sysinfo->refsel; + + if (!sysinfo->refr) + refr = 7; /* REFR: Refresh Rate - 8 refreshes */ + else + refr = sysinfo->refr; + + mmdc0->mdref = (refsel << 14) | (refr << 11); /* Step 13: Deassert config request - init complete */ mmdc0->mdscr = 0x00000000; diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index 12c30d2..9922409 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -408,6 +408,8 @@ struct mx6_ddr_sysinfo { u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */ u8 pd_fast_exit;/* enable precharge powerdown fast-exit */ u8 ddr_type; /* DDR type: DDR3(0) or LPDDR2(1) */ + u8 refsel; /* REF_SEL field of register MDREF */ + u8 refr; /* REFR field of register MDREF */ }; /* -- 1.9.1

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[U-Boot] [PATCH] nand: Fix nand info for no device
by Tony Lindgren 30 Aug '16

30 Aug '16

Looks like we have few more places where we're testing for nand_info[i]->name. We can now use just test for nand_info[i] instead. This fixes a data abort on devices with no NAND when doing nand info. Signed-off-by: Tony Lindgren <tony(a)atomide.com> --- cmd/nand.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cmd/nand.c b/cmd/nand.c --- a/cmd/nand.c +++ b/cmd/nand.c @@ -398,7 +398,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) putc('\n'); for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) { - if (nand_info[i]->name) + if (nand_info[i]) nand_print_and_set_info(i); } return 0; @@ -433,7 +433,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) * for another device is to be used. */ if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE || - !nand_info[dev]->name) { + !nand_info[dev]) { puts("\nno devices available\n"); return 1; } @@ -991,7 +991,7 @@ usage: idx = simple_strtoul(boot_device, NULL, 16); - if (idx < 0 || idx >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[idx]->name) { + if (idx < 0 || idx >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[idx]) { printf("\n** Device %d not available\n", idx); bootstage_error(BOOTSTAGE_ID_NAND_AVAILABLE); return 1; -- 2.9.3

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[U-Boot] [PATCH v2 1/3] mx6: ddr: Adjust MDREF register settings for MX6UL
by Fabio Estevam 29 Aug '16

29 Aug '16

From: Fabio Estevam <fabio.estevam(a)nxp.com> When running a NXP 4.1 kernel with U-Boot mainline we observe a hang when going into the lowest operational point of cpufreq. After comparing the SPL DDR initialization against the DCD table from NXP U-Boot, the key difference that causes the hang is the MDREF register setting. In all the DDR3 MX6UL boards we have the following configuration for MDREF: DATA 4 0x021B0020 0x00000800 ,which means: REF_SEL = 0 -->Periodic refresh cycle: 64kHz REFR = 1 ---> Refresh Rate - 2 refreshes So adjust the MDREF initialization for MX6UL to fix the kernel hang issue. Reported-by: Eric Nelson <eric(a)nelint.com> Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- Changes since v1: - Newly introduced in this version arch/arm/cpu/armv7/mx6/ddr.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index f151eec..56d3e65 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -1183,7 +1183,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, volatile struct mmdc_p_regs *mmdc0; volatile struct mmdc_p_regs *mmdc1; u32 val; - u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd; + u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd, refr, refsel; u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */ u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr; @@ -1472,9 +1472,15 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, MMDC1(mpzqhwctrl, val); /* Step 12: Configure and activate periodic refresh */ - mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */ - (7 << 11); /* REFR: Refresh Rate - 8 refreshes */ + if (!is_mx6ul()) { + refsel = 1; /* REF_SEL: Periodic refresh cycle: 32kHz */ + refr = 7; /* REFR: Refresh Rate - 8 refreshes */ + } else { + refsel = 0; /* REF_SEL: Periodic refresh cycle: 64kHz */ + refr = 1; /* REFR: Refresh Rate - 2 refreshes */ + } + mmdc0->mdref = (refsel << 14) | (refr << 11); /* Step 13: Deassert config request - init complete */ mmdc0->mdscr = 0x00000000; -- 1.9.1

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[U-Boot] [GIT] Pull request: u-boot-dfu
by Lukasz Majewski 29 Aug '16

29 Aug '16

Hi Marek, Please find following PR for u-boot dfu. Those changes are aimed to be placed on top of u-boot-usb/next tree. Moreover, they depend on already mainlined patch (but not yet available in your tree): https://patchwork.ozlabs.org/patch/661424/ With the above patch in place, no build errors are introduced. The following changes since commit fd69c4277c501a1082d118bbf8285db5f730ccdb: drivers: usb: xhci-fsl: Change burst beat and outstanding pipelined transfers requests (2016-08-26 14:05:03 +0200) are available in the git repository at: ssh://gu-dfu@git.denx.de/u-boot-dfu 02f0f6d276012f384620174bf7f72bf56785934f for you to fetch changes up to 02f0f6d276012f384620174bf7f72bf56785934f: cmd: dfu: Add error handling for failed registration (2016-08-29 14:36:35 +0200) ---------------------------------------------------------------- B, Ravi (5): spl: dfu: add dfu support in SPL common: dfu: saperate the dfu common functionality spl: dfu: adding dfu support functions for SPL-DFU dra7x: boot: add dfu bootmode support dra7x: configs: enable SPL-DFU support Sanchayan Maity (1): cmd: dfu: Add error handling for failed registration Kconfig | 27 +++++++++++++++++++++++++++ arch/arm/cpu/armv7/omap-common/boot-common.c | 5 +++++ arch/arm/include/asm/arch-omap5/spl.h | 2 +- cmd/dfu.c | 61 ++----------------------------------------------------------- common/Makefile | 3 +++ common/dfu.c | 92 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ common/spl/Makefile | 1 + common/spl/spl.c | 10 +++++++++- common/spl/spl_dfu.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/configs/dra7xx_evm.h | 20 +++++++++++++++++++- include/configs/ti_omap5_common.h | 2 -- include/g_dnl.h | 1 + include/spl.h | 8 ++++++++ scripts/Makefile.spl | 4 ++++ 14 files changed, 229 insertions(+), 64 deletions(-) create mode 100644 common/dfu.c create mode 100644 common/spl/spl_dfu.c Tested with HWT system at Exynos4412 and Exynos5422 -- Best regards, Lukasz Majewski Samsung R&D Institute Poland (SRPOL) | Linux Platform Group

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[U-Boot] [PATCH] mx6ul_14x14_evk: Fix DDR calibration values
by Fabio Estevam 29 Aug '16

29 Aug '16

From: Fabio Estevam <fabio.estevam(a)nxp.com> When running NXP 4.1 kernel with U-Boot mainline we observe a hang when going into the lowest operational point of cpufreq. Comparing the DDR calibration values against NXP U-Boot showed that the values were incorrect. Adjust the calibration values so that we can avoid such system hang. Reported-by: Eric Nelson <eric(a)nelint.com> Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index c213861..77c561d 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -784,10 +784,10 @@ static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { }; static struct mx6_mmdc_calibration mx6_mmcd_calib = { - .p0_mpwldectrl0 = 0x00070007, - .p0_mpdgctrl0 = 0x41490145, - .p0_mprddlctl = 0x40404546, - .p0_mpwrdlctl = 0x4040524D, + .p0_mpwldectrl0 = 0x00000000, + .p0_mpdgctrl0 = 0x41570155, + .p0_mprddlctl = 0x4040474A, + .p0_mpwrdlctl = 0x40405550, }; struct mx6_ddr_sysinfo ddr_sysinfo = { -- 2.7.4

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[U-Boot] [PATCH v2 1/3] mx6: ddr: Adjust MDREF register settings for MX6UL
by Fabio Estevam 29 Aug '16

29 Aug '16

From: Fabio Estevam <fabio.estevam(a)nxp.com> When running a NXP 4.1 kernel with U-Boot mainline we observe a hang when going into the lowest operational point of cpufreq. After comparing the SPL DDR initialization against the DCD table from NXP U-Boot, the key difference that causes the hang is the MDREF register setting. In all the DDR3 MX6UL boards we have the following configuration for MDREF: DATA 4 0x021B0020 0x00000800 ,which means: REF_SEL = 0 -->Periodic refresh cycle: 64kHz REFR = 1 ---> Refresh Rate - 2 refreshes So adjust the MDREF initialization for MX6UL to fix the kernel hang issue. Reported-by: Eric Nelson <eric(a)nelint.com> Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- Changes since v1: - Newly introduced in this version arch/arm/cpu/armv7/mx6/ddr.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index f151eec..56d3e65 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -1183,7 +1183,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, volatile struct mmdc_p_regs *mmdc0; volatile struct mmdc_p_regs *mmdc1; u32 val; - u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd; + u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd, refr, refsel; u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl; u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */ u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr; @@ -1472,9 +1472,15 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, MMDC1(mpzqhwctrl, val); /* Step 12: Configure and activate periodic refresh */ - mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */ - (7 << 11); /* REFR: Refresh Rate - 8 refreshes */ + if (!is_mx6ul()) { + refsel = 1; /* REF_SEL: Periodic refresh cycle: 32kHz */ + refr = 7; /* REFR: Refresh Rate - 8 refreshes */ + } else { + refsel = 0; /* REF_SEL: Periodic refresh cycle: 64kHz */ + refr = 1; /* REFR: Refresh Rate - 2 refreshes */ + } + mmdc0->mdref = (refsel << 14) | (refr << 11); /* Step 13: Deassert config request - init complete */ mmdc0->mdscr = 0x00000000; -- 1.9.1

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[U-Boot] [RFC] mmc: fsl_esdhc: fix misaligned cache operation warning
by Clemens Gruber 29 Aug '16

29 Aug '16

When using gzwrite to eMMC on an i.MX6Q board, the following warning occurs repeatedly: CACHE: Misaligned operation at range [4fd63318, 4fe63318] I tried to cache-line align the start and end parameter for flush_dcache_range in esdhc_setup_data. (Same approach as in https://patchwork.ozlabs.org/patch/656470/) After that, the "Misaligned operation" error message disappeared and everything still works for me. But is this safe and should I send the patch again with [PATCH] ? Signed-off-by: Clemens Gruber <clemens.gruber(a)pqgruber.com> --- drivers/mmc/fsl_esdhc.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 103b32e..f40b424 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -222,6 +222,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) dma_addr_t addr; #endif uint wml_value; + ulong start, end; wml_value = data->blocksize/4; @@ -243,9 +244,11 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) #endif } else { #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO - flush_dcache_range((ulong)data->src, - (ulong)data->src+data->blocks - *data->blocksize); + start = (ulong)data->src; + start &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); + end = ALIGN((ulong)data->src + data->blocks * data->blocksize, + CONFIG_SYS_CACHELINE_SIZE); + flush_dcache_range(start, end); #endif if (wml_value > WML_WR_WML_MAX) wml_value = WML_WR_WML_MAX_VAL; -- 2.9.3

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[U-Boot] mx6ul_14x14_evk
by Eric Nelson 29 Aug '16

29 Aug '16

Hi Fabio, Peng, and all. I just ran into a problem with bus frequency switching on the EVK and there appears to be a U-Boot component. Using the 4.1.15 kernel from git.freescale.com (commit a4d2a08) and the latest U-Boot from Stefano's imx tree (commit a3e5519) causes the EVK to hang during a bus frequency switch to LOW_POWER mode. The last gasp is this: Bus freq set to 24000000 start... And the code block in question is here: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/m… When using the binary U-Boot 2015.07 from the EVK package (commit d7d7c43 from git.freescale.com), the kernel gets through the frequency switch and produces this message. Bus freq set to 24000000 done! I first saw this problem with u-boot-fslc branch v2016.07 and linux-fslc (4.1.29 and 4.1.30). Has anybody else experienced this? Please advise, Eric

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[U-Boot] [PATCH v2 1/2] sunxi: add proper device tree for iNet D978 rev2 boards
by Icenowy Zheng 29 Aug '16

29 Aug '16

Add a proper dts for the iNet D978 rev2 based A33 tablets. Signed-off-by: Icenowy Zheng <icenowy(a)aosc.xyz> --- Changes since v2: - Use Hans's sun8i-reference-design-tablet.dtsi. (Note: it makes the patch depends on the sun8i-reference-design-tablet.dtsi patch) - Use the same dt file as applied into linux kernel. arch/arm/dts/Makefile | 1 + arch/arm/dts/sun8i-a33-inet-d978-rev2.dts | 88 +++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) create mode 100644 arch/arm/dts/sun8i-a33-inet-d978-rev2.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 223124e..d2749da 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -239,6 +239,7 @@ dtb-$(CONFIG_MACH_SUN8I_A23) += \ sun8i-a23-q8-tablet.dtb dtb-$(CONFIG_MACH_SUN8I_A33) += \ sun8i-a33-ga10h-v1.1.dtb \ + sun8i-a33-inet-d978-rev2.dtb \ sun8i-a33-q8-tablet.dtb \ sun8i-a33-sinlinx-sina33.dtb \ sun8i-r16-parrot.dtb diff --git a/arch/arm/dts/sun8i-a33-inet-d978-rev2.dts b/arch/arm/dts/sun8i-a33-inet-d978-rev2.dts new file mode 100644 index 0000000..0f52cd9 --- /dev/null +++ b/arch/arm/dts/sun8i-a33-inet-d978-rev2.dts @@ -0,0 +1,88 @@ +/* + * Copyright 2015 Hans de Goede <hdegoede(a)redhat.com> + * Copyright 2016 Icenowy Zheng <icenowy(a)aosc.xyz> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sun8i-reference-design-tablet.dtsi" + +/ { + model = "INet-D978 Rev 02"; + compatible = "primux,inet-d978-rev2", "allwinner,sun8i-a33"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_d978>; + + home { + label = "d978:blue:home"; + gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + }; + }; +}; + +&mmc1_pins_a { + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <&reg_dldo1>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8723bs: sdio_wifi@1 { + reg = <1>; + }; +}; + +&r_pio { + led_pin_d978: led_pin_d978@0 { + allwinner,pins = "PL5"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_20_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; -- 2.9.3

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