July 2016 - U-Boot

[U-Boot] keystone: k2h/e/l: Fix DMA coherency for QM PDSP
by Murali Karicheri 18 Jul '16

18 Jul '16

commit 1f807a9f32aa ("ARM: keystone2: Refactor MSMC macros to avoid #ifdeffery") refactored code, however K2HKLE_MSMC_SEGMENT_QM_PDSP is left under a macro KS2_MSMC_SEGMENT_QM_PDSP which is no longer valid. This, in effect disabled DMA coherency for QM PDSP. Given that msmc_k2hkle_common_setup is valid for all K2H/K/L/E SoCs, the #ifdef should been removed in the first place. Do the same. Signed-off-by: Murali Karicheri <m-karicheri2(a)ti.com> Acked-by: Nishanth Menon <nm(a)ti.com> --- arch/arm/mach-keystone/init.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c index 3b6d5ef..6e5a1e1 100644 --- a/arch/arm/mach-keystone/init.c +++ b/arch/arm/mach-keystone/init.c @@ -101,9 +101,7 @@ static void msmc_k2hkle_common_setup(void) msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0); msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM); msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP); -#ifdef KS2_MSMC_SEGMENT_QM_PDSP msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP); -#endif msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0); msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG); } -- 1.9.1

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[U-Boot] [PATCH] test: Adjust the of-platdata test run condition
by Simon Glass 18 Jul '16

18 Jul '16

This should be spl_of_platdata, since otherwise it will try to run on boards that don't support of-platdata. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- test/py/tests/test_ofplatdata.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/py/tests/test_ofplatdata.py b/test/py/tests/test_ofplatdata.py index c8b309e..457c405 100644 --- a/test/py/tests/test_ofplatdata.py +++ b/test/py/tests/test_ofplatdata.py @@ -34,7 +34,7 @@ string <NULL> stringarray "one" "" "" ''' -(a)pytest.mark.buildconfigspec('spl') +(a)pytest.mark.buildconfigspec('spl_of_platdata') def test_ofplatdata(u_boot_console): """Test that of-platdata can be generated and used in sandbox""" cons = u_boot_console -- 2.8.0.rc3.226.g39d4020

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[U-Boot] supported image compression types?
by Robert P. J. Day 18 Jul '16

18 Jul '16

reading u-boot wiki page on image formats: http://www.denx.de/wiki/view/DULG/UBootImages wherein one reads: "Compression Type (Provisions for uncompressed, gzip, bzip2, lzo; Currently supported: uncompressed, gzip, bzip2, lzo)." clearly, that wiki page list is incomplete, but there's more here. first, the full list appears to live in include/image.h: /* * Compression Types */ enum { IH_COMP_NONE = 0, /* No Compression Used */ IH_COMP_GZIP, /* gzip Compression Used */ IH_COMP_BZIP2, /* bzip2 Compression Used */ IH_COMP_LZMA, /* lzma Compression Used */ IH_COMP_LZO, /* lzo Compression Used */ IH_COMP_LZ4, /* lz4 Compression Used */ IH_COMP_COUNT, }; but how those types are selected seems a bit inconsistent. first, gzip appears to be automatic(?) for everyone, from include/config_defaults.h: #define CONFIG_GZIP 1 however, of all 5 types of compression, only one has a Kconfig file entry, LZ4, in lib/Kconfig: menu "Compression Support" config LZ4 bool "Enable LZ4 decompression support" help If this option is set, support for LZ4 compressed images is included. The LZ4 algorithm can run in-place as long as the compressed image is loaded to the end of the output buffer, and trades lower compression ratios for much faster decompression. NOTE: This implements the release version of the LZ4 frame format as generated by default by the 'lz4' command line tool. This is not the same as the outdated, less efficient legacy frame format currently (2015) implemented in the Linux kernel (generated by 'lz4 -l'). The two formats are incompatible. endmenu for consistency, isn't it standard for any CONFIG_* settings to be defined in Kconfig files? the other compression types seem to be selectable simply by manually setting them in config files, as in: $ grep -r "define CONFIG_LZMA" * include/configs/bfin_adi_common.h:#define CONFIG_LZMA include/configs/VCMA9.h:#define CONFIG_LZMA include/configs/ap143.h:#define CONFIG_LZMA include/configs/qemu-mips.h:#define CONFIG_LZMA include/configs/iconnect.h:#define CONFIG_LZMA include/configs/ap121.h:#define CONFIG_LZMA include/configs/nsa310s.h:#define CONFIG_LZMA include/configs/mv-plug-common.h:#define CONFIG_LZMA include/configs/ib62x0.h:#define CONFIG_LZMA include/configs/qemu-mips64.h:#define CONFIG_LZMA include/configs/tplink_wdr4300.h:#define CONFIG_LZMA include/configs/sandbox.h:#define CONFIG_LZMA include/configs/smdk2410.h:#define CONFIG_LZMA $ should not all compression types get their own entries in lib/Kconfig? anyway, i'll at least update the wiki page. movin' on ... rday -- ======================================================================== Robert P. J. Day Ottawa, Ontario, CANADA http://crashcourse.ca Twitter: http://twitter.com/rpjday LinkedIn: http://ca.linkedin.com/in/rpjday ========================================================================

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[U-Boot] [PATCH 1/3] ARM64: zynqmp: Enable CLK and SPL_CLK by default
by Michal Simek 18 Jul '16

18 Jul '16

Serial driver starts to use clk framework that's why enable it by default. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/Kconfig | 2 ++ configs/xilinx_zynqmp_ep_defconfig | 2 -- configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 2 -- configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 2 -- configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 2 -- configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 2 -- configs/xilinx_zynqmp_zcu102_defconfig | 2 -- configs/xilinx_zynqmp_zcu102_revB_defconfig | 2 -- 8 files changed, 2 insertions(+), 14 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3237a74f7223..f01eadf69f5e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -669,6 +669,8 @@ config ARCH_ZYNQMP select OF_CONTROL select DM_SERIAL select SUPPORT_SPL + select CLK + select SPL_CLK config TEGRA bool "NVIDIA Tegra" diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index fa380ef7f08f..b02ab0883543 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -42,8 +42,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_SYS_I2C_CADENCE=y CONFIG_DM_MMC=y CONFIG_ZYNQ_SDHCI=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 35226d6fd3c9..b11586211adb 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -33,8 +33,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_SYS_I2C_CADENCE=y CONFIG_DM_MMC=y CONFIG_ZYNQ_SDHCI=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index cc13179a1e5f..d1e8778dc4c8 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -33,8 +33,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_SYS_I2C_CADENCE=y CONFIG_DM_MMC=y CONFIG_NAND_ARASAN=y diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig index 65703481ae31..4342e0546b0c 100644 --- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@ -29,8 +29,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_SYS_I2C_CADENCE=y CONFIG_DM_MMC=y CONFIG_ZYNQ_SDHCI=y diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig index e1fc8b0ee271..06c07c128a65 100644 --- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig @@ -28,8 +28,6 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_SYS_I2C_CADENCE=y CONFIG_DM_MMC=y CONFIG_ZYNQ_SDHCI=y diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig index 28290296853d..140b80017295 100644 --- a/configs/xilinx_zynqmp_zcu102_defconfig +++ b/configs/xilinx_zynqmp_zcu102_defconfig @@ -32,8 +32,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_DM_MMC=y CONFIG_ZYNQ_SDHCI=y CONFIG_SPI_FLASH=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 92633d6fcc98..727e22c267ab 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -32,8 +32,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_EMBED=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y CONFIG_DM_MMC=y CONFIG_ZYNQ_SDHCI=y CONFIG_SPI_FLASH=y -- 1.9.1

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[U-Boot] [PATCH] mx6: clock: Fix the logic for reading axi_alt_sel
by Fabio Estevam 18 Jul '16

18 Jul '16

According to the IMX6DQRM Reference Manual, the description of bit 7 (axi_alt_sel) of the CCM_CBCDR register is: "AXI alternative clock select 0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock 1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock " The current logic is inverted, so fix it to match the reference manual. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- arch/arm/cpu/armv7/mx6/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index ff932aa..1904c96 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -433,9 +433,9 @@ static u32 get_axi_clk(void) if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) - root_freq = mxc_get_pll_pfd(PLL_BUS, 2); - else root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1); + else + root_freq = mxc_get_pll_pfd(PLL_BUS, 2); } else root_freq = get_periph_clk(); -- 1.9.1

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[U-Boot] [PATCH] Revert "Revert "rockchip: rk3288: correct sdram setting""
by John Keeping 18 Jul '16

18 Jul '16

The original commit was correct, except fot the priority of the mask when extracting "bw" to calculate the SDRAM size. Add the necessary parentheses so that we can apply the original fix. This reverts commit b525556e6325aa71427c0519f36247981cd444df. Signed-off-by: John Keeping <john(a)metanate.com> --- arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c index b36b6af..ef8b712 100644 --- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c @@ -575,14 +575,14 @@ static void dram_all_config(const struct dram_info *dram, &sdram_params->ch[chan]; sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); - sys_reg |= chan << SYS_REG_CHINFO_SHIFT(chan); + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); - sys_reg |= info->bk == 3 ? 1 << SYS_REG_BK_SHIFT(chan) : 0; + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); - sys_reg |= info->bw << SYS_REG_BW_SHIFT(chan); - sys_reg |= info->dbw << SYS_REG_DBW_SHIFT(chan); + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); } @@ -734,13 +734,13 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu) rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & SYS_REG_RANK_MASK); col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); - bk = sys_reg & (1 << SYS_REG_BK_SHIFT(ch)) ? 3 : 0; + bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & SYS_REG_CS0_ROW_MASK); cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & SYS_REG_CS1_ROW_MASK); - bw = (sys_reg >> SYS_REG_BW_SHIFT(ch)) & - SYS_REG_BW_MASK; + bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & + SYS_REG_BW_MASK)); row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & SYS_REG_ROW_3_4_MASK; -- 2.9.0.465.g8850cbc.dirty

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[U-Boot] [PATCH] mmc: rockchip: add SDHCI driver support for rockchip soc
by Kever Yang 18 Jul '16

18 Jul '16

Rockchip rk3399 using arasan sdhci-5.1 controller. This patch add the controller support to enable mmc device with full driver-model support, tested on rk3399 evb board. According to my test result, this driver should be OK, the command "part list mmc 0" can result in a right output, but all the mmc command failed like this: => mmc info No MMC device available Command failed, result=1 The result of get_mmc_num in cmd/mmc.c is always 0? Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- drivers/mmc/Kconfig | 6 +++ drivers/mmc/Makefile | 1 + drivers/mmc/rockchip_sdhci.c | 93 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 100 insertions(+) create mode 100644 drivers/mmc/rockchip_sdhci.c diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index e0adb9b..dc8f2b6 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -61,6 +61,12 @@ config ZYNQ_SDHCI help Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs platform +config ROCKCHIP_SDHCI + bool "Arasan SDHCI controller for Rockchip support" + depends on DM_MMC && BLK && DM_MMC_OPS + help + Support for Arasan SDHCI host controller on Rockchip ARM SoCs platform + config MMC_UNIPHIER bool "UniPhier SD/MMC Host Controller support" depends on ARCH_UNIPHIER diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index b44a12e..18351fb 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o +obj-$(CONFIG_ROCKCHIP_SDHCI) += rockchip_sdhci.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c new file mode 100644 index 0000000..023c29b --- /dev/null +++ b/drivers/mmc/rockchip_sdhci.c @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * Rockchip SD Host Controller Interface + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <malloc.h> +#include <sdhci.h> + +/* 400KHz is max freq for card ID etc. Use that as min */ +#define EMMC_MIN_FREQ 400000 + +struct rockchip_sdhc_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +struct rockchip_sdhc { + struct sdhci_host host; + void *base; +}; + +static int arasan_sdhci_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); + struct rockchip_sdhc *prv = dev_get_priv(dev); + struct sdhci_host *host = &prv->host; + int ret; + u32 caps; + + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; + + caps = sdhci_readl(host, SDHCI_CAPABILITIES); + ret = sdhci_setup_cfg(&plat->cfg, dev->name, host->bus_width, + caps, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ, EMMC_MIN_FREQ, + host->version, host->quirks, 0); + + host->mmc = &plat->mmc; + if (ret) + return ret; + host->mmc->priv = &prv->host; + host->mmc->dev = dev; + upriv->mmc = host->mmc; + + return sdhci_probe(dev); +} + +static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) +{ + struct sdhci_host *host = dev_get_priv(dev); + + host->name = dev->name; + host->ioaddr = dev_get_addr_ptr(dev); + + return 0; +} + +static int rockchip_sdhci_bind(struct udevice *dev) +{ + struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); + int ret; + + ret = sdhci_bind(dev, &plat->mmc, &plat->cfg); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id arasan_sdhci_ids[] = { + { .compatible = "arasan,sdhci-5.1" }, + { } +}; + +U_BOOT_DRIVER(arasan_sdhci_drv) = { + .name = "arasan_sdhci", + .id = UCLASS_MMC, + .of_match = arasan_sdhci_ids, + .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata, + .ops = &sdhci_ops, + .bind = rockchip_sdhci_bind, + .probe = arasan_sdhci_probe, + .priv_auto_alloc_size = sizeof(struct rockchip_sdhc), + .platdata_auto_alloc_size = sizeof(struct rockchip_sdhc_plat), +}; -- 1.9.1

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[U-Boot] [PATCH] rockchip: update fastboot usage
by Ziyuan Xu 18 Jul '16

18 Jul '16

Introduce how to use fastboot feature on rk3288. Signed-off-by: Ziyuan Xu <xzy.xu(a)rock-chips.com> --- doc/README.rockchip | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/doc/README.rockchip b/doc/README.rockchip index 3fc2582..c218a8b 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -144,6 +144,32 @@ For evb_rk3036 board: Note: rk3036 SDMMC and debug uart use the same iomux, so if you boot from SD, the debug uart must be disabled +Using fastboot on rk3288 +======================== +- Define GPT partition layout like kylin_rk3036(see include/configs/kylin_rk3036.h) +- Write GPT partition layout to mmc device which fastboot want to use it to +store the image + + => gpt write mmc 1 $partitions + +- Invoke fastboot command to prepare + + => fastboot 1 + +- Start fastboot request on PC + + fastboot -i 0x2207 flash loader evb-rk3288/spl/u-boot-spl-dtb.bin + +You should see something like: + + => fastboot 1 + WARNING: unknown variable: partition-type:loader + Starting download of 357796 bytes + .. + downloading of 357796 bytes finished + Flashing Raw Image + ........ wrote 357888 bytes to 'loader' + Booting from SPI ================ -- 1.9.1

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[U-Boot] [PATCH v2] mkimage: rockchip: add suport for rk33 serial
by Kever Yang 18 Jul '16

18 Jul '16

Add support for rockchip rk33 series Soc like rk3368 and rk3399 Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- Changes in v2: Using rk3399 instead of rk33xx tools/rkcommon.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 72621fd..0a072aa 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -56,6 +56,7 @@ struct spl_info { static struct spl_info spl_infos[] = { { "rk3036", "RK30", 0x1000 }, { "rk3288", "RK32", 0x8000 }, + { "rk3399", "RK33", 0x20000 }, }; static unsigned char rc4_key[16] = { -- 1.9.1

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[U-Boot] [mips][cfi] Unable to write into flash under qemu
by Alon Bar-Lev 18 Jul '16

18 Jul '16

Hello, I am using malta board within qemu. I tried recent releases and master of both. Two years ago in qemu-1.5 and qemu-1.6 I could use erase and cp.b in order to erase and write to the flash. Now when I try to erase flash I get an error suggesting the erase failed, however, I do see 0xff all over in the device backed file (-pflash). When I try to write I also receive a failure message. I am unsure how to debug this, I went back in time and tried the qemu-1.6 and got same error. I suspect it is has something to do with u-boot CFI driver. Can anyone help determine if issue is at qemu side or at u-boot side? How can I debug this? Thanks, Alon

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