June 2016 - U-Boot

[U-Boot] mmc hwpartition question
by Matthias Fuchs 03 Jun '16

03 Jun '16

Hi, I am trying to setup an eMMC chip's user data area fully as enhanced type. Well, trying is probably wrong because its an OTP action and therefore I try to figure out the correct command on first try :-) U-Boot's "mmc hwpartition" command should be able to do this, but how? Where can I find out the max value for the size parameter to get the _full_ chip into enhanced mode? Any ideas? Regards, Matthias

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[U-Boot] [PATCH] power: pfuze100: Update definitions
by Eran Matityahu 03 Jun '16

03 Jun '16

- Add definitions and macros for buck regulators SW2,SW3A/B and SW4 (SWx) with low and high output voltage ranges - Add definitions for LDO mode (ON/OFF/LPM combinations at Normal & Standby modes) Signed-off-by: Eran Matityahu <eran.m(a)variscite.com> --- include/power/pfuze100_pmic.h | 208 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 197 insertions(+), 11 deletions(-) diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h index 41cb710..04219be 100644 --- a/include/power/pfuze100_pmic.h +++ b/include/power/pfuze100_pmic.h @@ -73,9 +73,13 @@ enum { * Buck Regulators */ +#define SW_MODE_MASK 0xf +#define SW_MODE_SHIFT 0 + +/* SW1A/B/C */ #define PFUZE100_SW1ABC_SETP(x) ((x - 3000) / 250) -/* SW1A/B/C Output Voltage Configuration */ +/* Output Voltage Configuration */ #define SW1x_0_300V 0 #define SW1x_0_325V 1 #define SW1x_0_350V 2 @@ -141,18 +145,161 @@ enum { #define SW1x_1_850V 62 #define SW1x_1_875V 63 -#define SW1x_NORMAL_MASK 0x3f -#define SW1x_STBY_MASK 0x3f -#define SW1x_OFF_MASK 0x3f +#define SW1x_NORMAL_MASK 0x3f +#define SW1x_STBY_MASK 0x3f +#define SW1x_OFF_MASK 0x3f -#define SW_MODE_MASK 0xf -#define SW_MODE_SHIFT 0 +#define SW1xCONF_DVSSPEED_MASK 0xc0 +#define SW1xCONF_DVSSPEED_2US 0x00 +#define SW1xCONF_DVSSPEED_4US 0x40 +#define SW1xCONF_DVSSPEED_8US 0x80 +#define SW1xCONF_DVSSPEED_16US 0xc0 + + +/* SW2,SW3A/B and SW4 */ + +/* + * PFUZE100_SWxVOL[bit 6] == 0 -> Low Range used + * PFUZE100_SWxVOL[bit 6] == 1 -> High Range used + * + * In order to optimize the performance: + * 0.4V to 1.975V should be used in Low Range, and + * 2.0V to 3.300V should be used in the High Range + */ +#define PFUZE100_SWx_LR_SETP(x) ((x - 4000) / 250) +#define PFUZE100_SWx_HR_SETP(x) (((x - 8000) / 500) + 64) + +/* Output Voltage Configuration */ + +/* Low output voltage range */ +#define SWx_LR_0_400V 0 +#define SWx_LR_0_425V 1 +#define SWx_LR_0_450V 2 +#define SWx_LR_0_475V 3 +#define SWx_LR_0_500V 4 +#define SWx_LR_0_525V 5 +#define SWx_LR_0_550V 6 +#define SWx_LR_0_575V 7 +#define SWx_LR_0_600V 8 +#define SWx_LR_0_625V 9 +#define SWx_LR_0_650V 10 +#define SWx_LR_0_675V 11 +#define SWx_LR_0_700V 12 +#define SWx_LR_0_725V 13 +#define SWx_LR_0_750V 14 +#define SWx_LR_0_775V 15 +#define SWx_LR_0_800V 16 +#define SWx_LR_0_825V 17 +#define SWx_LR_0_850V 18 +#define SWx_LR_0_875V 19 +#define SWx_LR_0_900V 20 +#define SWx_LR_0_925V 21 +#define SWx_LR_0_950V 22 +#define SWx_LR_0_975V 23 +#define SWx_LR_1_000V 24 +#define SWx_LR_1_025V 25 +#define SWx_LR_1_050V 26 +#define SWx_LR_1_075V 27 +#define SWx_LR_1_100V 28 +#define SWx_LR_1_125V 29 +#define SWx_LR_1_150V 30 +#define SWx_LR_1_175V 31 +#define SWx_LR_1_200V 32 +#define SWx_LR_1_225V 33 +#define SWx_LR_1_250V 34 +#define SWx_LR_1_275V 35 +#define SWx_LR_1_300V 36 +#define SWx_LR_1_325V 37 +#define SWx_LR_1_350V 38 +#define SWx_LR_1_375V 39 +#define SWx_LR_1_400V 40 +#define SWx_LR_1_425V 41 +#define SWx_LR_1_450V 42 +#define SWx_LR_1_475V 43 +#define SWx_LR_1_500V 44 +#define SWx_LR_1_525V 45 +#define SWx_LR_1_550V 46 +#define SWx_LR_1_575V 47 +#define SWx_LR_1_600V 48 +#define SWx_LR_1_625V 49 +#define SWx_LR_1_650V 50 +#define SWx_LR_1_675V 51 +#define SWx_LR_1_700V 52 +#define SWx_LR_1_725V 53 +#define SWx_LR_1_750V 54 +#define SWx_LR_1_775V 55 +#define SWx_LR_1_800V 56 +#define SWx_LR_1_825V 57 +#define SWx_LR_1_850V 58 +#define SWx_LR_1_875V 59 +#define SWx_LR_1_900V 60 +#define SWx_LR_1_925V 61 +#define SWx_LR_1_950V 62 +#define SWx_LR_1_975V 63 + +/* High output voltage range */ +#define SWx_HR_0_800V 64 +#define SWx_HR_0_850V 65 +#define SWx_HR_0_900V 66 +#define SWx_HR_0_950V 67 +#define SWx_HR_1_000V 68 +#define SWx_HR_1_050V 69 +#define SWx_HR_1_100V 70 +#define SWx_HR_1_150V 71 +#define SWx_HR_1_200V 72 +#define SWx_HR_1_250V 73 +#define SWx_HR_1_300V 74 +#define SWx_HR_1_350V 75 +#define SWx_HR_1_400V 76 +#define SWx_HR_1_450V 77 +#define SWx_HR_1_500V 78 +#define SWx_HR_1_550V 79 +#define SWx_HR_1_600V 80 +#define SWx_HR_1_650V 81 +#define SWx_HR_1_700V 82 +#define SWx_HR_1_750V 83 +#define SWx_HR_1_800V 84 +#define SWx_HR_1_850V 85 +#define SWx_HR_1_900V 86 +#define SWx_HR_1_950V 87 +#define SWx_HR_2_000V 88 +#define SWx_HR_2_050V 89 +#define SWx_HR_2_100V 90 +#define SWx_HR_2_150V 91 +#define SWx_HR_2_200V 92 +#define SWx_HR_2_250V 93 +#define SWx_HR_2_300V 94 +#define SWx_HR_2_350V 95 +#define SWx_HR_2_400V 96 +#define SWx_HR_2_450V 97 +#define SWx_HR_2_500V 98 +#define SWx_HR_2_550V 99 +#define SWx_HR_2_600V 100 +#define SWx_HR_2_650V 101 +#define SWx_HR_2_700V 102 +#define SWx_HR_2_750V 103 +#define SWx_HR_2_800V 104 +#define SWx_HR_2_850V 105 +#define SWx_HR_2_900V 106 +#define SWx_HR_2_950V 107 +#define SWx_HR_3_000V 108 +#define SWx_HR_3_050V 109 +#define SWx_HR_3_100V 110 +#define SWx_HR_3_150V 111 +#define SWx_HR_3_200V 112 +#define SWx_HR_3_250V 113 +#define SWx_HR_3_300V 114 + +/* Note that bit 6 is read only */ +#define SWx_NORMAL_MASK 0x7f +#define SWx_STBY_MASK 0x7f +#define SWx_OFF_MASK 0x7f -#define SW1xCONF_DVSSPEED_MASK 0xc0 -#define SW1xCONF_DVSSPEED_2US 0x00 -#define SW1xCONF_DVSSPEED_4US 0x40 -#define SW1xCONF_DVSSPEED_8US 0x80 -#define SW1xCONF_DVSSPEED_16US 0xc0 +#define SWxCONF_DVSSPEED_MASK 0xc0 +#define SWxCONF_DVSSPEED_4US 0x00 +#define SWxCONF_DVSSPEED_8US 0x40 +#define SWxCONF_DVSSPEED_16US 0x80 +#define SWxCONF_DVSSPEED_32US 0xc0 /* * LDO Configuration @@ -195,12 +342,51 @@ enum { #define LDOB_3_30V 15 #define LDO_VOL_MASK 0xf + +/* + * LDO Mode Control + * + * VGENxCTL[4] + * Mode | value + * ON 0x0 + * OFF 0x1 + */ #define LDO_EN (1 << 4) #define LDO_MODE_SHIFT 4 #define LDO_MODE_MASK (1 << 4) #define LDO_MODE_OFF 0 #define LDO_MODE_ON 1 +/* + * LDO "Extended" Mode Control + * + * If LDO Mode (VGENxCTL[4]) is ON: + * + * VGENxCTL[6:5] + * Normal Mode | Standby Mode | value + * ON ON 0x0 + * LOW POWER LOW POWER 0x1 + * ON OFF 0x2 + * ON LOW POWER 0x3 + * + * + * If LDO Mode (VGENxCTL[4]) is OFF: + * + * VGENxCTL[6:5] + * Normal Mode | Standby Mode | value + * OFF OFF Irrelevant + * + */ +#define LDO_STBY (1 << 5) +#define LDO_LPWR (1 << 6) +#define LDO_EXT_MODE_SHIFT 5 +#define LDO_EXT_MODE_MASK (3 << 5) +#define LDO_EXT_MODE_ON_ON 0 +#define LDO_EXT_MODE_LPM_LPM 1 +#define LDO_EXT_MODE_ON_OFF 2 +#define LDO_EXT_MODE_ON_LPM 3 + + #define VREFDDRCON_EN (1 << 4) /* * Boost Regulator -- 1.9.1

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[U-Boot] [PATCH v2 00/12] am335x: add support for the am335x based bosch shc board
by Heiko Schocher 03 Jun '16

03 Jun '16

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[U-Boot] [PATCH] ti_armv7_common: env: Fix hard coded mmc device for uuid
by Ravi Babu 03 Jun '16

03 Jun '16

Avoid use of hard coded mmcdev value so finduuid works based on current mmcdev selected. Signed-off-by: Ravi Babu <ravibabu(a)ti.com> --- include/configs/ti_armv7_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 7db0881..bbff06b 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -59,7 +59,7 @@ #define DEFAULT_MMC_TI_ARGS \ "mmcdev=0\0" \ "mmcrootfstype=ext4 rootwait\0" \ - "finduuid=part uuid mmc 0:2 uuid\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ "args_mmc=run finduuid;setenv bootargs console=${console} " \ "${optargs} " \ "root=PARTUUID=${uuid} rw " \ -- 1.7.9.5

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[U-Boot] [PATCH] arm: Select CONFIG_ARM64 for Cavium ThunderX
by Marek Vasut 03 Jun '16

03 Jun '16

Select the config option, since this board is ARM64. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)konsulko.com> --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f82f5a8..77eab66 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -780,6 +780,7 @@ config ARCH_ROCKCHIP config TARGET_THUNDERX_88XX bool "Support ThunderX 88xx" + select ARM64 select OF_CONTROL endchoice -- 2.7.0

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[U-Boot] [PATCH] mips: wdr4300: Move the CONFIG_USE_PRIVATE_LIBGCC to Kconfig
by Marek Vasut 03 Jun '16

03 Jun '16

This fixes the last remaining libgcc warning, where the symbol was defined twice. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)konsulko.com> --- configs/tplink_wdr4300_defconfig | 1 + include/configs/tplink_wdr4300.h | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig index b1af2f6..3eec4c2 100644 --- a/configs/tplink_wdr4300_defconfig +++ b/configs/tplink_wdr4300_defconfig @@ -1,6 +1,7 @@ CONFIG_MIPS=y CONFIG_ARCH_ATH79=y CONFIG_BOARD_TPLINK_WDR4300=y +CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SYS_NS16550=y CONFIG_DM_SERIAL=y diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index 6273711..abe1da2 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -78,8 +78,6 @@ #define CONFIG_SYS_MEMTEST_END 0x83f00000 #define CONFIG_CMD_MEMTEST -#define CONFIG_USE_PRIVATE_LIBGCC - #define CONFIG_CMD_MII #define CONFIG_PHY_GIGE -- 2.7.0

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[U-Boot] [PATCH 1/2] tiny-printf: Support sprintf()
by Marek Vasut 03 Jun '16

03 Jun '16

Add a simple version of this function for SPL. It does not check the buffer size as this would add to the code size. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Stefan Roese <sr(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> Cc: lesne(a)alse-fr.com --- lib/tiny-printf.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c index 4b70263..5ea2555 100644 --- a/lib/tiny-printf.c +++ b/lib/tiny-printf.c @@ -147,8 +147,7 @@ static void putc_outstr(char ch) *outstr++ = ch; } -/* Note that size is ignored */ -int snprintf(char *buf, size_t size, const char *fmt, ...) +int sprintf(char *buf, const char *fmt, ...) { va_list va; int ret; @@ -161,3 +160,16 @@ int snprintf(char *buf, size_t size, const char *fmt, ...) return ret; } + +/* Note that size is ignored */ +int snprintf(char *buf, size_t size, const char *fmt, ...) +{ + va_list va; + int ret; + + va_start(va, fmt); + ret = sprintf(buf, fmt, va); + va_end(va); + + return ret; +} -- 2.7.0

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[U-Boot] [PATCH] ARM: k2g: Configure reset mux to device reset
by Lokesh Vutla 03 Jun '16

03 Jun '16

BOOTCFG_RSTMUX8 register controls the reset mux associated with the ARM. Timer5(dedicated to ARM) when used as WatchDog timer, the events it generates are routed to the above mux. Following are the 3 events that can controlled bt the reset mux: - Device Reset - An interrupt to the ARM_GIC - An interrupt to the ARM_GIC followed by a device reset. Right now to give a default watchdog behaviour "Device reset" is being selected. Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- arch/arm/mach-keystone/include/mach/hardware-k2g.h | 12 ++++++++++++ board/ti/ks2_evm/board_k2g.c | 16 ++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h index ca2a119..0f6bf61 100644 --- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h +++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h @@ -74,4 +74,16 @@ #define K2G_GPIO_DIR_OFFSET 0x0 #define K2G_GPIO_SETDATA_OFFSET 0x8 +/* BOOTCFG RESETMUX8 */ +#define KS2_RSTMUX8 (KS2_DEVICE_STATE_CTRL_BASE + 0x328) + +/* RESETMUX register definitions */ +#define RSTMUX_LOCK8_SHIFT 0x0 +#define RSTMUX_LOCK8_MASK (0x1 << 0) +#define RSTMUX_OMODE8_SHIFT 0x1 +#define RSTMUX_OMODE8_MASK (0x7 << 1) +#define RSTMUX_OMODE8_DEV_RESET 0x2 +#define RSTMUX_OMODE8_INT 0x3 +#define RSTMUX_OMODE8_INT_AND_DEV_RESET 0x4 + #endif /* __ASM_ARCH_HARDWARE_K2G_H */ diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index b62c412..8f16845 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -117,12 +117,28 @@ int board_mmc_init(bd_t *bis) #endif #ifdef CONFIG_BOARD_EARLY_INIT_F + +static void k2g_reset_mux_config(void) +{ + /* Unlock the reset mux register */ + clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK); + + /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */ + clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK, + RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT); + + /* lock the reset mux register to prevent any spurious writes. */ + setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK); +} + int board_early_init_f(void) { init_plls(); k2g_mux_config(); + k2g_reset_mux_config(); + /* deassert FLASH_HOLD */ clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET, BIT(9)); -- 2.8.2

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[U-Boot] [PATCH] spl: Allow settings malloc_f base address
by Marek Vasut 03 Jun '16

03 Jun '16

Allow configuring the begining of the malloc_f area in SPL. This patch uses the same CONFIG_MALLOC_F_ADDR established by the sandbox. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> Cc: Simon Glass <sjg(a)chromium.org> --- common/spl/spl.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/common/spl/spl.c b/common/spl/spl.c index 93f9bd1..56c64d1 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -160,6 +160,9 @@ int spl_init(void) debug("spl_init()\n"); #if defined(CONFIG_SYS_MALLOC_F_LEN) +#ifdef CONFIG_MALLOC_F_ADDR + gd->malloc_base = CONFIG_MALLOC_F_ADDR; +#endif gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN; gd->malloc_ptr = 0; #endif -- 2.7.0

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[U-Boot] [PATCH] serial: 16550: Drop OMAP1510 support
by Marek Vasut 03 Jun '16

03 Jun '16

The CONFIG_OMAP1510 is no longer defined, so remove this dead code. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> Cc: Simon Glass <sjg(a)chromium.org> --- drivers/serial/ns16550.c | 20 +++----------------- 1 file changed, 3 insertions(+), 17 deletions(-) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index a1a26a2..30ba0aa 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -128,27 +128,13 @@ static int ns16550_readb(NS16550_t port, int offset) (unsigned char *)addr - (unsigned char *)com_port) #endif -static inline int calc_divisor(NS16550_t port, int clock, int baudrate) +int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate) { const unsigned int mode_x_div = 16; return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate); } -int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate) -{ -#ifdef CONFIG_OMAP1510 - /* If can't cleanly clock 115200 set div to 1 */ - if ((clock == 12000000) && (baudrate == 115200)) { - port->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */ - return 1; /* return 1 for base divisor */ - } - port->osc_12m_sel = 0; /* clear if previsouly set */ -#endif - - return calc_divisor(port, clock, baudrate); -} - static void NS16550_setbrg(NS16550_t com_port, int baud_divisor) { serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); @@ -271,8 +257,8 @@ static inline void _debug_uart_init(void) * feasible. The better fix is to move all users of this driver to * driver model. */ - baud_divisor = calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, - CONFIG_BAUDRATE); + baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, + CONFIG_BAUDRATE); serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); serial_dout(&com_port->mcr, UART_MCRVAL); serial_dout(&com_port->fcr, UART_FCRVAL); -- 2.7.0

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