June 2016 - U-Boot

[U-Boot] moveconfig.py removes defconfig entries for "choice" Kconfig settings ?
by Hans de Goede 11 Jun '16

11 Jun '16

Hi All, While looking into adding a DISTRO_DEFAULTS Kconfig option, I noted that commit bb597c0eeb7e besides introducing the BOOT_DELAY issues we've been discussing also removes CONFIG_MACH_SUN4I=y From the defconfig of all sun4i (Allwinner A10) based boards. This is defined in board/sunxi/Kconfig : choice prompt "Sunxi SoC Variant" config MACH_SUN4I bool "sun4i (Allwinner A10)" select CPU_V7 select SUNXI_GEN_SUN4I select SUPPORT_SPL config MACH_SUN5I bool "sun5i (Allwinner A13)" select CPU_V7 select SUNXI_GEN_SUN4I select SUPPORT_SPL config MACH_SUN6I bool "sun6i (Allwinner A31)" select CPU_V7 select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select SUNXI_GEN_SUN6I select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT ... endchoice And it seems that moveconfig.py now has decided to remove the explicit setting of this from all defconfig's which were setting it to the first choice, this seems wrong, since this means that if we now choose to sort choice options differently all of a sudden things change. I guess this may be caused by: http://git.denx.de/?p=u-boot.git;a=commitdiff;h=1a5f0de08e86f2f127aaac928fe… But that commit in itself seems sensible, and this seems like a surprising result, since there is no default defined in the Kconfig. Anyways if this considered not a bug from the moveconfig.py pov then I'll revert the above commit, as I do want the sun?i family to be clearly stated in the defconfig in all cases. Regards, Hans

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Re: [U-Boot] U-Boot on Minnowboard Max
by Bin Meng 11 Jun '16

11 Jun '16

Hi, +Simon, ML and Stefan. On Wed, Jun 8, 2016 at 11:58 PM, vinoth eswaran <evinoth1206(a)gmail.com> wrote: > Hello Bin, > > Sorry that I don't know how not to reply without top-posting. I > don't know which settings to change, google didn't help me in this > case. > It's a posting style. See https://en.wikipedia.org/wiki/Posting_style. We use bottom-posting. > I have tested your patch on my target and found out that now mounting > root file system by sd card is fine. Thanks a lot :) > Great! > Now I am seeing another issue , the USB3.0 port (bottom) is not > working. I am sure that both ports are working fine with UEFI > Firmware. I tested by connecting a mouse to the USB port , in the > USB2.0 port (upper) it is working fine but in the USB3.0 port the > mouse is not getting detected. I am not sure why it is happening. I > looked into the kernel logs but I didn't get any error/debug messages. > Can you please check this on your board also. > Do you mean xHCI is not working under U-Boot? xHCI is not enabled in U-Boot yet. IIRC, U-Boot's xHCI driver does not support Intel controller yet. > Do you have any documents regarding the u-boot to kernel handover, > what all informations does u-boot handover to Linux Kernel. It would > be great help. This is documented in kernel doc: https://www.kernel.org/doc/Documentation/x86/boot.txt > I thought that the MMC driver issue is on Linux Kernel side, but it > was some offset and probing issue in the u-boot. > Umm, it's hard to tell. Starting from BayTrail, Intel's SoC is more and more like an ARM SoC, with many GPIOs and pinmux that needs to be configured. Linux kernel does provide driver for the BayTrail pinctrl, but so far no mainline driver is making use of it. The generic x86 kernel image is not aware of any board-specific I/O configuration so some peripherals (like in this case the SD controller) won't work out of the box. The mainline Linux kernel expects the underlying bootloader to do the I/O configuration, IOW, kernerl is not bootloader agnostic yet on x86. It relies on whatever bootloader (UEFI BIOS, coreboot, U-Boot) to do such kind of work. Regards, Bin

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[U-Boot] [PATCH v6 00/10] armv8: ls2080aqds: Enable QSPI boot support
by Yuan Yao 11 Jun '16

11 Jun '16

From: Yuan Yao <yao.yuan(a)nxp.com> This patch adds QSPI boot support for LS2080AQDS board. The QSPI boot image need to be programmed into the QSPI flash first. Then we can switch to booting from QSPI memory space. Yuan Yao (10): drivers: i2c: mxc: Add early init armv8: ls2080aqds: Select QSPI CLK div via SCFG configs: ls2080a_common: Remove duplicate NOR configs armv8: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable configs: ls2080aqds: Enable QSPI flash support Changed in v6. dm: dts: ls2080aqds: Add QSPI dts node armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot configs: ls2080a: Increase load image len in NAND boot ls2080aqds_nand_defconfig: Enable QSPI & its dependence Changed in v6. armv8: ls2080aqds: Enable QSPI boot support Changed in v6. arch/arm/dts/fsl-ls2080a-qds.dts | 14 +++++++ arch/arm/dts/fsl-ls2080a.dtsi | 10 +++++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 ++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 3 ++ board/freescale/ls2080aqds/ls2080aqds.c | 19 ++++++++++ configs/ls2080aqds_nand_defconfig | 8 ++++ configs/ls2080aqds_qspi_defconfig | 27 ++++++++++++++ drivers/i2c/i2c_core.c | 5 +++ drivers/i2c/mxc_i2c.c | 27 ++++++++++++++ include/configs/ls2080a_common.h | 11 ++---- include/configs/ls2080a_simu.h | 7 ++++ include/configs/ls2080aqds.h | 43 +++++++++++++++++++++- include/i2c.h | 3 ++ 13 files changed, 171 insertions(+), 10 deletions(-) create mode 100644 configs/ls2080aqds_qspi_defconfig -- 2.1.0.27.g96db324

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[U-Boot] [PATCH ] board: ls2080a: Add "mcinitcmd" env for MC & DPL deployment
by Pratiyush Mohan Srivastava 11 Jun '16

11 Jun '16

From: Pratiyush Mohan Srivastava <pratiyush.srivastava(a)nxp.com> Environment variable mcinitcmd is defined to initiate MC and DPL deployment from the location where it is stored(NOR, NAND, SD, SATA, USB)during u-boot booting.If this variable is not defined then macro MC_BOOT_ENV_VAR will be null and MC will not be booted and DPL will not be applied during U-boot booting. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava(a)nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 | 29 ++++++++++++++++++++++++++ board/freescale/ls2080aqds/eth.c | 5 +++++ board/freescale/ls2080ardb/eth_ls2080rdb.c | 5 +++++ 3 files changed, 39 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 index f9323c1..da5e052 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 +++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 @@ -121,6 +121,35 @@ mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined mcmemsize: MC DRAM block size. If this variable is not defined, the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. +mcinitcmd: This environment variable is defined to initiate MC and DPL deployment + from the location where it is stored(NOR, NAND, SD, SATA, USB)during + u-boot booting.If this variable is not defined then MC_BOOT_ENV_VAR + will be null and MC will not be booted and DPL will not be applied + during U-boot booting.However the MC, DPC and DPL can be applied from + console independently. + The variable needs to be set from the console once and then on + rebooting the parameters set in the varible will automatically be + executed. The commmand is demostrated taking an example of mc boot + using NOR Flash i.e. MC, DPL, and DPC is stored in the NOR flash: + + cp.b 0xa0000000 0x580300000 $filesize + cp.b 0x80000000 0x580800000 $filesize + cp.b 0x90000000 0x580700000 $filesize + + setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000' + + If only linux is to be booted then the mcinitcmd environment should be set as + + setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000' + + Here the addresses 0xa0000000, 0x80000000, 0x80000000 are of DDR to where + MC binary, DPC binary and DPL binary are stored and 0x580300000, 0x580800000 + and 0x580700000 are addresses in NOR where these are copied. It is to be + noted that these addresses in 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000' + can be replaced with the addresses of DDR to + which these will be copied in case of these binaries being stored in other + devices like SATA, USB, NAND, SD etc. + Booting from NAND ------------------- Booting from NAND requires two images, RCW and u-boot-with-spl.bin. diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 5b9c2d1..db9de77 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -20,6 +20,7 @@ #include "ls2080aqds_qixis.h" +#define MC_BOOT_ENV_VAR "mcinitcmd" #ifdef CONFIG_FSL_MC_ENET /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks. @@ -714,6 +715,7 @@ void ls2080a_handle_phy_interface_xsgmii(int i) int board_eth_init(bd_t *bis) { int error; + char *mc_boot_env_var; #ifdef CONFIG_FSL_MC_ENET struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & @@ -781,6 +783,9 @@ int board_eth_init(bd_t *bis) } } + mc_boot_env_var = getenv(MC_BOOT_ENV_VAR); + if (mc_boot_env_var) + run_command_list(mc_boot_env_var, -1, 0); error = cpu_eth_init(bis); if (hwconfig_f("xqsgmii", env_hwconfig)) { diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c index 58ea746..758bb3d 100644 --- a/board/freescale/ls2080ardb/eth_ls2080rdb.c +++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c @@ -20,9 +20,11 @@ DECLARE_GLOBAL_DATA_PTR; +#define MC_BOOT_ENV_VAR "mcinitcmd" int board_eth_init(bd_t *bis) { #if defined(CONFIG_FSL_MC_ENET) + char *mc_boot_env_var; int i, interface; struct memac_mdio_info mdio_info; struct mii_dev *dev; @@ -89,6 +91,9 @@ int board_eth_init(bd_t *bis) } } + mc_boot_env_var = getenv(MC_BOOT_ENV_VAR); + if (mc_boot_env_var) + run_command_list(mc_boot_env_var, -1, 0); cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ -- 1.9.1

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[U-Boot] [PATCH v5] armv8/ls2080a: configure PMU's PCTBENR to enable WDT
by Yunhui Cui 11 Jun '16

11 Jun '16

From: Yunhui Cui <yunhui.cui(a)nxp.com> The SP805-WDT module on LS2080A and LS2085A, requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. In order not to affect the sp805wdt driver frame, we enable the watchdog clk in advance. Signed-off-by: Yunhui Cui <yunhui.cui(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 12 ++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + 2 files changed, 13 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d939900..79eb4dc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -639,6 +639,9 @@ int timer_init(void) #ifdef CONFIG_FSL_LSCH3 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; #endif +#ifdef CONFIG_LS2080A + u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET; +#endif #ifdef COUNTER_FREQUENCY_REAL unsigned long cntfrq = COUNTER_FREQUENCY_REAL; @@ -653,6 +656,15 @@ int timer_init(void) out_le32(cltbenr, 0xf); #endif +#ifdef CONFIG_LS2080A + /* + * In certain Layerscape SoCs, the clock for each core's + * has an enable bit in the PMU Physical Core Time Base Enable + * Register (PCTBENR), which allows the watchdog to operate. + */ + setbits_le32(pctbenr, 0xff); +#endif + /* Enable clock for timer * This is a global setting. */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 1d3b336..8121939 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -26,6 +26,7 @@ #define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000 #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 0x18A0) +#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0) #define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000) #define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000) -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v2] sunxi: Increase SPL header size to 64 bytes to avoid code corruption
by Siarhei Siamashka 10 Jun '16

10 Jun '16

The current SPL header, created by the 'mksunxiboot' tool, has size 32 bytes. But the code in the boot ROM stores the information about the boot media at the offset 0x28 before passing control to the SPL. For example, when booting from the SD card, the magic number written by the boot ROM is 0. And when booting from the SPI flash, the magic number is 3. NAND and eMMC probably have their own special magic numbers too. Currently the corrupted byte is a part of one of the instructions in the reset vectors table: b reset ldr pc, _undefined_instruction ldr pc, _software_interrupt <- Corruption happens here ldr pc, _prefetch_abort ldr pc, _data_abort ldr pc, _not_used ldr pc, _irq ldr pc, _fiq In practice this does not cause any visible problems, but it's still better to fix it. As a bonus, the reported boot media type can be later used in the 'spl_boot_device' function, but this is out of the scope of this patch. Signed-off-by: Siarhei Siamashka <siarhei.siamashka(a)gmail.com> --- Changes in v2: - Increase the header size to 64 bytes instead of 48 bytes in order to satisfy the VBAR alignment requirements. arch/arm/include/asm/arch-sunxi/spl.h | 8 +++++++- include/configs/sunxi-common.h | 12 ++++++------ 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h index ca9a4f9..a0f33b0 100644 --- a/arch/arm/include/asm/arch-sunxi/spl.h +++ b/arch/arm/include/asm/arch-sunxi/spl.h @@ -18,6 +18,10 @@ #define SPL_ADDR 0x0 #endif +/* The low 8-bits of the 'boot_media' field in the SPL header */ +#define SUNXI_BOOTED_FROM_MMC0 0 +#define SUNXI_BOOTED_FROM_SPI 3 + /* boot head definition from sun4i boot code */ struct boot_file_head { uint32_t b_instruction; /* one intruction jumping to real code */ @@ -45,7 +49,9 @@ struct boot_file_head { uint8_t spl_signature[4]; }; uint32_t fel_script_address; - uint32_t reserved; /* padding, align to 32 bytes */ + uint32_t reserved1[3]; + uint32_t boot_media; /* written here by the boot ROM */ + uint32_t reserved2[5]; /* padding, align to 64 bytes */ }; #define is_boot0_magic(addr) (memcmp((void *)addr, BOOT0_MAGIC, 8) == 0) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 2406115..e2ee908 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -189,14 +189,14 @@ #define CONFIG_SPL_BOARD_LOAD_IMAGE #if defined(CONFIG_MACH_SUN9I) -#define CONFIG_SPL_TEXT_BASE 0x10020 /* sram start+header */ -#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* ? KiB on sun9i */ +#define CONFIG_SPL_TEXT_BASE 0x10040 /* sram start+header */ +#define CONFIG_SPL_MAX_SIZE 0x5fc0 /* ? KiB on sun9i */ #elif defined(CONFIG_MACH_SUN50I) -#define CONFIG_SPL_TEXT_BASE 0x10020 /* sram start+header */ -#define CONFIG_SPL_MAX_SIZE 0x7fe0 /* 32 KiB on sun50i */ +#define CONFIG_SPL_TEXT_BASE 0x10040 /* sram start+header */ +#define CONFIG_SPL_MAX_SIZE 0x7fc0 /* 32 KiB on sun50i */ #else -#define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */ -#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */ +#define CONFIG_SPL_TEXT_BASE 0x40 /* sram start+header */ +#define CONFIG_SPL_MAX_SIZE 0x5fc0 /* 24KB on sun4i/sun7i */ #endif #define CONFIG_SPL_LIBDISK_SUPPORT -- 2.7.3

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[U-Boot] [PATCH v2] sunxi: Support booting from SPI flash
by Siarhei Siamashka 10 Jun '16

10 Jun '16

Allwinner devices support SPI flash as one of the possible bootable media type. The SPI flash chip needs to be connected to SPI0 pins (port C) to make this work. More information is available at: https://linux-sunxi.org/Bootable_SPI_flash This patch adds the initial support for booting from SPI flash. The existing SPI frameworks are not used in order to reduce the SPL code size. Right now the SPL size grows by ~370 bytes when CONFIG_SPL_SPI_SUNXI option is enabled. While there are no popular Allwinner devices with SPI flash at the moment, testing can be done using a SPI flash module (it can be bought for ~2$ on ebay) and jumper wires with the boards, which expose relevant pins on the expansion header. The SPI flash chips themselves are very cheap (some prices are even listed as low as 4 cents) and should not cost much if somebody decides to design a development board with an SPI flash chip soldered on the PCB. Another nice feature of the SPI flash is that it can be safely accessed in a device-independent way (since we know that the boot ROM is already probing these pins during the boot time). And if, for example, Olimex boards opted to use SPI flash instead of EEPROM, then they would have been able to have U-Boot installed in the SPI flash now and boot the rest of the system from the SATA hard drive. Hopefully we may see new interesting Allwinner based development boards in the future, now that the software support for the SPI flash is in a better shape :-) Testing can be done by enabling the CONFIG_SPL_SPI_SUNXI option in a board defconfig, then building U-Boot and finally flashing the resulting u-boot-sunxi-with-spl.bin binary over USB OTG with a help of the sunxi-fel tool: sunxi-fel spiflash-write 0 u-boot-sunxi-with-spl.bin The device needs to be switched into FEL (USB recovery) mode first. The most suitable boards for testing are Orange Pi PC and Pine64. Because these boards are cheap, have no built-in NAND/eMMC and expose SPI0 pins on the Raspberry Pi compatible expansion header. The A13-OLinuXino-Micro board also can be used. Signed-off-by: Siarhei Siamashka <siarhei.siamashka(a)gmail.com> --- Changes in v2: - Add Kconfig option (CONFIG_SPL_SPI_SUNXI) and move the SPI flash support code into a separate source file - Use CONFIG_SYS_SPI_U_BOOT_OFFS instead of the hardcoded constant - Deinitialize the SPI controller and undo pin muxing after the job is done - Size reduction of the SPI transfer function - Add delay after each SPI transfer to ensure that the chip select deassert timing requirements (tSHSL) are always satisfied - More comments in the code arch/arm/include/asm/arch-sunxi/gpio.h | 3 + arch/arm/mach-sunxi/board.c | 5 + common/spl/spl.c | 4 +- drivers/mtd/spi/Kconfig | 12 ++ drivers/mtd/spi/Makefile | 1 + drivers/mtd/spi/sunxi_spi_spl.c | 283 +++++++++++++++++++++++++++++++++ include/configs/sunxi-common.h | 5 + 7 files changed, 311 insertions(+), 2 deletions(-) create mode 100644 drivers/mtd/spi/sunxi_spi_spl.c diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 1ace548..bff7d14 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -141,6 +141,7 @@ enum sunxi_gpio_number { /* GPIO pin function config */ #define SUNXI_GPIO_INPUT 0 #define SUNXI_GPIO_OUTPUT 1 +#define SUNXI_GPIO_DISABLE 7 #define SUNXI_GPA_EMAC 2 #define SUN6I_GPA_GMAC 2 @@ -162,8 +163,10 @@ enum sunxi_gpio_number { #define SUN50I_GPB_UART0 4 #define SUNXI_GPC_NAND 2 +#define SUNXI_GPC_SPI0 3 #define SUNXI_GPC_SDC2 3 #define SUN6I_GPC_SDC3 4 +#define SUN50I_GPC_SPI0 4 #define SUN8I_GPD_SDC1 3 #define SUNXI_GPD_LCD0 2 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index bd15b9b..025df4d 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -223,6 +223,11 @@ u32 spl_boot_device(void) if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */ return BOOT_DEVICE_BOARD; +#ifdef CONFIG_SPL_SPI_SUNXI + if (readb(SPL_ADDR + 0x28) == SUNXI_BOOTED_FROM_SPI) + return BOOT_DEVICE_SPI; +#endif + /* The BROM will try to boot from mmc0 first, so try that first. */ #ifdef CONFIG_MMC mmc_initialize(gd->bd); diff --git a/common/spl/spl.c b/common/spl/spl.c index c8dfc14..d49ce2b 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -265,7 +265,7 @@ struct boot_device_name boot_name_table[] = { #ifdef CONFIG_SPL_YMODEM_SUPPORT { BOOT_DEVICE_UART, "UART" }, #endif -#ifdef CONFIG_SPL_SPI_SUPPORT +#if defined(CONFIG_SPL_SPI_SUPPORT) || defined(CONFIG_SPL_SPI_FLASH_SUPPORT) { BOOT_DEVICE_SPI, "SPI" }, #endif #ifdef CONFIG_SPL_ETH_SUPPORT @@ -341,7 +341,7 @@ static int spl_load_image(u32 boot_device) case BOOT_DEVICE_UART: return spl_ymodem_load_image(); #endif -#ifdef CONFIG_SPL_SPI_SUPPORT +#if defined(CONFIG_SPL_SPI_SUPPORT) || defined(CONFIG_SPL_SPI_FLASH_SUPPORT) case BOOT_DEVICE_SPI: return spl_spi_load_image(); #endif diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 3f7433c..1f23c8e 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -128,4 +128,16 @@ config SPI_FLASH_MTD If unsure, say N +if SPL + +config SPL_SPI_SUNXI + bool "Support for SPI Flash on Allwinner SoCs in SPL" + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_H3 || MACH_SUN50I + ---help--- + Enable support for SPI Flash. This option allows SPL to read from + sunxi SPI Flash. It uses the same method as the boot ROM, so does + not need any extra configuration. + +endif + endmenu # menu "SPI Flash Support" diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index c665836..6f47a66 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o +obj-$(CONFIG_SPL_SPI_SUNXI) += sunxi_spi_spl.o endif obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o sf_params.o sf.o diff --git a/drivers/mtd/spi/sunxi_spi_spl.c b/drivers/mtd/spi/sunxi_spi_spl.c new file mode 100644 index 0000000..e3ded5b --- /dev/null +++ b/drivers/mtd/spi/sunxi_spi_spl.c @@ -0,0 +1,283 @@ +/* + * Copyright (C) 2016 Siarhei Siamashka <siarhei.siamashka(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <asm/gpio.h> +#include <asm/io.h> + +#ifdef CONFIG_SPL_OS_BOOT +#error CONFIG_SPL_OS_BOOT is not supported yet +#endif + +/* + * This is a very simple U-Boot image loading implementation, trying to + * replicate what the boot ROM is doing when loading the SPL. Because we + * know the exact pins where the SPI Flash is connected and also know + * that the Read Data Bytes (03h) command is supported, the hardware + * configuration is very simple and we don't need the extra flexibility + * of the SPI framework. Moreover, we rely on the default settings of + * the SPI controler hardware registers and only adjust what needs to + * be changed. This is good for the code size and this implementation + * adds less than 400 bytes to the SPL. + * + * There are two variants of the SPI controller in Allwinner SoCs: + * A10/A13/A20 (sun4i variant) and everything else (sun6i variant). + * Both of them are supported. + * + * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are + * supported at the moment. + */ + +/*****************************************************************************/ +/* SUN4I variant of the SPI controller */ +/*****************************************************************************/ + +#define SUN4I_SPI0_CCTL (0x01C05000 + 0x1C) +#define SUN4I_SPI0_CTL (0x01C05000 + 0x08) +#define SUN4I_SPI0_RX (0x01C05000 + 0x00) +#define SUN4I_SPI0_TX (0x01C05000 + 0x04) +#define SUN4I_SPI0_FIFO_STA (0x01C05000 + 0x28) +#define SUN4I_SPI0_BC (0x01C05000 + 0x20) +#define SUN4I_SPI0_TC (0x01C05000 + 0x24) + +#define SUN4I_CTL_ENABLE BIT(0) +#define SUN4I_CTL_MASTER BIT(1) +#define SUN4I_CTL_TF_RST BIT(8) +#define SUN4I_CTL_RF_RST BIT(9) +#define SUN4I_CTL_XCH BIT(10) + +/*****************************************************************************/ +/* SUN6I variant of the SPI controller */ +/*****************************************************************************/ + +#define SUN6I_SPI0_CCTL (0x01C68000 + 0x24) +#define SUN6I_SPI0_GCR (0x01C68000 + 0x04) +#define SUN6I_SPI0_TCR (0x01C68000 + 0x08) +#define SUN6I_SPI0_FIFO_STA (0x01C68000 + 0x1C) +#define SUN6I_SPI0_MBC (0x01C68000 + 0x30) +#define SUN6I_SPI0_MTC (0x01C68000 + 0x34) +#define SUN6I_SPI0_BCC (0x01C68000 + 0x38) +#define SUN6I_SPI0_TXD (0x01C68000 + 0x200) +#define SUN6I_SPI0_RXD (0x01C68000 + 0x300) + +#define SUN6I_CTL_ENABLE BIT(0) +#define SUN6I_CTL_MASTER BIT(1) +#define SUN6I_CTL_SRST BIT(31) +#define SUN6I_TCR_XCH BIT(31) + +/*****************************************************************************/ + +#define CCM_AHB_GATING0 (0x01C20000 + 0x60) +#define CCM_SPI0_CLK (0x01C20000 + 0xA0) +#define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0) + +#define AHB_RESET_SPI0_SHIFT 20 +#define AHB_GATE_OFFSET_SPI0 20 + +#define SPI0_CLK_DIV_BY_2 0x1000 +#define SPI0_CLK_DIV_BY_4 0x1001 + +/*****************************************************************************/ + +/* + * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting + * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3. + */ +static void spi0_pinmux_setup(unsigned int pin_function) +{ + unsigned int pin; + + for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++) + sunxi_gpio_set_cfgpin(pin, pin_function); + + if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I)) + sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function); + else + sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); +} + +/* + * Setup 6 MHz from OSC24M (because the BROM is doing the same). + */ +static void spi0_enable_clock(void) +{ + /* Deassert SPI0 reset on SUN6I */ + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + setbits_le32(SUN6I_BUS_SOFT_RST_REG0, + (1 << AHB_RESET_SPI0_SHIFT)); + + /* Open the SPI0 gate */ + setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); + + /* Divide by 4 */ + writel(SPI0_CLK_DIV_BY_4, IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ? + SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL); + /* 24MHz from OSC24M */ + writel((1 << 31), CCM_SPI0_CLK); + + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { + /* Enable SPI in the master mode and do a soft reset */ + setbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | + SUN6I_CTL_ENABLE | + SUN6I_CTL_SRST); + /* Wait for completion */ + while (readl(SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) + ; + } else { + /* Enable SPI in the master mode and reset FIFO */ + setbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | + SUN4I_CTL_ENABLE | + SUN4I_CTL_TF_RST | + SUN4I_CTL_RF_RST); + } +} + +static void spi0_disable_clock(void) +{ + /* Disable the SPI0 controller */ + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + clrbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | + SUN6I_CTL_ENABLE); + else + clrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | + SUN4I_CTL_ENABLE); + + /* Disable the SPI0 clock */ + writel(0, CCM_SPI0_CLK); + + /* Close the SPI0 gate */ + clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); + + /* Assert SPI0 reset on SUN6I */ + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + clrbits_le32(SUN6I_BUS_SOFT_RST_REG0, + (1 << AHB_RESET_SPI0_SHIFT)); +} + +static int spi0_init(void) +{ + unsigned int pin_function = SUNXI_GPC_SPI0; + if (IS_ENABLED(CONFIG_MACH_SUN50I)) + pin_function = SUN50I_GPC_SPI0; + + spi0_pinmux_setup(pin_function); + spi0_enable_clock(); +} + +static void spi0_deinit(void) +{ + /* New SoCs can disable pins, older could only set them as input */ + unsigned int pin_function = SUNXI_GPIO_INPUT; + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + pin_function = SUNXI_GPIO_DISABLE; + + spi0_disable_clock(); + spi0_pinmux_setup(pin_function); +} + +/*****************************************************************************/ + +#define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */ + +static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize, + u32 spi_ctl_reg, + u32 spi_ctl_xch_bitmask, + u32 spi_fifo_reg, + u32 spi_tx_reg, + u32 spi_rx_reg, + u32 spi_bc_reg, + u32 spi_tc_reg, + u32 spi_bcc_reg) +{ + writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */ + writel(4, spi_tc_reg); /* Transfer counter (bytes to send) */ + if (spi_bcc_reg) + writel(4, spi_bcc_reg); /* SUN6I also needs this */ + + /* Send the Read Data Bytes (03h) command header */ + writeb(0x03, spi_tx_reg); + writeb((u8)(addr >> 16), spi_tx_reg); + writeb((u8)(addr >> 8), spi_tx_reg); + writeb((u8)(addr), spi_tx_reg); + + /* Start the data transfer */ + setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask); + + /* Wait until everything is received in the RX FIFO */ + while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize) + ; + + /* Skip 4 bytes */ + readl(spi_rx_reg); + + /* Read the data */ + while (bufsize-- > 0) + *buf++ = readb(spi_rx_reg); + + /* tSHSL time is up to 100 ns in various SPI flash datasheets */ + udelay(1); +} + +static void spi0_read_data(void *buf, u32 addr, u32 len) +{ + u8 *buf8 = buf; + u32 chunk_len; + + while (len > 0) { + chunk_len = len; + if (chunk_len > SPI_READ_MAX_SIZE) + chunk_len = SPI_READ_MAX_SIZE; + + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { + sunxi_spi0_read_data(buf8, addr, chunk_len, + SUN6I_SPI0_TCR, + SUN6I_TCR_XCH, + SUN6I_SPI0_FIFO_STA, + SUN6I_SPI0_TXD, + SUN6I_SPI0_RXD, + SUN6I_SPI0_MBC, + SUN6I_SPI0_MTC, + SUN6I_SPI0_BCC); + } else { + sunxi_spi0_read_data(buf8, addr, chunk_len, + SUN4I_SPI0_CTL, + SUN4I_CTL_XCH, + SUN4I_SPI0_FIFO_STA, + SUN4I_SPI0_TX, + SUN4I_SPI0_RX, + SUN4I_SPI0_BC, + SUN4I_SPI0_TC, + 0); + } + + len -= chunk_len; + buf8 += chunk_len; + addr += chunk_len; + } +} + +/*****************************************************************************/ + +int spl_spi_load_image(void) +{ + int err; + struct image_header *header; + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE); + + spi0_init(); + + spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40); + err = spl_parse_image_header(header); + if (err) + return err; + + spi0_read_data((void *)spl_image.load_addr, CONFIG_SYS_SPI_U_BOOT_OFFS, + spl_image.size); + + spi0_deinit(); + return 0; +} diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index b33cfb8..7d244d9 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -137,6 +137,11 @@ #define CONFIG_SPL_NAND_SUPPORT 1 #endif +#ifdef CONFIG_SPL_SPI_SUNXI +#define CONFIG_SPL_SPI_FLASH_SUPPORT 1 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 +#endif + /* mmc config */ #ifdef CONFIG_MMC #define CONFIG_GENERIC_MMC -- 2.7.3

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[U-Boot] [PATCH 0/2] sunxi: Fix SRAM C corruption issue on Allwinner A64
by Siarhei Siamashka 10 Jun '16

10 Jun '16

The full SPL support is not quite ready for Allwinner A64 yet, but these fixes are likely to be necessary. Of course, unless the problem is actually caused by wrong voltages and the AXP803 PMIC support magically fixes it. PS. Discovered when developing a sunxi-fel based SPI flash programmer tool and trying to use the SRAM C on A64 as a temporary buffer (after loading the U-Boot SPL with the hope to gain more speed from the higher CPU and AHB clock speeds). Siarhei Siamashka (2): sunxi: Downclock AHB1 to 100MHz on Allwinner A64 sunxi: Move the SPL stack top to 0x1A000 on Allwinner A64/A80 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 +++++ include/configs/sunxi-common.h | 5 ++--- 2 files changed, 7 insertions(+), 3 deletions(-) -- 2.7.3

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[U-Boot] [PATCH 0/2] Prepare U-Boot for more Amlogic boards
by Carlo Caione 10 Jun '16

10 Jun '16

From: Carlo Caione <carlo(a)endlessm.com> Refactor the Odroid-C2 support code to prepare U-Boot for more Amlogic board submissions. The goal is to reduce the redundancy of the configuration files and unify all the board support files onto a single amlogic directory. Carlo Caione (2): configs: gxbb: Introduce a common config header file board: amlogic: Rename folder for Amlogic boards arch/arm/mach-meson/Kconfig | 2 +- board/amlogic/odroid-c2/Kconfig | 12 ++++++ board/amlogic/odroid-c2/MAINTAINERS | 6 +++ board/amlogic/odroid-c2/Makefile | 7 ++++ board/amlogic/odroid-c2/README | 60 ++++++++++++++++++++++++++++++ board/amlogic/odroid-c2/odroid-c2.c | 67 ++++++++++++++++++++++++++++++++++ board/hardkernel/odroid-c2/Kconfig | 12 ------ board/hardkernel/odroid-c2/MAINTAINERS | 6 --- board/hardkernel/odroid-c2/Makefile | 7 ---- board/hardkernel/odroid-c2/README | 60 ------------------------------ board/hardkernel/odroid-c2/odroid-c2.c | 67 ---------------------------------- include/configs/meson-gxbb-common.h | 45 +++++++++++++++++++++++ include/configs/odroid-c2.h | 34 +---------------- 13 files changed, 199 insertions(+), 186 deletions(-) create mode 100644 board/amlogic/odroid-c2/Kconfig create mode 100644 board/amlogic/odroid-c2/MAINTAINERS create mode 100644 board/amlogic/odroid-c2/Makefile create mode 100644 board/amlogic/odroid-c2/README create mode 100644 board/amlogic/odroid-c2/odroid-c2.c delete mode 100644 board/hardkernel/odroid-c2/Kconfig delete mode 100644 board/hardkernel/odroid-c2/MAINTAINERS delete mode 100644 board/hardkernel/odroid-c2/Makefile delete mode 100644 board/hardkernel/odroid-c2/README delete mode 100644 board/hardkernel/odroid-c2/odroid-c2.c create mode 100644 include/configs/meson-gxbb-common.h -- 2.7.4

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[U-Boot] [PATCH] ARM: AM437x: Enable FIT for hs platforms
by Srinivas, Madan 10 Jun '16

10 Jun '16

Adding FIT support to the SPL and u-boot for AM437x HS devices. Signed-off-by: Madan Srinivas <madans(a)ti.com> --- configs/am437x_hs_evm_defconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/configs/am437x_hs_evm_defconfig b/configs/am437x_hs_evm_defconfig index 3cd39eb..fac06a7 100644 --- a/configs/am437x_hs_evm_defconfig +++ b/configs/am437x_hs_evm_defconfig @@ -10,7 +10,9 @@ CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm" CONFIG_SPL=y CONFIG_ISW_ENTRY_ADDR=0x40302ae0 CONFIG_SPL_STACK_R=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1" +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,NAND" +CONFIG_SPL_LOAD_FIT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set @@ -33,6 +35,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y +CONFIG_OF_LIST="am437x-gp-evm" CONFIG_DM=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y @@ -53,3 +56,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Texas Instruments" CONFIG_G_DNL_VENDOR_NUM=0x0403 CONFIG_G_DNL_PRODUCT_NUM=0xbd00 +CONFIG_SPL_OF_LIBFDT=y -- 1.9.1

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