June 2016 - U-Boot

[U-Boot] [PATCH v2] verified-boot: Minimal support for booting U-Boot proper from SPL
by Teddy Reed 19 Jun '16

19 Jun '16

This allows a board to configure verified boot within the SPL using a FIT or FIT with external data. It also allows the SPL to perform signature verification without needing relocation. The board configuration will need to add the following feature defines: CONFIG_SPL_CRYPTO_SUPPORT CONFIG_SPL_HASH_SUPPORT CONFIG_SPL_SHA256 In this example, SHA256 is the only selected hashing algorithm. And the following booleans: CONFIG_SPL=y CONFIG_SPL_DM=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_OF_LIBFDT=y CONFIG_SPL_FIT_SIGNATURE=y Signed-off-by: Teddy Reed <teddy.reed(a)gmail.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: - Rebase to master Kconfig | 11 +++++++++++ common/Makefile | 1 + drivers/Makefile | 1 + drivers/crypto/rsa_mod_exp/mod_exp_sw.c | 1 + lib/Makefile | 9 ++++----- lib/rsa/Kconfig | 4 ++++ lib/rsa/Makefile | 2 +- 7 files changed, 23 insertions(+), 6 deletions(-) diff --git a/Kconfig b/Kconfig index 4b46216..817f4f0 100644 --- a/Kconfig +++ b/Kconfig @@ -183,6 +183,11 @@ config FIT verified boot (secure boot using RSA). This option enables that feature. +config SPL_FIT + bool "Support Flattened Image Tree within SPL" + depends on FIT + depends on SPL + config FIT_VERBOSE bool "Display verbose messages on FIT boot" depends on FIT @@ -205,6 +210,12 @@ config FIT_SIGNATURE format support in this case, enable it using CONFIG_IMAGE_FORMAT_LEGACY. +config SPL_FIT_SIGNATURE + bool "Enable signature verification of FIT firmware within SPL" + depends on SPL_FIT + depends on SPL_DM + select SPL_RSA + config FIT_BEST_MATCH bool "Select the best match for the kernel device tree" depends on FIT diff --git a/common/Makefile b/common/Makefile index 1557a04..97c59fe 100644 --- a/common/Makefile +++ b/common/Makefile @@ -93,6 +93,7 @@ obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o endif # !CONFIG_SPL_BUILD ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SPL_HASH_SUPPORT) += hash.o obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o obj-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o diff --git a/drivers/Makefile b/drivers/Makefile index f6295d2..db5317c 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_$(SPL_)RAM) += ram/ ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/ obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/ obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/ obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc/ diff --git a/drivers/crypto/rsa_mod_exp/mod_exp_sw.c b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c index dc6c064..3817fb3 100644 --- a/drivers/crypto/rsa_mod_exp/mod_exp_sw.c +++ b/drivers/crypto/rsa_mod_exp/mod_exp_sw.c @@ -32,6 +32,7 @@ U_BOOT_DRIVER(mod_exp_sw) = { .name = "mod_exp_sw", .id = UCLASS_MOD_EXP, .ops = &mod_exp_ops_sw, + .flags = DM_FLAG_PRE_RELOC, }; U_BOOT_DEVICE(mod_exp_sw) = { diff --git a/lib/Makefile b/lib/Makefile index f77befe..f48d901 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -9,7 +9,6 @@ ifndef CONFIG_SPL_BUILD obj-$(CONFIG_EFI) += efi/ obj-$(CONFIG_EFI_LOADER) += efi_loader/ -obj-$(CONFIG_RSA) += rsa/ obj-$(CONFIG_LZMA) += lzma/ obj-$(CONFIG_LZO) += lzo/ obj-$(CONFIG_ZLIB) += zlib/ @@ -25,8 +24,6 @@ obj-y += crc8.o obj-y += crc16.o obj-$(CONFIG_ERRNO_STR) += errno_str.o obj-$(CONFIG_FIT) += fdtdec_common.o -obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec_common.o -obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec.o obj-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o obj-$(CONFIG_GZIP) += gunzip.o obj-$(CONFIG_GZIP_COMPRESSED) += gzip.o @@ -39,15 +36,17 @@ obj-y += net_utils.o obj-$(CONFIG_PHYSMEM) += physmem.o obj-y += qsort.o obj-y += rc4.o -obj-$(CONFIG_SHA1) += sha1.o obj-$(CONFIG_SUPPORT_EMMC_RPMB) += sha256.o -obj-$(CONFIG_SHA256) += sha256.o obj-$(CONFIG_TPM) += tpm.o obj-$(CONFIG_RBTREE) += rbtree.o obj-$(CONFIG_BITREVERSE) += bitrev.o obj-y += list_sort.o endif +obj-$(CONFIG_$(SPL_)RSA) += rsa/ +obj-$(CONFIG_$(SPL_)SHA1) += sha1.o +obj-$(CONFIG_$(SPL_)SHA256) += sha256.o + obj-$(CONFIG_$(SPL_)OF_LIBFDT) += libfdt/ ifdef CONFIG_SPL_OF_CONTROL obj-$(CONFIG_OF_LIBFDT) += libfdt/ diff --git a/lib/rsa/Kconfig b/lib/rsa/Kconfig index 86df0a0..09ec358 100644 --- a/lib/rsa/Kconfig +++ b/lib/rsa/Kconfig @@ -13,6 +13,10 @@ config RSA option. The software based modular exponentiation is built into mkimage irrespective of this option. +config SPL_RSA + bool "Use RSA Library within SPL" + depends on RSA + if RSA config RSA_SOFTWARE_EXP bool "Enable driver for RSA Modular Exponentiation in software" diff --git a/lib/rsa/Makefile b/lib/rsa/Makefile index 6867e50..4b2c1ba 100644 --- a/lib/rsa/Makefile +++ b/lib/rsa/Makefile @@ -7,5 +7,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_FIT_SIGNATURE) += rsa-verify.o rsa-checksum.o +obj-$(CONFIG_$(SPL_)FIT_SIGNATURE) += rsa-verify.o rsa-checksum.o obj-$(CONFIG_RSA_SOFTWARE_EXP) += rsa-mod-exp.o -- 2.7.4

4 3

[U-Boot] [PATCH] ti_armv7_common: env: Remove no longer needed mem_reserve
by Andrew F. Davis 19 Jun '16

19 Jun '16

The kernel can now use DT to reserve memory carveouts and these areas are now the default for drivers that need reserved memory, so reserving more here is unneeded and any memory reserved this way will be wasted. Signed-off-by: Andrew F. Davis <afd(a)ti.com> --- include/configs/ti_armv7_keystone2.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 2c9028c..d7baf33 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -247,7 +247,6 @@ "tftp_root=/\0" \ "nfs_root=/export\0" \ "mem_lpae=1\0" \ - "mem_reserve=512M\0" \ "addr_ubi=0x82000000\0" \ "addr_secdb_key=0xc000000\0" \ "name_kern=zImage\0" \ -- 2.8.3

3 2

[U-Boot] [PATCH] arm: dra7xx: Assign omap_vcores based on board type
by Keerthy 19 Jun '16

19 Jun '16

Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm(a)ti.com> Signed-off-by: Keerthy <j-keerthy(a)ti.com> --- Boot tested on both dra7-evm and dra72-evm. arch/arm/cpu/armv7/omap5/hw_data.c | 78 -------------------------------- board/ti/dra7xx/evm.c | 91 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+), 78 deletions(-) diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index a517b13..65f43d6 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -364,82 +364,6 @@ struct vcores_data omap5430_volts_es2 = { .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK, }; -struct vcores_data dra752_volts = { - .mpu.value = VDD_MPU_DRA7, - .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, - .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .mpu.addr = TPS659038_REG_ADDR_SMPS12, - .mpu.pmic = &tps659038, - .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, - - .eve.value = VDD_EVE_DRA7, - .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, - .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .eve.addr = TPS659038_REG_ADDR_SMPS45, - .eve.pmic = &tps659038, - .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, - - .gpu.value = VDD_GPU_DRA7, - .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, - .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .gpu.addr = TPS659038_REG_ADDR_SMPS6, - .gpu.pmic = &tps659038, - .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, - - .core.value = VDD_CORE_DRA7, - .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, - .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .core.addr = TPS659038_REG_ADDR_SMPS7, - .core.pmic = &tps659038, - - .iva.value = VDD_IVA_DRA7, - .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, - .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .iva.addr = TPS659038_REG_ADDR_SMPS8, - .iva.pmic = &tps659038, - .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, -}; - -struct vcores_data dra722_volts = { - .mpu.value = VDD_MPU_DRA7, - .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, - .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .mpu.addr = TPS65917_REG_ADDR_SMPS1, - .mpu.pmic = &tps659038, - .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, - - .core.value = VDD_CORE_DRA7, - .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, - .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .core.addr = TPS65917_REG_ADDR_SMPS2, - .core.pmic = &tps659038, - - /* - * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x - * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM. - */ - .gpu.value = VDD_GPU_DRA7, - .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, - .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .gpu.addr = TPS65917_REG_ADDR_SMPS3, - .gpu.pmic = &tps659038, - .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, - - .eve.value = VDD_EVE_DRA7, - .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, - .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .eve.addr = TPS65917_REG_ADDR_SMPS3, - .eve.pmic = &tps659038, - .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, - - .iva.value = VDD_IVA_DRA7, - .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, - .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .iva.addr = TPS65917_REG_ADDR_SMPS3, - .iva.pmic = &tps659038, - .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, -}; - /* * Enable essential clock domains, modules and * do some additional special settings needed @@ -804,7 +728,6 @@ void __weak hw_data_init(void) case DRA752_ES2_0: *prcm = &dra7xx_prcm; *dplls_data = &dra7xx_dplls; - *omap_vcores = &dra752_volts; *ctrl = &dra7xx_ctrl; break; @@ -812,7 +735,6 @@ void __weak hw_data_init(void) case DRA722_ES2_0: *prcm = &dra7xx_prcm; *dplls_data = &dra72x_dplls; - *omap_vcores = &dra722_volts; *ctrl = &dra7xx_ctrl; break; diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 8c916a3..c5f7190 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -310,6 +310,82 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) } } +struct vcores_data dra752_volts = { + .mpu.value = VDD_MPU_DRA7, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = TPS659038_REG_ADDR_SMPS12, + .mpu.pmic = &tps659038, + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, + + .eve.value = VDD_EVE_DRA7, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = TPS659038_REG_ADDR_SMPS45, + .eve.pmic = &tps659038, + .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, + + .gpu.value = VDD_GPU_DRA7, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = TPS659038_REG_ADDR_SMPS6, + .gpu.pmic = &tps659038, + .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, + + .core.value = VDD_CORE_DRA7, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = TPS659038_REG_ADDR_SMPS7, + .core.pmic = &tps659038, + + .iva.value = VDD_IVA_DRA7, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = TPS659038_REG_ADDR_SMPS8, + .iva.pmic = &tps659038, + .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, +}; + +struct vcores_data dra722_volts = { + .mpu.value = VDD_MPU_DRA7, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = TPS65917_REG_ADDR_SMPS1, + .mpu.pmic = &tps659038, + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, + + .core.value = VDD_CORE_DRA7, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = TPS65917_REG_ADDR_SMPS2, + .core.pmic = &tps659038, + + /* + * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x + * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM. + */ + .gpu.value = VDD_GPU_DRA7, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = TPS65917_REG_ADDR_SMPS3, + .gpu.pmic = &tps659038, + .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, + + .eve.value = VDD_EVE_DRA7, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = TPS65917_REG_ADDR_SMPS3, + .eve.pmic = &tps659038, + .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, + + .iva.value = VDD_IVA_DRA7, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = TPS65917_REG_ADDR_SMPS3, + .iva.pmic = &tps659038, + .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, +}; + /** * @brief board_init * @@ -405,6 +481,21 @@ void do_board_detect(void) } #endif /* CONFIG_SPL_BUILD */ +void vcores_init(void) +{ + if (board_is_dra74x_evm()) { + *omap_vcores = &dra752_volts; + } else if (board_is_dra72x_evm()) { + *omap_vcores = &dra722_volts; + } else { + /* If EEPROM is not populated */ + if (is_dra72x()) + *omap_vcores = &dra722_volts; + else + *omap_vcores = &dra752_volts; + } +} + void set_muxconf_regs(void) { do_set_mux32((*ctrl)->control_padconf_core_base, -- 1.9.1

3 2

[U-Boot] Please pull u-boot-sunxi master
by Hans de Goede 19 Jun '16

19 Jun '16

Hi Tom, Here is the second sunxi pull-req for v2016.07, it contains a few improvements and fixes, nothing special. The following changes since commit 6b3943f1b04be60f147ee540fbd72c4c7ea89f80: siemens,am33x: add draco etamin board (2016-06-09 13:53:13 -0400) are available in the git repository at: http://git.denx.de/u-boot-sunxi.git master for you to fetch changes up to 1a83fb4a17d959d7b037999ab7ed7e62429abe34: sunxi: Move the SPL stack top to 0x1A000 on Allwinner A64/A80 (2016-06-10 13:04:06 +0200) ---------------------------------------------------------------- Hans de Goede (3): sunxi: Enable ALDO3 and ALDO4 in Wobo_i5_defconfig sunxi: Add INITIAL_USB_SCAN_DELAY to Mele_A1000G_quad_defconfig sunxi: musb: Properly turn of musb controller before booting Siarhei Siamashka (2): sunxi: Downclock AHB1 to 100MHz on Allwinner A64 sunxi: Move the SPL stack top to 0x1A000 on Allwinner A64/A80 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 +++++ configs/Mele_A1000G_quad_defconfig | 1 + configs/Wobo_i5_defconfig | 2 ++ drivers/usb/musb-new/sunxi.c | 7 +++++++ include/configs/sunxi-common.h | 5 ++--- 5 files changed, 17 insertions(+), 3 deletions(-) Regards, Hans

2 1

[U-Boot] Please pull u-boot-x86
by Bin Meng 19 Jun '16

19 Jun '16

Hi Tom, This includes a fix to acpi madt table, and fixes to card detect pin configuration of the SD controller on BayTrail SoC. The following changes since commit 6b3943f1b04be60f147ee540fbd72c4c7ea89f80: siemens,am33x: add draco etamin board (2016-06-09 13:53:13 -0400) are available in the git repository at: git://git.denx.de/u-boot-x86.git master for you to fetch changes up to 9769e05bcf79939bad23a719982dd1f85a110f3c: x86: broadwell: gpio: Remove the codes to set up pin control (2016-06-12 12:19:35 +0800) ---------------------------------------------------------------- Bin Meng (8): x86: ich6_gpio: Output return value of syscon_get_by_driver_data() x86: baytrail: Add 'reg' property in the pinctrl node x86: baytrail: Change fsp, emmc-boot-mode to "auto" x86: baytrail: Configure card detect pin of the SD controller x86: Update x86-pinctrl driver device-tree-bindings doc x86: Enable regmap and syscon for coreboot and qemu-x86 x86: Probe pinctrl driver in cpu_init_r() x86: broadwell: gpio: Remove the codes to set up pin control George McCollister (1): x86: acpi: Fix madt lapic generation arch/x86/cpu/cpu.c | 5 +++++ arch/x86/dts/bayleybay.dts | 22 +++++++++++++++++++++- arch/x86/dts/conga-qeval20-qa3-e3845.dts | 18 +++++++++++++++++- arch/x86/dts/minnowmax.dts | 18 +++++++++++++++++- arch/x86/lib/acpi_table.c | 12 ++++++------ configs/coreboot-x86_defconfig | 2 ++ configs/qemu-x86_defconfig | 2 ++ doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt | 16 ++++++++-------- drivers/gpio/intel_broadwell_gpio.c | 7 ------- drivers/gpio/intel_ich6_gpio.c | 5 ----- 10 files changed, 78 insertions(+), 29 deletions(-) Regards, Bin

2 1

[U-Boot] Please pull u-boot-fsl-qoriq master
by York Sun 19 Jun '16

19 Jun '16

Tom, The following changes since commit 6b3943f1b04be60f147ee540fbd72c4c7ea89f80: siemens,am33x: add draco etamin board (2016-06-09 13:53:13 -0400) are available in the git repository at: git://git.denx.de/u-boot-fsl-qoriq.git master for you to fetch changes up to a646f6698173ef4ff34c414f91541b4b8f014de1: armv8: ls2080aqds: Enable QSPI boot support (2016-06-10 13:45:01 -0700) ---------------------------------------------------------------- Pratiyush Mohan Srivastava (1): board: ls2080a: Add "mcinitcmd" env for MC & DPL deployment Yuan Yao (10): drivers: i2c: mxc: Add early init armv8: ls2080aqds: Select QSPI CLK div via SCFG configs: ls2080a_common: Remove duplicate NOR configs armv8: ls2080aqds: disable IFC NOR & QIXIS when QSPI enable configs: ls2080aqds: Enable QSPI flash support dts: ls2080aqds: Add QSPI dts node armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND boot configs: ls2080a: Increase load image len in NAND boot configs: ls2080aqds_nand_defconfig: Enable QSPI armv8: ls2080aqds: Enable QSPI boot support Yunhui Cui (1): armv8/ls2080a: configure PMU's PCTBENR to enable WDT arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 12 ++++++ arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 | 29 +++++++++++++ arch/arm/dts/fsl-ls2080a-qds.dts | 14 +++++++ arch/arm/dts/fsl-ls2080a.dtsi | 10 +++++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 ++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++ board/freescale/ls2080aqds/eth.c | 5 +++ board/freescale/ls2080aqds/ls2080aqds.c | 19 +++++++++ board/freescale/ls2080ardb/eth_ls2080rdb.c | 5 +++ configs/ls2080aqds_nand_defconfig | 9 ++++ configs/ls2080aqds_qspi_defconfig | 37 +++++++++++++++++ drivers/i2c/i2c_core.c | 5 +++ drivers/i2c/mxc_i2c.c | 27 ++++++++++++ include/configs/ls2080a_common.h | 11 ++--- include/configs/ls2080a_simu.h | 7 ++++ include/configs/ls2080aqds.h | 43 +++++++++++++++++++- include/i2c.h | 3 ++ 17 files changed, 234 insertions(+), 10 deletions(-) create mode 100644 configs/ls2080aqds_qspi_defconfig Thanks. York

2 1

[U-Boot] [PULL] Please pull u-boot-imx
by Stefano Babic 19 Jun '16

19 Jun '16

Hi Tom, please pull from u-boot-imx, thanks ! The following changes since commit d7d000311285e4b8d11e089ca13ea456a01be3b8: Merge branch 'master' of git://git.denx.de/u-boot-mips (2016-05-23 11:51:37 -0400) are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master for you to fetch changes up to d2ba7a6adcef6e6f8c4418c7b0caf9d7ab98a6d4: arm: mxs: Remove misleading comments (2016-06-07 18:23:51 +0200) ---------------------------------------------------------------- Andrew Shadura (6): board: ge: bx50v3: don't configure the backlight when there's no display board: ge: bx50v3: make CONFIG_VIDEO optional and disabled by default board: ge: bx50v3: make USB support optional and disabled by default board: ge: bx50v3: make network support optional and disabled by default board: ge: bx50v3: make SATA optional and disabled by default board: ge: bx50v3: disable unused features to improve size and boot speed Damien Riegel (1): ts4800: update environment to boot with device tree Kimmo Surakka (1): board: ge: bx50v3: add missing partnum variable Michael Heimpold (1): arm: mxs: Remove misleading comments Peng Fan (18): imx: correct speed grading info for i.MX6UL imx-common: introduce simpler macros for runtime dection imx: mx6: support i.MX6SOLO when enable/disable_ldb_di_clock_sources imx: mx6: use simpler runtime cpu dection macros imx-common: hab: support i.MX6SOLO imx-common: use simpler runtime cpu dection macros imx: mx6: ddr: support i.MX6D/QPlus imx: mx6: correct get_cpu_speed_grade_hz for i.MX6DQP imx-common: hab: support i.MX6DQPlus imx-common: sata: return failure if not i.MX6DQPlus imx-common: timer: support i.MX6DQPlus mtd: nand: mxs: use simpler runtime cpu dection macros ocotp: mxc: use simpler runtime cpu dection macros net: fec_mxc: use simpler runtime cpu dection macros block: dwc_ahsata: support i.MX6DQPlus board: mx6sabresd/auto: use simpler runtime cpu dection macros imx: mx6qsabreauto: drop duplicated net phy configuration imx: mx7: implement reset_misc Sebastien Bourdelin (2): ts4800: add CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 cosmetic: mx6slevk: Minor coding-style fix Stefano Babic (1): Merge branch 'master' of git://git.denx.de/u-boot Tim Harvey (22): imx: ventana: config: remove redundant config imx: ventana: gsc: remove dependence on env imx: ventana: use EEPROM register for falcon boot mode imx: ventana: remove SPL_EXT_SUPPORT imx: ventana: config: add env vars for disk and part imx: ventana: config: add fixfdt script to apply manual fdt fixups imx: ventana: config: use bootdir env var for directory of fdt files imx: ventana: config: use fs env var for block dev filesystem type imx: ventana: config: use explicit addr in loadscript imx: ventana: config: add PREBOOT support imx: ventana: SPL: only disable boot watchdog if Falcon mode imx: ventana: SPL: added support for 32bit IMX6DQ 8Gb density DRAM config imx: ventana: gsc: add gsc sleep command imx: ventana: gsc: fix negative temperature readings imx: ventana: gsc: show board temp on boot imx: ventana: export backlight gpio after gpio driver is available imx: ventana: fix invalid dio configuration for pwm mode imx: ventana: enable pwm device-tree property based on hwconfig imx: ventana: remove dependence on EECONFIG_SATA eeprom feature bit imx: ventana: remove several EEPROM config bit dependence imx: ventana: add GW553x support imx: ventana: add fdt fixup to enable UHS-I support on selected boards arch/arm/cpu/arm926ejs/mxs/mxs.c | 4 ++-- arch/arm/cpu/armv7/mx6/clock.c | 42 ++++++++++++++++------------------ arch/arm/cpu/armv7/mx6/ddr.c | 10 ++++---- arch/arm/cpu/armv7/mx6/soc.c | 26 ++++++++++++++++----- arch/arm/cpu/armv7/mx7/soc.c | 8 +++++++ arch/arm/imx-common/hab.c | 53 +++++++++++++++++++----------------------- arch/arm/imx-common/init.c | 5 ++-- arch/arm/imx-common/iomux-v3.c | 2 +- arch/arm/imx-common/sata.c | 2 +- arch/arm/imx-common/timer.c | 11 +++------ arch/arm/include/asm/imx-common/sys_proto.h | 8 +++++++ board/freescale/mx6qsabreauto/mx6qsabreauto.c | 37 ++---------------------------- board/freescale/mx6sabresd/mx6sabresd.c | 4 ++-- board/freescale/mx6slevk/mx6slevk.c | 16 ++++++------- board/gateworks/gw_ventana/README | 17 +++++--------- board/gateworks/gw_ventana/common.c | 100 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++---------- board/gateworks/gw_ventana/common.h | 3 +++ board/gateworks/gw_ventana/eeprom.c | 34 +++------------------------ board/gateworks/gw_ventana/gsc.c | 61 +++++++++++++++++++++++++++++++++++++++++++++---- board/gateworks/gw_ventana/gw_ventana.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++++++----- board/gateworks/gw_ventana/gw_ventana_spl.c | 45 ++++++++++++++++++++++++++++++++---- board/gateworks/gw_ventana/ventana_eeprom.h | 1 + board/ge/bx50v3/bx50v3.c | 3 +++ configs/ge_b450v3_defconfig | 12 +++++----- configs/ge_b650v3_defconfig | 12 +++++----- configs/ge_b850v3_defconfig | 12 +++++----- drivers/block/dwc_ahsata.c | 2 +- drivers/misc/mxc_ocotp.c | 4 ++-- drivers/mtd/nand/mxs_nand.c | 2 +- drivers/net/fec_mxc.c | 2 +- include/configs/ge_bx50v3.h | 41 ++++++++++++++++++++++----------- include/configs/gw_ventana.h | 42 ++++++++++++++++++++-------------- include/configs/ts4800.h | 19 ++++++++++++---- 33 files changed, 459 insertions(+), 250 deletions(-) -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

2 2

[U-Boot] [GIT PULL] u-boot-mips/master
by Daniel Schwierzeck 19 Jun '16

19 Jun '16

Hi Tom, this PR contains some fixes for the MIPS cache code. I've also applied the PIC32 SPI driver because there is no reaction from Jagan and the change is isolated. Please pull, thanks. The following changes since commit 6b3943f1b04be60f147ee540fbd72c4c7ea89f80: siemens,am33x: add draco etamin board (2016-06-09 13:53:13 -0400) are available in the git repository at: git://git.denx.de/u-boot-mips.git master for you to fetch changes up to e19b9004575cacf1f64fff894621adafe0e7ea7f: spi: pic32_spi: add SPI master driver for PIC32 SoC. (2016-06-10 12:31:12 +0200) ---------------------------------------------------------------- Paul Burton (2): MIPS: Fix invalidate_dcache_range to operate on L1 Dcache MIPS: Make CONFIG_SYS_DCACHE_LINE_SIZE int, not hex Purna Chandra Mandal (1): spi: pic32_spi: add SPI master driver for PIC32 SoC. arch/mips/Kconfig | 2 +- arch/mips/lib/cache.c | 2 +- drivers/spi/Kconfig | 8 +++ drivers/spi/Makefile | 1 + drivers/spi/pic32_spi.c | 448 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 459 insertions(+), 2 deletions(-) create mode 100644 drivers/spi/pic32_spi.c

2 1

[U-Boot] [PATCH] SPL: fat: Fix spl_parse_image_header() return value handling
by Marek Vasut 19 Jun '16

19 Jun '16

The spl_parse_image_header() can return 0 and it is not an error. Only treat non-zero return value as an error. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)nxp.com> Cc: Peng Fan <van.freenix(a)gmail.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> --- common/spl/spl_fat.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c index 338ea2f..5b0d969 100644 --- a/common/spl/spl_fat.c +++ b/common/spl/spl_fat.c @@ -58,7 +58,7 @@ int spl_load_image_fat(struct blk_desc *block_dev, goto end; err = spl_parse_image_header(header); - if (err <= 0) + if (err) goto end; err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0); -- 2.7.0

6 9

[U-Boot] Auto-detecting touchscreen controller and dealing with hw configuration differences on q8 tablets
by Hans de Goede 19 Jun '16

19 Jun '16

Hi All, The sunxi support in the kernel supports (amongst many other devices) the quite popular low cost q8 form factor 7" tablets. These are all based on the same case, with an allwinner SoC inside (there are non allwinner versions, but those are out of scope) and typically all based on the same reference design. Currently we support any such tablet with 4 u-boot defconfigs / 4 dts files: q8_a13_tablet q8_a23_tablet_800x480 q8_a33_tablet_800x480 q8_a33_tablet_1026x600 So all the user needs to know to get mainline running on these is which SoC his tablet is using and which resolution his lcd has. However the reference design gets completed by the manufacturers with whatever accelerometer, wifi chip and touchscreen controller are cheapest for the batch being produced that week. The plan is (was ?) to use auto-detection to figure out which components are used and adjust the dts using e.g. overlays. Recently I've been working together with some students from my local university to get a driver for the gsl1680 touchscreen controller used in most of these tablets upstream. So now I've been testing the touschscreen on all q8 tablets I own and unfortunately things are not so easy. The gsl1680 is quite flexible, it features a number of capacitive sense pins and these can be routed in random order to sense lines in the display, during init the controller gets feed a configuration data file with which pins go where and various lookup tables. Here is a table of all tablets I've tested: a13-94v-0: a082 a23-tj-a23-q88-v4.0_20140815/GSL1680E_700_FW.fw 1024x600 inverted-x a13-tzx-713b-v2.1: a082 a23-tj-a23-q88-v4.0_20140815/GSL1680E_700_FW.fw 1024x600 a23-q8h-v3: a082 a23-tj-a23-q88-v4.0_20140815/GSL1688_A70_FW.fw 800x480 swapped-x-y a23-tj-a23-q88-v4.0: a082 a23-tj-a23-q88-v4.0_20140815/GSL1680E_700_FW.fw 1024x600 a23-ippo-q8h-v1.2: a082 a23-tj-a23-q88-v4.0_20140815/GSL1688_A70_FW.fw 800x480 swapped-x-y a33-ippo-q8h-v1.2: a082 a23-tj-a23-q88-v4.0_20140815/GSL1688_A70_FW.fw 800x480 swapped-x-y a33-tzx-723q4: b482 a33-Q8_V2.4_1118/GSL1680_FW_D702.fw 960x480 inverted-x a33-q8-v2.4-1118: b482 a33-Q8_V2.4_1118/GSL1680_FW_D702.fw 960x480 a33-q8h-v1.5: b482 a33-q8h-v1.5/GSL1688_A70_FW.fw 960x480 The first column is <soc>-<pcb-marking>, the second is the chip-id from the gsl1680 (this can be read via i2c), the third column is the configdata file used for testing, the directory-name it is prefixed with is from which board's android image the firmware file was extracted. The 4th column shows the resolution of the reported coordinates and any necessary flags. Note that the resolution and if we need swapped-x-y actually is fixed for a given fw file, so we need to keep this information paired. So as you can see which fw file to use, and whether x is inverted or not vary from board to board. This leaves us with 2 options: 1) Move to 1 dts file per PCB variant solution, of ALL the q8 tablets I've seen I've only ever had 2 with identical PCB-s and those were from the same batch, so this seems unmaintainable. Which leaves us with: 2) Give the user some way to override the dts settings. Which after a somewhat long intro brings me to the actual purpose of this thread, discuss how to best deal with this. I again see 2 options: 1) Put a disabled gsl1680 node in the dts file, have a q8_autodetect.c in u-boot which probes i2c and if it finds the gsl1680 nodes enables it, and patches in a best-effort default for which fw file to use. Allow the user to set a touchscreen_fw u-boot env variable which will override this. Also allow the user to set a touchscreen_inverted_x env variable to add inverted-x to the dt node for the gsl1680. 2) Write an in kernel overlay manager which does auto-detect as described by 1, and loads an overlay for the detected touchscreen controller, with module options to allow specifying the fw-file, x-inversion, etc. One things which worries me about 2. is that we would need to have 2 overlay files per fw-file, one regular config, one inverted-x, or is it possible for the overlay manager to modify an overlay before applying it ? I tend towards doing the auto-detect in u-boot, since that will give the greatest flexibility (the dtb is fully read-writable in u-boot) and I can easily access things like i2c-busses, soc id/version register, etc. there. But before syncing a lot of time in either one of these I first wanted to discuss this, if the consensus is that an in kernel overlay manager is the way to go I will take a shot at that instead. Regards, Hans

1 0