May 2016 - U-Boot

[U-Boot] [PATCH] RFC: Secure boot to U-Boot proper from SPL
by Simon Glass 23 May '16

23 May '16

For those that have asked me about this, I have dug into the past and cannot find my experiment. In the end I managed to reduce U-Boot proper down to about 100KB of code (by dropping CONFIG_CMD and removing video and USB drivers) and this was small enough to fit in SRAM. So SPL was not needed. That said, my experiment drove a lot of the FIT and image refactoring and I think it is actually pretty easy now to enable the full FIT implementation in SPL, if your SoC limitations allow it. In the case of Chrome OS, both U-Boot SPL and U-Boot proper are in read-only memory so there is no need for this. But even then it is useful to be able to have the smallest amount of non-updateable software, so quite a bit of work was done (for pit/pi) to support loading a read-write 'U-Boot proper' from SPL. So I think it would be useful to support loading and verifying FIT images with public key encryption in U-Boot, and fairly straightforward. To help things along, here is a starting point for firefly-rk3288 (Thumb 2). This board already uses device tree in SPL (perhaps bravely given the SoC size limitations) so the additional code would be a few KB larger for platforms that don't. For firefly the code size increases from 26KB to 40 KB. There is a fair bit of opportunity to reduce this if needed, for example by cutting out strings. Please reply on this thread if you plan to pick this up and prepare a series to enable this in U-Boot, to reduce duplicated work. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Kconfig | 8 ++++++++ common/Makefile | 3 ++- common/image-fit.c | 2 +- common/spl/spl.c | 1 + configs/firefly-rk3288_defconfig | 5 +++++ drivers/Makefile | 1 + include/configs/rk3288_common.h | 2 ++ lib/Makefile | 3 ++- lib/rsa/rsa-verify.c | 5 ++++- 9 files changed, 26 insertions(+), 4 deletions(-) diff --git a/Kconfig b/Kconfig index f53759a..4ffcc76 100644 --- a/Kconfig +++ b/Kconfig @@ -183,6 +183,10 @@ config FIT verified boot (secure boot using RSA). This option enables that feature. +config SPL_FIT + bool "Support Flattened Image Tree in SPL" + depends on FIT + config FIT_VERBOSE bool "Display verbose messages on FIT boot" depends on FIT @@ -205,6 +209,10 @@ config FIT_SIGNATURE format support in this case, enable it using CONFIG_IMAGE_FORMAT_LEGACY. +config SPL_FIT_SIGNATURE + bool "Enable signature verification of FIT uImages in SPL" + depends on FIT_SIGNATURE + config FIT_BEST_MATCH bool "Select the best match for the kernel device tree" depends on FIT diff --git a/common/Makefile b/common/Makefile index b23f312..647a4ed 100644 --- a/common/Makefile +++ b/common/Makefile @@ -10,7 +10,6 @@ ifndef CONFIG_SPL_BUILD obj-y += init/ obj-y += main.o obj-y += exports.o -obj-y += hash.o ifdef CONFIG_SYS_HUSH_PARSER obj-y += cli_hush.o endif @@ -150,6 +149,8 @@ obj-y += fb_nand.o endif endif +obj-y += hash.o + # We always have this since drivers/ddr/fs/interactive.c needs it obj-$(CONFIG_CMDLINE) += cli_simple.o diff --git a/common/image-fit.c b/common/image-fit.c index 25f8a11..12c94e1 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -1502,7 +1502,7 @@ void fit_conf_print(const void *fit, int noffset, const char *p) static int fit_image_select(const void *fit, int rd_noffset, int verify) { - fit_image_print(fit, rd_noffset, " "); +// fit_image_print(fit, rd_noffset, " "); if (verify) { puts(" Verifying Hash Integrity ... "); diff --git a/common/spl/spl.c b/common/spl/spl.c index 82e7f58..017ca82 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -345,6 +345,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) int i; debug(">>spl:board_init_r()\n"); + fit_image_load(NULL, 0, NULL, NULL, 0, 0, 0, 0, NULL, NULL); #if defined(CONFIG_SYS_SPL_MALLOC_START) mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START, diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 0995f9b..596475c 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -69,3 +69,8 @@ CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y +CONFIG_SPL_FIT=y +CONFIG_SPL_OF_LIBFDT +CONFIG_FIT_SIGNATURE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_FIT=y diff --git a/drivers/Makefile b/drivers/Makefile index 6900097..baf9dee 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_SPL_WATCHDOG_SUPPORT) += watchdog/ obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += usb/host/ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/ obj-$(CONFIG_SPL_SATA_SUPPORT) += block/ +obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/ else diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 8a81397..39bffcb 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -11,6 +11,8 @@ #include <asm/arch/hardware.h> +#define CONFIG_SPL_CRYPTO_SUPPORT + #define CONFIG_SYS_NO_FLASH #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_ENV_SIZE 0x2000 diff --git a/lib/Makefile b/lib/Makefile index 02dfa29..b3ea4bd 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -9,7 +9,6 @@ ifndef CONFIG_SPL_BUILD obj-$(CONFIG_EFI) += efi/ obj-$(CONFIG_EFI_LOADER) += efi_loader/ -obj-$(CONFIG_RSA) += rsa/ obj-$(CONFIG_LZMA) += lzma/ obj-$(CONFIG_LZO) += lzo/ obj-$(CONFIG_ZLIB) += zlib/ @@ -49,6 +48,8 @@ obj-$(CONFIG_BITREVERSE) += bitrev.o obj-y += list_sort.o endif +obj-$(CONFIG_RSA) += rsa/ + obj-$(CONFIG_$(SPL_)OF_LIBFDT) += libfdt/ ifdef CONFIG_SPL_OF_CONTROL obj-$(CONFIG_OF_LIBFDT) += libfdt/ diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c index 60126d2..341ce2e 100644 --- a/lib/rsa/rsa-verify.c +++ b/lib/rsa/rsa-verify.c @@ -200,7 +200,10 @@ int rsa_verify(struct image_sign_info *info, } /* Look for a key that matches our hint */ - snprintf(name, sizeof(name), "key-%s", info->keyname); + // FIXME + //snprintf(name, sizeof(name), "key-%s", info->keyname); + strcpy(name, "key-"); + strcat(name, info->keyname); node = fdt_subnode_offset(blob, sig_node, name); ret = rsa_verify_with_keynode(info, hash, sig, sig_len, node); if (!ret) -- 2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 1/3] SPL: Let spl_parse_image_header() return value
by Marek Vasut 23 May '16

23 May '16

Allow the spl_parse_image_header() to return value. This is convenient for controlling the SPL boot flow if the loaded image is corrupted. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)nxp.com> Cc: Peng Fan <van.freenix(a)gmail.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> --- common/spl/spl.c | 3 ++- common/spl/spl_ext.c | 6 +++++- common/spl/spl_fat.c | 4 +++- common/spl/spl_mmc.c | 6 +++++- common/spl/spl_nand.c | 9 +++++++-- common/spl/spl_net.c | 4 +--- common/spl/spl_nor.c | 9 +++++++-- common/spl/spl_onenand.c | 5 ++++- common/spl/spl_ymodem.c | 7 +++++-- drivers/mtd/spi/spi_spl_load.c | 10 ++++++++-- include/spl.h | 2 +- 11 files changed, 48 insertions(+), 17 deletions(-) diff --git a/common/spl/spl.c b/common/spl/spl.c index 82e7f58..7259619 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -73,7 +73,7 @@ void spl_set_header_raw_uboot(void) spl_image.name = "U-Boot"; } -void spl_parse_image_header(const struct image_header *header) +int spl_parse_image_header(const struct image_header *header) { u32 header_size = sizeof(struct image_header); @@ -118,6 +118,7 @@ void spl_parse_image_header(const struct image_header *header) spl_set_header_raw_uboot(); #endif } + return 0; } __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c index b77dbf4..ade5496 100644 --- a/common/spl/spl_ext.c +++ b/common/spl/spl_ext.c @@ -48,7 +48,11 @@ int spl_load_image_ext(struct blk_desc *block_dev, goto end; } - spl_parse_image_header(header); + err = spl_parse_image_header(header); + if (err < 0) { + puts("spl: ext4fs_read failed\n"); + goto end; + } err = ext4fs_read((char *)spl_image.load_addr, filelen, &actlen); diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c index d761b26..338ea2f 100644 --- a/common/spl/spl_fat.c +++ b/common/spl/spl_fat.c @@ -57,7 +57,9 @@ int spl_load_image_fat(struct blk_desc *block_dev, if (err <= 0) goto end; - spl_parse_image_header(header); + err = spl_parse_image_header(header); + if (err <= 0) + goto end; err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0); diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 8d588d1..360c754 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -23,8 +23,12 @@ static int mmc_load_legacy(struct mmc *mmc, ulong sector, { u32 image_size_sectors; unsigned long count; + int ret; + + ret = spl_parse_image_header(header); + if (ret) + return ret; - spl_parse_image_header(header); /* convert size to sectors - round up */ image_size_sectors = (spl_image.size + mmc->read_bl_len - 1) / mmc->read_bl_len; diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 79388ff..bbd9546 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -32,7 +32,10 @@ static int spl_nand_load_element(int offset, struct image_header *header) if (err) return err; - spl_parse_image_header(header); + err = spl_parse_image_header(header); + if (err) + return err; + return nand_spl_load_image(offset, spl_image.size, (void *)(unsigned long)spl_image.load_addr); } @@ -77,7 +80,9 @@ int spl_nand_load_image(void) /* load linux */ nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS, sizeof(*header), (void *)header); - spl_parse_image_header(header); + err = spl_parse_image_header(header); + if (err) + return err; if (header->ih_os == IH_OS_LINUX) { /* happy - was a linux */ err = nand_spl_load_image( diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c index 63b20d8..ae71d26 100644 --- a/common/spl/spl_net.c +++ b/common/spl/spl_net.c @@ -34,7 +34,5 @@ int spl_net_load_image(const char *device) printf("Problem booting with BOOTP\n"); return rv; } - spl_parse_image_header((struct image_header *)load_addr); - - return 0; + return spl_parse_image_header((struct image_header *)load_addr); } diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index d0bd0b0..da2422f 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -9,6 +9,7 @@ int spl_nor_load_image(void) { + int ret; /* * Loading of the payload to SDRAM is done with skipping of * the mkimage header in this SPL NOR driver @@ -28,7 +29,9 @@ int spl_nor_load_image(void) if (image_get_os(header) == IH_OS_LINUX) { /* happy - was a Linux */ - spl_parse_image_header(header); + ret = spl_parse_image_header(header); + if (ret) + return ret; memcpy((void *)spl_image.load_addr, (void *)(CONFIG_SYS_OS_BASE + @@ -56,8 +59,10 @@ int spl_nor_load_image(void) * Load real U-Boot from its location in NOR flash to its * defined location in SDRAM */ - spl_parse_image_header( + ret = spl_parse_image_header( (const struct image_header *)CONFIG_SYS_UBOOT_BASE); + if (ret) + return ret; memcpy((void *)(unsigned long)spl_image.load_addr, (void *)(CONFIG_SYS_UBOOT_BASE + sizeof(struct image_header)), diff --git a/common/spl/spl_onenand.c b/common/spl/spl_onenand.c index af7d82e..1a28a84 100644 --- a/common/spl/spl_onenand.c +++ b/common/spl/spl_onenand.c @@ -17,6 +17,7 @@ int spl_onenand_load_image(void) { struct image_header *header; + int ret; debug("spl: onenand\n"); @@ -25,7 +26,9 @@ int spl_onenand_load_image(void) /* Load u-boot */ onenand_spl_load_image(CONFIG_SYS_ONENAND_U_BOOT_OFFS, CONFIG_SYS_ONENAND_PAGE_SIZE, (void *)header); - spl_parse_image_header(header); + ret = spl_parse_image_header(header); + if (ret) + return ret; onenand_spl_load_image(CONFIG_SYS_ONENAND_U_BOOT_OFFS, spl_image.size, (void *)spl_image.load_addr); diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c index 380d8dd..4f26ea5 100644 --- a/common/spl/spl_ymodem.c +++ b/common/spl/spl_ymodem.c @@ -40,8 +40,11 @@ int spl_ymodem_load_image(void) if (!ret) { while ((res = xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) { - if (addr == 0) - spl_parse_image_header((struct image_header *)buf); + if (addr == 0) { + ret = spl_parse_image_header((struct image_header *)buf); + if (ret) + return ret; + } store_addr = addr + spl_image.load_addr; size += res; addr += res; diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c index ca56fe9..46c98a9 100644 --- a/drivers/mtd/spi/spi_spl_load.c +++ b/drivers/mtd/spi/spi_spl_load.c @@ -23,6 +23,8 @@ static int spi_load_image_os(struct spi_flash *flash, struct image_header *header) { + int err; + /* Read for a header, parse or error out. */ spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, 0x40, (void *)header); @@ -30,7 +32,9 @@ static int spi_load_image_os(struct spi_flash *flash, if (image_get_magic(header) != IH_MAGIC) return -1; - spl_parse_image_header(header); + err = spl_parse_image_header(header); + if (err) + return err; spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, spl_image.size, (void *)spl_image.load_addr); @@ -81,7 +85,9 @@ int spl_spi_load_image(void) if (err) return err; - spl_parse_image_header(header); + err = spl_parse_image_header(header); + if (err) + return err; err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, spl_image.size, (void *)spl_image.load_addr); } diff --git a/include/spl.h b/include/spl.h index de4f70a..7edfab4 100644 --- a/include/spl.h +++ b/include/spl.h @@ -56,7 +56,7 @@ void preloader_console_init(void); u32 spl_boot_device(void); u32 spl_boot_mode(void); void spl_set_header_raw_uboot(void); -void spl_parse_image_header(const struct image_header *header); +int spl_parse_image_header(const struct image_header *header); void spl_board_prepare_for_linux(void); void __noreturn jump_to_image_linux(void *arg); int spl_start_uboot(void); -- 2.7.0

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[U-Boot] [PATCH v3 00/11] arm: rpi: Enable USB and Ethernet driver model Raspberry Pi
by Simon Glass 23 May '16

23 May '16

Raspberry Pi uses a DWC2 USB controller and a SMSC USB Ethernet adaptor. Driver model support for these was recently merged. This series does the following: - Move Raspberry Pi to use device tree control (u-boot-dtb.bin instead of u-boot.bin) - Remove GPIO platform data (now uses device tree) - Remove serial platform data (now uses device tree) - Enable CONFIG_DM_ETH and CONFIG_DM_USB on Raspberry Pi With Ethernet active the device list looks something like this: U-Boot> dm tree Class Probed Name ---------------------------------------- root [ + ] root_driver simple_bus [ + ] |-- soc gpio [ ] | |-- gpio@7e200000 serial [ + ] | |-- uart@7e201000 usb [ + ] | `-- usb@7e980000 usb_hub [ + ] | `-- usb_hub usb_hub [ + ] | `-- usb_hub eth [ + ] | `-- smsc95xx_eth simple_bus [ ] `-- clocks Changes in v3: - Drop applied patches from series - Drop patch to introduce usbethaddr for driver model - Rename binding file to pl01x.txt Changes in v2: - Add support for Raspberry Pi 2 Simon Glass (11): dm: serial: Update binding for PL01x serial UART arm: rpi: Define CONFIG_TFTP_TSIZE to show tftp size info arm: rpi: Bring in kernel device tree files arm: rpi: Device tree modifications for U-Boot arm: rpi: Add device tree files for Raspberry Pi 2 arm: rpi: Enable device tree control for Rasberry Pi arm: rpi: Enable device tree control for Rasberry Pi 2 arm: rpi: Drop the UART console platform data arm: rpi: Drop the GPIO platform data arm: rpi: Move to driver model for USB arm: rpi: Use driver model for Ethernet arch/arm/dts/Makefile | 3 + arch/arm/dts/bcm2835-rpi-b.dts | 24 ++++ arch/arm/dts/bcm2835.dtsi | 35 +++++ arch/arm/dts/bcm2836-rpi-2-b.dts | 30 +++++ arch/arm/dts/bcm2836.dtsi | 42 ++++++ arch/arm/dts/bcm283x-common.dtsi | 157 ++++++++++++++++++++++ arch/arm/dts/bcm283x-rpi.dtsi | 49 +++++++ arch/arm/dts/stv0991.dts | 2 +- arch/arm/mach-bcm283x/include/mach/gpio.h | 5 - board/raspberrypi/rpi/rpi.c | 24 ---- configs/rpi_2_defconfig | 6 + configs/rpi_defconfig | 6 + doc/device-tree-bindings/arm/bcm/brcm,bcm2835.txt | 8 ++ doc/device-tree-bindings/arm/bcm/brcm,bcm2836.txt | 10 ++ doc/device-tree-bindings/serial/pl01x.txt | 55 +++++++- drivers/gpio/bcm2835_gpio.c | 20 +++ drivers/serial/serial_pl01x.c | 6 +- include/configs/rpi-common.h | 6 +- include/dt-bindings/pinctrl/bcm2835.h | 27 ++++ 19 files changed, 474 insertions(+), 41 deletions(-) create mode 100644 arch/arm/dts/bcm2835-rpi-b.dts create mode 100644 arch/arm/dts/bcm2835.dtsi create mode 100644 arch/arm/dts/bcm2836-rpi-2-b.dts create mode 100644 arch/arm/dts/bcm2836.dtsi create mode 100644 arch/arm/dts/bcm283x-common.dtsi create mode 100644 arch/arm/dts/bcm283x-rpi.dtsi create mode 100644 doc/device-tree-bindings/arm/bcm/brcm,bcm2835.txt create mode 100644 doc/device-tree-bindings/arm/bcm/brcm,bcm2836.txt create mode 100644 include/dt-bindings/pinctrl/bcm2835.h -- 2.5.0.rc2.392.g76e840b

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[U-Boot] [PATCH] Rename reset to sysreset
by Stephen Warren 23 May '16

23 May '16

From: Stephen Warren <swarren(a)nvidia.com> The current reset API implements a method to reset the entire system. In the near future, I'd like to introduce code that implements the device tree reset bindings; i.e. the equivalent of the Linux kernel's reset API. This controls resets to individual HW blocks or external chips with reset signals. It doesn't make sense to merge the two APIs into one since they have different semantic purposes. Resolve the naming conflict by renaming the existing reset API to sysreset instead, so the new reset API can be called just reset. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- arch/arm/lib/Makefile | 2 +- arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 20 +++--- arch/arm/mach-rockchip/rk3288/reset_rk3288.c | 20 +++--- arch/arm/mach-snapdragon/reset.c | 18 ++--- arch/sandbox/cpu/state.c | 4 +- arch/sandbox/include/asm/state.h | 6 +- configs/chromebook_jerry_defconfig | 2 +- configs/dragonboard410c_defconfig | 2 +- configs/evb-rk3036_defconfig | 2 +- configs/firefly-rk3288_defconfig | 2 +- configs/kylin-rk3036_defconfig | 2 +- configs/rock2_defconfig | 2 +- configs/sandbox_defconfig | 2 +- drivers/clk/clk_rk3036.c | 2 +- drivers/clk/clk_rk3288.c | 2 +- drivers/misc/Kconfig | 10 +-- drivers/misc/Makefile | 4 +- drivers/misc/{reset-uclass.c => sysreset-uclass.c} | 32 ++++----- .../misc/{reset_sandbox.c => sysreset_sandbox.c} | 61 +++++++++-------- include/dm/uclass-id.h | 2 +- include/{reset.h => sysreset.h} | 42 ++++++------ test/dm/Makefile | 2 +- test/dm/{reset.c => sysreset.c} | 80 +++++++++++----------- 23 files changed, 161 insertions(+), 160 deletions(-) rename drivers/misc/{reset-uclass.c => sysreset-uclass.c} (55%) rename drivers/misc/{reset_sandbox.c => sysreset_sandbox.c} (46%) rename include/{reset.h => sysreset.h} (47%) rename test/dm/{reset.c => sysreset.c} (16%) diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 7a0fb5862e1b..b535dbef49a2 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -46,7 +46,7 @@ obj-y += interrupts_64.o else obj-y += interrupts.o endif -ifndef CONFIG_RESET +ifndef CONFIG_SYSRESET obj-y += reset.o endif diff --git a/arch/arm/mach-rockchip/rk3036/reset_rk3036.c b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c index fefb568f7aef..b3d211323992 100644 --- a/arch/arm/mach-rockchip/rk3036/reset_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c @@ -7,24 +7,24 @@ #include <common.h> #include <dm.h> #include <errno.h> -#include <reset.h> +#include <sysreset.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/cru_rk3036.h> #include <asm/arch/hardware.h> #include <linux/err.h> -int rk3036_reset_request(struct udevice *dev, enum reset_t type) +int rk3036_sysreset_request(struct udevice *dev, enum sysreset_t type) { struct rk3036_cru *cru = rockchip_get_cru(); if (IS_ERR(cru)) return PTR_ERR(cru); switch (type) { - case RESET_WARM: + case SYSRESET_WARM: writel(0xeca8, &cru->cru_glb_srst_snd_value); break; - case RESET_COLD: + case SYSRESET_COLD: writel(0xfdb9, &cru->cru_glb_srst_fst_value); break; default: @@ -34,12 +34,12 @@ int rk3036_reset_request(struct udevice *dev, enum reset_t type) return -EINPROGRESS; } -static struct reset_ops rk3036_reset = { - .request = rk3036_reset_request, +static struct sysreset_ops rk3036_sysreset = { + .request = rk3036_sysreset_request, }; -U_BOOT_DRIVER(reset_rk3036) = { - .name = "rk3036_reset", - .id = UCLASS_RESET, - .ops = &rk3036_reset, +U_BOOT_DRIVER(sysreset_rk3036) = { + .name = "rk3036_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rk3036_sysreset, }; diff --git a/arch/arm/mach-rockchip/rk3288/reset_rk3288.c b/arch/arm/mach-rockchip/rk3288/reset_rk3288.c index bf7540a5d24d..0aad1c216013 100644 --- a/arch/arm/mach-rockchip/rk3288/reset_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/reset_rk3288.c @@ -7,25 +7,25 @@ #include <common.h> #include <dm.h> #include <errno.h> -#include <reset.h> +#include <sysreset.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/cru_rk3288.h> #include <asm/arch/hardware.h> #include <linux/err.h> -int rk3288_reset_request(struct udevice *dev, enum reset_t type) +int rk3288_sysreset_request(struct udevice *dev, enum sysreset_t type) { struct rk3288_cru *cru = rockchip_get_cru(); if (IS_ERR(cru)) return PTR_ERR(cru); switch (type) { - case RESET_WARM: + case SYSRESET_WARM: rk_clrreg(&cru->cru_mode_con, 0xffff); writel(0xeca8, &cru->cru_glb_srst_snd_value); break; - case RESET_COLD: + case SYSRESET_COLD: rk_clrreg(&cru->cru_mode_con, 0xffff); writel(0xfdb9, &cru->cru_glb_srst_fst_value); break; @@ -36,12 +36,12 @@ int rk3288_reset_request(struct udevice *dev, enum reset_t type) return -EINPROGRESS; } -static struct reset_ops rk3288_reset = { - .request = rk3288_reset_request, +static struct sysreset_ops rk3288_sysreset = { + .request = rk3288_sysreset_request, }; -U_BOOT_DRIVER(reset_rk3288) = { - .name = "rk3288_reset", - .id = UCLASS_RESET, - .ops = &rk3288_reset, +U_BOOT_DRIVER(sysreset_rk3288) = { + .name = "rk3288_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rk3288_sysreset, }; diff --git a/arch/arm/mach-snapdragon/reset.c b/arch/arm/mach-snapdragon/reset.c index 2627eec18154..a6cabfb8b012 100644 --- a/arch/arm/mach-snapdragon/reset.c +++ b/arch/arm/mach-snapdragon/reset.c @@ -9,12 +9,12 @@ #include <common.h> #include <dm.h> #include <errno.h> -#include <reset.h> +#include <sysreset.h> #include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; -static int msm_reset_request(struct udevice *dev, enum reset_t type) +static int msm_sysreset_request(struct udevice *dev, enum sysreset_t type) { phys_addr_t addr = dev_get_addr(dev); if (!addr) @@ -23,18 +23,18 @@ static int msm_reset_request(struct udevice *dev, enum reset_t type) return -EINPROGRESS; } -static struct reset_ops msm_reset_ops = { - .request = msm_reset_request, +static struct sysreset_ops msm_sysreset_ops = { + .request = msm_sysreset_request, }; -static const struct udevice_id msm_reset_ids[] = { +static const struct udevice_id msm_sysreset_ids[] = { { .compatible = "qcom,pshold" }, { } }; U_BOOT_DRIVER(msm_reset) = { - .name = "msm_reset", - .id = UCLASS_RESET, - .of_match = msm_reset_ids, - .ops = &msm_reset_ops, + .name = "msm_sysreset", + .id = UCLASS_SYSRESET, + .of_match = msm_sysreset_ids, + .ops = &msm_sysreset_ops, }; diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index d2a7dc9b450f..2b4dbd341ff3 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -360,8 +360,8 @@ int state_init(void) assert(state->ram_buf); /* No reset yet, so mark it as such. Always allow power reset */ - state->last_reset = RESET_COUNT; - state->reset_allowed[RESET_POWER] = true; + state->last_sysreset = SYSRESET_COUNT; + state->sysreset_allowed[SYSRESET_POWER] = true; /* * Example of how to use GPIOs: diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index 11856c2fede6..149f28d8732f 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -7,7 +7,7 @@ #define __SANDBOX_STATE_H #include <config.h> -#include <reset.h> +#include <sysreset.h> #include <stdbool.h> #include <linux/stringify.h> @@ -60,8 +60,8 @@ struct sandbox_state { bool write_state; /* Write sandbox state on exit */ bool ignore_missing_state_on_read; /* No error if state missing */ bool show_lcd; /* Show LCD on start-up */ - enum reset_t last_reset; /* Last reset type */ - bool reset_allowed[RESET_COUNT]; /* Allowed reset types */ + enum sysreset_t last_sysreset; /* Last system reset type */ + bool sysreset_allowed[SYSRESET_COUNT]; /* Allowed system reset types */ enum state_terminal_raw term_raw; /* Terminal raw/cooked */ bool skip_delays; /* Ignore any time delays (for test) */ bool show_test_output; /* Don't suppress stdout in tests */ diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 25ead92778cc..d5bc5153b1b1 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y -CONFIG_RESET=y +CONFIG_SYSRESET=y CONFIG_DM_MMC=y CONFIG_ROCKCHIP_DWMMC=y CONFIG_PINCTRL=y diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index 2566ded58a44..37c5ea7761c9 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -23,7 +23,7 @@ CONFIG_MSM_GPIO=y CONFIG_PM8916_GPIO=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_RESET=y +CONFIG_SYSRESET=y CONFIG_DM_MMC=y CONFIG_MSM_SDHCI=y CONFIG_DM_PMIC=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 4dd458624342..9894fffcca20 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -28,7 +28,7 @@ CONFIG_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y -CONFIG_RESET=y +CONFIG_SYSRESET=y CONFIG_DM_MMC=y CONFIG_ROCKCHIP_DWMMC=y CONFIG_PINCTRL=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 0995f9b329fe..0cbc5398488d 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -40,7 +40,7 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y CONFIG_LED_GPIO=y -CONFIG_RESET=y +CONFIG_SYSRESET=y CONFIG_DM_MMC=y CONFIG_ROCKCHIP_DWMMC=y CONFIG_PINCTRL=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 50fbe654bf63..0ff6c6b9a4ac 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -28,7 +28,7 @@ CONFIG_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_LED=y -CONFIG_RESET=y +CONFIG_SYSRESET=y CONFIG_DM_MMC=y CONFIG_ROCKCHIP_DWMMC=y CONFIG_PINCTRL=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index fd32fb521eb6..3e16b805caa8 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -38,7 +38,7 @@ CONFIG_CLK=y CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_RESET=y +CONFIG_SYSRESET=y CONFIG_DM_MMC=y CONFIG_ROCKCHIP_DWMMC=y CONFIG_PINCTRL=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index afdf4a3ba715..9ad570c7fc49 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -95,7 +95,7 @@ CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y -CONFIG_RESET=y +CONFIG_SYSRESET=y CONFIG_DM_MMC=y CONFIG_SPI_FLASH_SANDBOX=y CONFIG_SPI_FLASH=y diff --git a/drivers/clk/clk_rk3036.c b/drivers/clk/clk_rk3036.c index bd5f22a753a4..7ec65bdff029 100644 --- a/drivers/clk/clk_rk3036.c +++ b/drivers/clk/clk_rk3036.c @@ -407,7 +407,7 @@ static int rk3036_clk_bind(struct udevice *dev) } /* The reset driver does not have a device node, so bind it here */ - ret = device_bind_driver(gd->dm_root, "rk3036_reset", "reset", &dev); + ret = device_bind_driver(gd->dm_root, "rk3036_sysreset", "reset", &dev); if (ret) debug("Warning: No RK3036 reset driver: ret=%d\n", ret); diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c index 2a85e93a6cc3..e763a1c8e91f 100644 --- a/drivers/clk/clk_rk3288.c +++ b/drivers/clk/clk_rk3288.c @@ -877,7 +877,7 @@ static int rk3288_clk_bind(struct udevice *dev) } /* The reset driver does not have a device node, so bind it here */ - ret = device_bind_driver(gd->dm_root, "rk3288_reset", "reset", &dev); + ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev); if (ret) debug("Warning: No RK3288 reset driver: ret=%d\n", ret); diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index af8667f030c5..48f23e61cf8e 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -121,13 +121,13 @@ config PCA9551_I2C_ADDR help The I2C address of the PCA9551 LED controller. -config RESET - bool "Enable support for reset drivers" +config SYSRESET + bool "Enable support for system reset drivers" depends on DM help - Enable reset drivers which can be used to reset the CPU or board. - Each driver can provide a reset method which will be called to - effect a reset. The uclass will try all available drivers when + Enable system reset drivers which can be used to reset the CPU or + board. Each driver can provide a reset method which will be called + to effect a reset. The uclass will try all available drivers when reset_walk() is called. config WINBOND_W83627 diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 5969d3444413..59c73415139c 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -27,7 +27,7 @@ obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o obj-$(CONFIG_NS87308) += ns87308.o obj-$(CONFIG_PDSP188x) += pdsp188x.o obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o -obj-$(CONFIG_SANDBOX) += reset_sandbox.o +obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o ifdef CONFIG_DM_I2C obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o endif @@ -40,6 +40,6 @@ obj-$(CONFIG_TWL4030_LED) += twl4030_led.o obj-$(CONFIG_FSL_IFC) += fsl_ifc.o obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o obj-$(CONFIG_PCA9551_LED) += pca9551_led.o -obj-$(CONFIG_RESET) += reset-uclass.o +obj-$(CONFIG_SYSRESET) += sysreset-uclass.o obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o diff --git a/drivers/misc/reset-uclass.c b/drivers/misc/sysreset-uclass.c similarity index 55% rename from drivers/misc/reset-uclass.c rename to drivers/misc/sysreset-uclass.c index fdb5c6fcff34..e41efcaca602 100644 --- a/drivers/misc/reset-uclass.c +++ b/drivers/misc/sysreset-uclass.c @@ -6,7 +6,7 @@ */ #include <common.h> -#include <reset.h> +#include <sysreset.h> #include <dm.h> #include <errno.h> #include <regmap.h> @@ -15,9 +15,9 @@ #include <dm/root.h> #include <linux/err.h> -int reset_request(struct udevice *dev, enum reset_t type) +int sysreset_request(struct udevice *dev, enum sysreset_t type) { - struct reset_ops *ops = reset_get_ops(dev); + struct sysreset_ops *ops = sysreset_get_ops(dev); if (!ops->request) return -ENOSYS; @@ -25,16 +25,16 @@ int reset_request(struct udevice *dev, enum reset_t type) return ops->request(dev, type); } -int reset_walk(enum reset_t type) +int sysreset_walk(enum sysreset_t type) { struct udevice *dev; int ret = -ENOSYS; - while (ret != -EINPROGRESS && type < RESET_COUNT) { - for (uclass_first_device(UCLASS_RESET, &dev); + while (ret != -EINPROGRESS && type < SYSRESET_COUNT) { + for (uclass_first_device(UCLASS_SYSRESET, &dev); dev; uclass_next_device(&dev)) { - ret = reset_request(dev, type); + ret = sysreset_request(dev, type); if (ret == -EINPROGRESS) break; } @@ -44,38 +44,38 @@ int reset_walk(enum reset_t type) return ret; } -void reset_walk_halt(enum reset_t type) +void sysreset_walk_halt(enum sysreset_t type) { int ret; - ret = reset_walk(type); + ret = sysreset_walk(type); /* Wait for the reset to take effect */ if (ret == -EINPROGRESS) mdelay(100); /* Still no reset? Give up */ - printf("Reset not supported on this platform\n"); + printf("System reset not supported on this platform\n"); hang(); } /** - * reset_cpu() - calls reset_walk(RESET_WARM) + * reset_cpu() - calls sysreset_walk(SYSRESET_WARM) */ void reset_cpu(ulong addr) { - reset_walk_halt(RESET_WARM); + sysreset_walk_halt(SYSRESET_WARM); } int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - reset_walk_halt(RESET_WARM); + sysreset_walk_halt(SYSRESET_WARM); return 0; } -UCLASS_DRIVER(reset) = { - .id = UCLASS_RESET, - .name = "reset", +UCLASS_DRIVER(sysreset) = { + .id = UCLASS_SYSRESET, + .name = "sysreset", }; diff --git a/drivers/misc/reset_sandbox.c b/drivers/misc/sysreset_sandbox.c similarity index 46% rename from drivers/misc/reset_sandbox.c rename to drivers/misc/sysreset_sandbox.c index 2691bb031a50..7ae7f386ee02 100644 --- a/drivers/misc/reset_sandbox.c +++ b/drivers/misc/sysreset_sandbox.c @@ -8,30 +8,31 @@ #include <common.h> #include <dm.h> #include <errno.h> -#include <reset.h> +#include <sysreset.h> #include <asm/state.h> #include <asm/test.h> DECLARE_GLOBAL_DATA_PTR; -static int sandbox_warm_reset_request(struct udevice *dev, enum reset_t type) +static int sandbox_warm_sysreset_request(struct udevice *dev, + enum sysreset_t type) { struct sandbox_state *state = state_get_current(); switch (type) { - case RESET_WARM: - state->last_reset = type; + case SYSRESET_WARM: + state->last_sysreset = type; break; default: return -ENOSYS; } - if (!state->reset_allowed[type]) + if (!state->sysreset_allowed[type]) return -EACCES; return -EINPROGRESS; } -static int sandbox_reset_request(struct udevice *dev, enum reset_t type) +static int sandbox_sysreset_request(struct udevice *dev, enum sysreset_t type) { struct sandbox_state *state = state_get_current(); @@ -44,57 +45,57 @@ static int sandbox_reset_request(struct udevice *dev, enum reset_t type) return -ENODEV; switch (type) { - case RESET_COLD: - state->last_reset = type; + case SYSRESET_COLD: + state->last_sysreset = type; break; - case RESET_POWER: - state->last_reset = type; - if (!state->reset_allowed[type]) + case SYSRESET_POWER: + state->last_sysreset = type; + if (!state->sysreset_allowed[type]) return -EACCES; sandbox_exit(); break; default: return -ENOSYS; } - if (!state->reset_allowed[type]) + if (!state->sysreset_allowed[type]) return -EACCES; return -EINPROGRESS; } -static struct reset_ops sandbox_reset_ops = { - .request = sandbox_reset_request, +static struct sysreset_ops sandbox_sysreset_ops = { + .request = sandbox_sysreset_request, }; -static const struct udevice_id sandbox_reset_ids[] = { +static const struct udevice_id sandbox_sysreset_ids[] = { { .compatible = "sandbox,reset" }, { } }; -U_BOOT_DRIVER(reset_sandbox) = { - .name = "reset_sandbox", - .id = UCLASS_RESET, - .of_match = sandbox_reset_ids, - .ops = &sandbox_reset_ops, +U_BOOT_DRIVER(sysreset_sandbox) = { + .name = "sysreset_sandbox", + .id = UCLASS_SYSRESET, + .of_match = sandbox_sysreset_ids, + .ops = &sandbox_sysreset_ops, }; -static struct reset_ops sandbox_warm_reset_ops = { - .request = sandbox_warm_reset_request, +static struct sysreset_ops sandbox_warm_sysreset_ops = { + .request = sandbox_warm_sysreset_request, }; -static const struct udevice_id sandbox_warm_reset_ids[] = { +static const struct udevice_id sandbox_warm_sysreset_ids[] = { { .compatible = "sandbox,warm-reset" }, { } }; -U_BOOT_DRIVER(warm_reset_sandbox) = { - .name = "warm_reset_sandbox", - .id = UCLASS_RESET, - .of_match = sandbox_warm_reset_ids, - .ops = &sandbox_warm_reset_ops, +U_BOOT_DRIVER(warm_sysreset_sandbox) = { + .name = "warm_sysreset_sandbox", + .id = UCLASS_SYSRESET, + .of_match = sandbox_warm_sysreset_ids, + .ops = &sandbox_warm_sysreset_ops, }; /* This is here in case we don't have a device tree */ -U_BOOT_DEVICE(reset_sandbox_non_fdt) = { - .name = "reset_sandbox", +U_BOOT_DEVICE(sysreset_sandbox_non_fdt) = { + .name = "sysreset_sandbox", }; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index cbf9b2ca2351..45ae9650e3dd 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -61,7 +61,6 @@ enum uclass_id { UCLASS_PWM, /* Pulse-width modulator */ UCLASS_PWRSEQ, /* Power sequence device */ UCLASS_REGULATOR, /* Regulator device */ - UCLASS_RESET, /* Reset device */ UCLASS_REMOTEPROC, /* Remote Processor device */ UCLASS_RTC, /* Real time clock device */ UCLASS_SERIAL, /* Serial UART */ @@ -70,6 +69,7 @@ enum uclass_id { UCLASS_SPI_FLASH, /* SPI flash */ UCLASS_SPI_GENERIC, /* Generic SPI flash target */ UCLASS_SYSCON, /* System configuration device */ + UCLASS_SYSRESET, /* System reset device */ UCLASS_THERMAL, /* Thermal sensor */ UCLASS_TIMER, /* Timer device */ UCLASS_TPM, /* Trusted Platform Module TIS interface */ diff --git a/include/reset.h b/include/sysreset.h similarity index 47% rename from include/reset.h rename to include/sysreset.h index 383761eb1fb0..393c7be3d811 100644 --- a/include/reset.h +++ b/include/sysreset.h @@ -5,20 +5,20 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __RESET_H -#define __RESET_H +#ifndef __SYSRESET_H +#define __SYSRESET_H -enum reset_t { - RESET_WARM, /* Reset CPU, keep GPIOs active */ - RESET_COLD, /* Reset CPU and GPIOs */ - RESET_POWER, /* Reset PMIC (remove and restore power) */ +enum sysreset_t { + SYSRESET_WARM, /* Reset CPU, keep GPIOs active */ + SYSRESET_COLD, /* Reset CPU and GPIOs */ + SYSRESET_POWER, /* Reset PMIC (remove and restore power) */ - RESET_COUNT, + SYSRESET_COUNT, }; -struct reset_ops { +struct sysreset_ops { /** - * request() - request a reset of the given type + * request() - request a sysreset of the given type * * Note that this function may return before the reset takes effect. * @@ -28,24 +28,24 @@ struct reset_ops { * by this device, 0 if the reset has already happened * (in which case this method will not actually return) */ - int (*request)(struct udevice *dev, enum reset_t type); + int (*request)(struct udevice *dev, enum sysreset_t type); }; -#define reset_get_ops(dev) ((struct reset_ops *)(dev)->driver->ops) +#define sysreset_get_ops(dev) ((struct sysreset_ops *)(dev)->driver->ops) /** - * reset_request() - request a reset + * sysreset_request() - request a sysreset * * @type: Reset type to request * @return 0 if OK, -EPROTONOSUPPORT if not supported by this device */ -int reset_request(struct udevice *dev, enum reset_t type); +int sysreset_request(struct udevice *dev, enum sysreset_t type); /** - * reset_walk() - cause a reset + * sysreset_walk() - cause a system reset * - * This works through the available reset devices until it finds one that can - * perform a reset. If the provided reset type is not available, the next one + * This works through the available sysreset devices until it finds one that can + * perform a reset. If the provided sysreset type is not available, the next one * will be tried. * * If this function fails to reset, it will display a message and halt @@ -53,18 +53,18 @@ int reset_request(struct udevice *dev, enum reset_t type); * @type: Reset type to request * @return -EINPROGRESS if a reset is in progress, -ENOSYS if not available */ -int reset_walk(enum reset_t type); +int sysreset_walk(enum sysreset_t type); /** - * reset_walk_halt() - try to reset, otherwise halt + * sysreset_walk_halt() - try to reset, otherwise halt * - * This calls reset_walk(). If it returns, indicating that reset is not + * This calls sysreset_walk(). If it returns, indicating that reset is not * supported, it prints a message and halts. */ -void reset_walk_halt(enum reset_t type); +void sysreset_walk_halt(enum sysreset_t type); /** - * reset_cpu() - calls reset_walk(RESET_WARM) + * reset_cpu() - calls sysreset_walk(SYSRESET_WARM) */ void reset_cpu(ulong addr); diff --git a/test/dm/Makefile b/test/dm/Makefile index 9a11ae0a147a..fd781e82cfe8 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -26,7 +26,7 @@ obj-$(CONFIG_DM_PCI) += pci.o obj-$(CONFIG_RAM) += ram.o obj-y += regmap.o obj-$(CONFIG_REMOTEPROC) += remoteproc.o -obj-$(CONFIG_RESET) += reset.o +obj-$(CONFIG_SYSRESET) += sysreset.o obj-$(CONFIG_DM_RTC) += rtc.o obj-$(CONFIG_DM_SPI_FLASH) += sf.o obj-$(CONFIG_DM_SPI) += spi.o diff --git a/test/dm/reset.c b/test/dm/sysreset.c similarity index 16% rename from test/dm/reset.c rename to test/dm/sysreset.c index 5d53f252bb5e..5e94c072b658 100644 --- a/test/dm/reset.c +++ b/test/dm/sysreset.c @@ -6,69 +6,69 @@ #include <common.h> #include <dm.h> -#include <reset.h> +#include <sysreset.h> #include <asm/state.h> #include <asm/test.h> #include <dm/test.h> #include <test/ut.h> -/* Test that we can use particular reset devices */ -static int dm_test_reset_base(struct unit_test_state *uts) +/* Test that we can use particular sysreset devices */ +static int dm_test_sysreset_base(struct unit_test_state *uts) { struct sandbox_state *state = state_get_current(); struct udevice *dev; /* Device 0 is the platform data device - it should never respond */ - ut_assertok(uclass_get_device(UCLASS_RESET, 0, &dev)); - ut_asserteq(-ENODEV, reset_request(dev, RESET_WARM)); - ut_asserteq(-ENODEV, reset_request(dev, RESET_COLD)); - ut_asserteq(-ENODEV, reset_request(dev, RESET_POWER)); + ut_assertok(uclass_get_device(UCLASS_SYSRESET, 0, &dev)); + ut_asserteq(-ENODEV, sysreset_request(dev, SYSRESET_WARM)); + ut_asserteq(-ENODEV, sysreset_request(dev, SYSRESET_COLD)); + ut_asserteq(-ENODEV, sysreset_request(dev, SYSRESET_POWER)); - /* Device 1 is the warm reset device */ - ut_assertok(uclass_get_device(UCLASS_RESET, 1, &dev)); - ut_asserteq(-EACCES, reset_request(dev, RESET_WARM)); - ut_asserteq(-ENOSYS, reset_request(dev, RESET_COLD)); - ut_asserteq(-ENOSYS, reset_request(dev, RESET_POWER)); + /* Device 1 is the warm sysreset device */ + ut_assertok(uclass_get_device(UCLASS_SYSRESET, 1, &dev)); + ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_WARM)); + ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_COLD)); + ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_POWER)); - state->reset_allowed[RESET_WARM] = true; - ut_asserteq(-EINPROGRESS, reset_request(dev, RESET_WARM)); - state->reset_allowed[RESET_WARM] = false; + state->sysreset_allowed[SYSRESET_WARM] = true; + ut_asserteq(-EINPROGRESS, sysreset_request(dev, SYSRESET_WARM)); + state->sysreset_allowed[SYSRESET_WARM] = false; - /* Device 2 is the cold reset device */ - ut_assertok(uclass_get_device(UCLASS_RESET, 2, &dev)); - ut_asserteq(-ENOSYS, reset_request(dev, RESET_WARM)); - ut_asserteq(-EACCES, reset_request(dev, RESET_COLD)); - state->reset_allowed[RESET_POWER] = false; - ut_asserteq(-EACCES, reset_request(dev, RESET_POWER)); - state->reset_allowed[RESET_POWER] = true; + /* Device 2 is the cold sysreset device */ + ut_assertok(uclass_get_device(UCLASS_SYSRESET, 2, &dev)); + ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_WARM)); + ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_COLD)); + state->sysreset_allowed[SYSRESET_POWER] = false; + ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_POWER)); + state->sysreset_allowed[SYSRESET_POWER] = true; return 0; } -DM_TEST(dm_test_reset_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); +DM_TEST(dm_test_sysreset_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); -/* Test that we can walk through the reset devices */ -static int dm_test_reset_walk(struct unit_test_state *uts) +/* Test that we can walk through the sysreset devices */ +static int dm_test_sysreset_walk(struct unit_test_state *uts) { struct sandbox_state *state = state_get_current(); - /* If we generate a power reset, we will exit sandbox! */ - state->reset_allowed[RESET_POWER] = false; - ut_asserteq(-EACCES, reset_walk(RESET_WARM)); - ut_asserteq(-EACCES, reset_walk(RESET_COLD)); - ut_asserteq(-EACCES, reset_walk(RESET_POWER)); + /* If we generate a power sysreset, we will exit sandbox! */ + state->sysreset_allowed[SYSRESET_POWER] = false; + ut_asserteq(-EACCES, sysreset_walk(SYSRESET_WARM)); + ut_asserteq(-EACCES, sysreset_walk(SYSRESET_COLD)); + ut_asserteq(-EACCES, sysreset_walk(SYSRESET_POWER)); /* - * Enable cold reset - this should make cold reset work, plus a warm - * reset should be promoted to cold, since this is the next step - * along. + * Enable cold system reset - this should make cold system reset work, + * plus a warm system reset should be promoted to cold, since this is + * the next step along. */ - state->reset_allowed[RESET_COLD] = true; - ut_asserteq(-EINPROGRESS, reset_walk(RESET_WARM)); - ut_asserteq(-EINPROGRESS, reset_walk(RESET_COLD)); - ut_asserteq(-EACCES, reset_walk(RESET_POWER)); - state->reset_allowed[RESET_COLD] = false; - state->reset_allowed[RESET_POWER] = true; + state->sysreset_allowed[SYSRESET_COLD] = true; + ut_asserteq(-EINPROGRESS, sysreset_walk(SYSRESET_WARM)); + ut_asserteq(-EINPROGRESS, sysreset_walk(SYSRESET_COLD)); + ut_asserteq(-EACCES, sysreset_walk(SYSRESET_POWER)); + state->sysreset_allowed[SYSRESET_COLD] = false; + state->sysreset_allowed[SYSRESET_POWER] = true; return 0; } -DM_TEST(dm_test_reset_walk, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); +DM_TEST(dm_test_sysreset_walk, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT); -- 2.8.2

3 4

[U-Boot] [PATCH V2 1/2] dm: allow setting driver_data before/during bind
by Stephen Warren 23 May '16

23 May '16

From: Stephen Warren <swarren(a)nvidia.com> This will allow a driver's bind function to use the driver data. One example is the Tegra186 GPIO driver, which instantiates child devices for each of its GPIO ports, yet supports two different HW instances each with a different set of ports, and identified by the udevice_id .data field. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- v2: * Introduce a separate function for the new functionality, rather than modifying device_bind(). This patch is a dependency for the upcoming Tegra186 GPIO driver too. --- doc/driver-model/README.txt | 23 ++++++++++++++--------- drivers/core/device.c | 25 ++++++++++++++++++++++--- drivers/core/lists.c | 4 ++-- include/dm/device-internal.h | 24 ++++++++++++++++++++++++ 4 files changed, 62 insertions(+), 14 deletions(-) diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt index 7a24552560d5..1b5ccec4b2e5 100644 --- a/doc/driver-model/README.txt +++ b/doc/driver-model/README.txt @@ -606,19 +606,24 @@ methods actually defined. 1. Bind stage -A device and its driver are bound using one of these two methods: +U-Boot discovers devices using one of these two methods: - - Scan the U_BOOT_DEVICE() definitions. U-Boot It looks up the -name specified by each, to find the appropriate driver. It then calls -device_bind() to create a new device and bind' it to its driver. This will -call the device's bind() method. + - Scan the U_BOOT_DEVICE() definitions. U-Boot looks up the name specified +by each, to find the appropriate U_BOOT_DRIVER() definition. In this case, +there is no path by which driver_data may be provided, but the U_BOOT_DEVICE() +may provide platdata. - Scan through the device tree definitions. U-Boot looks at top-level nodes in the the device tree. It looks at the compatible string in each node -and uses the of_match part of the U_BOOT_DRIVER() structure to find the -right driver for each node. It then calls device_bind() to bind the -newly-created device to its driver (thereby creating a device structure). -This will also call the device's bind() method. +and uses the of_match table of the U_BOOT_DRIVER() structure to find the +right driver for each node. In this case, the of_match table may provide a +driver_data value, but platdata cannot be provided until later. + +For each device that is discovered, U-Boot then calls device_bind() to create a +new device, initializes various core fields of the device object such as name, +uclass & driver, initializes any optional fields of the device object that are +applicable such as of_offset, driver_data & platdata, and finally calls the +driver's bind() method if one is defined. At this point all the devices are known, and bound to their drivers. There is a 'struct udevice' allocated for all devices. However, nothing has been diff --git a/drivers/core/device.c b/drivers/core/device.c index 2b12ce7835f0..a8f2380e4676 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -26,9 +26,10 @@ DECLARE_GLOBAL_DATA_PTR; -int device_bind(struct udevice *parent, const struct driver *drv, - const char *name, void *platdata, int of_offset, - struct udevice **devp) +static int device_bind_common(struct udevice *parent, const struct driver *drv, + const char *name, void *platdata, + ulong driver_data, int of_offset, + struct udevice **devp) { struct udevice *dev; struct uclass *uc; @@ -56,6 +57,7 @@ int device_bind(struct udevice *parent, const struct driver *drv, INIT_LIST_HEAD(&dev->devres_head); #endif dev->platdata = platdata; + dev->driver_data = driver_data; dev->name = name; dev->of_offset = of_offset; dev->parent = parent; @@ -193,6 +195,23 @@ fail_alloc1: return ret; } +int device_bind_with_driver_data(struct udevice *parent, + const struct driver *drv, const char *name, + ulong driver_data, int of_offset, + struct udevice **devp) +{ + return device_bind_common(parent, drv, name, NULL, driver_data, + of_offset, devp); +} + +int device_bind(struct udevice *parent, const struct driver *drv, + const char *name, void *platdata, int of_offset, + struct udevice **devp) +{ + return device_bind_common(parent, drv, name, platdata, 0, of_offset, + devp); +} + int device_bind_by_name(struct udevice *parent, bool pre_reloc_only, const struct driver_info *info, struct udevice **devp) { diff --git a/drivers/core/lists.c b/drivers/core/lists.c index a72db13a119a..0c2771779096 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -170,7 +170,8 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset, } dm_dbg(" - found match at '%s'\n", entry->name); - ret = device_bind(parent, entry, name, NULL, offset, &dev); + ret = device_bind_with_driver_data(parent, entry, name, + id->data, offset, &dev); if (ret == -ENODEV) { dm_dbg("Driver '%s' refuses to bind\n", entry->name); continue; @@ -180,7 +181,6 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset, ret); return ret; } else { - dev->driver_data = id->data; found = true; if (devp) *devp = dev; diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h index b348ad5231bd..0bf8707493a9 100644 --- a/include/dm/device-internal.h +++ b/include/dm/device-internal.h @@ -39,6 +39,30 @@ int device_bind(struct udevice *parent, const struct driver *drv, struct udevice **devp); /** + * device_bind_with_driver_data() - Create a device and bind it to a driver + * + * Called to set up a new device attached to a driver, in the case where the + * driver was matched to the device by means of a match table that provides + * driver_data. + * + * Once bound a device exists but is not yet active until device_probe() is + * called. + * + * @parent: Pointer to device's parent, under which this driver will exist + * @drv: Device's driver + * @name: Name of device (e.g. device tree node name) + * @driver_data: The driver_data field from the driver's match table. + * @of_offset: Offset of device tree node for this device. This is -1 for + * devices which don't use device tree. + * @devp: if non-NULL, returns a pointer to the bound device + * @return 0 if OK, -ve on error + */ +int device_bind_with_driver_data(struct udevice *parent, + const struct driver *drv, const char *name, + ulong driver_data, int of_offset, + struct udevice **devp); + +/** * device_bind_by_name: Create a device and bind it to a driver * * This is a helper function used to bind devices which do not use device -- 2.8.2

3 9

[U-Boot] [U-BOOT] [PATCH] net: Add EMAC driver for H3/A83T/A64
by Amit Singh Tomar 23 May '16

23 May '16

This patch add EMAC driver support for H3/A83T/A64 SoCs. It has been tested on Oragnepipc(H3) board that has internal PHY. Signed-off-by: Amit Singh Tomar <amittomer25(a)gmail.com> --- arch/arm/dts/sun8i-h3-orangepi-pc.dts | 10 + arch/arm/dts/sun8i-h3.dtsi | 7 + drivers/net/Kconfig | 8 + drivers/net/Makefile | 1 + drivers/net/sun8i_emac.c | 678 +++++++++++++++++++++++++++++++++ 5 files changed, 704 insertions(+) create mode 100644 drivers/net/sun8i_emac.c diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-orangepi-pc.dts index 30ccca0..3a40fb8 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts @@ -173,3 +173,13 @@ /* USB VBUS is always on */ status = "okay"; }; + +&emac { + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi index c2f63c5..1e403e3 100644 --- a/arch/arm/dts/sun8i-h3.dtsi +++ b/arch/arm/dts/sun8i-h3.dtsi @@ -616,6 +616,13 @@ status = "disabled"; }; + emac: ethernet@01c30000 { + compatible = "allwinner,sun8i-h3-emac"; + reg = <0x01c30000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + }; + gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 91b7690..3c21810 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -46,6 +46,14 @@ menuconfig NETDEVICES if NETDEVICES +config SUN8I_EMAC + bool "Allwinner Sun8i Ethernet MAC support" + depends on DM_ETH + select PHYLIB + help + This driver supports the Allwinner based SUN8I Ethernet MAC.It can + be found in Allwinners H3/A64/A83T based SoCs. + config ALTERA_TSE bool "Altera Triple-Speed Ethernet MAC support" depends on DM_ETH diff --git a/drivers/net/Makefile b/drivers/net/Makefile index fbedd04..f78fdc5 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -74,3 +74,4 @@ obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/ obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o obj-$(CONFIG_VSC9953) += vsc9953.o obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o +obj-$(CONFIG_SUN8I_EMAC) = sun8i_emac.o diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c new file mode 100644 index 0000000..0858235 --- /dev/null +++ b/drivers/net/sun8i_emac.c @@ -0,0 +1,678 @@ +/* + * (C) Copyright 2016 + * Author: Amit Singh Tomar, amittomer25(a)gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Ethernet driver for H3/A64 based SoC + */ + +#include <common.h> +#include <dm.h> +#include <linux/err.h> +#include <malloc.h> +#include <miiphy.h> +#include <net.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> + +#define SUN8I_AHB2_EPHY 0x02c8 + +#define AHB2_CFG_REG 0x005c + +#define BUS_SOFT_RST_REG0 0x02c0 +#define BUS_SOFT_RST_REG2 0x02c8 + +#define EPHY_RST (0x1 << 2) +#define EMAC_RST (0x1 << 17) + +#define SUN8I_CCU_BASE 0x01c20000 +#define SUN8I_SCTL_BASE 0x01c00000 + +#define SCTL_EMAC_TX_CLK_SRC_MII ((1 << 1) | (1 << 0)) +#define SCTL_EMAC_EPIT_MII (1 << 2) +#define SCTL_EMAC_CLK_SEL (1 << 18) /* 25 Mhz */ + +#define MDIO_CMD_MII_BUSY BIT(0) +#define MDIO_CMD_MII_WRITE BIT(1) + +#define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0 +#define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4 +#define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000 +#define MDIO_CMD_MII_PHY_ADDR_SHIFT 12 + +#define CONFIG_TX_DESCR_NUM 128 +#define CONFIG_RX_DESCR_NUM 128 +#define CONFIG_ETH_BUFSIZE 1522 + +#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) +#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) + +#define REG_DEFAULT_VALUE 0x58000 +#define REG_DEFAULT_MASK GENMASK(31, 15) + +#define REG_PHY_ADDR_SHIFT 20 +#define REG_PHY_ADDR_MASK GENMASK(4, 0) +#define REG_LED_POL BIT(17) /* 1: active low, 0: active high */ +#define REG_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ +#define REG_PHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ + +#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) + +#define AHB_GATE_OFFSET_GMAC 17 +#define AHB_GATE_OFFSET_EPHY 0 + +#define SUN8I_GPD8_GMAC 4 + +/* H3/A64 EMAC Register Base */ +#define SUN8I_EMAC_BASE 0x01c30000 + +/* H3/A64 EMAC Register's offset */ +#define CTL0 0x00 +#define CTL1 0x04 +#define INT_STA 0x08 +#define INT_EN 0x0c +#define TX_CTL0 0x10 +#define TX_CTL1 0x14 +#define TX_FLOW_CTL 0x1c +#define TX_DMA_DESC 0x20 +#define RX_CTL0 0x24 +#define RX_CTL1 0x28 +#define RX_DMA_DESC 0x34 +#define MII_CMD 0x48 +#define MII_DATA 0x4c +#define ADDR0_HIGH 0x50 +#define ADDR0_LOW 0x54 +#define TX_DMA_STA 0xb0 +#define TX_CUR_DESC 0xb4 +#define TX_CUR_BUF 0xb8 +#define RX_DMA_STA 0xc0 +#define RX_CUR_DESC 0xc4 + +/* CCM Register base */ +#define SUN8I_CCM_BASE 0x01c20000 + +/* CCM Register offset */ +#define CLK_GATING_REG0 0x60 +#define CLK_GATING_REG1 0x64 +#define CLK_GATING_REG2 0x68 +#define CLK_GATING_REG3 0x6c +#define CLK_GATING_REG4 0x70 + +/* System Control Register base */ +#define SUN8I_SCTL_BASE 0x01c00000 + +/* System Control Register's offset */ +#define VER_REG 0x24 +#define EMAC_CLK_REG 0x30 + +DECLARE_GLOBAL_DATA_PTR; + +struct emac_dma_desc { + u32 status; + u32 st; + void *buf_addr; + struct emac_dma_desc *next; +} __aligned(ARCH_DMA_MINALIGN); + +struct emac_eth_dev { + struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM]; + struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM]; + char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); + char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); + + u32 interface; + u32 phyaddr; + u32 link; + u32 speed; + u32 duplex; + u32 phy_configured; + u32 tx_currdescnum; + u32 rx_currdescnum; + u32 addr; + u32 tx_slot; + void *mac_reg; + void *sysctl_reg; + void *ccu_reg; + struct phy_device *phydev; + struct mii_dev *bus; +}; + +static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct emac_eth_dev *priv = bus->priv; + ulong start; + u32 miiaddr = 0; + int timeout = CONFIG_MDIO_TIMEOUT; + + miiaddr &= ~MDIO_CMD_MII_WRITE; + miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK; + miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) & + MDIO_CMD_MII_PHY_REG_ADDR_MASK; + + miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK; + + miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) & + MDIO_CMD_MII_PHY_ADDR_MASK; + + miiaddr |= MDIO_CMD_MII_BUSY; + + writel(miiaddr, priv->mac_reg + MII_CMD); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(priv->mac_reg + MII_CMD) & MDIO_CMD_MII_BUSY)) + return readl(priv->mac_reg + MII_DATA); + udelay(10); + }; + + return -1; +} + +static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct emac_eth_dev *priv = bus->priv; + ulong start; + u32 miiaddr = 0; + int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; + + miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK; + miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) & + MDIO_CMD_MII_PHY_REG_ADDR_MASK; + + miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK; + miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) & + MDIO_CMD_MII_PHY_ADDR_MASK; + + miiaddr |= MDIO_CMD_MII_WRITE; + miiaddr |= MDIO_CMD_MII_BUSY; + + writel(miiaddr, priv->mac_reg + MII_CMD); + writel(val, priv->mac_reg + MII_DATA); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(priv->mac_reg + MII_CMD) & MDIO_CMD_MII_BUSY)) { + ret = 0; + break; + } + udelay(10); + }; + + return ret; +} + +static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id) +{ + u32 macid_lo, macid_hi; + + macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + + (mac_id[3] << 24); + macid_hi = mac_id[4] + (mac_id[5] << 8); + + writel(macid_hi, priv->mac_reg + ADDR0_HIGH); + writel(macid_lo, priv->mac_reg + ADDR0_LOW); + + return 0; +} + +static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev) +{ + struct phy_device *phydev; + u32 val; + + /* H3 based SoC has an Internal PHY that needs + to be configured and powered up before use + */ + + val = readl(priv->sysctl_reg + EMAC_CLK_REG); + val = (val & ~REG_DEFAULT_MASK) | REG_DEFAULT_VALUE; + + val |= priv->phyaddr << REG_PHY_ADDR_SHIFT; + val &= ~REG_SHUTDOWN; + val |= REG_PHY_SELECT; + + setbits_le32((priv->sysctl_reg + EMAC_CLK_REG), (1 << 13)); + writel(val, (priv->sysctl_reg + EMAC_CLK_REG)); + + phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); + if (!phydev) + return -ENODEV; + + phy_connect_dev(phydev, dev); + + priv->phydev = phydev; + phy_config(phydev); + + return 0; +} + +static void sun8i_adjust_link(struct emac_eth_dev *priv, + struct phy_device *phydev) +{ + u32 v; + v = readl(priv->mac_reg + CTL0); + + if (phydev->duplex) + v |= BIT(0); + else + v &= ~BIT(0); + + v &= ~0x0C; + + switch (phydev->speed) { + case 1000: + break; + case 100: + v |= BIT(2); + v |= BIT(3); + break; + case 10: + v |= BIT(3); + break; + } + writel(v, priv->mac_reg + CTL0); +} + +static void rx_descs_init(struct emac_eth_dev *priv) +{ + struct emac_dma_desc *desc_table_p = &priv->rx_chain[0]; + char *rxbuffs = &priv->rxbuffer[0]; + struct emac_dma_desc *desc_p; + u32 idx; + + /* flush Rx buffers */ + flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs + + RX_TOTAL_BUFSIZE); + + for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { + desc_p = &desc_table_p[idx]; + desc_p->buf_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; + desc_p->next = &desc_table_p[idx + 1]; + desc_p->st |= CONFIG_ETH_BUFSIZE; + desc_p->status = BIT(31); + } + + /* Correcting the last pointer of the chain */ + desc_p->next = &desc_table_p[0]; + + flush_dcache_range((unsigned int)priv->rx_chain, + (unsigned int)priv->rx_chain + + sizeof(priv->rx_chain)); + + writel((ulong)&desc_table_p[0], (priv->mac_reg + RX_DMA_DESC)); + priv->rx_currdescnum = 0; +} + +static void tx_descs_init(struct emac_eth_dev *priv) +{ + struct emac_dma_desc *desc_table_p = &priv->tx_chain[0]; + char *txbuffs = &priv->txbuffer[0]; + struct emac_dma_desc *desc_p; + u32 idx; + + for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { + desc_p = &desc_table_p[idx]; + desc_p->buf_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE]; + desc_p->next = &desc_table_p[idx + 1]; + desc_p->status = (1 << 31); + desc_p->st = 0; + } + + /* Correcting the last pointer of the chain */ + desc_p->next = &desc_table_p[0]; + + /* Flush all Tx buffer descriptors */ + flush_dcache_range((unsigned int)priv->tx_chain, + (unsigned int)priv->tx_chain + + sizeof(priv->tx_chain)); + + writel((ulong)&desc_table_p[0], priv->mac_reg + TX_DMA_DESC); + priv->tx_currdescnum = 0; +} + +static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr) +{ + u32 reg, v; + int timeout = 100; + + reg = readl((priv->mac_reg + CTL1)); + + if (!(reg & 0x1)) { + /* Soft reset MAC */ + setbits_le32((priv->mac_reg + CTL1), 0x1 << 0); + do { + reg = readl(priv->mac_reg + CTL1); + } while ((reg & 0x01) != 0 && (--timeout)); + if (!timeout) { + printf("%s: Timeout\n", __func__); + return -1; + + } + + } + + /* Rewrite mac address after reset */ + _sun8i_write_hwaddr(priv, enetaddr); + + v = readl(priv->mac_reg + TX_CTL1); + /* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/ + v |= BIT(1); + writel(v, priv->mac_reg + TX_CTL1); + + v = readl(priv->mac_reg + RX_CTL1); + /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a + * complete frame has been written to RX DMA FIFO + */ + v |= BIT(1); + writel(v, priv->mac_reg + RX_CTL1); + + /* DMA */ + writel(8 << 24 , priv->mac_reg + CTL1); + + /* Initialize rx/tx descriptors */ + rx_descs_init(priv); + tx_descs_init(priv); + + /*Start up the PHY */ + if (phy_startup(priv->phydev)) { + printf("Could not initialize PHY %s\n", + priv->phydev->dev->name); + return -1; + } + + sun8i_adjust_link(priv, priv->phydev); + + /* Start RX DMA */ + v = readl(priv->mac_reg + RX_CTL1); + v |= BIT(30); + writel(v, priv->mac_reg + RX_CTL1); + /* Start TX DMA */ + v = readl(priv->mac_reg + TX_CTL1); + v |= BIT(30); + writel(v, priv->mac_reg + TX_CTL1); + + /* Enable RX/TX */ + setbits_le32(priv->mac_reg + RX_CTL0, 0x1 << 31); + setbits_le32(priv->mac_reg + TX_CTL0, 0x1 << 31); + + return 0; +} + +static void sun8i_emac_board_setup(struct emac_eth_dev *priv) +{ + priv->ccu_reg = (void *)SUN8I_CCU_BASE; + priv->sysctl_reg = (void *)SUN8I_SCTL_BASE; + int pin; + + /* Set clock gating for emac */ + setbits_le32((priv->ccu_reg + CLK_GATING_REG0), + 0x1 << AHB_GATE_OFFSET_GMAC); + + /* Set clock gating for ephy */ + setbits_le32((priv->ccu_reg + CLK_GATING_REG4), + 0x1 << AHB_GATE_OFFSET_EPHY); + + /* Set Tx clock source as MII with rate 25 MZ */ + clrbits_le32((priv->sysctl_reg + EMAC_CLK_REG), + SCTL_EMAC_TX_CLK_SRC_MII | + SCTL_EMAC_EPIT_MII | SCTL_EMAC_CLK_SEL); + + /* Set EMAC clock */ + setbits_le32((priv->ccu_reg + AHB2_CFG_REG), (0x1 << 1) | (0x1 << 0)); + + /* Deassert EPHY */ + setbits_le32((priv->ccu_reg + BUS_SOFT_RST_REG2), EPHY_RST); + + /* De-assert EMAC */ + setbits_le32((priv->ccu_reg + BUS_SOFT_RST_REG0), EMAC_RST); + + /* Pin mux setting for emac */ + for (pin = SUNXI_GPD(8); pin <= SUNXI_GPD(22); pin++) + sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC); +} + +static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp) +{ + u32 status, desc_num = priv->rx_currdescnum; + struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num]; + int length = -EAGAIN; + uint32_t desc_start = (uint32_t)desc_p; + uint32_t desc_end = desc_start + + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); + + uint32_t data_start = (uint32_t)desc_p->buf_addr; + uint32_t data_end; + + /* Invalidate entire buffer descriptor */ + invalidate_dcache_range(desc_start, desc_end); + + status = desc_p->status; + + /* Check for DMA own bit */ + if (!(status & BIT(31))) { + length = (desc_p->status >> 16) & 0x3FFF; + data_end = data_start + length; + /* Invalidate received data */ + invalidate_dcache_range(rounddown(data_start, + ARCH_DMA_MINALIGN), + roundup(data_end, + ARCH_DMA_MINALIGN)); + *packetp = desc_p->buf_addr; + } + return length; +} + +static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet, + int len) +{ + u32 v, desc_num = priv->tx_currdescnum; + struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num]; + uint32_t desc_start = (uint32_t)desc_p; + uint32_t desc_end = desc_start + + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); + + uint32_t data_start = (uint32_t)desc_p->buf_addr; + uint32_t data_end = data_start + + roundup(len, ARCH_DMA_MINALIGN); + + /* Invalidate entire buffer descriptor */ + invalidate_dcache_range(desc_start, desc_end); + + desc_p->st = len; + /* Mandatory undocumented bit */ + desc_p->st |= BIT(24); + + memcpy(desc_p->buf_addr, packet, len); + + /* Flush data to be sent */ + flush_dcache_range(data_start, data_end); + + /* frame end */ + desc_p->st |= BIT(30); + desc_p->st |= BIT(31); + + /*frame begin */ + desc_p->st |= BIT(29); + desc_p->status = BIT(31); + + /*Descriptors st and status field has changed, so FLUSH it */ + flush_dcache_range(desc_start, desc_end); + + /* Move to next Descriptor and wrap around */ + if (++desc_num >= CONFIG_TX_DESCR_NUM) + desc_num = 0; + priv->tx_currdescnum = desc_num; + + /* Start the DMA */ + v = readl(priv->mac_reg + TX_CTL1); + v |= BIT(31);/* mandatory */ + v |= BIT(30);/* mandatory */ + writel(v, priv->mac_reg + TX_CTL1); + + return 0; +} + +static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length) +{ + struct emac_eth_dev *priv = dev_get_priv(dev); + return _sun8i_emac_eth_send(priv, packet, length); +} + +static void sun8i_emac_eth_stop(struct udevice *dev) +{ + struct emac_eth_dev *priv = dev_get_priv(dev); + + /* Stop Rx/Tx transmitter */ + clrbits_le32(priv->mac_reg + RX_CTL0, BIT(31)); + clrbits_le32(priv->mac_reg + TX_CTL0, BIT(31)); + + /* Stop TX DMA */ + clrbits_le32(priv->mac_reg + TX_CTL1, BIT(30)); + + /* Disable Interrupt, This is required to leave + from U-boot and enter OS in proper Interrupt state */ + writel(0, priv->mac_reg + INT_EN); + + phy_shutdown(priv->phydev); +} + + +static int sun8i_emac_eth_start(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr); +} + +static int sun8i_mdio_init(const char *name, struct emac_eth_dev *priv) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = sun8i_mdio_read; + bus->write = sun8i_mdio_write; + snprintf(bus->name, sizeof(bus->name), name); + bus->priv = (void *)priv; + + return mdio_register(bus); +} + +static int sun8i_emac_eth_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct emac_eth_dev *priv = dev_get_priv(dev); + + priv->mac_reg = (void *)pdata->iobase; + sun8i_emac_board_setup(priv); + + sun8i_mdio_init(dev->name, priv); + priv->bus = miiphy_get_dev_by_name(dev->name); + + return sun8i_phy_init(priv, dev); +} + +static int sun8i_eth_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct emac_eth_dev *priv = dev_get_priv(dev); + return _sun8i_write_hwaddr(priv, pdata->enetaddr); +} + +static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct emac_eth_dev *priv = dev_get_priv(dev); + + return _sun8i_eth_recv(priv, packetp); +} + +static int _sun8i_free_pkt(struct emac_eth_dev *priv) +{ + u32 desc_num = priv->rx_currdescnum; + struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num]; + uint32_t desc_start = (uint32_t)desc_p; + uint32_t desc_end = desc_start + + roundup(sizeof(u32), ARCH_DMA_MINALIGN); + + /* Make the current descriptor valid again */ + desc_p->status |= BIT(31); + + /* Flush Status field of descriptor */ + flush_dcache_range(desc_start, desc_end); + + /* Move to next desc and wrap-around condition. */ + if (++desc_num >= CONFIG_RX_DESCR_NUM) + desc_num = 0; + priv->rx_currdescnum = desc_num; + + return 0; +} + +static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet, + int length) +{ + struct emac_eth_dev *priv = dev_get_priv(dev); + + return _sun8i_free_pkt(priv); +} + +static const struct eth_ops sun8i_emac_eth_ops = { + .start = sun8i_emac_eth_start, + .write_hwaddr = sun8i_eth_write_hwaddr, + .send = sun8i_emac_eth_send, + .recv = sun8i_emac_eth_recv, + .free_pkt = sun8i_eth_free_pkt, + .stop = sun8i_emac_eth_stop, +}; + +static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct emac_eth_dev *priv = dev_get_priv(dev); + const char *phy_mode; + int offset = 0; + pdata->iobase = dev_get_addr(dev); + + pdata->phy_interface = -1; + priv->phyaddr = -1; + + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, + "phy"); + if (offset > 0) + priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); + + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + + priv->interface = pdata->phy_interface; + + return 0; +} + +static const struct udevice_id sun8i_emac_eth_ids[] = { + { .compatible = "allwinner,sun8i-h3-emac" }, + { } +}; + +U_BOOT_DRIVER(eth_sun8i_emac) = { + .name = "eth_sun8i_emac", + .id = UCLASS_ETH, + .of_match = sun8i_emac_eth_ids, + .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata, + .probe = sun8i_emac_eth_probe, + .ops = &sun8i_emac_eth_ops, + .priv_auto_alloc_size = sizeof(struct emac_eth_dev), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; -- 1.7.9.5

5 4

[U-Boot] [PATCH 00/15] x86: Various updates and fixes
by Bin Meng 23 May '16

23 May '16

This series include various updates and fixes to x86 support. A major update is Intel Quark support, that MP table generation is enabled and working well with Linux kernel. This series is available at u-boot-x86/misc-working for testing. Bin Meng (15): acpi: Clean IASL generated intermediate files x86: crownbay: Disable boot stage support x86: Add some notes for MRC cache with Intel FSP x86: baytrail: Update to latest microcode x86: Use latest microcode for all BayTrail boards x86: galileo: Enable CPU driver x86: Don't touch IA32_APIC_BASE MSR on Intel Quark x86: Remove SMP limitation in lapic_setup() x86: Call lapic_setup() in interrupt_init() x86: quark: Assign a unique I/O APIC ID x86: broadwell: Correct I/O APIC ID x86: galileo: Enable MP table generation x86: kconfig: Add two options for SMBIOS manufacturer and product name x86: Switch to use SMBIOS Kconfig options when writing SMBIOS tables x86: galileo: Override SMBIOS product name Makefile | 1 + arch/x86/Kconfig | 23 + arch/x86/cpu/broadwell/pch.c | 3 +- arch/x86/cpu/interrupts.c | 8 +- arch/x86/cpu/ivybridge/model_206ax.c | 2 - arch/x86/cpu/lapic.c | 35 +- arch/x86/cpu/mp_init.c | 2 - arch/x86/cpu/quark/quark.c | 4 + arch/x86/dts/bayleybay.dts | 4 +- arch/x86/dts/conga-qeval20-qa3-e3845.dts | 4 +- arch/x86/dts/galileo.dts | 12 + arch/x86/dts/microcode/m0130673322.dtsi | 3284 ------------------------------ arch/x86/dts/microcode/m0130673325.dtsi | 3284 ++++++++++++++++++++++++++++++ arch/x86/dts/microcode/m0130679901.dtsi | 3284 ------------------------------ arch/x86/dts/microcode/m0130679907.dtsi | 3284 ++++++++++++++++++++++++++++++ arch/x86/dts/minnowmax.dts | 4 +- arch/x86/lib/smbios.c | 10 +- board/intel/galileo/Kconfig | 11 + configs/crownbay_defconfig | 3 - configs/galileo_defconfig | 3 + 20 files changed, 6657 insertions(+), 6608 deletions(-) delete mode 100644 arch/x86/dts/microcode/m0130673322.dtsi create mode 100644 arch/x86/dts/microcode/m0130673325.dtsi delete mode 100644 arch/x86/dts/microcode/m0130679901.dtsi create mode 100644 arch/x86/dts/microcode/m0130679907.dtsi -- 1.8.2.1

3 46

[U-Boot] [PATCH v2 00/18] x86: acpi: Support installation of Ubuntu/Windows and boot Windows
by Bin Meng 23 May '16

23 May '16

SeaBIOS can be loaded by U-Boot to aid the installation of Ubuntu and Windows to a SATA drive and boot from there. But till now this is broken. The installation either hangs forever or just crashes. This series fixed a bunch of issues that affect the installation of Ubuntu and Windows, and booting Windows. Testing was performed on MinnowMax by: - Install Ubuntu 14.04 and boot - Install Windows 8.1 and boot - Install Windows 10 and boot This series is available at u-boot-x86/acpi2-working. Changes in v2: - New patch to remove the unnecessary checksum calculation of DSDT - New patch to remove header length check when writing tables - New patch to enable SeaBIOS on all boards - New patch to add GPIO ASL description Bin Meng (18): x86: minnowmax: Adjust U-Boot environment address in SPI flash x86: Call board_final_cleanup() in last_stage_init() x86: Fix up PIRQ routing table checksum earlier x86: Compile coreboot_table.c only for SeaBIOS x86: Prepare configuration tables in dedicated high memory region x86: Unify reserve_arch() for all x86 boards x86: Reserve configuration tables in high memory x86: Use high_table_malloc() for tables passing to SeaBIOS x86: acpi: Switch to ACPI mode by ourselves instead of requested by OSPM x86: acpi: Remove the unnecessary checksum calculation of DSDT x86: acpi: Remove header length check when writing tables x86: doc: Update information about IGD with SeaBIOS x86: baytrail: Enable SeaBIOS on all boards x86: doc: Mention Ubuntu/Windows installation and boot support acpi: Quieten IASL output when 'make -s' is used x86: baytrail: Add internal UART ASL description x86: baytrail: Add GPIO ASL description x86: doc: Add porting hints for ACPI with Windows arch/x86/Kconfig | 14 ++++ arch/x86/cpu/baytrail/valleyview.c | 8 -- arch/x86/cpu/broadwell/sdram.c | 5 -- arch/x86/cpu/coreboot/coreboot.c | 20 +++-- arch/x86/cpu/cpu.c | 27 ++++++ arch/x86/cpu/irq.c | 4 + arch/x86/cpu/ivybridge/sdram.c | 5 -- arch/x86/cpu/quark/quark.c | 9 -- arch/x86/include/asm/acpi_table.h | 3 + arch/x86/include/asm/arch-baytrail/acpi/gpio.asl | 95 ++++++++++++++++++++++ .../include/asm/arch-baytrail/acpi/irqlinks.asl | 4 + arch/x86/include/asm/arch-baytrail/acpi/lpc.asl | 60 ++++++++++++++ .../include/asm/arch-baytrail/acpi/platform.asl | 3 + arch/x86/include/asm/coreboot_tables.h | 19 +++++ arch/x86/include/asm/global_data.h | 4 + arch/x86/lib/Makefile | 2 +- arch/x86/lib/acpi_table.c | 58 ++++++++----- arch/x86/lib/bootm.c | 9 -- arch/x86/lib/coreboot_table.c | 31 +++++++ arch/x86/lib/pirq_routing.c | 4 - arch/x86/lib/tables.c | 4 +- configs/bayleybay_defconfig | 1 + configs/conga-qeval20-qa3-e3845_defconfig | 1 + configs/minnowmax_defconfig | 1 + doc/README.x86 | 44 ++++++++-- include/configs/minnowmax.h | 2 +- scripts/Makefile.lib | 2 +- 27 files changed, 357 insertions(+), 82 deletions(-) create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/gpio.asl -- 1.8.2.1

2 56

[U-Boot] [PATCH] sunxi: Olimex A20 boards: Enable LDO3 and LDO4 regulators
by Stefan Mavrodiev 23 May '16

23 May '16

Sets LDO3 and LDO4 regulators at 2.8V. In the current config these are off. This causes kernel to hang during axp209 initialization. Signed-off-by: Stefan Mavrodiev <stefan.mavrodiev(a)gmail.com> --- configs/A20-OLinuXino_MICRO_defconfig | 2 ++ configs/A20-Olimex-SOM-EVB_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig index e952562..0dfa989 100644 --- a/configs/A20-OLinuXino_MICRO_defconfig +++ b/configs/A20-OLinuXino_MICRO_defconfig @@ -26,3 +26,5 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ETH_DESIGNWARE=y CONFIG_USB_EHCI_HCD=y +CONFIG_AXP_ALDO3_VOLT=2800 +CONFIG_AXP_ALDO4_VOLT=2800 diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig index cecf4c2..ed9bbb1 100644 --- a/configs/A20-Olimex-SOM-EVB_defconfig +++ b/configs/A20-Olimex-SOM-EVB_defconfig @@ -29,3 +29,5 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_RTL8211X_PHY_FORCE_MASTER=y CONFIG_ETH_DESIGNWARE=y CONFIG_USB_EHCI_HCD=y +CONFIG_AXP_ALDO3_VOLT=2800 +CONFIG_AXP_ALDO4_VOLT=2800 -- 2.8.1

1 0

[U-Boot] [PATCH v3 00/13] cleanup QEMU fw_cfg code
by Miao Yan 23 May '16

23 May '16

This patchset cleans the QEMU fw_cfg code: *) split qfw core and qfw command interface *) split x86 specific operations from qfw core *) move x86 ACPI generation code into qfw core as this can also be used by others like ARM64 *) various cleanups Changes in v2: *) make git format-patch detect renames *) add a patch to enable qfw for sandbox_defconfig *) address other trivial review comments Changes in v3: *) correct config option order in sandbox_defconfig *) squash patch v2 #8 and patch v2 #13 *) fix typos in commit message Miao Yan (13): x86: qemu: fix ACPI Kconfig options cmd: qfw: add API to iterate firmware list cmd: qfw: remove qemu_fwcfg_free_files() cmd: qfw: make fwcfg_present and fwcfg_dma_present public x86: qemu: split qfw command interface and qfw core x86: qemu: move x86 specific operations out of qfw core x86: qemu: add comment about qfw register endianness cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h] cmd: qfw: do not require default macros when building qfw command cmd: qfw: do not depend on x86 cmd: qfw: bring ACPI generation code into qfw core x86: qemu: rename qemu/acpi_table.c config: sandbox: enable qfw and cmd_qfw for testing arch/x86/Kconfig | 10 +- arch/x86/cpu/mp_init.c | 6 +- arch/x86/cpu/qemu/Makefile | 4 +- arch/x86/cpu/qemu/cpu.c | 2 +- arch/x86/cpu/qemu/e820.c | 43 ++++ arch/x86/cpu/qemu/qemu.c | 50 ++++- arch/x86/lib/Makefile | 2 +- cmd/Kconfig | 4 +- cmd/Makefile | 2 +- cmd/{qemu_fw_cfg.c => qfw.c} | 189 ++--------------- configs/qemu-x86_defconfig | 2 +- configs/sandbox_defconfig | 2 + drivers/misc/Kconfig | 6 + drivers/misc/Makefile | 1 + .../cpu/qemu/acpi_table.c => drivers/misc/qfw.c | 223 +++++++++++++++++---- include/{qemu_fw_cfg.h => qfw.h} | 28 ++- 16 files changed, 336 insertions(+), 238 deletions(-) create mode 100644 arch/x86/cpu/qemu/e820.c rename cmd/{qemu_fw_cfg.c => qfw.c} (54%) rename arch/x86/cpu/qemu/acpi_table.c => drivers/misc/qfw.c (57%) rename include/{qemu_fw_cfg.h => qfw.h} (84%) -- 1.9.1

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