February 2016 - U-Boot

[U-Boot] [PATCH v3 0/3] arm: at91/spl: add DDR3-SDRAM initialization support
by Wenyou Yang 02 Feb '16

02 Feb '16

This patch series is to add DDR3-SDRAM initialzation sequence support. The DDR3-SDRAM initialization sequence is implemented in accordance with the DDR3-SRAM/DDR3L-SDRAM initialization section described in the SAMA5D2 datasheet. Changes in v3: - fix unchanged board files (at91sam9m10ek, at91sam9n12ek, at91sam9x5ek, picosam9g45). - add 'base' argument to avoid specified base address. - collect Reviewed-by from Andreas. - add "base" argument for ddr2_decodtype_is_seq() to avoid specified base address. Changes in v2: - add Reviewed-by from Andreas. - remove comment accordingly after changing struct atmel_mpddr. - remove some registers which have different definitions on different SoCs to avoid confusion. - remove whitespace error. - rework commit log. - add Reviewed-by from Andreas. Wenyou Yang (3): arm: at91/spl: mpddrc: add struct atmel_mpddrc_config arm: at91/spl: mpddrc: add mpddrc DDR3-SDRAM initialization arm: at91/spl: mpddrc: use IP version to check configuration arch/arm/mach-at91/include/mach/atmel_mpddrc.h | 94 ++++++++++++++++++-- arch/arm/mach-at91/mpddrc.c | 107 +++++++++++++++++++++-- board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 4 +- board/atmel/at91sam9n12ek/at91sam9n12ek.c | 4 +- board/atmel/at91sam9x5ek/at91sam9x5ek.c | 4 +- board/atmel/sama5d3_xplained/sama5d3_xplained.c | 4 +- board/atmel/sama5d3xek/sama5d3xek.c | 4 +- board/atmel/sama5d4_xplained/sama5d4_xplained.c | 4 +- board/atmel/sama5d4ek/sama5d4ek.c | 4 +- board/mini-box/picosam9g45/picosam9g45.c | 4 +- board/siemens/corvus/board.c | 4 +- 11 files changed, 205 insertions(+), 32 deletions(-) -- 1.7.9.5

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[U-Boot] [PATCH 0/2] atmel_nand: add sama5d2 chip support, which support up to 32bit pmecc
by Josh Wu 02 Feb '16

02 Feb '16

This patch set will enable sama5d2 chip pmecc support, it includes: 1. update the pmecc registers and pmecc error location registers map. 2. add 32bit ecc support. Josh Wu (2): atmel_nand_ecc: update pmecc registers according to sama5d2 chip atmel_nand: Add 32 bit ecc support for sama5d2 chip drivers/mtd/nand/atmel_nand.c | 10 +++++++++- drivers/mtd/nand/atmel_nand_ecc.h | 36 ++++++++++++++++++++++++++++++++---- 2 files changed, 41 insertions(+), 5 deletions(-) -- 1.9.1

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[U-Boot] [RFC PATCH v1] dfu: introduce dfu_mtd support
by Heiko Schocher 02 Feb '16

02 Feb '16

With the new dfu_mtd layer, now dfu supports reading/writing to mtd partitions, found on mtd devices. With this approach it is also possible to read/write to concatenated mtd devices. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- This patch is based on patch: dfu: allow get_medium_size() to return bigger medium sizes than 2GiB Tested this driver on etamin module on the dxr2 board with a DDP nand with a size of 4GiB (2 CS -> 2 nand devices, concatenated with mtdconcat to a new mtd device) drivers/dfu/Makefile | 1 + drivers/dfu/dfu.c | 3 + drivers/dfu/dfu_mtd.c | 274 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/dfu.h | 23 +++++ 4 files changed, 301 insertions(+) create mode 100644 drivers/dfu/dfu_mtd.c diff --git a/drivers/dfu/Makefile b/drivers/dfu/Makefile index 61f2b71..c769d8c 100644 --- a/drivers/dfu/Makefile +++ b/drivers/dfu/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_USB_FUNCTION_DFU) += dfu.o obj-$(CONFIG_DFU_MMC) += dfu_mmc.o +obj-$(CONFIG_DFU_MTD) += dfu_mtd.o obj-$(CONFIG_DFU_NAND) += dfu_nand.o obj-$(CONFIG_DFU_RAM) += dfu_ram.o obj-$(CONFIG_DFU_SF) += dfu_sf.o diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 873dad5..bce619c 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -406,6 +406,9 @@ static int dfu_fill_entity(struct dfu_entity *dfu, char *s, int alt, if (strcmp(interface, "mmc") == 0) { if (dfu_fill_entity_mmc(dfu, devstr, s)) return -1; + } else if (strcmp(interface, "mtd") == 0) { + if (dfu_fill_entity_mtd(dfu, devstr, s)) + return -1; } else if (strcmp(interface, "nand") == 0) { if (dfu_fill_entity_nand(dfu, devstr, s)) return -1; diff --git a/drivers/dfu/dfu_mtd.c b/drivers/dfu/dfu_mtd.c new file mode 100644 index 0000000..de24f94 --- /dev/null +++ b/drivers/dfu/dfu_mtd.c @@ -0,0 +1,274 @@ +/* + * dfu_mtd.c -- DFU for MTD routines. + * + * Copyright (C) 2016 DENX Software Engineering GmbH <hs(a)denx.de> + * + * based on: + * Copyright (C) 2012-2013 Texas Instruments, Inc. + * + * Based on dfu_mmc.c which is: + * Copyright (C) 2012 Samsung Electronics + * author: Lukasz Majewski <l.majewski(a)samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <div64.h> +#include <dfu.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <jffs2/load_kernel.h> + +static int mtd_block_op(enum dfu_op op, struct dfu_entity *dfu, + u64 offset, void *buf, long long *len) +{ + loff_t start; + size_t retlen; + int length = *len; + int ret = 0; + struct mtd_info *mtd = dfu->data.mtd.mtd; + int bsize = mtd->erasesize; + int loops = length / bsize; + int rest = length % bsize; + char *curbuf; + int i = 0; + struct erase_info ei; + + /* if buf == NULL return total size of the area */ + if (buf == NULL) { + *len = dfu->data.mtd.part->size; + return 0; + } + + start = dfu->data.mtd.part->offset + dfu->bad_skip + offset; + if (start > dfu->data.mtd.part->offset + dfu->data.mtd.part->size) + return -EIO; + + if (offset % bsize) + return -EFAULT; + + if (rest) + loops++; + + curbuf = buf; + while (i < loops) { + ret = mtd_block_isbad(mtd, start); + if (ret == -EINVAL) + return ret; + + if (ret) { + /* we have a bad block */ + start += bsize; + dfu->bad_skip += bsize; + continue; + } + + if (op == DFU_OP_READ) { + ret = mtd_read(mtd, start, bsize, &retlen, + (u_char *)curbuf); + } else { + memset(&ei, 0, sizeof(struct erase_info)); + ei.mtd = mtd; + ei.addr = start; + ei.len = bsize; + ret = mtd_erase(mtd, &ei); + if (ret != 0) { + if (ret == -EIO) { + ret = mtd_block_isbad(mtd, start); + if (ret == -EINVAL) + return ret; + + if (ret) { + /* This is now a bad block */ + start += bsize; + dfu->bad_skip += bsize; + continue; + } + return -EIO; + } else { + /* else we have an error */ + return ret; + } + } + + /* now we are sure, we can write to the block */ + ret = mtd_write(mtd, start, bsize, &retlen, + (const u_char *)curbuf); + if (ret < 0) + return ret; + + if (retlen != bsize) + return -EIO; + } + curbuf += bsize; + start += bsize; + i++; + } + if (ret != 0) { + printf("%s: mtd %s call failed at %llx!\n", + __func__, op == DFU_OP_READ ? "read" : "write", + start); + return ret; + } + + dfu->data.mtd.start_erase = start; + return ret; +} + +static inline int mtd_block_write(struct dfu_entity *dfu, + u64 offset, void *buf, long long *len) +{ + return mtd_block_op(DFU_OP_WRITE, dfu, offset, buf, len); +} + +static inline int mtd_block_read(struct dfu_entity *dfu, + u64 offset, void *buf, long long *len) +{ + return mtd_block_op(DFU_OP_READ, dfu, offset, buf, len); +} + +static int dfu_write_medium_mtd(struct dfu_entity *dfu, + u64 offset, void *buf, long long *len) +{ + int ret = -1; + + switch (dfu->layout) { + case DFU_RAW_ADDR: + ret = mtd_block_write(dfu, offset, buf, len); + break; + default: + printf("%s: Layout (%s) not (yet) supported!\n", __func__, + dfu_get_layout(dfu->layout)); + } + + return ret; +} + +static int dfu_get_medium_size_mtd(struct dfu_entity *dfu, long long *size) +{ + if (!size) + return -EFAULT; + + *size = dfu->data.mtd.part->size; + return 0; +} + +static int dfu_read_medium_mtd(struct dfu_entity *dfu, u64 offset, void *buf, + long long *len) +{ + int ret = -1; + + switch (dfu->layout) { + case DFU_RAW_ADDR: + ret = mtd_block_read(dfu, offset, buf, len); + break; + default: + printf("%s: Layout (%s) not (yet) supported!\n", __func__, + dfu_get_layout(dfu->layout)); + } + + return ret; +} + +static int dfu_flush_medium_mtd(struct dfu_entity *dfu) +{ + int ret = 0; + + /* in case of ubi partition, erase rest of the partition */ + if (dfu->data.mtd.ubi) { + int ret; + struct erase_info ei; + int bsize = dfu->data.mtd.mtd->erasesize; + int loops; + int i = 0; + int len; + + memset(&ei, 0, sizeof(struct erase_info)); + ei.mtd = dfu->data.mtd.mtd; + ei.addr = dfu->data.mtd.start_erase; + ei.len = bsize; + len = dfu->data.mtd.part->size - + (ei.addr - dfu->data.mtd.part->offset); + loops = len / bsize; + + while (i < loops) { + ret = mtd_erase(dfu->data.mtd.mtd, &ei); + if (ret != 0) + printf("Failure erase: %d\n", ret); + i++; + ei.addr += bsize; + } + } + + return ret; +} + +static unsigned int dfu_polltimeout_mtd(struct dfu_entity *dfu) +{ + /* + * Currently, Poll Timeout != 0 is only needed on MTD + * ubi partition, as the not used sectors need an erase + */ + if (dfu->data.mtd.ubi) + return DFU_MANIFEST_POLL_TIMEOUT; + + return DFU_DEFAULT_POLL_TIMEOUT; +} + +int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char *s) +{ + char *st; + struct mtd_device *dev; + struct part_info *part; + + dfu->data.mtd.ubi = 0; + dfu->dev_type = DFU_DEV_MTD; + st = strsep(&s, " "); + if ((!strcmp(st, "mtddev")) || (!strcmp(st, "mtddevubi"))) { + char mtd_dev[16]; + u8 pnum; + + if (!strcmp(st, "mtddevubi")) + dfu->data.mtd.ubi = 1; + dfu->layout = DFU_RAW_ADDR; + /* + * Search the mtd device number where this partition + * is located + */ + if (mtdparts_init() != 0) { + printf("Error initializing mtdparts!\n"); + return -EINVAL; + } + + if (find_dev_and_part(dfu->name, &dev, &pnum, &part)) { + printf("Partition %s not found!\n", dfu->name); + return -ENODEV; + } + sprintf(mtd_dev, "%s%d", MTD_DEV_TYPE(dev->id->type), + dev->id->num); + dfu->data.mtd.mtd = get_mtd_device_nm(mtd_dev); + dfu->data.mtd.part = part; + if (IS_ERR(dfu->data.mtd.mtd)) { + printf("Partition %s not found on device %s!\n", + dfu->name, mtd_dev); + return -ENODEV; + } + } else { + printf("%s: Memory layout (%s) not supported!\n", __func__, st); + return -ENXIO; + } + + dfu->get_medium_size = dfu_get_medium_size_mtd; + dfu->read_medium = dfu_read_medium_mtd; + dfu->write_medium = dfu_write_medium_mtd; + dfu->flush_medium = dfu_flush_medium_mtd; + dfu->poll_timeout = dfu_polltimeout_mtd; + + /* initial state */ + dfu->inited = 0; + + return 0; +} diff --git a/include/dfu.h b/include/dfu.h index c327bb5..a0b111c 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -23,6 +23,7 @@ enum dfu_device_type { DFU_DEV_NAND, DFU_DEV_RAM, DFU_DEV_SF, + DFU_DEV_MTD, }; enum dfu_layout { @@ -67,6 +68,16 @@ struct nand_internal_data { unsigned int ubi; }; +struct mtd_internal_data { + struct mtd_info *mtd; + struct part_info *part; + + size_t len; + /* for MTD/ubi use */ + unsigned int ubi; + loff_t start_erase; +}; + struct ram_internal_data { void *start; unsigned int size; @@ -108,6 +119,7 @@ struct dfu_entity { struct nand_internal_data nand; struct ram_internal_data ram; struct sf_internal_data sf; + struct mtd_internal_data mtd; } data; int (*get_medium_size)(struct dfu_entity *dfu, long long *size); @@ -189,6 +201,17 @@ static inline int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr, } #endif +#ifdef CONFIG_DFU_MTD +extern int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char *s); +#else +static inline int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, + char *s) +{ + puts("MTD support not available!\n"); + return -1; +} +#endif + #ifdef CONFIG_DFU_NAND extern int dfu_fill_entity_nand(struct dfu_entity *dfu, char *devstr, char *s); #else -- 2.5.0

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[U-Boot] [PATCH] spl: define BOOT_DEVICE_USB
by Masahiro Yamada 02 Feb '16

02 Feb '16

This macro is referenced from common/spl/spl.c Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arm/include/asm/spl.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 5c5d33f..19c38f4 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -24,6 +24,7 @@ enum { BOOT_DEVICE_NOR, BOOT_DEVICE_UART, BOOT_DEVICE_SPI, + BOOT_DEVICE_USB, BOOT_DEVICE_SATA, BOOT_DEVICE_I2C, BOOT_DEVICE_BOARD, -- 1.9.1

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[U-Boot] [PATCH] patman: fix series-notes handling for buildman
by Albert ARIBAUD 02 Feb '16

02 Feb '16

A patman series with a 'Series-notes' section causes buildman to crash with: self.series.notes += self.section TypeError: cannot concatenate 'str' and 'list' objects Fix by initializing series.notes as a one-element array rathen than a scalar. Signed-off-by: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- tools/patman/series.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/patman/series.py b/tools/patman/series.py index 3399f2c..e8aad59 100644 --- a/tools/patman/series.py +++ b/tools/patman/series.py @@ -69,7 +69,7 @@ class Series(dict): # Otherwise just set the value elif name in valid_series: - self[name] = value + self[name] = [value] else: raise ValueError("In %s: line '%s': Unknown 'Series-%s': valid " "options are %s" % (commit.hash, line, name, -- 2.5.0

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[U-Boot] [RESEND PATCH v3 0/5] ARM: at91: improve peripheral and system clock handle functions
by Wenyou Yang 02 Feb '16

02 Feb '16

To reduce the duplicated code, rework the peripheral's and system's clock handle functions, use these functions to replace the clock handle code. Changes in v3: - fix incorrectly used the indicator '&' to achieve the variable pointer of pmc->pcer and pmc->pcdr. Changes in v2: - fix checkpatch warning. Wenyou Yang (5): ARM: at91: asm/at91_pmc.h: fix trival register offset ARM: at91: clock: add a new file to handle clock ARM: cpu: at91: clean up peripheral clock code board: atmel: clean up peripheral clock code drivers: at91: clean up peripheral clock code arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/arm920t/at91rm9200_devices.c | 13 +--- arch/arm/mach-at91/arm920t/timer.c | 4 +- arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c | 36 +++------- arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c | 28 ++------ arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c | 37 +++------- .../mach-at91/arm926ejs/at91sam9m10g45_devices.c | 33 +++------ arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c | 40 +++-------- arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c | 28 ++------ arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c | 38 +++-------- arch/arm/mach-at91/arm926ejs/clock.c | 7 -- arch/arm/mach-at91/arm926ejs/cpu.c | 1 - arch/arm/mach-at91/arm926ejs/timer.c | 5 +- arch/arm/mach-at91/armv7/clock.c | 26 ------- arch/arm/mach-at91/armv7/cpu.c | 1 - arch/arm/mach-at91/armv7/timer.c | 1 - arch/arm/mach-at91/clock.c | 72 ++++++++++++++++++++ arch/arm/mach-at91/include/mach/at91_pmc.h | 8 +-- arch/arm/mach-at91/include/mach/clk.h | 2 + arch/arm/mach-at91/phy.c | 1 - arch/arm/mach-at91/sdram.c | 1 - board/atmel/at91rm9200ek/at91rm9200ek.c | 1 - board/atmel/at91rm9200ek/led.c | 5 +- board/atmel/at91sam9260ek/at91sam9260ek.c | 15 ++-- board/atmel/at91sam9261ek/at91sam9261ek.c | 8 +-- board/atmel/at91sam9261ek/led.c | 6 +- board/atmel/at91sam9263ek/at91sam9263ek.c | 23 ++----- board/atmel/at91sam9263ek/led.c | 9 +-- board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 20 ++---- board/atmel/at91sam9m10g45ek/led.c | 7 +- board/atmel/at91sam9n12ek/at91sam9n12ek.c | 6 +- board/atmel/at91sam9rlek/at91sam9rlek.c | 18 ++--- board/atmel/at91sam9rlek/led.c | 7 +- board/atmel/at91sam9x5ek/at91sam9x5ek.c | 10 +-- board/atmel/sama5d2_xplained/sama5d2_xplained.c | 1 - board/atmel/sama5d3_xplained/sama5d3_xplained.c | 5 +- board/atmel/sama5d3xek/sama5d3xek.c | 5 +- board/atmel/sama5d4_xplained/sama5d4_xplained.c | 5 +- board/atmel/sama5d4ek/sama5d4ek.c | 5 +- board/bluewater/snapper9260/snapper9260.c | 15 ++-- board/calao/usb_a9263/usb_a9263.c | 11 ++- board/egnite/ethernut5/ethernut5.c | 20 +++--- board/esd/meesc/meesc.c | 15 ++-- board/mini-box/picosam9g45/led.c | 7 +- board/mini-box/picosam9g45/picosam9g45.c | 17 ++--- board/ronetix/pm9261/led.c | 7 +- board/ronetix/pm9261/pm9261.c | 22 ++---- board/ronetix/pm9263/led.c | 7 +- board/ronetix/pm9263/pm9263.c | 19 ++---- board/ronetix/pm9g45/pm9g45.c | 20 ++---- board/siemens/corvus/board.c | 6 +- board/siemens/smartweb/smartweb.c | 3 +- board/siemens/taurus/taurus.c | 3 +- drivers/net/at91_emac.c | 9 ++- drivers/usb/host/ehci-atmel.c | 8 --- drivers/usb/host/ohci-at91.c | 20 ++---- 56 files changed, 252 insertions(+), 496 deletions(-) create mode 100644 arch/arm/mach-at91/clock.c -- 1.7.9.5

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[U-Boot] [PATCH 1/2] pinctrl: imx: Introduce pinctrl driver for i.MX6
by Peng Fan 02 Feb '16

02 Feb '16

Introduce pinctrl for i.MX6 1. pinctrl-imx.c is for common usage. It's used by i.MX6/7. 2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry. 3. To the pinctrl_ops implementation, only set_state is implemented. To i.MX6/7, the pinctrl dts entry is as following: &iomuxc { pinctrl-names = "default"; pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 >; }; [.....] }; there is no property named function or groups. So pinctrl_generic_set_state can not be used here. 5. This driver is a simple implementation for i.mx iomux controller, only parse the fsl,pins property and write value to registers. 6. With DEBUG enabled, we can see log when "i2c bus 0": " set_state_simple op missing imx_pinctrl_set_state: i2c1grp mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x14c val 0x10 select_input: offset 0x5d8 val 0x1 write config: offset 0x3bc val 0x7f mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x148 val 0x10 select_input: offset 0x5d4 val 0x1 write config: offset 0x3b8 val 0x7f " this means imx6 pinctrl driver works as expected. Signed-off-by: Peng Fan <van.freenix(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)nxp.com> --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/nxp/Kconfig | 10 ++ drivers/pinctrl/nxp/Makefile | 2 + drivers/pinctrl/nxp/pinctrl-imx.c | 224 +++++++++++++++++++++++++++++++++++++ drivers/pinctrl/nxp/pinctrl-imx.h | 59 ++++++++++ drivers/pinctrl/nxp/pinctrl-imx6.c | 41 +++++++ 7 files changed, 338 insertions(+) create mode 100644 drivers/pinctrl/nxp/Kconfig create mode 100644 drivers/pinctrl/nxp/Makefile create mode 100644 drivers/pinctrl/nxp/pinctrl-imx.c create mode 100644 drivers/pinctrl/nxp/pinctrl-imx.h create mode 100644 drivers/pinctrl/nxp/pinctrl-imx6.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 57e6142..9fd8f62 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -133,6 +133,7 @@ config PINCTRL_SANDBOX endif +source "drivers/pinctrl/nxp/Kconfig" source "drivers/pinctrl/uniphier/Kconfig" endmenu diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 70d25dc..dcd20bf 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -5,6 +5,7 @@ obj-y += pinctrl-uclass.o obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o +obj-y += nxp/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig new file mode 100644 index 0000000..2032588 --- /dev/null +++ b/drivers/pinctrl/nxp/Kconfig @@ -0,0 +1,10 @@ +config PINCTRL_IMX + bool + +config PINCTRL_IMX6 + bool "IMX6 pinctrl driver" + depends on ARCH_MX6 + select DEVRES + select PINCTRL_IMX + help + Say Y here to enable the imx6ul pinctrl driver diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile new file mode 100644 index 0000000..7fd9850 --- /dev/null +++ b/drivers/pinctrl/nxp/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o +obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c new file mode 100644 index 0000000..09ffb1b --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx.c @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2016 Peng Fan <van.freenix(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mapmem.h> +#include <linux/io.h> +#include <linux/err.h> +#include <dm/device.h> +#include <dm/pinctrl.h> + +#include "pinctrl-imx.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) +{ + struct imx_pinctrl_priv *priv = dev_get_priv(dev); + struct imx_pinctrl_soc_info *info = priv->info; + int node = config->of_offset; + const struct fdt_property *prop; + unsigned int *pin_data; + int npins, size, pin_size; + int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val; + int i, j = 0; + + dev_dbg(dev, "%s: %s\n", __func__, config->name); + + if (info->flags & SHARE_MUX_CONF_REG) + pin_size = SHARE_FSL_PIN_SIZE; + else + pin_size = FSL_PIN_SIZE; + + prop = fdt_get_property(gd->fdt_blob, node, "fsl,pins", &size); + if (!prop) { + dev_err(dev, "No fsl,pins property in node %s\n", config->name); + return -EINVAL; + } + + if (!size || size % pin_size) { + dev_err(dev, "Invalid fsl,pins property in node %s\n", + config->name); + return -EINVAL; + } + + npins = size / pin_size; + pin_data = (unsigned int *)prop->data; + + for (i = 0; i < npins; i++) { + mux_reg = fdt32_to_cpu(pin_data[j++]); + + if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) + mux_reg = -1; + + if (info->flags & SHARE_MUX_CONF_REG) { + conf_reg = mux_reg; + } else { + conf_reg = fdt32_to_cpu(pin_data[j++]); + if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg) + conf_reg = -1; + } + + if ((mux_reg == -1) || (conf_reg == -1)) { + dev_err(dev, "Error mux_reg or conf_reg\n"); + return -EINVAL; + } + + input_reg = fdt32_to_cpu(pin_data[j++]); + mux_mode = fdt32_to_cpu(pin_data[j++]); + input_val = fdt32_to_cpu(pin_data[j++]); + config_val = fdt32_to_cpu(pin_data[j++]); + + dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, input_reg 0x%x, " + "mux_mode 0x%x, input_val 0x%x, config_val 0x%x\n", + mux_reg, conf_reg, input_reg, mux_mode, input_val, + config_val); + + if (config_val & IMX_PAD_SION) + mux_mode |= IOMUXC_CONFIG_SION; + + config_val &= ~IMX_PAD_SION; + + /* Set Mux */ + if (info->flags & SHARE_MUX_CONF_REG) { + clrsetbits_le32(info->base + mux_reg, 0x7 << 20, + mux_mode << 20); + } else { + writel(mux_mode, info->base + mux_reg); + } + + dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", mux_reg, + mux_mode); + + /* + * Set select input + * + * If the select input value begins with 0xff, it's a quirky + * select input and the value should be interpreted as below. + * 31 23 15 7 0 + * | 0xff | shift | width | select | + * It's used to work around the problem that the select + * input for some pin is not implemented in the select + * input register but in some general purpose register. + * We encode the select input value, width and shift of + * the bit field into input_val cell of pin function ID + * in device tree, and then decode them here for setting + * up the select input bits in general purpose register. + */ + + if (input_val >> 24 == 0xff) { + u32 val = input_val; + u8 select = val & 0xff; + u8 width = (val >> 8) & 0xff; + u8 shift = (val >> 16) & 0xff; + u32 mask = ((1 << width) - 1) << shift; + /* + * The input_reg[i] here is actually some IOMUXC general + * purpose register, not regular select input register. + */ + val = readl(info->base + input_reg); + val &= ~mask; + val |= select << shift; + writel(val, info->base + input_reg); + } else if (input_reg) { + /* + * Regular select input register can never be at offset + * 0, and we only print register value for regular case. + */ + if (info->input_sel_base) + writel(input_val, info->input_sel_base + + input_reg); + else + writel(input_val, info->base + input_reg); + + dev_dbg(dev, "select_input: offset 0x%x val 0x%x\n", + input_reg, input_val); + } + + /* Set config */ + if (!(config_val & IMX_NO_PAD_CTL)) { + if (info->flags & SHARE_MUX_CONF_REG) { + clrsetbits_le32(info->base + conf_reg, 0xffff, + config_val); + } else { + writel(config_val, info->base + conf_reg); + } + + dev_dbg(dev, "write config: offset 0x%x val 0x%x\n", + conf_reg, config_val); + } + } + + return 0; +} + +const struct pinctrl_ops imx_pinctrl_ops = { + .set_state = imx_pinctrl_set_state, +}; + +int imx_pinctrl_probe(struct udevice *dev, + struct imx_pinctrl_soc_info *info) +{ + struct imx_pinctrl_priv *priv = dev_get_priv(dev); + int node = dev->of_offset, ret; + struct fdtdec_phandle_args arg; + fdt_addr_t addr; + fdt_size_t size; + + if (!info) { + dev_err(dev, "wrong pinctrl info\n"); + return -EINVAL; + } + + priv->dev = dev; + priv->info = info; + + addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size); + + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + info->base = map_sysmem(addr, size); + if (!info->base) + return -ENOMEM; + priv->info = info; + + if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) { + ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, + node, "fsl,input-sel", + NULL, 0, 0, &arg); + if (ret) { + dev_err(dev, "iomuxc fsl,input-sel property not found\n"); + return -EINVAL; + } + + addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg", + &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + info->input_sel_base = map_sysmem(addr, size); + if (!info->input_sel_base) + return -ENOMEM; + } + + dev_info(dev, "initialized IMX pinctrl driver\n"); + + return 0; +} + +int imx_pinctrl_remove(struct udevice *dev) +{ + struct imx_pinctrl_priv *priv = dev_get_priv(dev); + struct imx_pinctrl_soc_info *info = priv->info; + + if (info->input_sel_base) + unmap_sysmem(info->input_sel_base); + if (info->base) + unmap_sysmem(info->base); + + return 0; +} diff --git a/drivers/pinctrl/nxp/pinctrl-imx.h b/drivers/pinctrl/nxp/pinctrl-imx.h new file mode 100644 index 0000000..597c170 --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx.h @@ -0,0 +1,59 @@ +/* + * IMX pinmux core definitions + * + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. + * Copyright (C) 2012 Linaro Ltd. + * + * Author: Dong Aisheng <dong.aisheng(a)linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DRIVERS_PINCTRL_IMX_H +#define __DRIVERS_PINCTRL_IMX_H + +/** + * @base: the address to the controller in virtual memory + * @input_sel_base: the address of the select input in virtual memory. + * @flags: flags specific for each soc + */ +struct imx_pinctrl_soc_info { + void __iomem *base; + void __iomem *input_sel_base; + unsigned int flags; +}; + +/** + * @dev: a pointer back to containing device + * @info: the soc info + */ +struct imx_pinctrl_priv { + struct udevice *dev; + struct imx_pinctrl_soc_info *info; +}; + +extern const struct pinctrl_ops imx_pinctrl_ops; + +/* The bits in CONFIG cell defined in binding doc*/ +#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ +#define IMX_PAD_SION 0x40000000 /* set SION */ + +/* + * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and + * 1 u32 CONFIG, so 24 types in total for each pin. + */ +#define FSL_PIN_SIZE 24 +#define SHARE_FSL_PIN_SIZE 20 + +#define SHARE_MUX_CONF_REG 0x1 +#define ZERO_OFFSET_VALID 0x2 + +#define IOMUXC_CONFIG_SION (0x1 << 4) + +int imx_pinctrl_probe(struct udevice *dev, struct imx_pinctrl_soc_info *info); + +int imx_pinctrl_remove(struct udevice *dev); +#endif /* __DRIVERS_PINCTRL_IMX_H */ diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c b/drivers/pinctrl/nxp/pinctrl-imx6.c new file mode 100644 index 0000000..24f139e --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx6.c @@ -0,0 +1,41 @@ + +/* + * Copyright (C) 2016 Peng Fan <van.freenix(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dm/device.h> +#include <dm/pinctrl.h> + +#include "pinctrl-imx.h" + +static struct imx_pinctrl_soc_info imx6_pinctrl_soc_info; + +static int imx6_pinctrl_probe(struct udevice *dev) +{ + struct imx_pinctrl_soc_info *info = + (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); + + return imx_pinctrl_probe(dev, info); +} + +static const struct udevice_id imx6_pinctrl_match[] = { + { .compatible = "fsl,imx6q-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, + { .compatible = "fsl,imx6dl-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, + { .compatible = "fsl,imx6sl-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, + { .compatible = "fsl,imx6sx-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, + { .compatible = "fsl,imx6ul-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(imx6_pinctrl) = { + .name = "imx6-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(imx6_pinctrl_match), + .probe = imx6_pinctrl_probe, + .remove = imx_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), + .ops = &imx_pinctrl_ops, + .flags = DM_FLAG_PRE_RELOC, +}; -- 2.6.2

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[U-Boot] [PATCH] fdt: __of_translate_address(): check parent's 'ranges' before translate
by Przemyslaw Marczak 02 Feb '16

02 Feb '16

The present implementation of __of_translate_address() taken from the Linux, is designed for translate bus/child address mappings by using 'ranges' property - and it doesn't allow for checking an address for a device's node with zero size-cells. The 'size-cells > 0' is required for bus/child address mapping, but is not required for non-memory mapped address, e.g.: I2C chip. Then when we need only raw 'reg' property's value. Since the I2C device address goes to a single-cell reg property, support for that case is welcome, but currently calling dev_get_addr() for I2C device will return 'FDT_ADDR_T_NONE', and print the warning: warning: __of_translate_address: Bad cell count for 'some-dev' The fix: The proper result by this commit, is achieved by skipping the condition check: 'size-cells > 0', when the parent doesn't provide the 'ranges' property and allows to return 1:1 address translation, if caller want's just the reg property's value. No additional argument is needed, the 'ranges' property existence decides, what type of translation is done when calling dev_get_addr(). And this should be, what the compatible driver expects. Now, by this commit the function __of_translate_address() can be used for the both reg property use-cases: Case 1: (ranges) ---------------- some-bus { address-cells = <1>; size-cells = <1>; ranges = <0x0 0x10000000 0x1000>; reg = <0x10000000 0x1000>; child1 { reg = <0xa00 0x100>; }; child2 { reg = <0xb00 0x100>; }; }; Return values (CONFIG_OF_TRANSLATE=y): - dev_get_addr(some-bus) - retrurns: 0x10000000 - correct - dev_get_addr(child1) - retrurns: 0x10000a00 - correct - dev_get_addr(child2) - retrurns: 0x10000b00 - correct This works as previous - this commit have no impact on this case. Case 2: (no ranges - e.g. I2C bus childs) - fixed ------------------------------------------------- I2C-bus { address-cells = <1>; size-cells = <0>; reg = <0x10000000>; chip1 { reg = <0xa00>; }; chip2 { reg = <0xb00>; }; }; Return values (CONFIG_OF_TRANSLATE=y): - dev_get_addr(I2C-bus) - retrurns: 0x10000000 - correct - dev_get_addr(chip1) - retrurns: 0xa00 - correct - dev_get_addr(chip2) - retrurns: 0xb00 - correct This is fixed, since the previously returned value for chip1 and chip2 was: 0xffffffff, which means: 'FDT_ADDR_T_NONE'. Signed-off-by: Przemyslaw Marczak <p.marczak(a)samsung.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Stephen Warren <swarren(a)nvidia.com> Cc: Stephen Warren <swarren(a)wwwdotorg.org> --- common/fdt_support.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index 66464db..1f472ca 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -952,8 +952,9 @@ void fdt_del_node_and_alias(void *blob, const char *alias) /* Max address size we deal with */ #define OF_MAX_ADDR_CELLS 4 #define OF_BAD_ADDR FDT_ADDR_T_NONE -#define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \ - (ns) > 0) +#define OF_CHECK_COUNTS(na, ns, skip_ns) \ + ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \ + (skip_ns || (ns) > 0)) /* Debug utility */ #ifdef DEBUG @@ -1104,11 +1105,12 @@ static int of_translate_one(void * blob, int parent, struct of_bus *bus, static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in_addr, const char *rprop) { - int parent; - struct of_bus *bus, *pbus; + const fdt32_t *pranges; fdt32_t addr[OF_MAX_ADDR_CELLS]; - int na, ns, pna, pns; + int na, ns, pna, pns, parent; + struct of_bus *bus, *pbus; u64 result = OF_BAD_ADDR; + bool skip_ns_check; debug("OF: ** translation for device %s **\n", fdt_get_name(blob, node_offset, NULL)); @@ -1119,9 +1121,16 @@ static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in goto bail; bus = &of_busses[0]; - /* Cound address cells & copy address locally */ + /* Chek 'ns' only if parent provides 'ranges' property */ + pranges = fdt_getprop(blob, parent, rprop, NULL); + if (pranges) + skip_ns_check = false; + else + skip_ns_check = true; + + /* Count address cells & copy address locally */ bus->count_cells(blob, parent, &na, &ns); - if (!OF_CHECK_COUNTS(na, ns)) { + if (!OF_CHECK_COUNTS(na, ns, skip_ns_check)) { printf("%s: Bad cell count for %s\n", __FUNCTION__, fdt_get_name(blob, node_offset, NULL)); goto bail; @@ -1148,7 +1157,7 @@ static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in /* Get new parent bus and counts */ pbus = &of_busses[0]; pbus->count_cells(blob, parent, &pna, &pns); - if (!OF_CHECK_COUNTS(pna, pns)) { + if (!OF_CHECK_COUNTS(pna, pns, skip_ns_check)) { printf("%s: Bad cell count for %s\n", __FUNCTION__, fdt_get_name(blob, node_offset, NULL)); break; -- 1.9.1

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[U-Boot] UBI attach issues
by Andy Ng 02 Feb '16

02 Feb '16

Dear u-boot team, Occasionally, I get corrupted rootfs if the system power goes away while u-boot is attaching the root file system in order to fetch the kernel. I am using imx6 Solo and u-boot 2013-10. Is there any way to stop uboot messing up the file system while making attachment of UBI? Does the latest u-boot provides a better way to protect the ubi file system during attachment. Any advice or guidance will be very much appreciated. Andy

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[U-Boot] [PATCH v1 0/2] Add back P2020DS
by York Sun 02 Feb '16

02 Feb '16

Recently Freescale (now NXP) received order to make more P2020DS. It's better have to U-Boot support than digging out old releases. Changes in v1: Add back P2020DS, using generic board structure. Initial patch to adjust DDR speed tables. York Sun (2): Revert "powerpc: mpc85xx: remove P2020DS board support" powerpc: p2020ds: Update DDR speed tables arch/powerpc/cpu/mpc85xx/Kconfig | 4 + board/freescale/p2020ds/Kconfig | 12 + board/freescale/p2020ds/MAINTAINERS | 10 + board/freescale/p2020ds/Makefile | 12 + board/freescale/p2020ds/ddr.c | 151 +++++++ board/freescale/p2020ds/law.c | 20 + board/freescale/p2020ds/p2020ds.c | 261 ++++++++++++ board/freescale/p2020ds/tlb.c | 91 +++++ configs/P2020DS_36BIT_defconfig | 9 + configs/P2020DS_DDR2_defconfig | 9 + configs/P2020DS_SDCARD_defconfig | 9 + configs/P2020DS_SPIFLASH_defconfig | 9 + configs/P2020DS_defconfig | 8 + doc/README.scrapyard | 1 - include/configs/P2020DS.h | 755 +++++++++++++++++++++++++++++++++++ 15 files changed, 1360 insertions(+), 1 deletion(-) create mode 100644 board/freescale/p2020ds/Kconfig create mode 100644 board/freescale/p2020ds/MAINTAINERS create mode 100644 board/freescale/p2020ds/Makefile create mode 100644 board/freescale/p2020ds/ddr.c create mode 100644 board/freescale/p2020ds/law.c create mode 100644 board/freescale/p2020ds/p2020ds.c create mode 100644 board/freescale/p2020ds/tlb.c create mode 100644 configs/P2020DS_36BIT_defconfig create mode 100644 configs/P2020DS_DDR2_defconfig create mode 100644 configs/P2020DS_SDCARD_defconfig create mode 100644 configs/P2020DS_SPIFLASH_defconfig create mode 100644 configs/P2020DS_defconfig create mode 100644 include/configs/P2020DS.h -- 1.7.9.5

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