February 2016 - U-Boot

[U-Boot] [PATCH] test/py: make each unit test a pytest
by Stephen Warren 02 Feb '16

02 Feb '16

From: Stephen Warren <swarren(a)nvidia.com> A custom fixture named ut_subtest is implemented which is parametrized with the names of all unit tests that the U-Boot binary supports. This causes each U-Boot unit test to be exposes as a separate pytest. In turn, this allows more fine-grained pass/fail counts and test selection, e.g.: test.py --bd sandbox -k ut_dm_usb ... will run about 8 tests at present. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- This depends on at least my recently sent "test/py: run C-based unit tests". test/py/conftest.py | 105 ++++++++++++++++++++++++++++++++++++----------- test/py/tests/test_ut.py | 14 +++---- 2 files changed, 86 insertions(+), 33 deletions(-) diff --git a/test/py/conftest.py b/test/py/conftest.py index 3e162cafcc4a..05491a2453c0 100644 --- a/test/py/conftest.py +++ b/test/py/conftest.py @@ -21,7 +21,9 @@ import pexpect import pytest from _pytest.runner import runtestprotocol import ConfigParser +import re import StringIO +import subprocess import sys # Globals: The HTML log file, and the connection to the U-Boot console. @@ -189,8 +191,43 @@ def pytest_configure(config): import u_boot_console_exec_attach console = u_boot_console_exec_attach.ConsoleExecAttach(log, ubconfig) -def pytest_generate_tests(metafunc): - """pytest hook: parameterize test functions based on custom rules. +re_ut_test_list = re.compile(r'_u_boot_list_2_(dm|env)_test_2_\1_test_(.*)\s*$') +def generate_ut_subtest(metafunc, fixture_name): + """Provide parametrization for a ut_subtest fixture. + + Determines the set of unit tests built into a U-Boot binary by parsing the + list of symbols present in the U-Boot binary. Provides this information to + test functions by parameterizing their ut_subtest fixture parameter. + + Args: + metafunc: The pytest test function. + fixture_name: The fixture name to test. + + Returns: + Nothing. + """ + + # This does rely on an objdump binary, but that's quite likely to be + # present. This approach trivially takes care of any source or Makefile- + # level conditional compilation which may occur, and matches the test + # execution order of a plain "ut dm" command. A source-scanning approach + # would not do neither. This approach also doesn't require access to the + # U-Boot source tree when running tests. + + cmd = 'objdump -t "%s" | sort' % (console.config.build_dir + '/u-boot') + out = subprocess.check_output(cmd, shell=True) + vals = [] + for l in out.splitlines(): + m = re_ut_test_list.search(l) + if not m: + continue + vals.append(m.group(1) + ' ' + m.group(2)) + + ids = ['ut_' + s.replace(' ', '_') for s in vals] + metafunc.parametrize(fixture_name, vals, ids=ids) + +def generate_config(metafunc, fixture_name): + """Provide parametrization for {env,brd}__ fixtures. If a test function takes parameter(s) (fixture names) of the form brd__xxx or env__xxx, the brd and env configuration dictionaries are consulted to @@ -199,6 +236,7 @@ def pytest_generate_tests(metafunc): Args: metafunc: The pytest test function. + fixture_name: The fixture name to test. Returns: Nothing. @@ -208,30 +246,49 @@ def pytest_generate_tests(metafunc): 'brd': console.config.brd, 'env': console.config.env, } + parts = fixture_name.split('__') + if len(parts) < 2: + return + if parts[0] not in subconfigs: + return + subconfig = subconfigs[parts[0]] + vals = [] + val = subconfig.get(fixture_name, []) + # If that exact name is a key in the data source: + if val: + # ... use the dict value as a single parameter value. + vals = (val, ) + else: + # ... otherwise, see if there's a key that contains a list of + # values to use instead. + vals = subconfig.get(fixture_name+ 's', []) + def fixture_id(index, val): + try: + return val['fixture_id'] + except: + return fixture_name + str(index) + ids = [fixture_id(index, val) for (index, val) in enumerate(vals)] + metafunc.parametrize(fixture_name, vals, ids=ids) + +def pytest_generate_tests(metafunc): + """pytest hook: parameterize test functions based on custom rules. + + Check each test function parameter (fixture name) to see if it is one of + our custom names, and if so, provide the correct parametrization for that + parameter. + + Args: + metafunc: The pytest test function. + + Returns: + Nothing. + """ + for fn in metafunc.fixturenames: - parts = fn.split('__') - if len(parts) < 2: + if fn == 'ut_subtest': + generate_ut_subtest(metafunc, fn) continue - if parts[0] not in subconfigs: - continue - subconfig = subconfigs[parts[0]] - vals = [] - val = subconfig.get(fn, []) - # If that exact name is a key in the data source: - if val: - # ... use the dict value as a single parameter value. - vals = (val, ) - else: - # ... otherwise, see if there's a key that contains a list of - # values to use instead. - vals = subconfig.get(fn + 's', []) - def fixture_id(index, val): - try: - return val["fixture_id"] - except: - return fn + str(index) - ids = [fixture_id(index, val) for (index, val) in enumerate(vals)] - metafunc.parametrize(fn, vals, ids=ids) + generate_config(metafunc, fn) @pytest.fixture(scope='function') def u_boot_console(request): diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py index b033ca54d756..cd85b3ddc0ce 100644 --- a/test/py/tests/test_ut.py +++ b/test/py/tests/test_ut.py @@ -6,8 +6,8 @@ import os.path import pytest @pytest.mark.buildconfigspec('ut_dm') -def test_ut_dm(u_boot_console): - """Execute the "ut dm" command.""" +def test_ut_dm_init(u_boot_console): + """Initialize data for ut dm tests.""" fn = u_boot_console.config.source_dir + '/testflash.bin' if not os.path.exists(fn): @@ -16,14 +16,10 @@ def test_ut_dm(u_boot_console): with open(fn, 'wb') as fh: fh.write(data) - output = u_boot_console.run_command('ut dm') - assert output.endswith('Failures: 0') - -(a)pytest.mark.buildconfigspec('ut_env') -def test_ut_env(u_boot_console): - """Execute the "ut env" command.""" +def test_ut(u_boot_console, ut_subtest): + """Execute a "ut" subtest.""" - output = u_boot_console.run_command('ut env') + output = u_boot_console.run_command('ut ' + ut_subtest) assert output.endswith('Failures: 0') @pytest.mark.buildconfigspec('ut_time') -- 2.7.0

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[U-Boot] [PATCH] fsl_qspi: fix address mask issue
by Ye Li 02 Feb '16

02 Feb '16

The OFFSET_BITS_MASK should mask bit from 0-23. By using GENMASK(24, 0), when using the fast read common (0xb), a invalid sf_addr 0x1000000 is produced by swab32(txbuf) & OFFSET_BITS_MASK. Signed-off-by: Ye Li <ye.li(a)nxp.com> --- drivers/spi/fsl_qspi.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index feec3e8..542b6cf 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; #define TX_BUFFER_SIZE 0x40 #endif -#define OFFSET_BITS_MASK GENMASK(24, 0) +#define OFFSET_BITS_MASK GENMASK(23, 0) #define FLASH_STATUS_WEL 0x02 -- 1.7.4.1

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[U-Boot] [PATCHv2 0/8] Migrate NXP/Freescale Vybrid based boards to support pure DT
by Bhuvanchandra DV 02 Feb '16

02 Feb '16

Changes since V1: - Update the license string in device tree's. - Update all lpuart's uart nodes in device tree. - Dropped *_dtb_defconfig and updated the default defconfig's with DT support. - Reordered defconfig's using defconfig via savedefconfig. - Use one patch to update all Vybrid based board defconfig's. - Dropped vybrid_gpio driver legacy code. Thanks! Stefan for pointing this. - Dropped the legacy way of enabling GPIO, UART and SPI on NXP/Freescale Vybrid based board's. - Compile checked for vf610twr and pcm052 since I don't have access to such hardware at my end. Reviewer's and tester's welcome! Bhuvanchandra DV (8): arm: vybrid: Enable lpuart support arm: colibri-vf: Enable serial support dm: lpuart: Drop the legacy code dm: vybrid_gpio: Drop legacy code arm: vybrid: Drop enabling gpio, uart and spi in legacy mode arm: vf610-twr: Add device tree files arm: pcm052: Add device tree files arm: vybrid: Update defconfig's arch/arm/dts/Makefile | 4 +- arch/arm/dts/pcm052.dts | 22 +++++++++ arch/arm/dts/vf-colibri.dtsi | 9 ++++ arch/arm/dts/vf.dtsi | 47 ++++++++++++++++-- arch/arm/dts/vf500-colibri.dts | 5 -- arch/arm/dts/vf610-colibri.dts | 5 -- arch/arm/dts/vf610-twr.dts | 22 +++++++++ configs/colibri_vf_defconfig | 8 ++++ configs/colibri_vf_dtb_defconfig | 14 ------ configs/pcm052_defconfig | 7 +++ configs/vf610twr_defconfig | 7 +++ configs/vf610twr_nand_defconfig | 7 +++ drivers/gpio/vybrid_gpio.c | 18 ------- drivers/serial/serial_lpuart.c | 101 +-------------------------------------- include/configs/colibri_vf.h | 13 ----- include/configs/pcm052.h | 3 -- include/configs/vf610twr.h | 3 -- 17 files changed, 129 insertions(+), 166 deletions(-) create mode 100644 arch/arm/dts/pcm052.dts create mode 100644 arch/arm/dts/vf610-twr.dts delete mode 100644 configs/colibri_vf_dtb_defconfig -- 2.7.0

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[U-Boot] [PATCH] arm: socfpga: Fix booting from QSPI flash on socdk board.
by shengjiangwu 02 Feb '16

02 Feb '16

Added missing parameter 'u-boot,dm-pre-reloc' for qspi and flash0 in dts file arch/arm/dts/socfpga_cyclone5_socdk.dts to make it support booting from QSPI flash. Signed-off-by: shengjiangwu <shengjiangwu(a)icloud.com> Cc: Chin Liang See <clsee(a)altera.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Stefan Roese <sr(a)denx.de> --- arch/arm/dts/socfpga_cyclone5_socdk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index a202709..bc60419 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -83,9 +83,11 @@ }; &qspi { + u-boot,dm-pre-reloc; status = "okay"; flash0: n25q00@0 { + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "n25q00"; -- 1.7.9.5

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[U-Boot] [PATCH v7 5/7] mips: ath79: add spi driver
by Wills Wang 02 Feb '16

02 Feb '16

Reviewed-by: Thomas Chou <thomas(a)wytron.com.tw> Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v7: - Define spi_cs_activate/spi_cs_deactivate - Rename MHZ to ATH79_SPI_MHZ - Use clrsetbits_32 Changes in v6: - Add rrw_delay in ath79_spi_priv for more accurate timing - Remove ath79_spi_delay - Calculate delay in ath79_spi_set_speed Changes in v5: - remove ar933x_spi_platdata - Import document "spi-ath79.txt" from kernel - Add delay for bitbang operation Changes in v4: - Use get_bus_freq instead of hardcode in SPI driver Changes in v3: - Convert spi driver to driver model Changes in v2: - Add a compatible spi driver doc/device-tree-bindings/spi/spi-ath79.txt | 19 +++ drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/ath79_spi.c | 237 +++++++++++++++++++++++++++++ 4 files changed, 265 insertions(+) create mode 100644 doc/device-tree-bindings/spi/spi-ath79.txt create mode 100644 drivers/spi/ath79_spi.c diff --git a/doc/device-tree-bindings/spi/spi-ath79.txt b/doc/device-tree-bindings/spi/spi-ath79.txt new file mode 100644 index 0000000..3fd9d67 --- /dev/null +++ b/doc/device-tree-bindings/spi/spi-ath79.txt @@ -0,0 +1,19 @@ +Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller + +Required properties: +- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback. +- reg: Base address and size of the controllers memory area +- #address-cells: <1>, as required by generic SPI binding. +- #size-cells: <0>, also as required by generic SPI binding. + +Child nodes as per the generic SPI binding. + +Example: + + spi@1f000000 { + compatible = "qca,ar9132-spi", "qca,ar7100-spi"; + reg = <0x1f000000 0x10>; + + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 2cdb110..0ab2741 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -23,6 +23,14 @@ config ALTERA_SPI IP core. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config ATH79_SPI + bool "Atheros SPI driver" + help + Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used + to access SPI NOR flash and other SPI peripherals. This driver + uses driver model and requires a device tree binding to operate. + please refer to doc/device-tree-bindings/spi/spi-ath79.txt. + config CADENCE_QSPI bool "Cadence QSPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 3eca745..7fb2926 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -17,6 +17,7 @@ endif obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o +obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BFIN_SPI) += bfin_spi.o diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c new file mode 100644 index 0000000..568548f --- /dev/null +++ b/drivers/spi/ath79_spi.c @@ -0,0 +1,237 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spi.h> +#include <dm.h> +#include <div64.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> + +/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */ +#define ATH79_SPI_CLK_DIV(x) (((x) >> 1) - 1) +#define ATH79_SPI_RRW_DELAY_FACTOR 12000 +#define ATH79_SPI_MHZ (1000 * 1000) + +struct ath79_spi_priv { + void __iomem *regs; + u32 rrw_delay; +}; + +static inline u32 ath79_spi_read(struct udevice *bus, u32 offset) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + return readl(priv->regs + offset); +} + +static inline void ath79_spi_write(struct udevice *bus, + u32 val, u32 offset) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + writel(val, priv->regs + offset); +} + +static void spi_cs_activate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS); + ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC); +} + +static void spi_cs_deactivate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + + ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL, AR71XX_SPI_REG_IOC); + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS); +} + +static int ath79_spi_claim_bus(struct udevice *dev) +{ + return 0; +} + +static int ath79_spi_release_bus(struct udevice *dev) +{ + return 0; +} + +static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct ath79_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev); + u8 *rx = din; + const u8 *tx = dout; + u8 curbyte, curbitlen, restbits; + u32 bytes = bitlen / 8; + u32 out, in; + u64 tick; + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(dev); + + restbits = (bitlen % 8); + if (restbits) + bytes++; + + out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs)); + while (bytes > 0) { + bytes--; + curbyte = 0; + if (tx) + curbyte = *tx++; + + if (restbits && !bytes) { + curbitlen = restbits; + curbyte <<= 8 - restbits; + } else { + curbitlen = 8; + } + + for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) { + if (curbyte & 0x80) + out |= AR71XX_SPI_IOC_DO; + else + out &= ~(AR71XX_SPI_IOC_DO); + + ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC); + + /* delay for low level */ + if (priv->rrw_delay) { + tick = get_ticks() + priv->rrw_delay; + while (get_ticks() < tick) + /*NOP*/; + } + + ath79_spi_write(bus, out | AR71XX_SPI_IOC_CLK, + AR71XX_SPI_REG_IOC); + + /* delay for high level */ + if (priv->rrw_delay) { + tick = get_ticks() + priv->rrw_delay; + while (get_ticks() < tick) + /*NOP*/; + } + + curbyte <<= 1; + } + + if (!bytes) + ath79_spi_write(bus, out, AR71XX_SPI_REG_IOC); + + in = ath79_spi_read(bus, AR71XX_SPI_REG_RDS); + if (rx) { + if (restbits && !bytes) + *rx++ = (in << (8 - restbits)); + else + *rx++ = in; + } + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(dev); + + return 0; +} + + +static int ath79_spi_set_speed(struct udevice *bus, uint speed) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + u32 val, div = 0; + u64 time; + + if (speed) + div = get_bus_freq(0) / speed; + + if (div > 63) + div = 63; + + if (div < 5) + div = 5; + + /* calculate delay */ + time = get_tbclk(); + do_div(time, speed / 2); + val = get_bus_freq(0) / ATH79_SPI_MHZ; + val = ATH79_SPI_RRW_DELAY_FACTOR / val; + if (time > val) + priv->rrw_delay = time - val + 1; + else + priv->rrw_delay = 0; + + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS); + clrsetbits_32(priv->regs + AR71XX_SPI_REG_CTRL, + AR71XX_SPI_CTRL_DIV_MASK, ATH79_SPI_CLK_DIV(div)); + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS); + return 0; +} + +static int ath79_spi_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} + +static int ath79_spi_probe(struct udevice *bus) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + fdt_addr_t addr; + + addr = dev_get_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = map_physmem(addr, + AR71XX_SPI_SIZE, + MAP_NOCACHE); + + /* Init SPI Hardware, disable remap, set clock */ + ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS); + ath79_spi_write(bus, AR71XX_SPI_CTRL_RD | ATH79_SPI_CLK_DIV(8), + AR71XX_SPI_REG_CTRL); + ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS); + + return 0; +} + +static int ath79_cs_info(struct udevice *bus, uint cs, + struct spi_cs_info *info) +{ + /* Always allow activity on CS 0/1/2 */ + if (cs >= 3) + return -ENODEV; + + return 0; +} + +static const struct dm_spi_ops ath79_spi_ops = { + .claim_bus = ath79_spi_claim_bus, + .release_bus = ath79_spi_release_bus, + .xfer = ath79_spi_xfer, + .set_speed = ath79_spi_set_speed, + .set_mode = ath79_spi_set_mode, + .cs_info = ath79_cs_info, +}; + +static const struct udevice_id ath79_spi_ids[] = { + { .compatible = "qca,ar7100-spi" }, + {} +}; + +U_BOOT_DRIVER(ath79_spi) = { + .name = "ath79_spi", + .id = UCLASS_SPI, + .of_match = ath79_spi_ids, + .ops = &ath79_spi_ops, + .priv_auto_alloc_size = sizeof(struct ath79_spi_priv), + .probe = ath79_spi_probe, +}; -- 1.9.1

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[U-Boot] Please pull u-boot-fsl-qoriq master
by york sun 02 Feb '16

02 Feb '16

Tom, The following changes since commit 8cdae1dacde7dbe74d53a8ac1a05761a53c4f191: video: Correct 'tor' typo in comment (2016-01-30 10:58:47 +0100) are available in the git repository at: git://git.denx.de/u-boot-fsl-qoriq.git master for you to fetch changes up to 7711cc0a0648e215571b1d1768381963d92a1d97: arm8: ls2080: Move the core errata defines out of board specific file (2016-02-01 13:59:55 -0800) ---------------------------------------------------------------- Alison Wang (1): armv7: ls102xa: Increase the supported kernel size Ashish kumar (2): armv8: ls2080a: Implement workaround for core errata 829520, 833471 arm8: ls2080: Move the core errata defines out of board specific file Prabhakar Kushwaha (3): board: ls2085aqds: Update kernel_size env variable driver: net: fsl-mc: Memset dprc_cfg before configuring driver: net: fsl-mc: Update print to reflect correct string Qianyu Gong (1): armv8/ls1043aqds: fix DSPI/QSPI node in dts file arch/arm/cpu/armv8/start.S | 19 +++++++++ arch/arm/dts/fsl-ls1043a-qds.dtsi | 46 +++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 +++ drivers/net/fsl-mc/mc.c | 3 +- include/configs/ls1021aqds.h | 1 + include/configs/ls1021atwr.h | 1 + include/configs/ls2080a_common.h | 3 -- include/configs/ls2080aqds.h | 2 +- 8 files changed, 76 insertions(+), 5 deletions(-) Thanks. York

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[U-Boot] [PULL] u-boot-atmel/master -> u-boot/master
by Andreas Bießmann 02 Feb '16

02 Feb '16

Hi Tom, please pull these changes into u-boot/master ... eventually before tagging rc1 ;) Andreas The following changes since commit 9e4de7fd4acc8f99b6d383c711d21c0159849629: Merge branch 'master' of http://git.denx.de/u-boot-sunxi (2016-01-26 17:45:37 -0500) are available in the git repository at: git://git.denx.de/u-boot-atmel.git master for you to fetch changes up to 37dadbca0c8b9bff00f892fd87a978cbe0a98b3a: board: atmel: sama5d2_xplained: add SPL support (2016-02-02 11:49:13 +0100) ---------------------------------------------------------------- Gregory CLEMENT (2): mmc: atmel: Properly fix clock configuration net: macb: Not all the GEM are gigabit capable Josh Wu (5): atmel_nand: use nand ecc_{strength, step}_ds instead of our own function atmel_nand: add '\n' in the end of error message for better display atmel_nand: use the definition: PMECC_OOB_RESERVED_BYTES instead magic number atmel_nand_ecc: update pmecc registers according to sama5d2 chip atmel_nand: Add 32 bit ecc support for sama5d2 chip Wenyou Yang (4): arm: at91/spl: mpddrc: add struct atmel_mpddrc_config arm: at91/spl: mpddrc: add mpddrc DDR3-SDRAM initialization arm: at91/spl: mpddrc: use IP version to check configuration board: atmel: sama5d2_xplained: add SPL support arch/arm/mach-at91/Kconfig | 1 + arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/include/mach/atmel_mpddrc.h | 94 +++++++++++++++++++-- arch/arm/mach-at91/include/mach/sama5d2.h | 32 +++++++ arch/arm/mach-at91/mpddrc.c | 107 ++++++++++++++++++++++-- board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 4 +- board/atmel/at91sam9n12ek/at91sam9n12ek.c | 4 +- board/atmel/at91sam9x5ek/at91sam9x5ek.c | 4 +- board/atmel/sama5d2_xplained/sama5d2_xplained.c | 103 +++++++++++++++++++++++ board/atmel/sama5d3_xplained/sama5d3_xplained.c | 4 +- board/atmel/sama5d3xek/sama5d3xek.c | 4 +- board/atmel/sama5d4_xplained/sama5d4_xplained.c | 4 +- board/atmel/sama5d4ek/sama5d4ek.c | 4 +- board/mini-box/picosam9g45/picosam9g45.c | 4 +- board/siemens/corvus/board.c | 4 +- configs/sama5d2_xplained_mmc_defconfig | 1 + configs/sama5d2_xplained_spiflash_defconfig | 1 + drivers/mmc/gen_atmel_mci.c | 15 +++- drivers/mtd/nand/atmel_nand.c | 60 +++++-------- drivers/mtd/nand/atmel_nand_ecc.h | 36 +++++++- drivers/net/macb.c | 21 ++++- include/configs/sama5d2_xplained.h | 39 +++++++++ 22 files changed, 465 insertions(+), 82 deletions(-)

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[U-Boot] [PATCH 1/2] net: phy: micrel: add documentation for Micrel KSZ90x1 binding
by dinguyen＠opensource.altera.com 02 Feb '16

02 Feb '16

From: Dinh Nguyen <dinguyen(a)opensource.altera.com> Add the DTS documentation for the Micrel KSZ90x1 binding. The original document was from: [commit 4b405efbe12de28b26289282b431323d73992381 from the Linux kernel] This takes the original document and adds a clarification on how the skew values are represented in the code. References: Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014. http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014. http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf Signed-off-by: Dinh Nguyen <dinguyen(a)opensource.altera.com> --- doc/device-tree-bindings/net/micrel-ksz90x1.txt | 165 ++++++++++++++++++++++++ 1 file changed, 165 insertions(+) create mode 100644 doc/device-tree-bindings/net/micrel-ksz90x1.txt diff --git a/doc/device-tree-bindings/net/micrel-ksz90x1.txt b/doc/device-tree-bindings/net/micrel-ksz90x1.txt new file mode 100644 index 0000000..307f53f --- /dev/null +++ b/doc/device-tree-bindings/net/micrel-ksz90x1.txt @@ -0,0 +1,165 @@ +Micrel KSZ9021/KSZ9031 Gigabit Ethernet PHY + +Some boards require special tuning values, particularly when it comes to +clock delays. You can specify clock delay values by adding +micrel-specific properties to an Ethernet OF device node. + +Note that these settings are applied after any phy-specific fixup from +phy_fixup_list (see phy_init_hw() from drivers/net/phy/phy_device.c), +and therefore may overwrite them. + +KSZ9021: + + All skew control options are specified in picoseconds. The minimum + value is 0, the maximum value is 1800, and it is incremented by 120ps + steps. + + Optional properties: + + - rxc-skew-ps : Skew control of RXC pad + - rxdv-skew-ps : Skew control of RX CTL pad + - txc-skew-ps : Skew control of TXC pad + - txen-skew-ps : Skew control of TX CTL pad + - rxd0-skew-ps : Skew control of RX data 0 pad + - rxd1-skew-ps : Skew control of RX data 1 pad + - rxd2-skew-ps : Skew control of RX data 2 pad + - rxd3-skew-ps : Skew control of RX data 3 pad + - txd0-skew-ps : Skew control of TX data 0 pad + - txd1-skew-ps : Skew control of TX data 1 pad + - txd2-skew-ps : Skew control of TX data 2 pad + - txd3-skew-ps : Skew control of TX data 3 pad + +KSZ9031: + + All skew control options are specified in picoseconds. The minimum + value is 0, and the maximum is property-dependent. The increment + step is 60ps. + + The KSZ9031 hardware supports a range of skew values from negative to + positive, where the specific range is property dependent. All values + specified in the devicetree are offset by the minimum value so they + can be represented as positive integers in the devicetree since it's + difficult to represent a negative number in the devictree. + + The following 5-bit values table apply to rxc-skew-ps and txc-skew-ps. + + Pad Skew Value Delay (ps) Devicetree Value + ------------------------------------------------------ + 0_0000 -900ps 0 + 0_0001 -840ps 60 + 0_0010 -780ps 120 + 0_0011 -720ps 180 + 0_0100 -660ps 240 + 0_0101 -600ps 300 + 0_0110 -540ps 360 + 0_0111 -480ps 420 + 0_1000 -420ps 480 + 0_1001 -360ps 540 + 0_1010 -300ps 600 + 0_1011 -240ps 660 + 0_1100 -180ps 720 + 0_1101 -120ps 780 + 0_1110 -60ps 840 + 0_1111 0ps 900 + 1_0000 60ps 960 + 1_0001 120ps 1020 + 1_0010 180ps 1080 + 1_0011 240ps 1140 + 1_0100 300ps 1200 + 1_0101 360ps 1260 + 1_0110 420ps 1320 + 1_0111 480ps 1380 + 1_1000 540ps 1440 + 1_1001 600ps 1500 + 1_1010 660ps 1560 + 1_1011 720ps 1620 + 1_1100 780ps 1680 + 1_1101 840ps 1740 + 1_1110 900ps 1800 + 1_1111 960ps 1860 + + The following 4-bit values table apply to the txdX-skew-ps, rxdX-skew-ps + data pads, and the rxdv-skew-ps, txen-skew-ps control pads. + + Pad Skew Value Delay (ps) Devicetree Value + ------------------------------------------------------ + 0000 -420ps 0 + 0001 -360ps 60 + 0010 -300ps 120 + 0011 -240ps 180 + 0100 -180ps 240 + 0101 -120ps 300 + 0110 -60ps 360 + 0111 0ps 420 + 1000 60ps 480 + 1001 120ps 540 + 1010 180ps 600 + 1011 240ps 660 + 1100 300ps 720 + 1101 360ps 780 + 1110 420ps 840 + 1111 480ps 900 + + Optional properties: + + Maximum value of 1860: + + - rxc-skew-ps : Skew control of RX clock pad + - txc-skew-ps : Skew control of TX clock pad + + Maximum value of 900: + + - rxdv-skew-ps : Skew control of RX CTL pad + - txen-skew-ps : Skew control of TX CTL pad + - rxd0-skew-ps : Skew control of RX data 0 pad + - rxd1-skew-ps : Skew control of RX data 1 pad + - rxd2-skew-ps : Skew control of RX data 2 pad + - rxd3-skew-ps : Skew control of RX data 3 pad + - txd0-skew-ps : Skew control of TX data 0 pad + - txd1-skew-ps : Skew control of TX data 1 pad + - txd2-skew-ps : Skew control of TX data 2 pad + - txd3-skew-ps : Skew control of TX data 3 pad + +Examples: + + /* Attach to an Ethernet device with autodetected PHY */ + &enet { + rxc-skew-ps = <1800>; + rxdv-skew-ps = <0>; + txc-skew-ps = <1800>; + txen-skew-ps = <0>; + status = "okay"; + }; + + /* Attach to an explicitly-specified PHY */ + mdio { + phy0: ethernet-phy@0 { + rxc-skew-ps = <1800>; + rxdv-skew-ps = <0>; + txc-skew-ps = <1800>; + txen-skew-ps = <0>; + reg = <0>; + }; + }; + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + +References + + Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014. + http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf + + Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014. + http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf + +Notes: + + Note that a previous version of the Micrel ksz9021rl/rn Data Sheet + was missing extended register 106 (transmit data pad skews), and + incorrectly specified the ps per step as 200ps/step instead of + 120ps/step. The latest update to this document reflects the latest + revision of the Micrel specification even though usage in the kernel + still reflects that incorrect document. -- 2.6.2

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[U-Boot] [RFC PATCH v2] dfu: allow get_medium_size() to return bigger medium sizes than 2GiB
by Heiko Schocher 02 Feb '16

02 Feb '16

change the get_medium_size() function from - long (*get_medium_size)(struct dfu_entity *dfu); + int (*get_medium_size)(struct dfu_entity *dfu, long long *size); so it can return bigger medium sizes than 2GiB, and the return value is seperate from the size. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- I just have a DDP nand with a size of 4GiB, and the last mtd partition layout is: device nand2 <omap2-nand.0>, # parts = 9 #: name size offset mask_flags 0: spl 0x00080000 0x00000000 0 1: spl.backup1 0x00080000 0x00080000 0 2: spl.backup2 0x00080000 0x00100000 0 3: spl.backup3 0x00080000 0x00180000 0 4: u-boot 0x00780000 0x00200000 0 5: u-boot.env0 0x00200000 0x00980000 0 6: u-boot.env1 0x00200000 0x00b80000 0 7: mtdoops 0x00200000 0x00d80000 0 8: rootfs 0xff080000 0x00f80000 0 so the last partition is to big for returning the size in a long. - nand/mtd dfu modules tested only, please verify mmc, sf Changes in v2: - add comments from Luaksz: use long long instead u64 (also recommended from Joe) change b_left also into long long -> read_medium and write_medium needs also adaptions - add comments from Joe check if size is not NULL, before dereferencing it drivers/dfu/dfu.c | 12 ++++++------ drivers/dfu/dfu_mmc.c | 25 ++++++++++++++++--------- drivers/dfu/dfu_nand.c | 18 +++++++++++------- drivers/dfu/dfu_ram.c | 14 +++++++++----- drivers/dfu/dfu_sf.c | 19 +++++++++++++------ include/dfu.h | 10 +++++----- 6 files changed, 60 insertions(+), 38 deletions(-) diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 8f5915e..873dad5 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -134,7 +134,7 @@ static char *dfu_get_hash_algo(void) static int dfu_write_buffer_drain(struct dfu_entity *dfu) { - long w_size; + long long w_size; int ret; /* flush size? */ @@ -279,7 +279,7 @@ static int dfu_read_buffer_fill(struct dfu_entity *dfu, void *buf, int size) readn = 0; while (size > 0) { /* get chunk that can be read */ - chunk = min((long)size, dfu->b_left); + chunk = min((long long)size, dfu->b_left); /* consume */ if (chunk > 0) { memcpy(buf, dfu->i_buf, chunk); @@ -335,11 +335,11 @@ int dfu_read(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) if (dfu->i_buf_start == NULL) return -ENOMEM; - dfu->r_left = dfu->get_medium_size(dfu); - if (dfu->r_left < 0) - return dfu->r_left; + ret = dfu->get_medium_size(dfu, &dfu->r_left); + if (ret < 0) + return ret; - debug("%s: %s %ld [B]\n", __func__, dfu->name, dfu->r_left); + debug("%s: %s %lld [B]\n", __func__, dfu->name, dfu->r_left); dfu->i_blk_seq_num = 0; dfu->crc = 0; diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index 395d472..e256664 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -169,17 +169,18 @@ static int mmc_file_op(enum dfu_op op, struct dfu_entity *dfu, } int dfu_write_medium_mmc(struct dfu_entity *dfu, - u64 offset, void *buf, long *len) + u64 offset, void *buf, long long *len) { int ret = -1; + long len_long = *len; switch (dfu->layout) { case DFU_RAW_ADDR: - ret = mmc_block_op(DFU_OP_WRITE, dfu, offset, buf, len); + ret = mmc_block_op(DFU_OP_WRITE, dfu, offset, buf, &len_long); break; case DFU_FS_FAT: case DFU_FS_EXT4: - ret = mmc_file_buffer(dfu, buf, len); + ret = mmc_file_buffer(dfu, buf, &len_long); break; default: printf("%s: Layout (%s) not (yet) supported!\n", __func__, @@ -205,14 +206,17 @@ int dfu_flush_medium_mmc(struct dfu_entity *dfu) return ret; } -long dfu_get_medium_size_mmc(struct dfu_entity *dfu) +int dfu_get_medium_size_mmc(struct dfu_entity *dfu, long long *size) { int ret; long len; + if (!size) + return -EFAULT; + switch (dfu->layout) { case DFU_RAW_ADDR: - return dfu->data.mmc.lba_size * dfu->data.mmc.lba_blk_size; + *size = dfu->data.mmc.lba_size * dfu->data.mmc.lba_blk_size; case DFU_FS_FAT: case DFU_FS_EXT4: dfu_file_buf_filled = -1; @@ -221,12 +225,14 @@ long dfu_get_medium_size_mmc(struct dfu_entity *dfu) return ret; if (len > CONFIG_SYS_DFU_MAX_FILE_SIZE) return -1; - return len; + *size = len; default: printf("%s: Layout (%s) not (yet) supported!\n", __func__, dfu_get_layout(dfu->layout)); return -1; } + + return 0; } static int mmc_file_unbuffer(struct dfu_entity *dfu, u64 offset, void *buf, @@ -251,17 +257,18 @@ static int mmc_file_unbuffer(struct dfu_entity *dfu, u64 offset, void *buf, } int dfu_read_medium_mmc(struct dfu_entity *dfu, u64 offset, void *buf, - long *len) + long long *len) { int ret = -1; + long len_long = *len; switch (dfu->layout) { case DFU_RAW_ADDR: - ret = mmc_block_op(DFU_OP_READ, dfu, offset, buf, len); + ret = mmc_block_op(DFU_OP_READ, dfu, offset, buf, &len_long); break; case DFU_FS_FAT: case DFU_FS_EXT4: - ret = mmc_file_unbuffer(dfu, offset, buf, len); + ret = mmc_file_unbuffer(dfu, offset, buf, &len_long); break; default: printf("%s: Layout (%s) not (yet) supported!\n", __func__, diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c index a975492..da2278e 100644 --- a/drivers/dfu/dfu_nand.c +++ b/drivers/dfu/dfu_nand.c @@ -20,7 +20,7 @@ #include <nand.h> static int nand_block_op(enum dfu_op op, struct dfu_entity *dfu, - u64 offset, void *buf, long *len) + u64 offset, void *buf, long long *len) { loff_t start, lim; size_t count, actual; @@ -86,19 +86,19 @@ static int nand_block_op(enum dfu_op op, struct dfu_entity *dfu, } static inline int nand_block_write(struct dfu_entity *dfu, - u64 offset, void *buf, long *len) + u64 offset, void *buf, long long *len) { return nand_block_op(DFU_OP_WRITE, dfu, offset, buf, len); } static inline int nand_block_read(struct dfu_entity *dfu, - u64 offset, void *buf, long *len) + u64 offset, void *buf, long long *len) { return nand_block_op(DFU_OP_READ, dfu, offset, buf, len); } static int dfu_write_medium_nand(struct dfu_entity *dfu, - u64 offset, void *buf, long *len) + u64 offset, void *buf, long long *len) { int ret = -1; @@ -114,13 +114,17 @@ static int dfu_write_medium_nand(struct dfu_entity *dfu, return ret; } -long dfu_get_medium_size_nand(struct dfu_entity *dfu) +int dfu_get_medium_size_nand(struct dfu_entity *dfu, long long *size) { - return dfu->data.nand.size; + if (!size) + return -EFAULT; + + *size = dfu->data.nand.size; + return 0; } static int dfu_read_medium_nand(struct dfu_entity *dfu, u64 offset, void *buf, - long *len) + long long *len) { int ret = -1; diff --git a/drivers/dfu/dfu_ram.c b/drivers/dfu/dfu_ram.c index e094a94..e63c682 100644 --- a/drivers/dfu/dfu_ram.c +++ b/drivers/dfu/dfu_ram.c @@ -15,7 +15,7 @@ #include <dfu.h> static int dfu_transfer_medium_ram(enum dfu_op op, struct dfu_entity *dfu, - u64 offset, void *buf, long *len) + u64 offset, void *buf, long long *len) { if (dfu->layout != DFU_RAM_ADDR) { error("unsupported layout: %s\n", dfu_get_layout(dfu->layout)); @@ -36,18 +36,22 @@ static int dfu_transfer_medium_ram(enum dfu_op op, struct dfu_entity *dfu, } static int dfu_write_medium_ram(struct dfu_entity *dfu, u64 offset, - void *buf, long *len) + void *buf, long long *len) { return dfu_transfer_medium_ram(DFU_OP_WRITE, dfu, offset, buf, len); } -long dfu_get_medium_size_ram(struct dfu_entity *dfu) +int dfu_get_medium_size_ram(struct dfu_entity *dfu, long long *size) { - return dfu->data.ram.size; + if (!size) + return -EFAULT; + + *size = dfu->data.ram.size; + return 0; } static int dfu_read_medium_ram(struct dfu_entity *dfu, u64 offset, - void *buf, long *len) + void *buf, long long *len) { return dfu_transfer_medium_ram(DFU_OP_READ, dfu, offset, buf, len); } diff --git a/drivers/dfu/dfu_sf.c b/drivers/dfu/dfu_sf.c index 9702eee..8ed565d 100644 --- a/drivers/dfu/dfu_sf.c +++ b/drivers/dfu/dfu_sf.c @@ -12,15 +12,21 @@ #include <spi.h> #include <spi_flash.h> -static long dfu_get_medium_size_sf(struct dfu_entity *dfu) +static int dfu_get_medium_size_sf(struct dfu_entity *dfu, long long *size) { - return dfu->data.sf.size; + if (!size) + return -EFAULT; + + *size = dfu->data.sf.size; + return 0; } static int dfu_read_medium_sf(struct dfu_entity *dfu, u64 offset, void *buf, - long *len) + long long *len) { - return spi_flash_read(dfu->data.sf.dev, offset, *len, buf); + size_t size = *len; + + return spi_flash_read(dfu->data.sf.dev, offset, size, buf); } static u64 find_sector(struct dfu_entity *dfu, u64 start, u64 offset) @@ -30,9 +36,10 @@ static u64 find_sector(struct dfu_entity *dfu, u64 start, u64 offset) } static int dfu_write_medium_sf(struct dfu_entity *dfu, - u64 offset, void *buf, long *len) + u64 offset, void *buf, long long *len) { int ret; + size_t size = *len; ret = spi_flash_erase(dfu->data.sf.dev, find_sector(dfu, dfu->data.sf.start, offset), @@ -41,7 +48,7 @@ static int dfu_write_medium_sf(struct dfu_entity *dfu, return ret; ret = spi_flash_write(dfu->data.sf.dev, dfu->data.sf.start + offset, - *len, buf); + size, buf); if (ret) return ret; diff --git a/include/dfu.h b/include/dfu.h index 6118dc2..c327bb5 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -110,13 +110,13 @@ struct dfu_entity { struct sf_internal_data sf; } data; - long (*get_medium_size)(struct dfu_entity *dfu); + int (*get_medium_size)(struct dfu_entity *dfu, long long *size); int (*read_medium)(struct dfu_entity *dfu, - u64 offset, void *buf, long *len); + u64 offset, void *buf, long long *len); int (*write_medium)(struct dfu_entity *dfu, - u64 offset, void *buf, long *len); + u64 offset, void *buf, long long *len); int (*flush_medium)(struct dfu_entity *dfu); unsigned int (*poll_timeout)(struct dfu_entity *dfu); @@ -132,8 +132,8 @@ struct dfu_entity { u8 *i_buf; u8 *i_buf_start; u8 *i_buf_end; - long r_left; - long b_left; + long long r_left; + long long b_left; u32 bad_skip; /* for nand use */ -- 2.5.0

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[U-Boot] [PATCH v2] board: atmel: sama5d2_xplained: add SPL support
by Wenyou Yang 02 Feb '16

02 Feb '16

The sama5d2 Xplained SPL supports the boot medias: spi flash and SD Card. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> --- This patch is base on [U-Boot] [PATCH v3 0/3] arm: at91/spl: add DDR3-SDRAM initialization support http://lists.denx.de/pipermail/u-boot/2016-February/244228.html Changes in v2: - adapt to ddr3_init() declaration variation. arch/arm/mach-at91/Kconfig | 1 + arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/include/mach/sama5d2.h | 32 +++++++ board/atmel/sama5d2_xplained/sama5d2_xplained.c | 103 +++++++++++++++++++++++ configs/sama5d2_xplained_mmc_defconfig | 1 + configs/sama5d2_xplained_spiflash_defconfig | 1 + include/configs/sama5d2_xplained.h | 39 +++++++++ 7 files changed, 178 insertions(+) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index c333647..9426302b 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -74,6 +74,7 @@ config TARGET_AT91SAM9X5EK config TARGET_SAMA5D2_XPLAINED bool "SAMA5D2 Xplained board" select CPU_V7 + select SUPPORT_SPL config TARGET_SAMA5D3_XPLAINED bool "SAMA5D3 Xplained board" diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 5b89617..abd1d13 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o +obj-$(CONFIG_SAMA5D2) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o obj-y += spl.o diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h index c85571c..dd5a2a7 100644 --- a/arch/arm/mach-at91/include/mach/sama5d2.h +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -106,6 +106,7 @@ #define ATMEL_BASE_MPDDRC 0xf000c000 #define ATMEL_BASE_XDMAC0 0xf0010000 #define ATMEL_BASE_PMC 0xf0014000 +#define ATMEL_BASE_MATRIX0 0xf0018000 #define ATMEL_BASE_QSPI0 0xf0020000 #define ATMEL_BASE_QSPI1 0xf0024000 #define ATMEL_BASE_SPI0 0xf8000000 @@ -117,6 +118,7 @@ #define ATMEL_BASE_UART1 0xf8020000 #define ATMEL_BASE_UART2 0xf8024000 #define ATMEL_BASE_TWI0 0xf8028000 +#define ATMEL_BASE_SFR 0xf8030000 #define ATMEL_BASE_SYSC 0xf8048000 #define ATMEL_BASE_SPI1 0xfc000000 #define ATMEL_BASE_UART3 0xfc008000 @@ -125,6 +127,7 @@ #define ATMEL_BASE_UDPHS 0xfc02c000 #define ATMEL_BASE_PIOA 0xfc038000 +#define ATMEL_BASE_MATRIX1 0xfc03c000 #define ATMEL_CHIPID_CIDR 0xfc069000 #define ATMEL_CHIPID_EXID 0xfc069004 @@ -171,6 +174,35 @@ #define CPU_HAS_PCR #define CPU_HAS_H32MXDIV +/* AICREDIR Unlock Key */ +#define ATMEL_SFR_AICREDIR_KEY 0xB6D81C4D + +/* MATRIX0(H64MX) slave id definitions */ +#define H64MX_SLAVE_AXIMX_BRIDGE 0 /* Bridge from H64MX to AXIMX */ +#define H64MX_SLAVE_PERIPH_BRIDGE 1 /* H64MX Peripheral Bridge */ +#define H64MX_SLAVE_DDRC_PORT0 2 /* DDR2 Port0-AESOTF */ +#define H64MX_SLAVE_DDRC_PORT1 3 /* DDR2 Port1 */ +#define H64MX_SLAVE_DDRC_PORT2 4 /* DDR2 Port2 */ +#define H64MX_SLAVE_DDRC_PORT3 5 /* DDR2 Port3 */ +#define H64MX_SLAVE_DDRC_PORT4 6 /* DDR2 Port4 */ +#define H64MX_SLAVE_DDRC_PORT5 7 /* DDR2 Port5 */ +#define H64MX_SLAVE_DDRC_PORT6 8 /* DDR2 Port6 */ +#define H64MX_SLAVE_DDRC_PORT7 9 /* DDR2 Port7 */ +#define H64MX_SLAVE_SRAM 10 /* Internal SRAM 128K */ +#define H64MX_SLAVE_CACHE_L2 11 /* Internal SRAM 128K(L2) */ +#define H64MX_SLAVE_QSPI0 12 /* QSPI0 */ +#define H64MX_SLAVE_QSPI1 13 /* QSPI1 */ +#define H64MX_SLAVE_AESB 14 /* AESB */ + +/* MATRIX1(H32MX) slave id definitions */ +#define H32MX_SLAVE_H64MX_BRIDGE 0 /* Bridge from H32MX to H64MX */ +#define H32MX_SLAVE_PERIPH_BRIDGE0 1 /* H32MX Peripheral Bridge 0 */ +#define H32MX_SLAVE_PERIPH_BRIDGE1 2 /* H32MX Peripheral Bridge 1 */ +#define H32MX_SLAVE_EBI 3 /* External Bus Interface */ +#define H32MX_SLAVE_NFC_CMD 3 /* NFC command Register */ +#define H32MX_SLAVE_NFC_SRAM 4 /* NFC SRAM */ +#define H32MX_SLAVE_USB 5 /* USB Device & Host */ + /* SAMA5D2 series chip id definitions */ #define ARCH_ID_SAMA5D2 0x8a5c08c0 #define ARCH_EXID_SAMA5D21CU 0x0000005a diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index 0b3397f..8ed01dd 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -17,6 +17,7 @@ #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/atmel_pio4.h> +#include <asm/arch/atmel_mpddrc.h> #include <asm/arch/atmel_usba_udc.h> #include <asm/arch/atmel_sdhci.h> #include <asm/arch/clk.h> @@ -281,3 +282,105 @@ int board_eth_init(bd_t *bis) return rc; } + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ +#ifdef CONFIG_SYS_USE_SERIALFLASH + board_spi0_hw_init(); +#endif +#ifdef CONFIG_ATMEL_SDHCI +#ifdef CONFIG_ATMEL_SDHCI0 + board_sdhci0_hw_init(); +#endif +#ifdef CONFIG_ATMEL_SDHCI1 + board_sdhci1_hw_init(); +#endif +#endif +} + +static void ddrc_conf(struct atmel_mpddrc_config *ddrc) +{ + ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM); + + ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS5 | + ATMEL_MPDDRC_CR_DIC_DS | + ATMEL_MPDDRC_CR_DIS_DLL | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddrc->rtr = 0x511; + + ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET | + 29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET); + + ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET | + 0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + struct atmel_mpddrc_config ddrc_config; + u32 reg; + + ddrc_conf(&ddrc_config); + + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + writel(AT91_PMC_DDR, &pmc->scer); + + reg = readl(&mpddrc->io_calibr); + reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; + reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55; + reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; + reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100); + writel(reg, &mpddrc->io_calibr); + + writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE, + &mpddrc->rd_data_path); + + ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); + + writel(0x3, &mpddrc->cal_mr4); + writel(64, &mpddrc->tim_cal); +} + +void at91_pmc_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(82) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + writel(0x0 << 8, &pmc->pllicpr); + + tmp = AT91_PMC_MCKR_H32MXDIV | + AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index c1dcbef..75b1713 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D2_XPLAINED=y +CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC" # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index 0271e8e..6d61a7e 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_SAMA5D2_XPLAINED=y +CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH" # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index ae5ba3d..272257e 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -25,8 +25,12 @@ #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS #define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x210000 +#else #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ @@ -119,4 +123,39 @@ #endif +/* SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x200000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SYS_MONITOR_LEN (512 << 10) + +#ifdef CONFIG_SYS_USE_MMC +#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/armv7/u-boot-spl.lds +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT + +#elif CONFIG_SYS_USE_SERIALFLASH +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 + +#endif + #endif -- 1.7.9.5

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