February 2016 - U-Boot

[U-Boot] [PATCH v2] spl: define BOOT_DEVICE_USB
by Masahiro Yamada 14 Feb '16

14 Feb '16

This enum is referenced from common/spl/spl.c. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- Changes in v2: - s/macro/enum/ arch/arm/include/asm/spl.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 5c5d33f..19c38f4 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -24,6 +24,7 @@ enum { BOOT_DEVICE_NOR, BOOT_DEVICE_UART, BOOT_DEVICE_SPI, + BOOT_DEVICE_USB, BOOT_DEVICE_SATA, BOOT_DEVICE_I2C, BOOT_DEVICE_BOARD, -- 1.9.1

1 2

[U-Boot] [PATCH v2] ARM: uniphier: update U-Boot file names
by Masahiro Yamada 14 Feb '16

14 Feb '16

Since commit ad1ecd2063da ("fdt: Build a U-Boot binary without device tree") and commit 03c25bcd263a ("fdt: Build an SPL binary without device tree"), we can use shorter file names for the output images. The default configuration for UniPhier SoCs enables CONFIG_OF_SEPARATE and CONFIG_SPL_OF_CONTROL. In this case, spl/u-boot-spl-dtb.bin is the same as spl/u-boot-spl.bin. Likewise, u-boot-dtb.img is the same as u-boot.img. So, this change of the flow has no impact. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- Changes in v2: - Also update include/configs/uniphier.h doc/README.uniphier | 6 +++--- include/configs/uniphier.h | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/doc/README.uniphier b/doc/README.uniphier index bce70cf..bcf0ac3 100644 --- a/doc/README.uniphier +++ b/doc/README.uniphier @@ -68,8 +68,8 @@ Burn U-Boot images to NAND -------------------------- Write two files to the NAND device as follows: - - spl/u-boot-spl-dtb.bin at the offset address 0x00000000 - - u-boot-dtb.img at the offset address 0x00010000 + - spl/u-boot-spl.bin at the offset address 0x00000000 + - u-boot.img at the offset address 0x00010000 If a TFTP server is available, the images can be easily updated. Just copy the u-boot-spl-dtb.bin and u-boot-dtb.img to the TFTP public @@ -145,4 +145,4 @@ newer SoCs. Even if it is, EA[25] is not connected on most of the boards. -- Masahiro Yamada <yamada.masahiro(a)socionext.com> -Aug. 2015 +Feb. 2016 diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 97168e9..8856044 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -230,9 +230,9 @@ "nor_base=0x42000000\0" \ "bootm_low=0x80000000\0" \ "nandupdate=nand erase 0 0x00100000 &&" \ - "tftpboot u-boot-spl-dtb.bin &&" \ + "tftpboot u-boot-spl.bin &&" \ "nand write $loadaddr 0 0x00010000 &&" \ - "tftpboot u-boot-dtb.img &&" \ + "tftpboot u-boot.img &&" \ "nand write $loadaddr 0x00010000 0x000f0000\0" \ LINUXBOOT_ENV_SETTINGS -- 1.9.1

2 2

[U-Boot] [PATCH] ARM: uniphier: support some more DRAM use cases on PH1-Pro4
by Masahiro Yamada 14 Feb '16

14 Feb '16

Some of PH1-Pro4 boards are equipped with larger amount of DRAM than the reference board. Add UMC settings to support them. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 80 ++++++++++++++++++++---------- 1 file changed, 53 insertions(+), 27 deletions(-) diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index 4d976e3..261f7cf 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -13,6 +13,16 @@ #include "ddrphy-regs.h" #include "umc-regs.h" +enum dram_size { + DRAM_SZ_128M, + DRAM_SZ_256M, + DRAM_SZ_512M, + DRAM_SZ_NR, +}; + +static u32 umc_initctlb[DRAM_SZ_NR] = {0x43030d3f, 0x43030d3f, 0x7b030d3f}; +static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617, 0x00770617}; + static void umc_start_ssif(void __iomem *ssif_base) { writel(0x00000001, ssif_base + 0x0000b004); @@ -56,19 +66,36 @@ static void umc_start_ssif(void __iomem *ssif_base) writel(0x00000001, ssif_base + UMC_DMDRST); } -static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq) +static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int width) { + enum dram_size dram_size; + + switch (size / (width / 16)) { + case SZ_128M: + dram_size = DRAM_SZ_128M; + break; + case SZ_256M: + dram_size = DRAM_SZ_256M; + break; + case SZ_512M: + dram_size = DRAM_SZ_512M; + break; + default: + printf("unsupported DRAM size\n"); + return -EINVAL; + } + writel(0x66bb0f17, dramcont + UMC_CMDCTLA); writel(0x18c6aa44, dramcont + UMC_CMDCTLB); writel(0x5101387f, dramcont + UMC_INITCTLA); - writel(0x43030d3f, dramcont + UMC_INITCTLB); + writel(umc_initctlb[dram_size], dramcont + UMC_INITCTLB); writel(0x00ff00ff, dramcont + UMC_INITCTLC); writel(0x00000d71, dramcont + UMC_DRMMR0); writel(0x00000006, dramcont + UMC_DRMMR1); writel(0x00000298, dramcont + UMC_DRMMR2); writel(0x00000000, dramcont + UMC_DRMMR3); - writel(0x003f0617, dramcont + UMC_SPCCTLA); + writel(umc_spcctla[dram_size], dramcont + UMC_SPCCTLA); writel(0x00ff0008, dramcont + UMC_SPCCTLB); writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); writel(0x000c00ae, dramcont + UMC_RDATACTL_D1); @@ -90,9 +117,11 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, writel(0x200a0a00, dramcont + UMC_SPCSETB); writel(0x00010000, dramcont + UMC_SPCSETD); writel(0x80000020, dramcont + UMC_DFICUPDCTLA); + + return 0; } -static int umc_init_sub(int freq, int size_ch0, int size_ch1) +int ph1_pro4_umc_init(const struct uniphier_board_data *bd) { void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); @@ -103,6 +132,12 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1) void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1); void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1); + int ret; + + if (bd->dram_freq != 1600) { + pr_err("Unsupported DDR configuration\n"); + return -EINVAL; + } umc_dram_init_start(dramcont0); umc_dram_init_start(dramcont1); @@ -111,52 +146,43 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1) writel(0x00000101, dramcont0 + UMC_DIOCTLA); - ph1_pro4_ddrphy_init(phy0_0, freq, size_ch0); + ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch0_size); ddrphy_prepare_training(phy0_0, 0); ddrphy_training(phy0_0); writel(0x00000103, dramcont0 + UMC_DIOCTLA); - ph1_pro4_ddrphy_init(phy0_1, freq, size_ch0); + ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch0_size); ddrphy_prepare_training(phy0_1, 1); ddrphy_training(phy0_1); writel(0x00000101, dramcont1 + UMC_DIOCTLA); - ph1_pro4_ddrphy_init(phy1_0, freq, size_ch1); + ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch1_size); ddrphy_prepare_training(phy1_0, 0); ddrphy_training(phy1_0); writel(0x00000103, dramcont1 + UMC_DIOCTLA); - ph1_pro4_ddrphy_init(phy1_1, freq, size_ch1); + ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch1_size); ddrphy_prepare_training(phy1_1, 1); ddrphy_training(phy1_1); - umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); - umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); + ret = umc_dramcont_init(dramcont0, ca_base0, bd->dram_ch0_size, + bd->dram_ch0_width); + if (ret) + return ret; + + ret = umc_dramcont_init(dramcont1, ca_base1, bd->dram_ch1_size, + bd->dram_ch1_width); + if (ret) + return ret; umc_start_ssif(ssif_base); return 0; } - -int ph1_pro4_umc_init(const struct uniphier_board_data *bd) -{ - if (((bd->dram_ch0_size == SZ_512M && bd->dram_ch0_width == 32) || - (bd->dram_ch0_size == SZ_256M && bd->dram_ch0_width == 16)) && - ((bd->dram_ch1_size == SZ_512M && bd->dram_ch1_width == 32) || - (bd->dram_ch1_size == SZ_256M && bd->dram_ch1_width == 16)) && - bd->dram_freq == 1600) { - return umc_init_sub(bd->dram_freq, - bd->dram_ch0_size / SZ_128M, - bd->dram_ch1_size / SZ_128M); - } else { - pr_err("Unsupported DDR configuration\n"); - return -EINVAL; - } -} -- 1.9.1

1 1

[U-Boot] [PATCH 0/4] ARM: uniphier: several fixes of include/configs/uniphiers.h
by Masahiro Yamada 14 Feb '16

14 Feb '16

Masahiro Yamada (4): ARM: uniphier: fix NOR boot command ARM: uniphier: add default bootm_low to fix FIT boot ARM: uniphier: factor out common part of boot commands ARM: uniphier: fix nfsboot command include/configs/uniphier.h | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-) -- 1.9.1

1 5

[U-Boot] [PATCH] ARM: uniphier: remove unused header mio-regs.h
by Masahiro Yamada 14 Feb '16

14 Feb '16

This header is no longer used. This is the last file in arch/arm/mach-uniphier/include/mach/. At last, I've succeeded in eliminating the mach directory. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arm/mach-uniphier/include/mach/mio-regs.h | 20 -------------------- 1 file changed, 20 deletions(-) delete mode 100644 arch/arm/mach-uniphier/include/mach/mio-regs.h diff --git a/arch/arm/mach-uniphier/include/mach/mio-regs.h b/arch/arm/mach-uniphier/include/mach/mio-regs.h deleted file mode 100644 index 3306934..0000000 --- a/arch/arm/mach-uniphier/include/mach/mio-regs.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * UniPhier MIO (Media I/O) registers - * - * Copyright (C) 2014 Panasonic Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef ARCH_MIO_REGS_H -#define ARCH_MIO_REGS_H - -#define MIO_BASE 0x59810000 - -#define MIO_CLKCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0020) -#define MIO_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0110) -#define MIO_USB_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0114) - -#define MIO_USB_RSTCTRL_XRST (0x1 << 0) - -#endif /* ARCH_MIO_REGS_H */ -- 1.9.1

1 1

[U-Boot] [PATCH 00/13] ARM: uniphier: a collection of clean-ups and new clock driver
by Masahiro Yamada 14 Feb '16

14 Feb '16

Masahiro Yamada (13): ARM: uniphier: change stack pointer address for SPL ARM: uniphier: create early page table at run-time ARM: uniphier: add missing static qualifier ARM: uniphier: support USB boot mode for ProXstream2 / PH1-LD6b SoC clk: uniphier: add Media I/O clock driver for UniPhier SoCs ARM: dts: uniphier: add reference clock nodes ARM: dts: uniphier: add device nodes for system control blocks ARM: dts: uniphier: add device nodes for Peripheral control block ARM: dts: uniphier: add device nodes for MIO control block ARM: dts: uniphier: switch to use clock drivers usb: remove UniPhier EHCI driver ARM: uniphier: enable generic EHCI driver ARM: uniphier: drop unneeded EHCI pin mux settings arch/arm/Kconfig | 1 + arch/arm/dts/uniphier-common32.dtsi | 27 ++++ arch/arm/dts/uniphier-ph1-ld4.dtsi | 23 +++ arch/arm/dts/uniphier-ph1-pro4.dtsi | 22 +++ arch/arm/dts/uniphier-ph1-pro5.dtsi | 20 +++ arch/arm/dts/uniphier-ph1-sld3.dtsi | 26 +++ arch/arm/dts/uniphier-ph1-sld8.dtsi | 23 +++ arch/arm/dts/uniphier-proxstream2.dtsi | 20 +++ arch/arm/mach-uniphier/Makefile | 1 - arch/arm/mach-uniphier/board_late_init.c | 8 +- arch/arm/mach-uniphier/boot-mode/boot-device.h | 2 + .../boot-mode/boot-mode-proxstream2.c | 5 +- arch/arm/mach-uniphier/boot-mode/boot-mode.c | 11 +- arch/arm/mach-uniphier/clk/clk-ph1-ld4.c | 4 +- arch/arm/mach-uniphier/clk/clk-ph1-pro4.c | 4 +- arch/arm/mach-uniphier/init_page_table.S | 32 ---- arch/arm/mach-uniphier/lowlevel_init.S | 103 +++++++++++- arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c | 9 -- arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c | 7 - arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c | 2 +- arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c | 9 -- configs/uniphier_ld4_sld8_defconfig | 2 + configs/uniphier_sld3_defconfig | 2 + drivers/clk/Kconfig | 2 + drivers/clk/Makefile | 1 + drivers/clk/uniphier/Kconfig | 13 ++ drivers/clk/uniphier/Makefile | 3 + drivers/clk/uniphier/clk-uniphier-core.c | 159 ++++++++++++++++++ drivers/clk/uniphier/clk-uniphier-mio.c | 178 +++++++++++++++++++++ drivers/clk/uniphier/clk-uniphier.h | 57 +++++++ drivers/usb/host/Kconfig | 7 - drivers/usb/host/Makefile | 1 - drivers/usb/host/ehci-uniphier.c | 75 --------- include/configs/uniphier.h | 2 +- 34 files changed, 703 insertions(+), 158 deletions(-) delete mode 100644 arch/arm/mach-uniphier/init_page_table.S create mode 100644 drivers/clk/uniphier/Kconfig create mode 100644 drivers/clk/uniphier/Makefile create mode 100644 drivers/clk/uniphier/clk-uniphier-core.c create mode 100644 drivers/clk/uniphier/clk-uniphier-mio.c create mode 100644 drivers/clk/uniphier/clk-uniphier.h delete mode 100644 drivers/usb/host/ehci-uniphier.c -- 1.9.1

2 15

[U-Boot] [PATCH v2 0/5] x86: ivybridge: Add Intel FSP support
by Bin Meng 14 Feb '16

14 Feb '16

This series adds Intel FSP support to IvyBridge processor and Panther Point chipset (aka Chief River platform), and is validated on Intel Cougar Canyon 2 board. This only adds basic features like serial, keyboard, RTC, timer, SPI, GPIO, PCI, SATA, USB. Other features will be enabled in future patch set. Changes in v2: - Drop patches which were already applied - Rebase on top of u-boot-x86/master - Change fsp files license from Intel to GPL-2.0+ - Introduce a Kconfig option to wrap these codes - Change include order - <asm/...> go after the normal includes - Use PCH uclass driver and change to use dm pci config APIs Bin Meng (5): x86: ivybridge: Add FSP support superio: Add SMSC SIO1007 driver x86: fsp: Make sure HOB list is not overwritten by U-Boot x86: ivybridge: bd82x6x: Support FSP enabled configuration x86: Add Intel Cougar Canyon 2 board arch/x86/Kconfig | 10 ++ arch/x86/cpu/ivybridge/Kconfig | 12 ++ arch/x86/cpu/ivybridge/Makefile | 6 +- arch/x86/cpu/ivybridge/bd82x6x.c | 4 + arch/x86/cpu/ivybridge/fsp_configs.c | 45 ++++++++ arch/x86/cpu/ivybridge/ivybridge.c | 22 ++++ arch/x86/dts/Makefile | 1 + arch/x86/dts/cougarcanyon2.dts | 104 +++++++++++++++++ .../include/asm/arch-ivybridge/fsp/fsp_configs.h | 40 +++++++ arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h | 12 ++ arch/x86/lib/fsp/fsp_support.c | 33 ++++++ board/intel/Kconfig | 9 ++ board/intel/cougarcanyon2/Kconfig | 25 ++++ board/intel/cougarcanyon2/MAINTAINERS | 6 + board/intel/cougarcanyon2/Makefile | 7 ++ board/intel/cougarcanyon2/cougarcanyon2.c | 58 ++++++++++ board/intel/cougarcanyon2/start.S | 9 ++ configs/cougarcanyon2_defconfig | 21 ++++ drivers/misc/Makefile | 1 + drivers/misc/smsc_sio1007.c | 126 +++++++++++++++++++++ include/configs/cougarcanyon2.h | 34 ++++++ include/smsc_sio1007.h | 115 +++++++++++++++++++ 22 files changed, 699 insertions(+), 1 deletion(-) create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c create mode 100644 arch/x86/dts/cougarcanyon2.dts create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h create mode 100644 board/intel/cougarcanyon2/Kconfig create mode 100644 board/intel/cougarcanyon2/MAINTAINERS create mode 100644 board/intel/cougarcanyon2/Makefile create mode 100644 board/intel/cougarcanyon2/cougarcanyon2.c create mode 100644 board/intel/cougarcanyon2/start.S create mode 100644 configs/cougarcanyon2_defconfig create mode 100644 drivers/misc/smsc_sio1007.c create mode 100644 include/configs/cougarcanyon2.h create mode 100644 include/smsc_sio1007.h -- 1.8.2.1

2 9

[U-Boot] [PATCH] openrisc: updating build tools naming convention
by Guillaume REMBERT 13 Feb '16

13 Feb '16

Dear u-boot community, I just made a small change on the openrisc-generic platform configuration to take in account the new naming convention (or1k instead of or32, so the build process gets fine). Could you take care to review and approve the following patch, please? Kind regards, -- ____________________________________________ Guillaume REMBERT Phone/Fax: 0033 9 72 32 55 76 Mobile: 0033 6 83 27 98 19 E-Mail: guillaume.rembert(a)euryecetelecom.com ____________________________________________ On Earth and Space... EURYECE TELECOM ... where failure is not an option http://www.euryecetelecom.com __________________________________ 51d13f5355943e14db4b95a7f8ae4cd87eba1fe1 arch/openrisc/config.mk | 2 +- arch/openrisc/cpu/u-boot.lds | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/openrisc/config.mk b/arch/openrisc/config.mk index cd95f24..bfdb71f 100644 --- a/arch/openrisc/config.mk +++ b/arch/openrisc/config.mk @@ -6,7 +6,7 @@ # ifeq ($(CROSS_COMPILE),) -CROSS_COMPILE := or32-elf- +CROSS_COMPILE := or1k-elf- endif # r10 used for global object pointer, already set in OR32 GCC but just to be diff --git a/arch/openrisc/cpu/u-boot.lds b/arch/openrisc/cpu/u-boot.lds index d9bb7b7..854088b 100644 --- a/arch/openrisc/cpu/u-boot.lds +++ b/arch/openrisc/cpu/u-boot.lds @@ -1,5 +1,5 @@ #include <config.h> -OUTPUT_ARCH(or32) +OUTPUT_ARCH(or1k) __DYNAMIC = 0; MEMORY

3 5

[U-Boot] oddity(?) in selection of FCC Ethernet index in 2014 version of u-boot
by Robert P. J. Day 13 Feb '16

13 Feb '16

at the moment, i'm trying to get a minimal u-boot running on an MPC8280-based target board (please, no jokes), and for the sake of expediency, i just used git to check out a version of u-boot just before it removed the definition of a target board (MPC8260ads) that seems moderately close to what i'm after. so i checked out git commit 373a9788f05dfab47e01badc046459dead163104, which is dated May of 2014 to see what I could do with that, and I found the following oddity(?). I actually selected the (8280-based) PQ2FADS board: $ make PQ2FADS_config and started tweaking until i got to configuring Ethernet support on FCC. the board definition file MPC8260ADS.h contains the following snippet for selecting Ethernet on FCC: #ifdef CONFIG_ETHER_ON_FCC #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ #if CONFIG_ETHER_INDEX == 1 # define CONFIG_SYS_PHY_ADDR 0 # define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10) # define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) #elif CONFIG_ETHER_INDEX == 2 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */ # define CONFIG_SYS_PHY_ADDR 3 # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16) #else /* RxCLK is CLK13, TxCLK is CLK14 */ # define CONFIG_SYS_PHY_ADDR 0 # define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ # define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) #endif /* CONFIG_ETHER_INDEX */ fair enough ... the above clearly implies that Ethernet on FCC will be defined by the values of the two variables: CONFIG_ETHER_ON_FCC CONFIG_ETHER_INDEX but here's the puzzler -- this appears to be implemented by the source file arch/powerpc/cpu/mpc8260/ether_fcc.c (it is in fact compiled), but that file contains the snippet: #if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) static struct ether_fcc_info_s { int ether_index; int proff_enet; ulong cpm_cr_enet_sblock; ulong cpm_cr_enet_page; ulong cmxfcr_mask; ulong cmxfcr_value; } ether_fcc_info[] = { #ifdef CONFIG_ETHER_ON_FCC1 { 0, PROFF_FCC1, CPM_CR_FCC1_SBLOCK, CPM_CR_FCC1_PAGE, CONFIG_SYS_CMXFCR_MASK1, CONFIG_SYS_CMXFCR_VALUE1 }, #endif #ifdef CONFIG_ETHER_ON_FCC2 ... snip ... note that the board header file sets CONFIG_ETHER_INDEX to identify the channel, but that source file checks the variables CONFIG_ETHER_ON_FCC1, CONFIG_ETHER_ON_FCC2 and so on, which are not set in the board definition file. i took a look and, back then, some boards defined CONFIG_ETHER_ON_FCCn, while others set CONFIG_ETHER_INDEX. it seems that doing it that second way could not possibly have worked. i'm just writing this off to bit-rot in that nobody really looked at those old boards for a long time. but am i right in concluding that using CONFIG_ETHER_INDEX to select the FCC channel could not possibly have worked? or am i missing something? rday p.s. to be more precise about the target board, a group of us are porting linux to the Mitel 3300 AX Controller. so if you've been down that or a similar road, i'd love to hear from you.

1 0

[U-Boot] [PATCH v3 1/2] zynqmp: nand: Add Nand driver support for zynqmp
by Siva Durga Prasad Paladugu 13 Feb '16

13 Feb '16

Add nand driver support for zynqmp. The Nand controller used in ZynqMP is Arasan Nand Flash controller. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- Changes from v2: - Moved config NAND_ARASAN to driver/mtd/nand/Kconfig as per review comment Changes from v1: - Newly added in series --- arch/arm/include/asm/arch-zynqmp/hardware.h | 2 ++ configs/xilinx_zynqmp_ep_defconfig | 1 + drivers/mtd/nand/Kconfig | 7 +++++++ include/configs/xilinx_zynqmp.h | 9 +++++++++ 4 files changed, 19 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index 0f03c24..3c9f08c 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -25,6 +25,8 @@ #define ZYNQ_SDHCI_BASEADDR0 0xFF160000 #define ZYNQ_SDHCI_BASEADDR1 0xFF170000 +#define ARASAN_NAND_BASEADDR 0xFF100000 + #define ZYNQMP_SATA_BASEADDR 0xFD0C0000 #define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000 diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index 79304c1..43a24a7 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQMP=y CONFIG_ZYNQMP_USB=y +CONFIG_NAND_ARASAN=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108" CONFIG_SYS_PROMPT="ZynqMP> " diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 9a74064..6e35213 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -71,6 +71,13 @@ config NAND_SUNXI Enable support for NAND. This option allows SPL to read from sunxi NAND using DMA transfers. +config NAND_ARASAN + bool "Configure Arasan Nand" + help + This enables Nand driver support for Arasan nand flash + controller. This uses the hardware ECC for read and + write operations. + comment "Generic NAND options" # Enhance depends when converting drivers to Kconfig which use this config diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 36c1100..1f17adb 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -101,6 +101,15 @@ # define CONFIG_CMD_EXT4_WRITE #endif +#ifdef CONFIG_NAND_ARASAN +# define CONFIG_CMD_NAND +# define CONFIG_CMD_NAND_LOCK_UNLOCK +# define CONFIG_SYS_MAX_NAND_DEVICE 1 +# define CONFIG_SYS_NAND_SELF_INIT +# define CONFIG_SYS_NAND_ONFI_DETECTION +# define CONFIG_MTD_DEVICE +#endif + /* Miscellaneous configurable options */ #define CONFIG_SYS_LOAD_ADDR 0x8000000 -- 1.7.1

2 3